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Differential D117207

[AArch64] Add native CPU detection for Neoverse-V1.
ClosedPublic

Authored by sdesmalen on Jan 13 2022, 3:37 AM.

Details

Reviewers
david-arm
dmgreen
SjoerdMeijer
Commits
rGb92102a6d79f: [AArch64] Add native CPU detection for Neoverse-V1.
Summary

Map Main ID part number 0xd40 to neoverse-v1, as described in the
Neoverse-V1 Technical Reference Manual:

https://developer.arm.com/documentation/101427/0101/Register-descriptions/AArch64-system-registers/MIDR-EL1--Main-ID-Register--EL1

Diff Detail

Event Timeline

sdesmalen created this revision.Jan 13 2022, 3:37 AM
Herald added subscribers: dexonsmith, hiraditya, kristof.beyls. · View Herald TranscriptJan 13 2022, 3:37 AM
sdesmalen requested review of this revision.Jan 13 2022, 3:37 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 13 2022, 3:37 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
sdesmalen added reviewers: david-arm, dmgreen, SjoerdMeijer.Jan 13 2022, 3:37 AM
dmgreen accepted this revision.Jan 13 2022, 4:02 AM

LGTM

This revision is now accepted and ready to land.Jan 13 2022, 4:02 AM
Harbormaster completed remote builds in B143124: Diff 399620.Jan 13 2022, 4:10 AM
Closed by commit rGb92102a6d79f: [AArch64] Add native CPU detection for Neoverse-V1. (authored by sdesmalen). · Explain WhyJan 13 2022, 4:59 AM
This revision was automatically updated to reflect the committed changes.
sdesmalen added a commit: rGb92102a6d79f: [AArch64] Add native CPU detection for Neoverse-V1..

Revision Contents

PathSize
llvm/
lib/
Support/
1 line
unittests/
Support/
3 lines

Diff 399636

llvm/lib/Support/Host.cpp

Show First 20 Lines • Show All 207 Lines • ▼ Show 20 Lines return StringSwitch<const char *>(Part)
.Case("0xd09", "cortex-a73") .Case("0xd09", "cortex-a73")
.Case("0xd0a", "cortex-a75") .Case("0xd0a", "cortex-a75")
.Case("0xd0b", "cortex-a76") .Case("0xd0b", "cortex-a76")
.Case("0xd0d", "cortex-a77") .Case("0xd0d", "cortex-a77")
.Case("0xd41", "cortex-a78") .Case("0xd41", "cortex-a78")
.Case("0xd44", "cortex-x1") .Case("0xd44", "cortex-x1")
.Case("0xd0c", "neoverse-n1") .Case("0xd0c", "neoverse-n1")
.Case("0xd49", "neoverse-n2") .Case("0xd49", "neoverse-n2")
.Case("0xd40", "neoverse-v1")
.Default("generic"); .Default("generic");
} }
if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium. if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
return StringSwitch<const char *>(Part) return StringSwitch<const char *>(Part)
.Case("0x516", "thunderx2t99") .Case("0x516", "thunderx2t99")
.Case("0x0516", "thunderx2t99") .Case("0x0516", "thunderx2t99")
.Case("0xaf", "thunderx2t99") .Case("0xaf", "thunderx2t99")
▲ Show 20 Lines • Show All 1,545 Lines • Show Last 20 Lines

llvm/unittests/Support/Host.cpp

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
} }
TEST(getLinuxHostCPUName, AArch64) { TEST(getLinuxHostCPUName, AArch64) {
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n" EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
"CPU part : 0xd03"), "CPU part : 0xd03"),
"cortex-a53"); "cortex-a53");
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n" EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
"CPU part : 0xd40"),
"neoverse-v1");
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
"CPU part : 0xd0c"), "CPU part : 0xd0c"),
"neoverse-n1"); "neoverse-n1");
// Verify that both CPU implementer and CPU part are checked: // Verify that both CPU implementer and CPU part are checked:
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x40\n" EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x40\n"
"CPU part : 0xd03"), "CPU part : 0xd03"),
"generic"); "generic");
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n" EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
"CPU part : 0x201"), "CPU part : 0x201"),
▲ Show 20 Lines • Show All 401 Lines • Show Last 20 Lines