[AArch64] Basic demand elements for some intrinsics

[dmgreen]

Summary

A lot of neon intrinsics work lane-wise, meaning that non-demanded elements in and not demanded out. This teaches that to AArch64TTIImpl::simplifyDemandedVectorEltsIntrinsic for some simple single-input truncate intrinsics, which can help remove unnecessary instructions in the final result.

[david-arm]

The change looks sensible to me, although I was a little confused by the commit message? It looks like what your patch is doing is just adding an AArch64 version of simplifyDemandedVectorEltsIntrinsic, that allows us to potentially simplify the input operand to the intrinsic based on the demanded elements. So, for example, if we know that we are only going to use the first N elements of the intrinsic result we can use that information to simplify the intrinsic operand too.

[dmgreen]

It looks like what your patch is doing is just adding an AArch64 version of simplifyDemandedVectorEltsIntrinsic, that allows us to potentially simplify the input operand to the intrinsic based on the demanded elements. So, for example, if we know that we are only going to use the first N elements of the intrinsic result we can use that information to simplify the intrinsic operand too.

Yep. I had written "single element" where I meant "single source". I can see that being confusing, but you have the right idea.

We could do it for binops too, but I've not looked at those here, just truncates with a single input.

[david-arm]

LGTM!

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h

public:
   }
 
   InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
                                         TTI::TargetCostKind CostKind);
 
   Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
                                                IntrinsicInst &II) const;
 
+  Optional<Value *> simplifyDemandedVectorEltsIntrinsic(
+      InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
+      APInt &UndefElts2, APInt &UndefElts3,
+      std::function<void(Instruction *, unsigned, APInt, APInt &)>
+          SimplifyAndSetOp) const;
+
   TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
     switch (K) {
     case TargetTransformInfo::RGK_Scalar:
       return TypeSize::getFixed(64);
     case TargetTransformInfo::RGK_FixedWidthVector:
       if (ST->hasSVE())
         return TypeSize::getFixed(
             std::max(ST->getMinSVEVectorSizeInBits(), 128u));

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

case Intrinsic::aarch64_sve_st1:
     return instCombineSVEST1(IC, II, DL);
   case Intrinsic::aarch64_sve_sdiv:
     return instCombineSVESDIV(IC, II);
   }
 
   return None;
 }
 
+Optional<Value *> AArch64TTIImpl::simplifyDemandedVectorEltsIntrinsic(
+    InstCombiner &IC, IntrinsicInst &II, APInt OrigDemandedElts,
+    APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
+    std::function<void(Instruction *, unsigned, APInt, APInt &)>
+        SimplifyAndSetOp) const {
+  switch (II.getIntrinsicID()) {
+  default:
+    break;
+  case Intrinsic::aarch64_neon_fcvtxn:
+  case Intrinsic::aarch64_neon_rshrn:
+  case Intrinsic::aarch64_neon_sqrshrn:
+  case Intrinsic::aarch64_neon_sqrshrun:
+  case Intrinsic::aarch64_neon_sqshrn:
+  case Intrinsic::aarch64_neon_sqshrun:
+  case Intrinsic::aarch64_neon_sqxtn:
+  case Intrinsic::aarch64_neon_sqxtun:
+  case Intrinsic::aarch64_neon_uqrshrn:
+  case Intrinsic::aarch64_neon_uqshrn:
+  case Intrinsic::aarch64_neon_uqxtn:
+    SimplifyAndSetOp(&II, 0, OrigDemandedElts, UndefElts);
+    break;
+  }
+
+  return None;
+}
+
 bool AArch64TTIImpl::isWideningInstruction(Type *DstTy, unsigned Opcode,
                                            ArrayRef<const Value *> Args) {
 
   // A helper that returns a vector type from the given type. The number of
   // elements in type Ty determine the vector width.
   auto toVectorTy = [&](Type *ArgTy) {
     return VectorType::get(ArgTy->getScalarType(),
                            cast<VectorType>(DstTy)->getElementCount());

llvm/test/Transforms/InstCombine/AArch64/demandelts.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -instcombine -mtriple aarch64-none-eabi < %s | FileCheck %s
 
 define <2 x float> @fcvtxn(<2 x double> %d1) {
 ; CHECK-LABEL: @fcvtxn(
-; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x double> [[D1:%.*]], <2 x double> undef, <2 x i32> zeroinitializer
-; CHECK-NEXT:    [[I:%.*]] = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> [[A]])
+; CHECK-NEXT:    [[I:%.*]] = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> [[D1:%.*]])
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <2 x float> [[I]], <2 x float> undef, <2 x i32> <i32 0, i32 undef>
 ; CHECK-NEXT:    ret <2 x float> [[S]]
 ;
   %a = shufflevector <2 x double> %d1, <2 x double> undef, <2 x i32> <i32 0, i32 0>
   %i = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %a)
   %s = shufflevector <2 x float> %i, <2 x float> undef, <2 x i32> <i32 0, i32 undef>
   ret <2 x float> %s
 }
 
 define <4 x i16> @rshrn(<2 x i32> %d1, <2 x i32> %d2) {
 ; CHECK-LABEL: @rshrn(
-; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[A]], i32 9)
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[S]]
 ;
   %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %i = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %a, i32 9)
   %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @sqrshrn(<2 x i32> %d1, <2 x i32> %d2) {
 ; CHECK-LABEL: @sqrshrn(
-; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> [[A]], i32 9)
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[S]]
 ;
   %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %i = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %a, i32 9)
   %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @sqrshrun(<2 x i32> %d1, <2 x i32> %d2) {
 ; CHECK-LABEL: @sqrshrun(
-; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> [[A]], i32 9)
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[S]]
 ;
   %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %i = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %a, i32 9)
   %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @sqshrn(<2 x i32> %d1, <2 x i32> %d2) {
 ; CHECK-LABEL: @sqshrn(
-; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> [[A]], i32 9)
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[S]]
 ;
   %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %i = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %a, i32 9)
   %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @sqshrun(<2 x i32> %d1, <2 x i32> %d2) {
 ; CHECK-LABEL: @sqshrun(
-; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> [[A]], i32 9)
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[S]]
 ;
   %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %i = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %a, i32 9)
   %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @sqxtn(<2 x i32> %d1, <2 x i32> %d2) {
 ; CHECK-LABEL: @sqxtn(
-; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> [[A]])
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[S]]
 ;
   %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %i = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %a)
   %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @sqxtun(<2 x i32> %d1, <2 x i32> %d2) {
 ; CHECK-LABEL: @sqxtun(
-; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> [[A]])
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[S]]
 ;
   %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %i = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %a)
   %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @uqrshrn(<2 x i32> %d1, <2 x i32> %d2) {
 ; CHECK-LABEL: @uqrshrn(
-; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> [[A]], i32 9)
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[S]]
 ;
   %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %i = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %a, i32 9)
   %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @uqshrn(<2 x i32> %d1, <2 x i32> %d2) {
 ; CHECK-LABEL: @uqshrn(
-; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> [[A]], i32 9)
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[S]]
 ;
   %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %i = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %a, i32 9)
   %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   ret <4 x i16> %s
 }
 
 define <4 x i16> @uqxtn(<2 x i32> %d1, <2 x i32> %d2) {
 ; CHECK-LABEL: @uqxtn(
-; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> [[A]])
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[S]]
 ;
   %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %i = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %a)
   %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   ret <4 x i16> %s