[MLIR] Update allocs to memref.allocs in documentation.

[dfki-jugr]

Summary

Changed the remaining appearances of alloc to memref.alloc in several
documentation sections, since they lead to misunderstandings, if they
are used.

[mehdi_amini]

Thanks!

mlir/include/mlir/Dialect/Affine/IR/AffineOps.h

 /// overlap the behavior of this operation is not defined.
 //
 // For example, an AffineDmaStartOp operation that transfers 256 elements of a
 // memref '%src' in memory space 0 at indices [%i + 3, %j] to memref '%dst' in
 // memory space 1 at indices [%k + 7, %l], would be specified as follows:
 //
 //   %num_elements = arith.constant 256
 //   %idx = arith.constant 0 : index
-//   %tag = alloc() : memref<1xi32, 4>
+//   %tag = memref.alloc() : memref<1xi32, 4>
 //   affine.dma_start %src[%i + 3, %j], %dst[%k + 7, %l], %tag[%idx],
 //     %num_elements :
 //       memref<40x128xf32, 0>, memref<2x1024xf32, 1>, memref<1xi32, 2>
 //
 //   If %stride and %num_elt_per_stride are specified, the DMA is expected to
 //   transfer %num_elt_per_stride elements every %stride elements apart from
 //   memory space 0 until %num_elements are transferred.
 //

mlir/include/mlir/Dialect/Affine/Passes.td

let description = [{
     for affine memref accesses and potentially eliminates the entire memref
     if all its accesses are forwarded.
 
     Input
 
     ```mlir
     func @store_load_affine_apply() -> memref<10x10xf32> {
       %cf7 = arith.constant 7.0 : f32
-      %m = alloc() : memref<10x10xf32>
+      %m = memref.alloc() : memref<10x10xf32>
       affine.for %i0 = 0 to 10 {
         affine.for %i1 = 0 to 10 {
           affine.store %cf7, %m[%i0, %i1] : memref<10x10xf32>
           %v0 = affine.load %m[%i0, %i1] : memref<10x10xf32>
           %v1 = arith.addf %v0, %v0 : f32
         }
       }
       return %m : memref<10x10xf32>
     }
     ```
 
     Output
 
     ```mlir
     module {
       func @store_load_affine_apply() -> memref<10x10xf32> {
         %cst = arith.constant 7.000000e+00 : f32
-        %0 = alloc() : memref<10x10xf32>
+        %0 = memref.alloc() : memref<10x10xf32>
         affine.for %arg0 = 0 to 10 {
           affine.for %arg1 = 0 to 10 {
             affine.store %cst, %0[%arg0, %arg1] : memref<10x10xf32>
             %1 = arith.addf %cst, %cst : f32
           }
         }
         return %0 : memref<10x10xf32>
       }

mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td

let description = [{
     ```mlir
     #map0 = affine_map<(d0) -> (d0)>
     module {
       func @condBranch(%arg0: i1, %arg1: memref<2xf32>, %arg2: memref<2xf32>) {
         cond_br %arg0, ^bb1, ^bb2
       ^bb1:
         br ^bb3(%arg1 : memref<2xf32>)
       ^bb2:
-        %0 = alloc() : memref<2xf32>
+        %0 = memref.alloc() : memref<2xf32>
         linalg.generic {
           args_in = 1 : i64,
           args_out = 1 : i64,
           indexing_maps = [#map0, #map0],
           iterator_types = ["parallel"]} %arg1, %0 {
         ^bb0(%gen1_arg0: f32, %gen1_arg1: f32):
           %tmp1 = exp %gen1_arg0 : f32
           linalg.yield %tmp1 : f32
let description = [{
     Output
 
     ```mlir
     #map0 = affine_map<(d0) -> (d0)>
     module {
       func @condBranch(%arg0: i1, %arg1: memref<2xf32>, %arg2: memref<2xf32>) {
         cond_br %arg0, ^bb1, ^bb2
       ^bb1:  // pred: ^bb0
-        %0 = alloc() : memref<2xf32>
+        %0 = memref.alloc() : memref<2xf32>
         linalg.copy(%arg1, %0) : memref<2xf32>, memref<2xf32>
         br ^bb3(%0 : memref<2xf32>)
       ^bb2:  // pred: ^bb0
-        %1 = alloc() : memref<2xf32>
+        %1 = memref.alloc() : memref<2xf32>
         linalg.generic {
           args_in = 1 : i64,
           args_out = 1 : i64,
           indexing_maps = [#map0, #map0],
           iterator_types = ["parallel"]} %arg1, %1 {
         ^bb0(%arg3: f32, %arg4: f32):  // no predecessors
           %4 = exp %arg3 : f32
           linalg.yield %4 : f32
         }: memref<2xf32>, memref<2xf32>
-        %2 = alloc() : memref<2xf32>
+        %2 = memref.alloc() : memref<2xf32>
         linalg.copy(%1, %2) : memref<2xf32>, memref<2xf32>
         dealloc %1 : memref<2xf32>
         br ^bb3(%2 : memref<2xf32>)
       ^bb3(%3: memref<2xf32>):  // 2 preds: ^bb1, ^bb2
         linalg.copy(%3, %arg2) : memref<2xf32>, memref<2xf32>
         dealloc %3 : memref<2xf32>
         return
       }

mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td

let description = [{
 
     For example, a DmaStartOp operation that transfers 256 elements of a memref
     '%src' in memory space 0 at indices [%i, %j] to memref '%dst' in memory
     space 1 at indices [%k, %l], would be specified as follows:
 
     ```mlir
     %num_elements = arith.constant 256
     %idx = arith.constant 0 : index
-    %tag = alloc() : memref<1 x i32, affine_map<(d0) -> (d0)>, 4>
+    %tag = memref.alloc() : memref<1 x i32, affine_map<(d0) -> (d0)>, 4>
     dma_start %src[%i, %j], %dst[%k, %l], %num_elements, %tag[%idx] :
       memref<40 x 128 x f32>, affine_map<(d0) -> (d0)>, 0>,
       memref<2 x 1024 x f32>, affine_map<(d0) -> (d0)>, 1>,
       memref<1 x i32>, affine_map<(d0) -> (d0)>, 2>
     ```
 
     If %stride and %num_elt_per_stride are specified, the DMA is expected to
     transfer %num_elt_per_stride elements every %stride elements apart from
let description = [{
     Stores the contents of a tensor into a memref. The first operand is a value
     of tensor type, the second operand is a value of memref type. The shapes and
     element types of these must match, and are specified by the memref type.
 
     Example:
 
     ```mlir
     %9 = dim %8, 1 : tensor<4x?xf32>
-    %10 = alloc(%9) : memref<4x?xf32, #layout, memspace0>
+    %10 = memref.alloc(%9) : memref<4x?xf32, #layout, memspace0>
     memref.tensor_store %8, %10 : memref<4x?xf32, #layout, memspace0>
     ```
   }];
 
   let arguments = (ins AnyTensor:$tensor, Arg<AnyRankedOrUnrankedMemRef,
                        "the reference to store to", [MemWrite]>:$memref);
   // TensorStoreOp is fully verified by traits.
   let verifier = ?;

mlir/include/mlir/Dialect/Vector/VectorOps.td

let description = [{
 
     ```
     operation ::= `vector.type_cast` ssa-use : memref-type to memref-type
     ```
 
     Example:
 
     ```mlir
-    %A  = alloc() : memref<5x4x3xf32>
+    %A  = memref.alloc() : memref<5x4x3xf32>
     %VA = vector.type_cast %A : memref<5x4x3xf32> to memref<vector<5x4x3xf32>>
     ```
   }];
 
   /// Build the canonical memRefType with a single vector.
   /// E.g. memref<4 x 5 x vector<6 x f32>> -> memref<vector<4 x 5 x 6 x f32>>.
   let builders = [OpBuilder<(ins "Value":$source)>];
 

mlir/include/mlir/Transforms/Passes.td

let description = [{
     benefits are sometimes achieved at the expense of redundant computation
     through a cost model that evaluates available choices such as the depth at
     which a source slice should be materialized in the designation slice.
 
     Example 1: Producer-consumer fusion.
     Input:
     ```mlir
     func @producer_consumer_fusion(%arg0: memref<10xf32>, %arg1: memref<10xf32>) {
-      %0 = alloc() : memref<10xf32>
-      %1 = alloc() : memref<10xf32>
+      %0 = memref.alloc() : memref<10xf32>
+      %1 = memref.alloc() : memref<10xf32>
       %cst = arith.constant 0.000000e+00 : f32
       affine.for %arg2 = 0 to 10 {
         affine.store %cst, %0[%arg2] : memref<10xf32>
         affine.store %cst, %1[%arg2] : memref<10xf32>
       }
       affine.for %arg2 = 0 to 10 {
         %2 = affine.load %0[%arg2] : memref<10xf32>
         %3 = arith.addf %2, %2 : f32
         affine.store %3, %arg0[%arg2] : memref<10xf32>
       }
       affine.for %arg2 = 0 to 10 {
         %2 = affine.load %1[%arg2] : memref<10xf32>
         %3 = arith.mulf %2, %2 : f32
         affine.store %3, %arg1[%arg2] : memref<10xf32>
       }
       return
     }
     ```
     Output:
     ```mlir
     func @producer_consumer_fusion(%arg0: memref<10xf32>, %arg1: memref<10xf32>) {
-      %0 = alloc() : memref<1xf32>
-      %1 = alloc() : memref<1xf32>
+      %0 = memref.alloc() : memref<1xf32>
+      %1 = memref.alloc() : memref<1xf32>
       %cst = arith.constant 0.000000e+00 : f32
       affine.for %arg2 = 0 to 10 {
         affine.store %cst, %0[0] : memref<1xf32>
         affine.store %cst, %1[0] : memref<1xf32>
         %2 = affine.load %1[0] : memref<1xf32>
         %3 = arith.mulf %2, %2 : f32
         affine.store %3, %arg1[%arg2] : memref<10xf32>
         %4 = affine.load %0[0] : memref<1xf32>
let description = [{
     This pass performs a transformation to overlap non-blocking DMA operations
     in a loop with computations through double buffering. This is achieved by
     advancing dma_start operations with respect to other operations.
 
     Input
 
     ```mlir
     func @pipelinedatatransfer() {
-      %0 = alloc() : memref<256xf32>
-      %1 = alloc() : memref<32xf32, 1>
-      %2 = alloc() : memref<1xf32>
+      %0 = memref.alloc() : memref<256xf32>
+      %1 = memref.alloc() : memref<32xf32, 1>
+      %2 = memref.alloc() : memref<1xf32>
       %c0 = arith.constant 0 : index
       %c128 = arith.constant 128 : index
       affine.for %i0 = 0 to 8 {
         affine.dma_start %0[%i0], %1[%i0], %2[%c0], %c128 : memref<256xf32>, memref<32xf32, 1>, memref<1xf32>
         affine.dma_wait %2[%c0], %c128 : memref<1xf32>
         %3 = affine.load %1[%i0] : memref<32xf32, 1>
         %4 = "compute"(%3) : (f32) -> f32
         affine.store %4, %1[%i0] : memref<32xf32, 1>
       }
       return
     }
     ```
 
     Output
 
     ```mlir
     module {
       func @pipelinedatatransfer() {
         %c8 = arith.constant 8 : index
         %c0 = arith.constant 0 : index
-        %0 = alloc() : memref<256xf32>
+        %0 = memref.alloc() : memref<256xf32>
         %c0_0 = arith.constant 0 : index
         %c128 = arith.constant 128 : index
-        %1 = alloc() : memref<2x32xf32, 1>
-        %2 = alloc() : memref<2x1xf32>
+        %1 = memref.alloc() : memref<2x32xf32, 1>
+        %2 = memref.alloc() : memref<2x1xf32>
         affine.dma_start %0[%c0], %1[%c0 mod 2, %c0], %2[%c0 mod 2, symbol(%c0_0)], %c128 : memref<256xf32>, memref<2x32xf32, 1>, memref<2x1xf32>
         affine.for %arg0 = 1 to 8 {
           affine.dma_start %0[%arg0], %1[%arg0 mod 2, %arg0], %2[%arg0 mod 2, symbol(%c0_0)], %c128 : memref<256xf32>, memref<2x32xf32, 1>, memref<2x1xf32>
           %8 = affine.apply #map3(%arg0)
           %9 = affine.apply #map4(%8)
           %10 = affine.apply #map4(%8)
           affine.dma_wait %2[%8 mod 2, symbol(%c0_0)], %c128 : memref<2x1xf32>
           %11 = affine.load %1[%8 mod 2, %8] : memref<2x32xf32, 1>
           %12 = "compute"(%11) : (f32) -> f32
           affine.store %12, %1[%8 mod 2, %8] : memref<2x32xf32, 1>
         }
         %3 = affine.apply #map3(%c8)
         %4 = affine.apply #map4(%3)
         %5 = affine.apply #map4(%3)
         affine.dma_wait %2[%3 mod 2, symbol(%c0_0)], %c128 : memref<2x1xf32>
         %6 = affine.load %1[%3 mod 2, %3] : memref<2x32xf32, 1>
         %7 = "compute"(%6) : (f32) -> f32
         affine.store %7, %1[%3 mod 2, %3] : memref<2x32xf32, 1>
-        dealloc %2 : memref<2x1xf32>
-        dealloc %1 : memref<2x32xf32, 1>
+        memref.dealloc %2 : memref<2x1xf32>
+        memref.dealloc %1 : memref<2x32xf32, 1>
         return
       }
     }
     ```
   }];
   let constructor = "mlir::createPipelineDataTransferPass()";
 }
 
let description = [{
     #tile = affine_map<(i) -> (i floordiv 4, i mod 4)>
     func @matmul(%A: memref<16xf64, #tile>,
                  %B: index, %C: memref<16xf64>) -> (memref<16xf64, #tile>) {
       affine.for %arg3 = 0 to 16 {
             %a = affine.load %A[%arg3] : memref<16xf64, #tile>
             %p = arith.mulf %a, %a : f64
             affine.store %p, %A[%arg3] : memref<16xf64, #tile>
       }
-      %c = alloc() : memref<16xf64, #tile>
+      %c = memref.alloc() : memref<16xf64, #tile>
       %d = affine.load %c[0] : memref<16xf64, #tile>
       return %A: memref<16xf64, #tile>
     }
     ```
 
     Output
 
     ```mlir
     func @matmul(%arg0: memref<4x4xf64>, %arg1: index, %arg2: memref<16xf64>)
       -> memref<4x4xf64> {
       affine.for %arg3 = 0 to 16 {
         %3 = affine.load %arg0[%arg3 floordiv 4, %arg3 mod 4]: memref<4x4xf64>
         %4 = arith.mulf %3, %3 : f64
         affine.store %4, %arg0[%arg3 floordiv 4, %arg3 mod 4]: memref<4x4xf64>
       }
-      %0 = alloc() : memref<4x4xf64>
+      %0 = memref.alloc() : memref<4x4xf64>
       %1 = affine.apply #map1()
       %2 = affine.load %0[0, 0] : memref<4x4xf64>
       return %arg0 : memref<4x4xf64>
     }
     ```
 
     Input
 

mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp

 /// The -affine-vectorize pass with the following arguments:
 /// ```
 /// -affine-vectorize="virtual-vector-size=256 test-fastest-varying=0"
 /// ```
 ///
 /// produces this standard innermost-loop vectorized code:
 /// ```mlir
 /// func @vector_add_2d(%arg0 : index, %arg1 : index) -> f32 {
-///   %0 = alloc(%arg0, %arg1) : memref<?x?xf32>
-///   %1 = alloc(%arg0, %arg1) : memref<?x?xf32>
-///   %2 = alloc(%arg0, %arg1) : memref<?x?xf32>
+///   %0 = memref.alloc(%arg0, %arg1) : memref<?x?xf32>
+///   %1 = memref.alloc(%arg0, %arg1) : memref<?x?xf32>
+///   %2 = memref.alloc(%arg0, %arg1) : memref<?x?xf32>
 ///   %cst = arith.constant 1.0 : f32
 ///   %cst_0 = arith.constant 2.0 : f32
 ///   affine.for %i0 = 0 to %arg0 {
 ///     affine.for %i1 = 0 to %arg1 step 256 {
 ///       %cst_1 = arith.constant dense<vector<256xf32>, 1.0> :
 ///                vector<256xf32>
 ///       vector.transfer_write %cst_1, %0[%i0, %i1] :
 ///                vector<256xf32>, memref<?x?xf32>

 /// The -affine-vectorize pass with the following arguments:
 /// ```
 /// -affine-vectorize="virtual-vector-size=32,256 test-fastest-varying=1,0"
 /// ```
 ///
 /// produces this more interesting mixed outer-innermost-loop vectorized code:
 /// ```mlir
 /// func @vector_add_2d(%arg0 : index, %arg1 : index) -> f32 {
-///   %0 = alloc(%arg0, %arg1) : memref<?x?xf32>
-///   %1 = alloc(%arg0, %arg1) : memref<?x?xf32>
-///   %2 = alloc(%arg0, %arg1) : memref<?x?xf32>
+///   %0 = memref.alloc(%arg0, %arg1) : memref<?x?xf32>
+///   %1 = memref.alloc(%arg0, %arg1) : memref<?x?xf32>
+///   %2 = memref.alloc(%arg0, %arg1) : memref<?x?xf32>
 ///   %cst = arith.constant 1.0 : f32
 ///   %cst_0 = arith.constant 2.0 : f32
 ///   affine.for %i0 = 0 to %arg0 step 32 {
 ///     affine.for %i1 = 0 to %arg1 step 256 {
 ///       %cst_1 = arith.constant dense<vector<32x256xf32>, 1.0> :
 ///                vector<32x256xf32>
 ///       vector.transfer_write %cst_1, %0[%i0, %i1] :
 ///                vector<32x256xf32>, memref<?x?xf32>