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Differential D115483

[RISCV] Convert (splat_vector (load)) to vlse with 0 stride.
ClosedPublic

Authored by craig.topper on Dec 9 2021, 4:56 PM.

Details

Reviewers
frasercrmck
rogfer01
Commits
rG7598ac5ec5a6: [RISCV] Convert (splat_vector (load)) to vlse with 0 stride.
Summary

We already do this for splat nodes that carry a VL, but not for
splats that use VLMAX.

Diff Detail

Event Timeline

craig.topper created this revision.Dec 9 2021, 4:56 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 25 others. · View Herald TranscriptDec 9 2021, 4:56 PM
craig.topper requested review of this revision.Dec 9 2021, 4:56 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 9 2021, 4:56 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B138564: Diff 393337.Dec 9 2021, 6:02 PM
frasercrmck accepted this revision.Dec 14 2021, 12:28 AM

LGTM

This revision is now accepted and ready to land.Dec 14 2021, 12:28 AM
This revision was landed with ongoing or failed builds.Dec 14 2021, 9:17 AM
Closed by commit rG7598ac5ec5a6: [RISCV] Convert (splat_vector (load)) to vlse with 0 stride. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG7598ac5ec5a6: [RISCV] Convert (splat_vector (load)) to vlse with 0 stride..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
6 lines
test/
CodeGen/
RISCV/
rvv/
517 lines
282 lines

Diff 393337

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

//===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===// //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===//
Lint: Lint
Inline Actions

clang-format not found in user’s local PATH; not linting file.

Lint: Lint: clang-format not found in user’s local PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 1,501 Lines • ▼ Show 20 Lines if (SubRegIdx == RISCV::NoSubRegister) {
ReplaceNode(Node, NewNode); ReplaceNode(Node, NewNode);
return; return;
} }
SDValue Extract = CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, V); SDValue Extract = CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, V);
ReplaceNode(Node, Extract.getNode()); ReplaceNode(Node, Extract.getNode());
return; return;
} }
case ISD::SPLAT_VECTOR:
case RISCVISD::VMV_V_X_VL: case RISCVISD::VMV_V_X_VL:
case RISCVISD::VFMV_V_F_VL: { case RISCVISD::VFMV_V_F_VL: {
// Try to match splat of a scalar load to a strided load with stride of x0. // Try to match splat of a scalar load to a strided load with stride of x0.
SDValue Src = Node->getOperand(0); SDValue Src = Node->getOperand(0);
auto *Ld = dyn_cast<LoadSDNode>(Src); auto *Ld = dyn_cast<LoadSDNode>(Src);
if (!Ld) if (!Ld)
break; break;
EVT MemVT = Ld->getMemoryVT(); EVT MemVT = Ld->getMemoryVT();
// The memory VT should be the same size as the element type. // The memory VT should be the same size as the element type.
if (MemVT.getStoreSize() != VT.getVectorElementType().getStoreSize()) if (MemVT.getStoreSize() != VT.getVectorElementType().getStoreSize())
break; break;
if (!IsProfitableToFold(Src, Node, Node) || if (!IsProfitableToFold(Src, Node, Node) ||
!IsLegalToFold(Src, Node, Node, TM.getOptLevel())) !IsLegalToFold(Src, Node, Node, TM.getOptLevel()))
break; break;
SDValue VL; SDValue VL;
if (Node->getOpcode() == ISD::SPLAT_VECTOR)
VL = CurDAG->getTargetConstant(RISCV::VLMaxSentinel, DL, XLenVT);
else
selectVLOp(Node->getOperand(1), VL); selectVLOp(Node->getOperand(1), VL);
unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits());
SDValue SEW = CurDAG->getTargetConstant(Log2SEW, DL, XLenVT); SDValue SEW = CurDAG->getTargetConstant(Log2SEW, DL, XLenVT);
SDValue Operands[] = {Ld->getBasePtr(), SDValue Operands[] = {Ld->getBasePtr(),
CurDAG->getRegister(RISCV::X0, XLenVT), VL, SEW, CurDAG->getRegister(RISCV::X0, XLenVT), VL, SEW,
Ld->getChain()}; Ld->getChain()};
▲ Show 20 Lines • Show All 486 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>) declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>)
define half @vreduce_fadd_v1f16(<1 x half>* %x, half %s) { define half @vreduce_fadd_v1f16(<1 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v1f16: ; CHECK-LABEL: vreduce_fadd_v1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
Show All 21 Lines; CHECK-NEXT: ret
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>) declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>)
define half @vreduce_fadd_v2f16(<2 x half>* %x, half %s) { define half @vreduce_fadd_v2f16(<2 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v2f16: ; CHECK-LABEL: vreduce_fadd_v2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI2_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI2_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x %v = load <2 x half>, <2 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
ret half %red ret half %red
Show All 15 Lines; CHECK-NEXT: ret
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>) declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>)
define half @vreduce_fadd_v4f16(<4 x half>* %x, half %s) { define half @vreduce_fadd_v4f16(<4 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v4f16: ; CHECK-LABEL: vreduce_fadd_v4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI4_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI4_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x %v = load <4 x half>, <4 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
ret half %red ret half %red
Show All 15 Lines; CHECK-NEXT: ret
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>) declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>)
define half @vreduce_fadd_v8f16(<8 x half>* %x, half %s) { define half @vreduce_fadd_v8f16(<8 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v8f16: ; CHECK-LABEL: vreduce_fadd_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI6_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI6_0)(a1)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI6_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x half>, <8 x half>* %x %v = load <8 x half>, <8 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)
ret half %red ret half %red
Show All 15 Lines; CHECK-NEXT: ret
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.v16f16(half, <16 x half>) declare half @llvm.vector.reduce.fadd.v16f16(half, <16 x half>)
define half @vreduce_fadd_v16f16(<16 x half>* %x, half %s) { define half @vreduce_fadd_v16f16(<16 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v16f16: ; CHECK-LABEL: vreduce_fadd_v16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI8_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI8_0)(a1)
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI8_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v10, (a0), zero
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v10 ; CHECK-NEXT: vfredusum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <16 x half>, <16 x half>* %x %v = load <16 x half>, <16 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
ret half %red ret half %red
Show All 13 Lines; CHECK-NEXT: ret
%v = load <16 x half>, <16 x half>* %x %v = load <16 x half>, <16 x half>* %x
%red = call half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v) %red = call half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.v32f16(half, <32 x half>) declare half @llvm.vector.reduce.fadd.v32f16(half, <32 x half>)
define half @vreduce_fadd_v32f16(<32 x half>* %x, half %s) { define half @vreduce_fadd_v32f16(<32 x half>* %x, half %s) {
; RV32-LABEL: vreduce_fadd_v32f16: ; CHECK-LABEL: vreduce_fadd_v32f16:
; RV32: # %bb.0: ; CHECK: # %bb.0:
; RV32-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; RV32-NEXT: lui a2, %hi(.LCPI10_0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; RV32-NEXT: flh ft0, %lo(.LCPI10_0)(a2) ; CHECK-NEXT: vle16.v v8, (a0)
; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; RV32-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_0)
; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
; RV32-NEXT: vfmv.v.f v12, ft0 ; CHECK-NEXT: vlse16.v v12, (a0), zero
; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; RV32-NEXT: vfredusum.vs v8, v8, v12 ; CHECK-NEXT: vfredusum.vs v8, v8, v12
; RV32-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; RV32-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, ft0
; RV32-NEXT: ret ; CHECK-NEXT: ret
;
; RV64-LABEL: vreduce_fadd_v32f16:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, %hi(.LCPI10_0)
; RV64-NEXT: flh ft0, %lo(.LCPI10_0)(a1)
; RV64-NEXT: li a1, 32
; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; RV64-NEXT: vfmv.v.f v12, ft0
; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; RV64-NEXT: vfredusum.vs v8, v8, v12
; RV64-NEXT: vfmv.f.s ft0, v8
; RV64-NEXT: fadd.h fa0, fa0, ft0
; RV64-NEXT: ret
%v = load <32 x half>, <32 x half>* %x %v = load <32 x half>, <32 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_v32f16(<32 x half>* %x, half %s) { define half @vreduce_ord_fadd_v32f16(<32 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v32f16: ; CHECK-LABEL: vreduce_ord_fadd_v32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 9 Lines; CHECK-NEXT: ret
%v = load <32 x half>, <32 x half>* %x %v = load <32 x half>, <32 x half>* %x
%red = call half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v) %red = call half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.v64f16(half, <64 x half>) declare half @llvm.vector.reduce.fadd.v64f16(half, <64 x half>)
define half @vreduce_fadd_v64f16(<64 x half>* %x, half %s) { define half @vreduce_fadd_v64f16(<64 x half>* %x, half %s) {
; RV32-LABEL: vreduce_fadd_v64f16: ; CHECK-LABEL: vreduce_fadd_v64f16:
; RV32: # %bb.0: ; CHECK: # %bb.0:
; RV32-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; RV32-NEXT: lui a2, %hi(.LCPI12_0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; RV32-NEXT: flh ft0, %lo(.LCPI12_0)(a2) ; CHECK-NEXT: vle16.v v8, (a0)
; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI12_0)
; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
; RV32-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vlse16.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; RV32-NEXT: vfredusum.vs v8, v8, v16 ; CHECK-NEXT: vfredusum.vs v8, v8, v16
; RV32-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; RV32-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, ft0
; RV32-NEXT: ret ; CHECK-NEXT: ret
;
; RV64-LABEL: vreduce_fadd_v64f16:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, %hi(.LCPI12_0)
; RV64-NEXT: flh ft0, %lo(.LCPI12_0)(a1)
; RV64-NEXT: li a1, 64
; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; RV64-NEXT: vle16.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; RV64-NEXT: vfmv.v.f v16, ft0
; RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; RV64-NEXT: vfredusum.vs v8, v8, v16
; RV64-NEXT: vfmv.f.s ft0, v8
; RV64-NEXT: fadd.h fa0, fa0, ft0
; RV64-NEXT: ret
%v = load <64 x half>, <64 x half>* %x %v = load <64 x half>, <64 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_ord_fadd_v64f16(<64 x half>* %x, half %s) { define half @vreduce_ord_fadd_v64f16(<64 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v64f16: ; CHECK-LABEL: vreduce_ord_fadd_v64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 16 Lines
define half @vreduce_fadd_v128f16(<128 x half>* %x, half %s) { define half @vreduce_fadd_v128f16(<128 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v128f16: ; CHECK-LABEL: vreduce_fadd_v128f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: vfadd.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI14_0)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16 ; CHECK-NEXT: vfredusum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <128 x half>, <128 x half>* %x %v = load <128 x half>, <128 x half>* %x
%red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
ret half %red ret half %red
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>) declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>)
define float @vreduce_fadd_v2f32(<2 x float>* %x, float %s) { define float @vreduce_fadd_v2f32(<2 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v2f32: ; CHECK-LABEL: vreduce_fadd_v2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI18_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI18_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI18_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI18_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <2 x float>, <2 x float>* %x %v = load <2 x float>, <2 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
ret float %red ret float %red
Show All 15 Lines; CHECK-NEXT: ret
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>) declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)
define float @vreduce_fadd_v4f32(<4 x float>* %x, float %s) { define float @vreduce_fadd_v4f32(<4 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v4f32: ; CHECK-LABEL: vreduce_fadd_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI20_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI20_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI20_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI20_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x %v = load <4 x float>, <4 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
ret float %red ret float %red
Show All 15 Lines; CHECK-NEXT: ret
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>) declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>)
define float @vreduce_fadd_v8f32(<8 x float>* %x, float %s) { define float @vreduce_fadd_v8f32(<8 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v8f32: ; CHECK-LABEL: vreduce_fadd_v8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI22_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI22_0)(a1)
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI22_0)
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI22_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v10, (a0), zero
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v10 ; CHECK-NEXT: vfredusum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x float>, <8 x float>* %x %v = load <8 x float>, <8 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)
ret float %red ret float %red
Show All 15 Lines; CHECK-NEXT: ret
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fadd.v16f32(float, <16 x float>) declare float @llvm.vector.reduce.fadd.v16f32(float, <16 x float>)
define float @vreduce_fadd_v16f32(<16 x float>* %x, float %s) { define float @vreduce_fadd_v16f32(<16 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v16f32: ; CHECK-LABEL: vreduce_fadd_v16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI24_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI24_0)(a1)
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI24_0)
; CHECK-NEXT: vfmv.v.f v12, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI24_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v12, (a0), zero
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v12 ; CHECK-NEXT: vfredusum.vs v8, v8, v12
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <16 x float>, <16 x float>* %x %v = load <16 x float>, <16 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)
ret float %red ret float %red
Show All 13 Lines; CHECK-NEXT: ret
%v = load <16 x float>, <16 x float>* %x %v = load <16 x float>, <16 x float>* %x
%red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v) %red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fadd.v32f32(float, <32 x float>) declare float @llvm.vector.reduce.fadd.v32f32(float, <32 x float>)
define float @vreduce_fadd_v32f32(<32 x float>* %x, float %s) { define float @vreduce_fadd_v32f32(<32 x float>* %x, float %s) {
; RV32-LABEL: vreduce_fadd_v32f32: ; CHECK-LABEL: vreduce_fadd_v32f32:
; RV32: # %bb.0: ; CHECK: # %bb.0:
; RV32-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; RV32-NEXT: lui a2, %hi(.LCPI26_0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV32-NEXT: flw ft0, %lo(.LCPI26_0)(a2) ; CHECK-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI26_0)
; RV32-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI26_0)
; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
; RV32-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: vlse32.v v16, (a0), zero
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV32-NEXT: vfredusum.vs v8, v8, v16 ; CHECK-NEXT: vfredusum.vs v8, v8, v16
; RV32-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; RV32-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, ft0
; RV32-NEXT: ret ; CHECK-NEXT: ret
;
; RV64-LABEL: vreduce_fadd_v32f32:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, %hi(.LCPI26_0)
; RV64-NEXT: flw ft0, %lo(.LCPI26_0)(a1)
; RV64-NEXT: li a1, 32
; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; RV64-NEXT: vfmv.v.f v16, ft0
; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV64-NEXT: vfredusum.vs v8, v8, v16
; RV64-NEXT: vfmv.f.s ft0, v8
; RV64-NEXT: fadd.s fa0, fa0, ft0
; RV64-NEXT: ret
%v = load <32 x float>, <32 x float>* %x %v = load <32 x float>, <32 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_ord_fadd_v32f32(<32 x float>* %x, float %s) { define float @vreduce_ord_fadd_v32f32(<32 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v32f32: ; CHECK-LABEL: vreduce_ord_fadd_v32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 16 Lines
define float @vreduce_fadd_v64f32(<64 x float>* %x, float %s) { define float @vreduce_fadd_v64f32(<64 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v64f32: ; CHECK-LABEL: vreduce_fadd_v64f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle32.v v16, (a0) ; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI28_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI28_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: vfadd.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI28_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI28_0)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16 ; CHECK-NEXT: vfredusum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <64 x float>, <64 x float>* %x %v = load <64 x float>, <64 x float>* %x
%red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
ret float %red ret float %red
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>) declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>)
define double @vreduce_fadd_v2f64(<2 x double>* %x, double %s) { define double @vreduce_fadd_v2f64(<2 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_fadd_v2f64: ; CHECK-LABEL: vreduce_fadd_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI32_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI32_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI32_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI32_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <2 x double>, <2 x double>* %x %v = load <2 x double>, <2 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v)
ret double %red ret double %red
Show All 15 Lines; CHECK-NEXT: ret
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fadd.v4f64(double, <4 x double>) declare double @llvm.vector.reduce.fadd.v4f64(double, <4 x double>)
define double @vreduce_fadd_v4f64(<4 x double>* %x, double %s) { define double @vreduce_fadd_v4f64(<4 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_fadd_v4f64: ; CHECK-LABEL: vreduce_fadd_v4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI34_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI34_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI34_0)
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI34_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v10 ; CHECK-NEXT: vfredusum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x %v = load <4 x double>, <4 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)
ret double %red ret double %red
Show All 15 Lines; CHECK-NEXT: ret
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fadd.v8f64(double, <8 x double>) declare double @llvm.vector.reduce.fadd.v8f64(double, <8 x double>)
define double @vreduce_fadd_v8f64(<8 x double>* %x, double %s) { define double @vreduce_fadd_v8f64(<8 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_fadd_v8f64: ; CHECK-LABEL: vreduce_fadd_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI36_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI36_0)(a1)
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI36_0)
; CHECK-NEXT: vfmv.v.f v12, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI36_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v12 ; CHECK-NEXT: vfredusum.vs v8, v8, v12
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <8 x double>, <8 x double>* %x %v = load <8 x double>, <8 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)
ret double %red ret double %red
Show All 15 Lines; CHECK-NEXT: ret
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fadd.v16f64(double, <16 x double>) declare double @llvm.vector.reduce.fadd.v16f64(double, <16 x double>)
define double @vreduce_fadd_v16f64(<16 x double>* %x, double %s) { define double @vreduce_fadd_v16f64(<16 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_fadd_v16f64: ; CHECK-LABEL: vreduce_fadd_v16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI38_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI38_0)(a1)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI38_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI38_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16 ; CHECK-NEXT: vfredusum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <16 x double>, <16 x double>* %x %v = load <16 x double>, <16 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)
ret double %red ret double %red
Show All 19 Lines
define double @vreduce_fadd_v32f64(<32 x double>* %x, double %s) { define double @vreduce_fadd_v32f64(<32 x double>* %x, double %s) {
; CHECK-LABEL: vreduce_fadd_v32f64: ; CHECK-LABEL: vreduce_fadd_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle64.v v16, (a0) ; CHECK-NEXT: vle64.v v16, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI40_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI40_0)(a0)
; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: vfadd.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI40_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI40_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v16 ; CHECK-NEXT: vfredusum.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x double>, <32 x double>* %x %v = load <32 x double>, <32 x double>* %x
%red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
ret double %red ret double %red
Show All 22 Lines; CHECK-NEXT: ret
ret double %red ret double %red
} }
declare half @llvm.vector.reduce.fmin.v2f16(<2 x half>) declare half @llvm.vector.reduce.fmin.v2f16(<2 x half>)
define half @vreduce_fmin_v2f16(<2 x half>* %x) { define half @vreduce_fmin_v2f16(<2 x half>* %x) {
; CHECK-LABEL: vreduce_fmin_v2f16: ; CHECK-LABEL: vreduce_fmin_v2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI42_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI42_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI42_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI42_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x %v = load <2 x half>, <2 x half>* %x
%red = call half @llvm.vector.reduce.fmin.v2f16(<2 x half> %v) %red = call half @llvm.vector.reduce.fmin.v2f16(<2 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>) declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)
define half @vreduce_fmin_v4f16(<4 x half>* %x) { define half @vreduce_fmin_v4f16(<4 x half>* %x) {
; CHECK-LABEL: vreduce_fmin_v4f16: ; CHECK-LABEL: vreduce_fmin_v4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI43_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI43_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI43_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI43_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x %v = load <4 x half>, <4 x half>* %x
%red = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v) %red = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_fmin_v4f16_nonans(<4 x half>* %x) { define half @vreduce_fmin_v4f16_nonans(<4 x half>* %x) {
; CHECK-LABEL: vreduce_fmin_v4f16_nonans: ; CHECK-LABEL: vreduce_fmin_v4f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI44_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI44_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI44_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI44_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x %v = load <4 x half>, <4 x half>* %x
%red = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v) %red = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_fmin_v4f16_nonans_noinfs(<4 x half>* %x) { define half @vreduce_fmin_v4f16_nonans_noinfs(<4 x half>* %x) {
; CHECK-LABEL: vreduce_fmin_v4f16_nonans_noinfs: ; CHECK-LABEL: vreduce_fmin_v4f16_nonans_noinfs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI45_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI45_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI45_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI45_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x %v = load <4 x half>, <4 x half>* %x
%red = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v) %red = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fmin.v128f16(<128 x half>) declare half @llvm.vector.reduce.fmin.v128f16(<128 x half>)
define half @vreduce_fmin_v128f16(<128 x half>* %x) { define half @vreduce_fmin_v128f16(<128 x half>* %x) {
; CHECK-LABEL: vreduce_fmin_v128f16: ; CHECK-LABEL: vreduce_fmin_v128f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI46_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI46_0)(a0)
; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI46_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI46_0)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v16 ; CHECK-NEXT: vfredmin.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <128 x half>, <128 x half>* %x %v = load <128 x half>, <128 x half>* %x
%red = call half @llvm.vector.reduce.fmin.v128f16(<128 x half> %v) %red = call half @llvm.vector.reduce.fmin.v128f16(<128 x half> %v)
ret half %red ret half %red
} }
declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>) declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)
define float @vreduce_fmin_v2f32(<2 x float>* %x) { define float @vreduce_fmin_v2f32(<2 x float>* %x) {
; CHECK-LABEL: vreduce_fmin_v2f32: ; CHECK-LABEL: vreduce_fmin_v2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI47_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI47_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI47_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI47_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <2 x float>, <2 x float>* %x %v = load <2 x float>, <2 x float>* %x
%red = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %v) %red = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %v)
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>) declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
define float @vreduce_fmin_v4f32(<4 x float>* %x) { define float @vreduce_fmin_v4f32(<4 x float>* %x) {
; CHECK-LABEL: vreduce_fmin_v4f32: ; CHECK-LABEL: vreduce_fmin_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI48_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI48_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI48_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI48_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x %v = load <4 x float>, <4 x float>* %x
%red = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v) %red = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_fmin_v4f32_nonans(<4 x float>* %x) { define float @vreduce_fmin_v4f32_nonans(<4 x float>* %x) {
; CHECK-LABEL: vreduce_fmin_v4f32_nonans: ; CHECK-LABEL: vreduce_fmin_v4f32_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI49_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI49_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI49_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI49_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x %v = load <4 x float>, <4 x float>* %x
%red = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v) %red = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_fmin_v4f32_nonans_noinfs(<4 x float>* %x) { define float @vreduce_fmin_v4f32_nonans_noinfs(<4 x float>* %x) {
; CHECK-LABEL: vreduce_fmin_v4f32_nonans_noinfs: ; CHECK-LABEL: vreduce_fmin_v4f32_nonans_noinfs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI50_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI50_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI50_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI50_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x %v = load <4 x float>, <4 x float>* %x
%red = call nnan ninf float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v) %red = call nnan ninf float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fmin.v128f32(<128 x float>) declare float @llvm.vector.reduce.fmin.v128f32(<128 x float>)
define float @vreduce_fmin_v128f32(<128 x float>* %x) { define float @vreduce_fmin_v128f32(<128 x float>* %x) {
; CHECK-LABEL: vreduce_fmin_v128f32: ; CHECK-LABEL: vreduce_fmin_v128f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a2, a0, 384 ; CHECK-NEXT: addi a2, a0, 384
; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: addi a2, a0, 128
; CHECK-NEXT: vle32.v v16, (a2) ; CHECK-NEXT: vle32.v v16, (a2)
; CHECK-NEXT: addi a2, a0, 256
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: addi a0, a0, 256 ; CHECK-NEXT: vle32.v v0, (a2)
; CHECK-NEXT: vle32.v v0, (a0) ; CHECK-NEXT: vfmin.vv v16, v24, v16
; CHECK-NEXT: vfmin.vv v8, v16, v8 ; CHECK-NEXT: vfmin.vv v8, v8, v0
; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: lui a0, %hi(.LCPI51_0) ; CHECK-NEXT: lui a0, %hi(.LCPI51_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI51_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI51_0)
; CHECK-NEXT: vfmin.vv v16, v24, v0 ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmin.vv v8, v16, v8 ; CHECK-NEXT: vlse32.v v16, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v16 ; CHECK-NEXT: vfredmin.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <128 x float>, <128 x float>* %x %v = load <128 x float>, <128 x float>* %x
%red = call float @llvm.vector.reduce.fmin.v128f32(<128 x float> %v) %red = call float @llvm.vector.reduce.fmin.v128f32(<128 x float> %v)
ret float %red ret float %red
} }
declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>) declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
define double @vreduce_fmin_v2f64(<2 x double>* %x) { define double @vreduce_fmin_v2f64(<2 x double>* %x) {
; CHECK-LABEL: vreduce_fmin_v2f64: ; CHECK-LABEL: vreduce_fmin_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI52_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI52_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI52_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI52_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <2 x double>, <2 x double>* %x %v = load <2 x double>, <2 x double>* %x
%red = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %v) %red = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %v)
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fmin.v4f64(<4 x double>) declare double @llvm.vector.reduce.fmin.v4f64(<4 x double>)
define double @vreduce_fmin_v4f64(<4 x double>* %x) { define double @vreduce_fmin_v4f64(<4 x double>* %x) {
; CHECK-LABEL: vreduce_fmin_v4f64: ; CHECK-LABEL: vreduce_fmin_v4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI53_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI53_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI53_0)
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI53_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v10 ; CHECK-NEXT: vfredmin.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x %v = load <4 x double>, <4 x double>* %x
%red = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v) %red = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_fmin_v4f64_nonans(<4 x double>* %x) { define double @vreduce_fmin_v4f64_nonans(<4 x double>* %x) {
; CHECK-LABEL: vreduce_fmin_v4f64_nonans: ; CHECK-LABEL: vreduce_fmin_v4f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI54_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI54_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI54_0)
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI54_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v10 ; CHECK-NEXT: vfredmin.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x %v = load <4 x double>, <4 x double>* %x
%red = call nnan double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v) %red = call nnan double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_fmin_v4f64_nonans_noinfs(<4 x double>* %x) { define double @vreduce_fmin_v4f64_nonans_noinfs(<4 x double>* %x) {
; CHECK-LABEL: vreduce_fmin_v4f64_nonans_noinfs: ; CHECK-LABEL: vreduce_fmin_v4f64_nonans_noinfs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI55_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI55_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI55_0)
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI55_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v10 ; CHECK-NEXT: vfredmin.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x %v = load <4 x double>, <4 x double>* %x
%red = call nnan ninf double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v) %red = call nnan ninf double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fmin.v32f64(<32 x double>) declare double @llvm.vector.reduce.fmin.v32f64(<32 x double>)
define double @vreduce_fmin_v32f64(<32 x double>* %x) { define double @vreduce_fmin_v32f64(<32 x double>* %x) {
; CHECK-LABEL: vreduce_fmin_v32f64: ; CHECK-LABEL: vreduce_fmin_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle64.v v16, (a0) ; CHECK-NEXT: vle64.v v16, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI56_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI56_0)(a0)
; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI56_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI56_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v16 ; CHECK-NEXT: vfredmin.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x double>, <32 x double>* %x %v = load <32 x double>, <32 x double>* %x
%red = call double @llvm.vector.reduce.fmin.v32f64(<32 x double> %v) %red = call double @llvm.vector.reduce.fmin.v32f64(<32 x double> %v)
ret double %red ret double %red
} }
declare half @llvm.vector.reduce.fmax.v2f16(<2 x half>) declare half @llvm.vector.reduce.fmax.v2f16(<2 x half>)
define half @vreduce_fmax_v2f16(<2 x half>* %x) { define half @vreduce_fmax_v2f16(<2 x half>* %x) {
; CHECK-LABEL: vreduce_fmax_v2f16: ; CHECK-LABEL: vreduce_fmax_v2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI57_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI57_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI57_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI57_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x %v = load <2 x half>, <2 x half>* %x
%red = call half @llvm.vector.reduce.fmax.v2f16(<2 x half> %v) %red = call half @llvm.vector.reduce.fmax.v2f16(<2 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fmax.v4f16(<4 x half>) declare half @llvm.vector.reduce.fmax.v4f16(<4 x half>)
define half @vreduce_fmax_v4f16(<4 x half>* %x) { define half @vreduce_fmax_v4f16(<4 x half>* %x) {
; CHECK-LABEL: vreduce_fmax_v4f16: ; CHECK-LABEL: vreduce_fmax_v4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI58_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI58_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI58_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI58_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x %v = load <4 x half>, <4 x half>* %x
%red = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v) %red = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_fmax_v4f16_nonans(<4 x half>* %x) { define half @vreduce_fmax_v4f16_nonans(<4 x half>* %x) {
; CHECK-LABEL: vreduce_fmax_v4f16_nonans: ; CHECK-LABEL: vreduce_fmax_v4f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI59_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI59_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI59_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI59_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x %v = load <4 x half>, <4 x half>* %x
%red = call nnan half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v) %red = call nnan half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_fmax_v4f16_nonans_noinfs(<4 x half>* %x) { define half @vreduce_fmax_v4f16_nonans_noinfs(<4 x half>* %x) {
; CHECK-LABEL: vreduce_fmax_v4f16_nonans_noinfs: ; CHECK-LABEL: vreduce_fmax_v4f16_nonans_noinfs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI60_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI60_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI60_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI60_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x %v = load <4 x half>, <4 x half>* %x
%red = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v) %red = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fmax.v128f16(<128 x half>) declare half @llvm.vector.reduce.fmax.v128f16(<128 x half>)
define half @vreduce_fmax_v128f16(<128 x half>* %x) { define half @vreduce_fmax_v128f16(<128 x half>* %x) {
; CHECK-LABEL: vreduce_fmax_v128f16: ; CHECK-LABEL: vreduce_fmax_v128f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle16.v v16, (a0) ; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI61_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI61_0)(a0)
; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI61_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI61_0)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v16, (a0), zero
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v16 ; CHECK-NEXT: vfredmax.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <128 x half>, <128 x half>* %x %v = load <128 x half>, <128 x half>* %x
%red = call half @llvm.vector.reduce.fmax.v128f16(<128 x half> %v) %red = call half @llvm.vector.reduce.fmax.v128f16(<128 x half> %v)
ret half %red ret half %red
} }
declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>) declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>)
define float @vreduce_fmax_v2f32(<2 x float>* %x) { define float @vreduce_fmax_v2f32(<2 x float>* %x) {
; CHECK-LABEL: vreduce_fmax_v2f32: ; CHECK-LABEL: vreduce_fmax_v2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI62_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI62_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI62_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI62_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <2 x float>, <2 x float>* %x %v = load <2 x float>, <2 x float>* %x
%red = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %v) %red = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %v)
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>) declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
define float @vreduce_fmax_v4f32(<4 x float>* %x) { define float @vreduce_fmax_v4f32(<4 x float>* %x) {
; CHECK-LABEL: vreduce_fmax_v4f32: ; CHECK-LABEL: vreduce_fmax_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI63_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI63_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI63_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI63_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x %v = load <4 x float>, <4 x float>* %x
%red = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v) %red = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_fmax_v4f32_nonans(<4 x float>* %x) { define float @vreduce_fmax_v4f32_nonans(<4 x float>* %x) {
; CHECK-LABEL: vreduce_fmax_v4f32_nonans: ; CHECK-LABEL: vreduce_fmax_v4f32_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI64_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI64_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI64_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI64_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x %v = load <4 x float>, <4 x float>* %x
%red = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v) %red = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_fmax_v4f32_nonans_noinfs(<4 x float>* %x) { define float @vreduce_fmax_v4f32_nonans_noinfs(<4 x float>* %x) {
; CHECK-LABEL: vreduce_fmax_v4f32_nonans_noinfs: ; CHECK-LABEL: vreduce_fmax_v4f32_nonans_noinfs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI65_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI65_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI65_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI65_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x float>, <4 x float>* %x %v = load <4 x float>, <4 x float>* %x
%red = call nnan ninf float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v) %red = call nnan ninf float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fmax.v128f32(<128 x float>) declare float @llvm.vector.reduce.fmax.v128f32(<128 x float>)
define float @vreduce_fmax_v128f32(<128 x float>* %x) { define float @vreduce_fmax_v128f32(<128 x float>* %x) {
; CHECK-LABEL: vreduce_fmax_v128f32: ; CHECK-LABEL: vreduce_fmax_v128f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32 ; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: addi a2, a0, 384 ; CHECK-NEXT: addi a2, a0, 384
; CHECK-NEXT: vle32.v v8, (a2)
; CHECK-NEXT: addi a2, a0, 128
; CHECK-NEXT: vle32.v v16, (a2) ; CHECK-NEXT: vle32.v v16, (a2)
; CHECK-NEXT: addi a2, a0, 256
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: addi a0, a0, 256 ; CHECK-NEXT: vle32.v v0, (a2)
; CHECK-NEXT: vle32.v v0, (a0) ; CHECK-NEXT: vfmax.vv v16, v24, v16
; CHECK-NEXT: vfmax.vv v8, v16, v8 ; CHECK-NEXT: vfmax.vv v8, v8, v0
; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: lui a0, %hi(.LCPI66_0) ; CHECK-NEXT: lui a0, %hi(.LCPI66_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI66_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI66_0)
; CHECK-NEXT: vfmax.vv v16, v24, v0 ; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmax.vv v8, v16, v8 ; CHECK-NEXT: vlse32.v v16, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v16, ft0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v16 ; CHECK-NEXT: vfredmax.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <128 x float>, <128 x float>* %x %v = load <128 x float>, <128 x float>* %x
%red = call float @llvm.vector.reduce.fmax.v128f32(<128 x float> %v) %red = call float @llvm.vector.reduce.fmax.v128f32(<128 x float> %v)
ret float %red ret float %red
} }
declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>) declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)
define double @vreduce_fmax_v2f64(<2 x double>* %x) { define double @vreduce_fmax_v2f64(<2 x double>* %x) {
; CHECK-LABEL: vreduce_fmax_v2f64: ; CHECK-LABEL: vreduce_fmax_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI67_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI67_0)(a1)
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI67_0)
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI67_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <2 x double>, <2 x double>* %x %v = load <2 x double>, <2 x double>* %x
%red = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %v) %red = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %v)
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>) declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>)
define double @vreduce_fmax_v4f64(<4 x double>* %x) { define double @vreduce_fmax_v4f64(<4 x double>* %x) {
; CHECK-LABEL: vreduce_fmax_v4f64: ; CHECK-LABEL: vreduce_fmax_v4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI68_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI68_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI68_0)
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI68_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v10 ; CHECK-NEXT: vfredmax.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x %v = load <4 x double>, <4 x double>* %x
%red = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v) %red = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_fmax_v4f64_nonans(<4 x double>* %x) { define double @vreduce_fmax_v4f64_nonans(<4 x double>* %x) {
; CHECK-LABEL: vreduce_fmax_v4f64_nonans: ; CHECK-LABEL: vreduce_fmax_v4f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI69_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI69_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI69_0)
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI69_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v10 ; CHECK-NEXT: vfredmax.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x %v = load <4 x double>, <4 x double>* %x
%red = call nnan double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v) %red = call nnan double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_fmax_v4f64_nonans_noinfs(<4 x double>* %x) { define double @vreduce_fmax_v4f64_nonans_noinfs(<4 x double>* %x) {
; CHECK-LABEL: vreduce_fmax_v4f64_nonans_noinfs: ; CHECK-LABEL: vreduce_fmax_v4f64_nonans_noinfs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI70_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI70_0)(a1)
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI70_0)
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI70_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v10 ; CHECK-NEXT: vfredmax.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <4 x double>, <4 x double>* %x %v = load <4 x double>, <4 x double>* %x
%red = call nnan ninf double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v) %red = call nnan ninf double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fmax.v32f64(<32 x double>) declare double @llvm.vector.reduce.fmax.v32f64(<32 x double>)
define double @vreduce_fmax_v32f64(<32 x double>* %x) { define double @vreduce_fmax_v32f64(<32 x double>* %x) {
; CHECK-LABEL: vreduce_fmax_v32f64: ; CHECK-LABEL: vreduce_fmax_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle64.v v16, (a0) ; CHECK-NEXT: vle64.v v16, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI71_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI71_0)(a0)
; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI71_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI71_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v16 ; CHECK-NEXT: vfredmax.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = load <32 x double>, <32 x double>* %x %v = load <32 x double>, <32 x double>* %x
%red = call double @llvm.vector.reduce.fmax.v32f64(<32 x double> %v) %red = call double @llvm.vector.reduce.fmax.v32f64(<32 x double> %v)
ret double %red ret double %red
} }

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
declare half @llvm.vector.reduce.fadd.nxv1f16(half, <vscale x 1 x half>) declare half @llvm.vector.reduce.fadd.nxv1f16(half, <vscale x 1 x half>)
define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) { define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv1f16: ; CHECK-LABEL: vreduce_fadd_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI0_0) ; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI0_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)
ret half %red ret half %red
} }
Show All 12 Lines
} }
declare half @llvm.vector.reduce.fadd.nxv2f16(half, <vscale x 2 x half>) declare half @llvm.vector.reduce.fadd.nxv2f16(half, <vscale x 2 x half>)
define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) { define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv2f16: ; CHECK-LABEL: vreduce_fadd_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI2_0) ; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI2_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)
ret half %red ret half %red
} }
Show All 12 Lines
} }
declare half @llvm.vector.reduce.fadd.nxv4f16(half, <vscale x 4 x half>) declare half @llvm.vector.reduce.fadd.nxv4f16(half, <vscale x 4 x half>)
define half @vreduce_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) { define half @vreduce_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv4f16: ; CHECK-LABEL: vreduce_fadd_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI4_0) ; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI4_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.h fa0, fa0, ft0 ; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)
ret half %red ret half %red
} }
Show All 10 Lines
} }
declare float @llvm.vector.reduce.fadd.nxv1f32(float, <vscale x 1 x float>) declare float @llvm.vector.reduce.fadd.nxv1f32(float, <vscale x 1 x float>)
define float @vreduce_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) { define float @vreduce_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {
; CHECK-LABEL: vreduce_fadd_nxv1f32: ; CHECK-LABEL: vreduce_fadd_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI6_0) ; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI6_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)
ret float %red ret float %red
} }
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} }
declare float @llvm.vector.reduce.fadd.nxv2f32(float, <vscale x 2 x float>) declare float @llvm.vector.reduce.fadd.nxv2f32(float, <vscale x 2 x float>)
define float @vreduce_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) { define float @vreduce_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {
; CHECK-LABEL: vreduce_fadd_nxv2f32: ; CHECK-LABEL: vreduce_fadd_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI8_0) ; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI8_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)
ret float %red ret float %red
} }
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} }
declare float @llvm.vector.reduce.fadd.nxv4f32(float, <vscale x 4 x float>) declare float @llvm.vector.reduce.fadd.nxv4f32(float, <vscale x 4 x float>)
define float @vreduce_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) { define float @vreduce_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {
; CHECK-LABEL: vreduce_fadd_nxv4f32: ; CHECK-LABEL: vreduce_fadd_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI10_0) ; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vlse32.v v10, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v10 ; CHECK-NEXT: vfredusum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.s fa0, fa0, ft0 ; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v) %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)
ret float %red ret float %red
} }
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} }
declare double @llvm.vector.reduce.fadd.nxv1f64(double, <vscale x 1 x double>) declare double @llvm.vector.reduce.fadd.nxv1f64(double, <vscale x 1 x double>)
define double @vreduce_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) { define double @vreduce_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {
; CHECK-LABEL: vreduce_fadd_nxv1f64: ; CHECK-LABEL: vreduce_fadd_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI12_0) ; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI12_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)
ret double %red ret double %red
} }
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} }
declare double @llvm.vector.reduce.fadd.nxv2f64(double, <vscale x 2 x double>) declare double @llvm.vector.reduce.fadd.nxv2f64(double, <vscale x 2 x double>)
define double @vreduce_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) { define double @vreduce_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {
; CHECK-LABEL: vreduce_fadd_nxv2f64: ; CHECK-LABEL: vreduce_fadd_nxv2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI14_0) ; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI14_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v10 ; CHECK-NEXT: vfredusum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)
ret double %red ret double %red
} }
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} }
declare double @llvm.vector.reduce.fadd.nxv4f64(double, <vscale x 4 x double>) declare double @llvm.vector.reduce.fadd.nxv4f64(double, <vscale x 4 x double>)
define double @vreduce_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) { define double @vreduce_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {
; CHECK-LABEL: vreduce_fadd_nxv4f64: ; CHECK-LABEL: vreduce_fadd_nxv4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI16_0) ; CHECK-NEXT: lui a0, %hi(.LCPI16_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI16_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI16_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v12, ft0 ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfredusum.vs v8, v8, v12 ; CHECK-NEXT: vfredusum.vs v8, v8, v12
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: fadd.d fa0, fa0, ft0 ; CHECK-NEXT: fadd.d fa0, fa0, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v) %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)
ret double %red ret double %red
} }
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} }
declare half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half>) declare half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half>)
define half @vreduce_fmin_nxv1f16(<vscale x 1 x half> %v) { define half @vreduce_fmin_nxv1f16(<vscale x 1 x half> %v) {
; CHECK-LABEL: vreduce_fmin_nxv1f16: ; CHECK-LABEL: vreduce_fmin_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI18_0) ; CHECK-NEXT: lui a0, %hi(.LCPI18_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI18_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI18_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v) %red = call half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_fmin_nxv1f16_nonans(<vscale x 1 x half> %v) #0 { define half @vreduce_fmin_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {
; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans: ; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI19_0) ; CHECK-NEXT: lui a0, %hi(.LCPI19_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI19_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI19_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call nnan half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v) %red = call nnan half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_fmin_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 { define half @vreduce_fmin_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {
; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans_noinfs: ; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans_noinfs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI20_0) ; CHECK-NEXT: lui a0, %hi(.LCPI20_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI20_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI20_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call nnan ninf half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v) %red = call nnan ninf half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half>) declare half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half>)
define half @vreduce_fmin_nxv2f16(<vscale x 2 x half> %v) { define half @vreduce_fmin_nxv2f16(<vscale x 2 x half> %v) {
; CHECK-LABEL: vreduce_fmin_nxv2f16: ; CHECK-LABEL: vreduce_fmin_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI21_0) ; CHECK-NEXT: lui a0, %hi(.LCPI21_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI21_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI21_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half> %v) %red = call half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half>) declare half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half>)
define half @vreduce_fmin_nxv4f16(<vscale x 4 x half> %v) { define half @vreduce_fmin_nxv4f16(<vscale x 4 x half> %v) {
; CHECK-LABEL: vreduce_fmin_nxv4f16: ; CHECK-LABEL: vreduce_fmin_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI22_0) ; CHECK-NEXT: lui a0, %hi(.LCPI22_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI22_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI22_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half> %v) %red = call half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half>) declare half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half>)
define half @vreduce_fmin_nxv64f16(<vscale x 64 x half> %v) { define half @vreduce_fmin_nxv64f16(<vscale x 64 x half> %v) {
; CHECK-LABEL: vreduce_fmin_nxv64f16: ; CHECK-LABEL: vreduce_fmin_nxv64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI23_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI23_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI23_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI23_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v16, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v16 ; CHECK-NEXT: vfredmin.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half> %v) %red = call half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half> %v)
ret half %red ret half %red
} }
declare float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float>) declare float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float>)
define float @vreduce_fmin_nxv1f32(<vscale x 1 x float> %v) { define float @vreduce_fmin_nxv1f32(<vscale x 1 x float> %v) {
; CHECK-LABEL: vreduce_fmin_nxv1f32: ; CHECK-LABEL: vreduce_fmin_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI24_0) ; CHECK-NEXT: lui a0, %hi(.LCPI24_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI24_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI24_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v) %red = call float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_fmin_nxv1f32_nonans(<vscale x 1 x float> %v) { define float @vreduce_fmin_nxv1f32_nonans(<vscale x 1 x float> %v) {
; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans: ; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI25_0) ; CHECK-NEXT: lui a0, %hi(.LCPI25_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI25_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI25_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call nnan float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v) %red = call nnan float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_fmin_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) { define float @vreduce_fmin_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {
; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans_noinfs: ; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans_noinfs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI26_0) ; CHECK-NEXT: lui a0, %hi(.LCPI26_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI26_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI26_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call nnan ninf float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v) %red = call nnan ninf float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>) declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>)
define float @vreduce_fmin_nxv2f32(<vscale x 2 x float> %v) { define float @vreduce_fmin_nxv2f32(<vscale x 2 x float> %v) {
; CHECK-LABEL: vreduce_fmin_nxv2f32: ; CHECK-LABEL: vreduce_fmin_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI27_0) ; CHECK-NEXT: lui a0, %hi(.LCPI27_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI27_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI27_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> %v) %red = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> %v)
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float>) declare float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float>)
define float @vreduce_fmin_nxv4f32(<vscale x 4 x float> %v) { define float @vreduce_fmin_nxv4f32(<vscale x 4 x float> %v) {
; CHECK-LABEL: vreduce_fmin_nxv4f32: ; CHECK-LABEL: vreduce_fmin_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI28_0) ; CHECK-NEXT: lui a0, %hi(.LCPI28_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI28_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI28_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vlse32.v v10, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v10 ; CHECK-NEXT: vfredmin.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> %v) %red = call float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> %v)
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float>) declare float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float>)
define float @vreduce_fmin_nxv32f32(<vscale x 32 x float> %v) { define float @vreduce_fmin_nxv32f32(<vscale x 32 x float> %v) {
; CHECK-LABEL: vreduce_fmin_nxv32f32: ; CHECK-LABEL: vreduce_fmin_nxv32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI29_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI29_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI29_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI29_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v16, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v16 ; CHECK-NEXT: vfredmin.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float> %v) %red = call float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float> %v)
ret float %red ret float %red
} }
declare double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double>) declare double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double>)
define double @vreduce_fmin_nxv1f64(<vscale x 1 x double> %v) { define double @vreduce_fmin_nxv1f64(<vscale x 1 x double> %v) {
; CHECK-LABEL: vreduce_fmin_nxv1f64: ; CHECK-LABEL: vreduce_fmin_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI30_0) ; CHECK-NEXT: lui a0, %hi(.LCPI30_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI30_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI30_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v) %red = call double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_fmin_nxv1f64_nonans(<vscale x 1 x double> %v) { define double @vreduce_fmin_nxv1f64_nonans(<vscale x 1 x double> %v) {
; CHECK-LABEL: vreduce_fmin_nxv1f64_nonans: ; CHECK-LABEL: vreduce_fmin_nxv1f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI31_0) ; CHECK-NEXT: lui a0, %hi(.LCPI31_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI31_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI31_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call nnan double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v) %red = call nnan double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_fmin_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) { define double @vreduce_fmin_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) {
; CHECK-LABEL: vreduce_fmin_nxv1f64_nonans_noinfs: ; CHECK-LABEL: vreduce_fmin_nxv1f64_nonans_noinfs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI32_0) ; CHECK-NEXT: lui a0, %hi(.LCPI32_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI32_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI32_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vfredmin.vs v8, v8, v9 ; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call nnan ninf double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v) %red = call nnan ninf double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double>) declare double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double>)
define double @vreduce_fmin_nxv2f64(<vscale x 2 x double> %v) { define double @vreduce_fmin_nxv2f64(<vscale x 2 x double> %v) {
; CHECK-LABEL: vreduce_fmin_nxv2f64: ; CHECK-LABEL: vreduce_fmin_nxv2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI33_0) ; CHECK-NEXT: lui a0, %hi(.LCPI33_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI33_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI33_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v10 ; CHECK-NEXT: vfredmin.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double> %v) %red = call double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double> %v)
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double>) declare double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double>)
define double @vreduce_fmin_nxv4f64(<vscale x 4 x double> %v) { define double @vreduce_fmin_nxv4f64(<vscale x 4 x double> %v) {
; CHECK-LABEL: vreduce_fmin_nxv4f64: ; CHECK-LABEL: vreduce_fmin_nxv4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI34_0) ; CHECK-NEXT: lui a0, %hi(.LCPI34_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI34_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI34_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v12, ft0 ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v12 ; CHECK-NEXT: vfredmin.vs v8, v8, v12
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double> %v) %red = call double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double> %v)
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double>) declare double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double>)
define double @vreduce_fmin_nxv16f64(<vscale x 16 x double> %v) { define double @vreduce_fmin_nxv16f64(<vscale x 16 x double> %v) {
; CHECK-LABEL: vreduce_fmin_nxv16f64: ; CHECK-LABEL: vreduce_fmin_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI35_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI35_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: vfmin.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI35_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI35_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfredmin.vs v8, v8, v16 ; CHECK-NEXT: vfredmin.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double> %v) %red = call double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double> %v)
ret double %red ret double %red
} }
declare half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half>) declare half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half>)
define half @vreduce_fmax_nxv1f16(<vscale x 1 x half> %v) { define half @vreduce_fmax_nxv1f16(<vscale x 1 x half> %v) {
; CHECK-LABEL: vreduce_fmax_nxv1f16: ; CHECK-LABEL: vreduce_fmax_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI36_0) ; CHECK-NEXT: lui a0, %hi(.LCPI36_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI36_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI36_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v) %red = call half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_fmax_nxv1f16_nonans(<vscale x 1 x half> %v) #0 { define half @vreduce_fmax_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {
; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans: ; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI37_0) ; CHECK-NEXT: lui a0, %hi(.LCPI37_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI37_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI37_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call nnan half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v) %red = call nnan half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_fmax_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 { define half @vreduce_fmax_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {
; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans_noinfs: ; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans_noinfs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI38_0) ; CHECK-NEXT: lui a0, %hi(.LCPI38_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI38_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI38_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call nnan ninf half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v) %red = call nnan ninf half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half>) declare half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half>)
define half @vreduce_fmax_nxv2f16(<vscale x 2 x half> %v) { define half @vreduce_fmax_nxv2f16(<vscale x 2 x half> %v) {
; CHECK-LABEL: vreduce_fmax_nxv2f16: ; CHECK-LABEL: vreduce_fmax_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI39_0) ; CHECK-NEXT: lui a0, %hi(.LCPI39_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI39_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI39_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half> %v) %red = call half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half>) declare half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half>)
define half @vreduce_fmax_nxv4f16(<vscale x 4 x half> %v) { define half @vreduce_fmax_nxv4f16(<vscale x 4 x half> %v) {
; CHECK-LABEL: vreduce_fmax_nxv4f16: ; CHECK-LABEL: vreduce_fmax_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI40_0) ; CHECK-NEXT: lui a0, %hi(.LCPI40_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI40_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI40_0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse16.v v9, (a0), zero
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half> %v) %red = call half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half>) declare half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half>)
define half @vreduce_fmax_nxv64f16(<vscale x 64 x half> %v) { define half @vreduce_fmax_nxv64f16(<vscale x 64 x half> %v) {
; CHECK-LABEL: vreduce_fmax_nxv64f16: ; CHECK-LABEL: vreduce_fmax_nxv64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI41_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI41_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI41_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI41_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vlse16.v v16, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v16 ; CHECK-NEXT: vfredmax.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half> %v) %red = call half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half> %v)
ret half %red ret half %red
} }
declare float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float>) declare float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float>)
define float @vreduce_fmax_nxv1f32(<vscale x 1 x float> %v) { define float @vreduce_fmax_nxv1f32(<vscale x 1 x float> %v) {
; CHECK-LABEL: vreduce_fmax_nxv1f32: ; CHECK-LABEL: vreduce_fmax_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI42_0) ; CHECK-NEXT: lui a0, %hi(.LCPI42_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI42_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI42_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v) %red = call float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_fmax_nxv1f32_nonans(<vscale x 1 x float> %v) { define float @vreduce_fmax_nxv1f32_nonans(<vscale x 1 x float> %v) {
; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans: ; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI43_0) ; CHECK-NEXT: lui a0, %hi(.LCPI43_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI43_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI43_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call nnan float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v) %red = call nnan float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
ret float %red ret float %red
} }
define float @vreduce_fmax_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) { define float @vreduce_fmax_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {
; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans_noinfs: ; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans_noinfs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI44_0) ; CHECK-NEXT: lui a0, %hi(.LCPI44_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI44_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI44_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call nnan ninf float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v) %red = call nnan ninf float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float>) declare float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float>)
define float @vreduce_fmax_nxv2f32(<vscale x 2 x float> %v) { define float @vreduce_fmax_nxv2f32(<vscale x 2 x float> %v) {
; CHECK-LABEL: vreduce_fmax_nxv2f32: ; CHECK-LABEL: vreduce_fmax_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI45_0) ; CHECK-NEXT: lui a0, %hi(.LCPI45_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI45_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI45_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse32.v v9, (a0), zero
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> %v) %red = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> %v)
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float>) declare float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float>)
define float @vreduce_fmax_nxv4f32(<vscale x 4 x float> %v) { define float @vreduce_fmax_nxv4f32(<vscale x 4 x float> %v) {
; CHECK-LABEL: vreduce_fmax_nxv4f32: ; CHECK-LABEL: vreduce_fmax_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI46_0) ; CHECK-NEXT: lui a0, %hi(.LCPI46_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI46_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI46_0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vlse32.v v10, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v10 ; CHECK-NEXT: vfredmax.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float> %v) %red = call float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float> %v)
ret float %red ret float %red
} }
declare float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float>) declare float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float>)
define float @vreduce_fmax_nxv32f32(<vscale x 32 x float> %v) { define float @vreduce_fmax_nxv32f32(<vscale x 32 x float> %v) {
; CHECK-LABEL: vreduce_fmax_nxv32f32: ; CHECK-LABEL: vreduce_fmax_nxv32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI47_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI47_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI47_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI47_0)
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vlse32.v v16, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v16 ; CHECK-NEXT: vfredmax.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float> %v) %red = call float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float> %v)
ret float %red ret float %red
} }
declare double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double>) declare double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double>)
define double @vreduce_fmax_nxv1f64(<vscale x 1 x double> %v) { define double @vreduce_fmax_nxv1f64(<vscale x 1 x double> %v) {
; CHECK-LABEL: vreduce_fmax_nxv1f64: ; CHECK-LABEL: vreduce_fmax_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI48_0) ; CHECK-NEXT: lui a0, %hi(.LCPI48_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI48_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI48_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v) %red = call double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_fmax_nxv1f64_nonans(<vscale x 1 x double> %v) { define double @vreduce_fmax_nxv1f64_nonans(<vscale x 1 x double> %v) {
; CHECK-LABEL: vreduce_fmax_nxv1f64_nonans: ; CHECK-LABEL: vreduce_fmax_nxv1f64_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI49_0) ; CHECK-NEXT: lui a0, %hi(.LCPI49_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI49_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI49_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call nnan double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v) %red = call nnan double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
ret double %red ret double %red
} }
define double @vreduce_fmax_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) { define double @vreduce_fmax_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) {
; CHECK-LABEL: vreduce_fmax_nxv1f64_nonans_noinfs: ; CHECK-LABEL: vreduce_fmax_nxv1f64_nonans_noinfs:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI50_0) ; CHECK-NEXT: lui a0, %hi(.LCPI50_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI50_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI50_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, ft0 ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vfredmax.vs v8, v8, v9 ; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call nnan ninf double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v) %red = call nnan ninf double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double>) declare double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double>)
define double @vreduce_fmax_nxv2f64(<vscale x 2 x double> %v) { define double @vreduce_fmax_nxv2f64(<vscale x 2 x double> %v) {
; CHECK-LABEL: vreduce_fmax_nxv2f64: ; CHECK-LABEL: vreduce_fmax_nxv2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI51_0) ; CHECK-NEXT: lui a0, %hi(.LCPI51_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI51_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI51_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v10, ft0 ; CHECK-NEXT: vlse64.v v10, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v10 ; CHECK-NEXT: vfredmax.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double> %v) %red = call double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double> %v)
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double>) declare double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double>)
define double @vreduce_fmax_nxv4f64(<vscale x 4 x double> %v) { define double @vreduce_fmax_nxv4f64(<vscale x 4 x double> %v) {
; CHECK-LABEL: vreduce_fmax_nxv4f64: ; CHECK-LABEL: vreduce_fmax_nxv4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI52_0) ; CHECK-NEXT: lui a0, %hi(.LCPI52_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI52_0)(a0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI52_0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v12, ft0 ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v12 ; CHECK-NEXT: vfredmax.vs v8, v8, v12
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double> %v) %red = call double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double> %v)
ret double %red ret double %red
} }
declare double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double>) declare double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double>)
define double @vreduce_fmax_nxv16f64(<vscale x 16 x double> %v) { define double @vreduce_fmax_nxv16f64(<vscale x 16 x double> %v) {
; CHECK-LABEL: vreduce_fmax_nxv16f64: ; CHECK-LABEL: vreduce_fmax_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI53_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI53_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: vfmax.vv v8, v8, v16
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: lui a0, %hi(.LCPI53_0)
; CHECK-NEXT: vfmv.v.f v16, ft0 ; CHECK-NEXT: addi a0, a0, %lo(.LCPI53_0)
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfredmax.vs v8, v8, v16 ; CHECK-NEXT: vfredmax.vs v8, v8, v16
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double> %v) %red = call double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double> %v)
ret double %red ret double %red
} }