[PowerPC] Fix load/store selection infrastructure when load/store intrinsics are used on P10.

[amyk]

Summary

The load/store infrastructure previously made an incorrect assumption that whenever it is used with
a load/store intrinsic on Power10 - those intrinsics would automatically be the lxvp/stxvp intrinsics
introduced in Power10. However, this is obviously not the case as there are multiple instances of
pre-P10 intrinsics that use the refactored load/store implementation.

This patch corrects this assumption, and produces the expected intrinsic on pre-P10.

[nemanjai]

You might want to avoid adding new check prefixes in the tests if the sequence is exactly the same. Maybe just change it from CHECK-P9 to CHECK-P9UP. Otherwise LGTM.

[amyk]

I've updated the checks to be P9UP on the commit, while also removing the P10 run lines from vsx-p9.ll as this test case does not exercise the refactored load/store infrastructure.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if ((FlagSet & PPC::MOF_SubtargetP10) && isPCRelNode(N))
     return FlagSet;
 
   // If the node is the paired load/store intrinsics, compute flags for
   // address computation and return early.
   unsigned ParentOp = Parent->getOpcode();
   if (Subtarget.isISA3_1() && ((ParentOp == ISD::INTRINSIC_W_CHAIN) ||
                                (ParentOp == ISD::INTRINSIC_VOID))) {
     unsigned ID = cast<ConstantSDNode>(Parent->getOperand(1))->getZExtValue();
-    assert(
-        ((ID == Intrinsic::ppc_vsx_lxvp) || (ID == Intrinsic::ppc_vsx_stxvp)) &&
-        "Only the paired load and store (lxvp/stxvp) intrinsics are valid.");
-    SDValue IntrinOp = (ID == Intrinsic::ppc_vsx_lxvp) ? Parent->getOperand(2)
-                                                       : Parent->getOperand(3);
+    if ((ID == Intrinsic::ppc_vsx_lxvp) || (ID == Intrinsic::ppc_vsx_stxvp)) {
+      SDValue IntrinOp = (ID == Intrinsic::ppc_vsx_lxvp)
+                             ? Parent->getOperand(2)
       computeFlagsForAddressComputation(IntrinOp, FlagSet, DAG);
       FlagSet |= PPC::MOF_Vector;
       return FlagSet;
     }
+  }
 
   // Mark this as something we don't want to handle here if it is atomic
   // or pre-increment instruction.
   if (const LSBaseSDNode *LSB = dyn_cast<LSBaseSDNode>(Parent))
     if (LSB->isIndexed())
       return PPC::MOF_None;
 
   // Compute in-memory type flags. This is based on if there are scalars,

llvm/test/CodeGen/PowerPC/lxvw4x-bug.ll

 ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr8 \
 ; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
 
 ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr9 \
 ; RUN:   -mtriple=powerpc64le-unknown-unknown < %s \
 ; RUN:   | FileCheck %s --check-prefix=CHECK-P9 --implicit-check-not xxswapd
 
 ; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr9 -mattr=-power9-vector \
 ; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
 
+; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr10 \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s \
+; RUN:   | FileCheck %s --check-prefix=CHECK-P10
+
+; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr10 \
+; RUN:   -mtriple=powerpc64-unknown-unknown < %s \
+; RUN:   | FileCheck %s --check-prefix=CHECK-P10
+
 ; Function Attrs: nounwind
 define void @test() {
 entry:
   %__a.addr.i = alloca i32, align 4
   %__b.addr.i = alloca <4 x i32>*, align 8
   %i = alloca <4 x i32>, align 16
   %j = alloca <4 x i32>, align 16
   store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* %i, align 16
   store i32 0, i32* %__a.addr.i, align 4
   store <4 x i32>* %i, <4 x i32>** %__b.addr.i, align 8
   %0 = load i32, i32* %__a.addr.i, align 4
   %1 = load <4 x i32>*, <4 x i32>** %__b.addr.i, align 8
   %2 = bitcast <4 x i32>* %1 to i8*
   %3 = getelementptr i8, i8* %2, i32 %0
   %4 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %3)
 ; CHECK: lwa [[REG0:[0-9]+]],
 ; CHECK: lxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]]
 ; CHECK: xxswapd [[REG1]], [[REG1]]
 ; CHECK-P9: lwa [[REG0:[0-9]+]],
 ; CHECK-P9: lxvx [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]]
+; CHECK-P10: lwa [[REG0:[0-9]+]],
+; CHECK-P10: lxvx [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]]
   store <4 x i32> %4, <4 x i32>* %j, align 16
   ret void
 }
 
 ; Function Attrs: nounwind readonly
 declare <4 x i32> @llvm.ppc.vsx.lxvw4x(i8*)

llvm/test/CodeGen/PowerPC/swaps-le-8.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr8 \
 ; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 \
+; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-P9
+; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr10 \
+; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-P10
 define dso_local void @test(i64* %Src, i64* nocapture %Tgt) local_unnamed_addr {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxvd2x 0, 0, 3
 ; CHECK-NEXT:    xxswapd 0, 0
 ; CHECK-NEXT:    stxvd2x 0, 0, 4
 ; CHECK-NEXT:    blr
+;
+; CHECK-P9-LABEL: test:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    lxvd2x 0, 0, 3
+; CHECK-P9-NEXT:    stxv 0, 0(4)
+; CHECK-P9-NEXT:    blr
+;
+; CHECK-P10-LABEL: test:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    lxvd2x 0, 0, 3
+; CHECK-P10-NEXT:    stxv 0, 0(4)
+; CHECK-P10-NEXT:    blr
 entry:
   %0 = bitcast i64* %Src to i8*
   %1 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %0) #2
   %2 = bitcast i64* %Tgt to <2 x double>*
   store <2 x double> %1, <2 x double>* %2, align 1
   ret void
 }
 
 declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8*) #1

llvm/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -O2 \
 ; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O2 \
 ; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
 ; RUN:   --check-prefix=CHECK-P9
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector -O2 \
 ; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 -O2 \
+; RUN:   -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-P10
+
 @vf = global <4 x float> <float -1.500000e+00, float 2.500000e+00, float -3.500000e+00, float 4.500000e+00>, align 16
 @vd = global <2 x double> <double 3.500000e+00, double -7.500000e+00>, align 16
 @vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 16
 @vui = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
 @vsll = global <2 x i64> <i64 255, i64 -937>, align 16
 @vull = global <2 x i64> <i64 1447, i64 2894>, align 16
 @res_vsi = common global <4 x i32> zeroinitializer, align 16
 @res_vui = common global <4 x i32> zeroinitializer, align 16
 @res_vf = common global <4 x float> zeroinitializer, align 16
 @res_vsll = common global <2 x i64> zeroinitializer, align 16
 @res_vull = common global <2 x i64> zeroinitializer, align 16
 @res_vd = common global <2 x double> zeroinitializer, align 16
 
 define void @test1() {
 entry:
 ; CHECK-LABEL: test1
 ; CHECK-P9-LABEL: test1
+; CHECK-P10-LABEL: test1
 ; CHECK: lxvd2x
 ; CHECK-P9-DAG: lxv
+; CHECK-P10-DAG: lxv
   %0 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x i32>* @vsi to i8*))
 ; CHECK: stxvd2x
 ; CHECK-P9-DAG: stxv
+; CHECK-P10-DAG: stxv
   store <4 x i32> %0, <4 x i32>* @res_vsi, align 16
 ; CHECK: lxvd2x
 ; CHECK-P9-DAG: lxv
+; CHECK-P10-DAG: lxv
   %1 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x i32>* @vui to i8*))
 ; CHECK: stxvd2x
 ; CHECK-P9-DAG: stxv
+; CHECK-P10-DAG: stxv
   store <4 x i32> %1, <4 x i32>* @res_vui, align 16
 ; CHECK: lxvd2x
 ; CHECK-P9-DAG: lxv
+; CHECK-P10-DAG: lxv
   %2 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x float>* @vf to i8*))
   %3 = bitcast <4 x i32> %2 to <4 x float>
 ; CHECK: stxvd2x
 ; CHECK-P9-DAG: stxv
+; CHECK-P10-DAG: stxv
   store <4 x float> %3, <4 x float>* @res_vf, align 16
 ; CHECK: lxvd2x
 ; CHECK-P9-DAG: lxv
+; CHECK-P10-DAG: lxv
   %4 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x i64>* @vsll to i8*))
   %5 = bitcast <2 x double> %4 to <2 x i64>
 ; CHECK: stxvd2x
 ; CHECK-P9-DAG: stxv
+; CHECK-P10-DAG: stxv
   store <2 x i64> %5, <2 x i64>* @res_vsll, align 16
 ; CHECK: lxvd2x
 ; CHECK-P9-DAG: lxv
+; CHECK-P10-DAG: lxv
   %6 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x i64>* @vull to i8*))
   %7 = bitcast <2 x double> %6 to <2 x i64>
 ; CHECK: stxvd2x
 ; CHECK-P9-DAG: stxv
+; CHECK-P10-DAG: stxv
   store <2 x i64> %7, <2 x i64>* @res_vull, align 16
 ; CHECK: lxvd2x
 ; CHECK-P9-DAG: lxv
+; CHECK-P10-DAG: lxv
   %8 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x double>* @vd to i8*))
 ; CHECK: stxvd2x
 ; CHECK-P9-DAG: stxv
+; CHECK-P10-DAG: stxv
   store <2 x double> %8, <2 x double>* @res_vd, align 16
 ; CHECK: lxvd2x
 ; CHECK-P9-DAG: lxv
+; CHECK-P10-DAG: lxv
   %9 = load <4 x i32>, <4 x i32>* @vsi, align 16
 ; CHECK: stxvd2x
 ; CHECK-P9-DAG: stxv
+; CHECK-P10-DAG: stxv
   call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %9, i8* bitcast (<4 x i32>* @res_vsi to i8*))
 ; CHECK: lxvd2x
 ; CHECK-P9-DAG: lxv
+; CHECK-P10-DAG: lxv
   %10 = load <4 x i32>, <4 x i32>* @vui, align 16
 ; CHECK: stxvd2x
 ; CHECK-P9-DAG: stxv
+; CHECK-P10-DAG: stxv
   call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %10, i8* bitcast (<4 x i32>* @res_vui to i8*))
 ; CHECK: lxvd2x
 ; CHECK-P9-DAG: lxv
+; CHECK-P10-DAG: lxv
   %11 = load <4 x float>, <4 x float>* @vf, align 16
   %12 = bitcast <4 x float> %11 to <4 x i32>
 ; CHECK: stxvd2x
 ; CHECK-P9-DAG: stxv
+; CHECK-P10-DAG: stxv
   call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %12, i8* bitcast (<4 x float>* @res_vf to i8*))
 ; CHECK: lxvd2x
 ; CHECK-P9-DAG: lxv
+; CHECK-P10-DAG: lxv
   %13 = load <2 x i64>, <2 x i64>* @vsll, align 16
   %14 = bitcast <2 x i64> %13 to <2 x double>
 ; CHECK: stxvd2x
 ; CHECK-P9-DAG: stxv
+; CHECK-P10-DAG: stxv
   call void @llvm.ppc.vsx.stxvd2x(<2 x double> %14, i8* bitcast (<2 x i64>* @res_vsll to i8*))
 ; CHECK: lxvd2x
 ; CHECK-P9-DAG: lxv
+; CHECK-P10-DAG: lxv
   %15 = load <2 x i64>, <2 x i64>* @vull, align 16
   %16 = bitcast <2 x i64> %15 to <2 x double>
 ; CHECK: stxvd2x
 ; CHECK-P9-DAG: stxv
+; CHECK-P10-DAG: stxv
   call void @llvm.ppc.vsx.stxvd2x(<2 x double> %16, i8* bitcast (<2 x i64>* @res_vull to i8*))
 ; CHECK: lxvd2x
 ; CHECK-P9-DAG: lxv
+; CHECK-P10-DAG: lxv
   %17 = load <2 x double>, <2 x double>* @vd, align 16
 ; CHECK: stxvd2x
 ; CHECK-P9-DAG: stxv
+; CHECK-P10-DAG: stxv
   call void @llvm.ppc.vsx.stxvd2x(<2 x double> %17, i8* bitcast (<2 x double>* @res_vd to i8*))
   ret void
 }
 
 declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, i8*)
 declare void @llvm.ppc.vsx.stxvw4x(<4 x i32>, i8*)
 declare <2 x double> @llvm.ppc.vsx.lxvd2x(i8*)
 declare <4 x i32> @llvm.ppc.vsx.lxvw4x(i8*)

llvm/test/CodeGen/PowerPC/vsx-p9.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 \
 ; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 \
 ; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
 
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 \
+; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
+
 @uca = global <16 x i8> zeroinitializer, align 16
 @ucb = global <16 x i8> zeroinitializer, align 16
 @sca = global <16 x i8> zeroinitializer, align 16
 @scb = global <16 x i8> zeroinitializer, align 16
 @usa = global <8 x i16> zeroinitializer, align 16
 @usb = global <8 x i16> zeroinitializer, align 16
 @ssa = global <8 x i16> zeroinitializer, align 16
 @ssb = global <8 x i16> zeroinitializer, align 16

llvm/test/CodeGen/PowerPC/vsx_builtins.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector \
 ; RUN:     -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
 ; RUN:     --check-prefixes=CHECK,CHECK-INTRIN
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx \
 ; RUN:     -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
 ; RUN:     --check-prefixes=CHECK,CHECK-INTRIN
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 \
+; RUN:     -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:     --check-prefixes=CHECK,CHECK-P10
+; RUN: llc -verify-machineinstrs -mcpu=pwr10 \
+; RUN:     -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:     --check-prefixes=CHECK,CHECK-P10
 
 ; Function Attrs: nounwind readnone
 define <4 x i32> @test1(i8* %a) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxvw4x v2, 0, r3
 ; CHECK-NEXT:    blr
   entry:

 ; CHECK-NOINTRIN-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-NOINTRIN-NEXT:    xxswapd v2, vs0
 ; CHECK-NOINTRIN-NEXT:    blr
 ;
 ; CHECK-INTRIN-LABEL: test_lxvd2x:
 ; CHECK-INTRIN:       # %bb.0: # %entry
 ; CHECK-INTRIN-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-INTRIN-NEXT:    blr
+;
+; CHECK-P10-LABEL: test_lxvd2x:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    lxv v2, 0(r3)
+; CHECK-P10-NEXT:    blr
 entry:
   %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %a)
   ret <2 x double> %0
 }
 ; Function Attrs: nounwind readnone
 declare <2 x double> @llvm.ppc.vsx.lxvd2x(i8*)
 
 ; Function Attrs: nounwind readnone
 define void @test_stxvd2x(<2 x double> %a, i8* %b) {
 ; CHECK-P9-LABEL: test_stxvd2x:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    stxv v2, 0(r5)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-NOINTRIN-LABEL: test_stxvd2x:
 ; CHECK-NOINTRIN:       # %bb.0: # %entry
 ; CHECK-NOINTRIN-NEXT:    xxswapd vs0, v2
 ; CHECK-NOINTRIN-NEXT:    stxvd2x vs0, 0, r5
 ; CHECK-NOINTRIN-NEXT:    blr
 ;
 ; CHECK-INTRIN-LABEL: test_stxvd2x:
 ; CHECK-INTRIN:       # %bb.0: # %entry
 ; CHECK-INTRIN-NEXT:    stxvd2x v2, 0, r5
 ; CHECK-INTRIN-NEXT:    blr
+;
+; CHECK-P10-LABEL: test_stxvd2x:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    stxv v2, 0(r5)
+; CHECK-P10-NEXT:    blr
 entry:
   tail call void @llvm.ppc.vsx.stxvd2x(<2 x double> %a, i8* %b)
   ret void
 }
 ; Function Attrs: nounwind readnone
 declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, i8*)