[PowerPC][AIX] Add toc-data support for 64-bit AIX

[yoalione]

Summary

The patch handles the addition of global variables to the table of contents for 64-bit AIX. This was previously supported for 32-bit (https://reviews.llvm.org/D101178).

The patch expands toc-data attribute support to 64-bit.

[sfertile]

Nice work Yousuf. Can you start by adding the context for the patch (for example if you used git diff or git show then adding -U9999 will give you 9999 lines of surrounding context in the diff), and running clang format on the patch?

[yoalione]

Address comments and combine common code.

[sfertile]

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

892

minor nit: no need to have an if/else for this. We don't have to be too formal with assert messages and having "Invalid operand for ADDItoc[8]." is fine.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5833

Minor nir: I'm guessing this changed because you ran clang-format on the whole file? We try not to touch otherwise unchanged lines. Can you put it back to what it originally was.

[yoalione]

Address review comments.

[sfertile]

LGTM!

[nemanjai]

In D114654#3156432, @sfertile wrote:

Nice work Yousuf. Can you start by adding the context for the patch (for example if you used git diff or git show then adding -U9999 will give you 9999 lines of surrounding context in the diff), and running clang format on the patch?

Please note that you probably need at least another 9 to make it -U99999 since there will be files that are well over 10kloc (looking at you PPCISelLowering.cpp). :)

[nemanjai]

My comments are just minor nits that don't require another review and can be addressed when committing the patch.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5832

The isAIXABI check here should be unnecessary since we would break out of here at line 5795. I think it would be clearer if we just add an assert for isAIXABI just above this line instead.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

776

This is already in a isCodeGenOnly = 1 block isn't it?

[yoalione]

Address review comments.

[yoalione]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5832

I think it should be within the if (so a line after).

llvm/lib/Target/PowerPC/P10InstrResources.td

def : InstRW<[P10W_SX, P10W_DISP_ANY],
     DCBA,
     DCBI,
     DCBZL,
     DCCCI,
     ICBLC,
     ICBLQ,
     ICBTLS,
     ICCCI,
-    LA,
+    LA, LA8,
     LDMX,
     MFDCR,
     MFPMR,
     MFSRIN,
     MSYNC,
     MTDCR,
     MTPMR,
     MTSRIN,
def : InstRW<[P10W_vMU_7C, P10W_DISP_ANY, P10vMU_Read, P10vMU_Read, P10vMU_Read],
     VMSUMMBM,
     VMSUMSHM,
     VMSUMSHS,
     VMSUMUBM,
     VMSUMUDM,
     VMSUMUHM,
     VMSUMUHS
 )>;
+

llvm/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
     (instregex "AND(C)?(8)?(_rec)?$"),
     (instregex "NOR(8)?(_rec)?$"),
     (instregex "OR(C)?(8)?(_rec)?$"),
     (instregex "EQV(8)?(_rec)?$"),
     (instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(_rec)?$"),
     (instregex "ADD(4|8)(TLS)?(_)?$"),
     (instregex "NEG(8)?(O)?$"),
     (instregex "ADDI(S)?toc(HA|L)(8)?$"),
+    (instregex "LA(8)?$"),
     COPY,
     MCRF,
     MCRXRX,
     XSNABSDP,
     XSXEXPDP,
     XSABSDP,
     XSNEGDP,
     XSCPSGNDP,
     MFVSRWZ,
     MFVRWZ,
     EXTSWSLI,
     SRADI_32,
     RLDIC,
     RFEBB,
-    LA,
     TBEGIN,
     TRECHKPT,
     NOP,
     WAIT
 )>;
 
 // Restricted Dispatch ALU operation for 2 cycles. The operation runs on a
 // single slice. However, since it is Restricted, it requires all 3 dispatches

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

case PPC::LWZtoc: {
     // '.LTOC' to manifest the toc-relative offset.
     const MCExpr *PB = MCSymbolRefExpr::create(
         OutContext.getOrCreateSymbol(Twine(".LTOC")), OutContext);
     Exp = MCBinaryExpr::createSub(Exp, PB, OutContext);
     TmpInst.getOperand(1) = MCOperand::createExpr(Exp);
     EmitToStreamer(*OutStreamer, TmpInst);
     return;
   }
-  case PPC::ADDItoc: {
+  case PPC::ADDItoc:
+  case PPC::ADDItoc8: {
     assert(IsAIX && TM.getCodeModel() == CodeModel::Small &&
-           "Operand only valid in AIX 32 bit mode");
+           "PseudoOp only valid for small code model AIX");
 
-    // Transform %rN = ADDItoc @op1, %r2.
+    // Transform %rN = ADDItoc/8 @op1, %r2.
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
 
     // Change the opcode to load address.
-    TmpInst.setOpcode(PPC::LA);
+    TmpInst.setOpcode((!IsPPC64) ? (PPC::LA) : (PPC::LA8));
 
     const MachineOperand &MO = MI->getOperand(1);
-    assert(MO.isGlobal() && "Invalid operand for ADDItoc.");
+    assert(MO.isGlobal() && "Invalid operand for ADDItoc[8].");
 
     // Map the operand to its corresponding MCSymbol.
     const MCSymbol *const MOSymbol = getMCSymbolForTOCPseudoMO(MO, *this);
 
     const MCExpr *Exp =
         MCSymbolRefExpr::create(MOSymbol, MCSymbolRefExpr::VK_None, OutContext);
 
     TmpInst.getOperand(1) = TmpInst.getOperand(2);
     TmpInst.getOperand(2) = MCOperand::createExpr(Exp);
     EmitToStreamer(*OutStreamer, TmpInst);

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

static bool hasTocDataAttr(SDValue Val, unsigned PointerSize) {
   const GlobalVariable *GV = dyn_cast_or_null<GlobalVariable>(GA->getGlobal());
   if (!GV)
     return false;
 
   if (!GV->hasAttribute("toc-data"))
     return false;
 
   // TODO: These asserts should be updated as more support for the toc data
-  // transformation is added (64 bit, struct support, etc.).
+  // transformation is added (struct support, etc.).
 
-  assert(PointerSize == 4 && "Only 32 Bit Codegen is currently supported by "
-                             "the toc data transformation.");
-
-  assert(PointerSize >= GV->getAlign().valueOrOne().value() &&
-         "GlobalVariables with an alignment requirement stricter then 4-bytes "
-         "not supported by the toc data transformation.");
+  assert(
+      PointerSize >= GV->getAlign().valueOrOne().value() &&
+      "GlobalVariables with an alignment requirement stricter than TOC entry "
+      "size not supported by the toc data transformation.");
 
   Type *GVType = GV->getValueType();
 
   assert(GVType->isSized() && "A GlobalVariable's size must be known to be "
                               "supported by the toc data transformation.");
 
   if (GVType->isVectorTy())
     report_fatal_error("A GlobalVariable of Vector type is not currently "
                        "supported by the toc data transformation.");
 
   if (GVType->isArrayTy())
     report_fatal_error("A GlobalVariable of Array type is not currently "
                        "supported by the toc data transformation.");
 
   if (GVType->isStructTy())
     report_fatal_error("A GlobalVariable of Struct type is not currently "
                        "supported by the toc data transformation.");
 
   assert(GVType->getPrimitiveSizeInBits() <= PointerSize * 8 &&
-         "A GlobalVariable with size larger than 32 bits is not currently "
+         "A GlobalVariable with size larger than a TOC entry is not currently "
          "supported by the toc data transformation.");
 
   if (GV->hasLocalLinkage() || GV->hasPrivateLinkage())
     report_fatal_error("A GlobalVariable with private or local linkage is not "
                        "currently supported by the toc data transformation.");
 
   assert(!GV->hasCommonLinkage() &&
          "Tentative definitions cannot have the mapping class XMC_TD.");
case PPCISD::TOC_ENTRY: {
     // PowerPC only support small, medium and large code model.
     const CodeModel::Model CModel = TM.getCodeModel();
     assert(!(CModel == CodeModel::Tiny || CModel == CodeModel::Kernel) &&
            "PowerPC doesn't support tiny or kernel code models.");
 
     if (isAIXABI && CModel == CodeModel::Medium)
       report_fatal_error("Medium code model is not supported on AIX.");
 
-    // For 64-bit small code model, we allow SelectCodeCommon to handle this,
-    // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
-    if (isPPC64 && CModel == CodeModel::Small)
+    // For 64-bit ELF small code model, we allow SelectCodeCommon to handle
+    // this, selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA. For AIX
+    // small code model, we need to check for a toc-data attribute.
+    if (isPPC64 && !isAIXABI && CModel == CodeModel::Small)
       break;
 
-    // Handle 32-bit small code model.
-    if (!isPPC64) {
-      // Transforms the ISD::TOC_ENTRY node to passed in Opcode, either
-      // PPC::ADDItoc, or PPC::LWZtoc
-      auto replaceWith = [this, &dl](unsigned OpCode, SDNode *TocEntry) {
-        SDValue GA = TocEntry->getOperand(0);
-        SDValue TocBase = TocEntry->getOperand(1);
-        SDNode *MN = CurDAG->getMachineNode(OpCode, dl, MVT::i32, GA, TocBase);
-        transferMemOperands(TocEntry, MN);
-        ReplaceNode(TocEntry, MN);
-      };
+    auto replaceWith = [this, &dl](unsigned OpCode, SDNode *TocEntry,
+                                   EVT OperandTy) {
+      SDNode *MN = CurDAG->getMachineNode(OpCode, dl, OperandTy, GA, TocBase);
 
+    // Handle 32-bit small code model.
+    if (!isPPC64 && CModel == CodeModel::Small) {
+      // Transforms the ISD::TOC_ENTRY node to passed in Opcode, either
+      // PPC::ADDItoc, or PPC::LWZtoc
       if (isELFABI) {
         assert(TM.isPositionIndependent() &&
                "32-bit ELF can only have TOC entries in position independent"
                " code.");
         // 32-bit ELF always uses a small code model toc access.
-        replaceWith(PPC::LWZtoc, N);
+        replaceWith(PPC::LWZtoc, N, MVT::i32);
         return;
       }
 
-      if (isAIXABI && CModel == CodeModel::Small) {
-        if (hasTocDataAttr(N->getOperand(0),
-                           CurDAG->getDataLayout().getPointerSize()))
-          replaceWith(PPC::ADDItoc, N);
-        else
-          replaceWith(PPC::LWZtoc, N);
+      assert(isAIXABI && "ELF ABI already handled");
+
+                         CurDAG->getDataLayout().getPointerSize())) {
+        replaceWith(PPC::ADDItoc, N, MVT::i32);
+        return;
+      }
+
+      replaceWith(PPC::LWZtoc, N, MVT::i32);
+      return;
+    }
 
+    if (isPPC64 && isAIXABI && CModel == CodeModel::Small) {
+      if (hasTocDataAttr(N->getOperand(0),
+                         CurDAG->getDataLayout().getPointerSize())) {
+        replaceWith(PPC::ADDItoc8, N, MVT::i64);
         return;
       }
+      // Break if it doesn't have toc data attribute. Proceed with common
+      // SelectCode.
+      break;
     }
 
     assert(CModel != CodeModel::Small && "All small code models handled.");
 
     assert((isPPC64 || (isAIXABI && !isPPC64)) && "We are dealing with 64-bit"
            " ELF/AIX or 32-bit AIX in the following.");
 
     // Transforms the ISD::TOC_ENTRY node for 32-bit AIX large code model mode
     // or 64-bit medium (ELF-only) or large (ELF and AIX) code model code. We
     // generate two instructions as described below. The first source operand
     // is a symbol reference. If it must be toc-referenced according to
     // Subtarget, we generate:
     // [32-bit AIX]

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
                      [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
 def ADDI8  : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
                      "addi $rD, $rA, $imm", IIC_IntSimple,
                      [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
                      "addis $rD, $rA, $imm", IIC_IntSimple,
                      [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
 
+let isCodeGenOnly = 1 in
+def LA8     : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$sym),
+                     "la $rD, $sym($rA)", IIC_IntGeneral,
+                     [(set i64:$rD, (add i64:$rA,
+                                    (PPClo tglobaladdr:$sym, 0)))]>;
+
 let Defs = [CARRY] in {
 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
                      "subfic $rD, $rA, $imm", IIC_IntGeneral,
                      [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
 }
 defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                         "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
                         [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,

 // Support for medium and large code model.
 let hasSideEffects = 0 in {
 let isReMaterializable = 1 in {
 def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
                        "#ADDIStocHA8", []>, isPPC64;
 def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
                      "#ADDItocL", []>, isPPC64;
 }
+
+// Local Data Transform
+def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
+                   "#ADDItoc8",
+                   [(set i64:$rD,
+                     (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
+
 let mayLoad = 1 in
 def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
                    "#LDtocL", []>, isPPC64;
 }
 
 // Support for thread-local storage.
 def ADDISgotTprelHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
                          "#ADDISgotTprelHA",

llvm/test/CodeGen/PowerPC/basic-toc-data-extern.ll

 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s
 ; RUN: not --crash llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff  \
 ; RUN:                 -verify-machineinstrs < %s 2>&1 | \
-; RUN:   FileCheck %s --check-prefix=OBJ
+; RUN:   FileCheck %s --check-prefix=OBJ32
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s
+; RUN: not --crash llc -filetype=obj -mtriple powerpc64-ibm-aix-xcoff  \
+; RUN:                 -verify-machineinstrs < %s 2>&1 | \
+; RUN:   FileCheck %s --check-prefix=OBJ64
 
 @i = external global i32, align 4  #0
 
 ; Function Attrs: noinline nounwind optnone
 define i32* @get() {
   entry:
     ret i32* @i
 }
 
 ; CHECK:        la 3, i[TD](2)
 ; CHECK:        .toc
 ; CHECK-NEXT:   .extern i[TD]
 
-; OBJ: LLVM ERROR:  toc-data not yet supported when writing object files.
+; OBJ32: LLVM ERROR:  toc-data not yet supported when writing object files.
+; OBJ64: LLVM ERROR:  64-bit XCOFF object files are not supported yet.
 
 attributes #0 = { "toc-data" }

llvm/test/CodeGen/PowerPC/basic-toc-data-local-linkage.ll

 ; RUN: not --crash llc  -mtriple powerpc-ibm-aix-xcoff  -verify-machineinstrs \
 ; RUN:     < %s 2>&1 | FileCheck %s
+; RUN: not --crash llc  -mtriple powerpc64-ibm-aix-xcoff  -verify-machineinstrs \
+; RUN:     < %s 2>&1 | FileCheck %s
 
 @ilocal = internal global i32 0, align 4 #0
 
 define dso_local i32 @read_i32_local_linkage() {
   entry:
     %0 = load i32, i32* @ilocal, align 4
     ret i32 %0
 }
 
 ; CHECK: LLVM ERROR: A GlobalVariable with private or local linkage is not currently supported by the toc data transformation.
 
 attributes #0 = { "toc-data" }

llvm/test/CodeGen/PowerPC/toc-data.ll

 ; REQUIRES: asserts
 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s \
-; RUN:     -stop-before=ppc-ctr-loops-verify | FileCheck %s
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix TEST
+; RUN:     -stop-before=ppc-ctr-loops-verify | FileCheck %s --check-prefix CHECK32
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s \
+; RUN:     -stop-before=ppc-ctr-loops-verify | FileCheck %s --check-prefix CHECK64
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix TEST32
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix TEST64
 
 @i = dso_local global i32 0, align 4 #0
 @d = dso_local local_unnamed_addr global double 3.141590e+00, align 8
 @f = dso_local local_unnamed_addr global float 0x4005BE76C0000000, align 4 #0
 @ll = dso_local local_unnamed_addr global i64 55, align 8
 @ilocal = internal global i32 0, align 4
 
 define dso_local void @write_int(i32 signext %in) {
   entry:
     store i32 %in, i32* @i, align 4
     ret void
 }
-; CHECK: name:            write_int
-; CHECK:      %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @i, $r2
-; CHECK-NEXT: STW %{{[0-9]+}}, 0, killed %[[SCRATCH]] :: (store (s32) into @i)
-
-; TEST:         .write_int:
-; TEST:           la 4, i[TD](2)
-; TEST-NEXT:      stw 3, 0(4)
+; CHECK32: name:            write_int
+; CHECK32:      %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @i, $r2
+; CHECK32-NEXT: STW %{{[0-9]+}}, 0, killed %[[SCRATCH]] :: (store (s32) into @i)
+
+; TEST32:         .write_int:
+; TEST32:           la 4, i[TD](2)
+; TEST32-NEXT:      stw 3, 0(4)
+
+; CHECK64: name:            write_int
+; CHECK64:      %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @i, $x2
+; CHECK64-NEXT: STW8 %{{[0-9]+}}, 0, killed %[[SCRATCH]] :: (store (s32) into @i)
+
+; TEST64:         .write_int:
+; TEST64:           la 4, i[TD](2)
+; TEST64-NEXT:      stw 3, 0(4)
+
 
 define dso_local i64 @read_ll() {
   entry:
     %0 = load i64, i64* @ll, align 8
     ret i64 %0
 }
-; CHECK: name:            read_ll
-; CHECK: LWZtoc @ll, $r2 :: (load (s32) from got)
+; CHECK32: name:            read_ll
+; CHECK32: LWZtoc @ll, $r2 :: (load (s32) from got)
+
+; TEST32:       .read_ll:
+; TEST32:         lwz 4, L..C0(2)
+; TEST32-NEXT:    lwz 3, 0(4)
+; TEST32-NEXT:    lwz 4, 4(4)
+
+; CHECK64: name:            read_ll
+; CHECK64: LDtoc @ll, $x2 :: (load (s64) from got)
+
+; TEST64:       .read_ll:
+; TEST64:         ld 3, L..C0(2)
+; TEST64-NEXT:    ld 3, 0(3)
 
-; TEST:       .read_ll:
-; TEST:         lwz 4, L..C0(2)
-; TEST-NEXT:    lwz 3, 0(4)
-; TEST-NEXT:    lwz 4, 4(4)
 
 define dso_local float @read_float() {
   entry:
     %0 = load float, float* @f, align 4
     ret float %0
 }
-; CHECK: name:            read_float
-; CHECK: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @f, $r2
-; CHECK: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]] :: (dereferenceable load (s32) from @f)
-
-; TEST:       .read_float:
-; TEST:         la 3, f[TD](2)
-; TEST-NEXT:    lfs 1, 0(3)
+; CHECK32: name:            read_float
+; CHECK32: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @f, $r2
+; CHECK32: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]] :: (dereferenceable load (s32) from @f)
+
+; TEST32:       .read_float:
+; TEST32:         la 3, f[TD](2)
+; TEST32-NEXT:    lfs 1, 0(3)
+
+; CHECK64: name:            read_float
+; CHECK64: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @f, $x2
+; CHECK64: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]] :: (dereferenceable load (s32) from @f)
+
+; TEST64:       .read_float:
+; TEST64:         la 3, f[TD](2)
+; TEST64-NEXT:    lfs 1, 0(3)
+
 
 define dso_local void @write_double(double %in) {
   entry:
     store double %in, double* @d, align 8
     ret void
 }
-; CHECK: name:            write_double
-; CHECK: LWZtoc @d, $r2 :: (load (s32) from got)
+; CHECK32: name:            write_double
+; CHECK32: LWZtoc @d, $r2 :: (load (s32) from got)
+
+; TEST32:       .write_double
+; TEST32:         lwz 3, L..C1(2)
+; TEST32-NEXT:    stfd 1, 0(3)
+
+; CHECK64: name:            write_double
+; CHECK64: LDtoc @d, $x2 :: (load (s64) from got)
+
+; TEST64:       .write_double
+; TEST64:         ld 3, L..C1(2)
+; TEST64-NEXT:    stfd 1, 0(3)
 
-; TEST:       .write_double
-; TEST:         lwz 3, L..C1(2)
-; TEST-NEXT:    stfd 1, 0(3)
 
 define dso_local nonnull i32* @addr() {
   entry:
     ret i32* @i
 }
-; CHECK: name:            addr
-; CHECK:       %[[SCRATCH:[0-9]+]]:gprc = ADDItoc @i, $r2
-; CHECK-NEXT:  $r3 = COPY %[[SCRATCH]]
-
-; TEST:       .addr
-; TEST:         la 3, i[TD](2)
-
+; CHECK32: name:            addr
+; CHECK32:       %[[SCRATCH:[0-9]+]]:gprc = ADDItoc @i, $r2
+; CHECK32-NEXT:  $r3 = COPY %[[SCRATCH]]
+
+; TEST32:       .addr
+; TEST32:         la 3, i[TD](2)
+
+; CHECK64: name:            addr
+; CHECK64:       %[[SCRATCH:[0-9]+]]:g8rc = ADDItoc8 @i, $x2
+; CHECK64-NEXT:  $x3 = COPY %[[SCRATCH]]
+
+; TEST64:       .addr
+; TEST64:         la 3, i[TD](2)
+
+; TEST32:         .toc
+; TEST32:           .tc ll[TC],ll[RW]
+; TEST32-NOT:       .csect ll[TD]
+; TEST32:           .tc d[TC],d[RW]
+; TEST32-NOT:       .csect d[TD],2
+; TEST32:           .csect i[TD],2
+; TEST32-NEXT:      .globl  i[TD]
+; TEST32-NEXT:      .align  2
+; TEST32-NOT:       .tc i[TC],i[RW]
+; TEST32:           .csect f[TD],2
+; TEST32-NEXT:      .globl f[TD]
+; TEST32-NOT:       .tc f[TD],f[RW]
+
+; TEST64:         .toc
+; TEST64:           .tc ll[TC],ll[RW]
+; TEST64-NOT:       .csect ll[TD]
+; TEST64:           .tc d[TC],d[RW]
+; TEST64-NOT:       .csect d[TD],2
+; TEST64:           .csect i[TD],2
+; TEST64-NEXT:      .globl  i[TD]
+; TEST64-NEXT:      .align  2
+; TEST64-NOT:       .tc i[TC],i[RW]
+; TEST64:           .csect f[TD],2
+; TEST64-NEXT:      .globl f[TD]
+; TEST64-NOT:       .tc f[TD],f[RW]
 
 attributes #0 = { "toc-data" }