[ARM] Convert fptoi.sat to fixed point multiply

[dmgreen]

Summary

This is a very small addition to the existing MVE fixed point vcvt code to also create them from FP_TO_SINT_SAT and FP_TO_UINT_SAT nodes, which should be equally valid for native saturating converts under MVE.

[samtebbs]

Nice

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

bool ARMDAGToDAGISel::tryFP_TO_INT(SDNode *N, SDLoc dl) {
   // Transform a floating-point to fixed-point conversion to a VCVT
   if (!Subtarget->hasMVEFloatOps())
     return false;
   EVT Type = N->getValueType(0);
   if (!Type.isVector())
     return false;
   unsigned int ScalarBits = Type.getScalarSizeInBits();
 
-  bool IsUnsigned = N->getOpcode() == ISD::FP_TO_UINT;
+  bool IsUnsigned = N->getOpcode() == ISD::FP_TO_UINT ||
+                    N->getOpcode() == ISD::FP_TO_UINT_SAT;
   SDNode *Node = N->getOperand(0).getNode();
 
   // floating-point to fixed-point with one fractional bit gets turned into an
   // FP_TO_[U|S]INT(FADD (x, x)) rather than an FP_TO_[U|S]INT(FMUL (x, y))
   if (Node->getOpcode() == ISD::FADD) {
     if (Node->getOperand(0) != Node->getOperand(1))
       return false;
     SDNodeFlags Flags = Node->getFlags();
case ISD::SRL:
     break;
   case ISD::SIGN_EXTEND_INREG:
   case ISD::SRA:
     if (tryV6T2BitfieldExtractOp(N, true))
       return;
     break;
   case ISD::FP_TO_UINT:
   case ISD::FP_TO_SINT:
+  case ISD::FP_TO_UINT_SAT:
+  case ISD::FP_TO_SINT_SAT:
     if (tryFP_TO_INT(N, dl))
       return;
     break;
   case ISD::FMUL:
     if (tryFMULFixed(N, dl))
       return;
     break;
   case ISD::MUL:

llvm/test/CodeGen/Thumb2/mve-vcvt-float-to-fixed.ll

; CHECK-NEXT:    bx lr
   ret <4 x i32> %3
 }
 
 
 
 define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_s16_1(<8 x half> %0) {
 ; CHECK-LABEL: vcvt_sat_s16_1:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vadd.f16 q0, q0, q0
-; CHECK-NEXT:    vcvt.s16.f16 q0, q0
+; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #1
 ; CHECK-NEXT:    bx lr
   %2 = fmul fast <8 x half> %0, <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000>
   %3 = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)
   ret <8 x i16> %3
 }
 
 define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_u16_1(<8 x half> %0) {
 ; CHECK-LABEL: vcvt_sat_u16_1:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vadd.f16 q0, q0, q0
-; CHECK-NEXT:    vcvt.u16.f16 q0, q0
+; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #1
 ; CHECK-NEXT:    bx lr
   %2 = fmul fast <8 x half> %0, <half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000, half 0xH4000>
   %3 = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)
   ret <8 x i16> %3
 }
 
 define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_s16_6(<8 x half> %0) {
 ; CHECK-LABEL: vcvt_sat_s16_6:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov.i16 q1, #0x5400
-; CHECK-NEXT:    vmul.f16 q0, q0, q1
-; CHECK-NEXT:    vcvt.s16.f16 q0, q0
+; CHECK-NEXT:    vcvt.s16.f16 q0, q0, #6
 ; CHECK-NEXT:    bx lr
   %2 = fmul fast <8 x half> %0, <half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400, half 0xH5400>
   %3 = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %2)
   ret <8 x i16> %3
 }
 
 define arm_aapcs_vfpcc <8 x i16> @vcvt_sat_u16_7(<8 x half> %0) {
 ; CHECK-LABEL: vcvt_sat_u16_7:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov.i16 q1, #0x5800
-; CHECK-NEXT:    vmul.f16 q0, q0, q1
-; CHECK-NEXT:    vcvt.u16.f16 q0, q0
+; CHECK-NEXT:    vcvt.u16.f16 q0, q0, #7
 ; CHECK-NEXT:    bx lr
   %2 = fmul fast <8 x half> %0, <half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800, half 0xH5800>
   %3 = call <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half> %2)
   ret <8 x i16> %3
 }
 
 
 define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_s32_1(<4 x float> %0) {
 ; CHECK-LABEL: vcvt_sat_s32_1:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vadd.f32 q0, q0, q0
-; CHECK-NEXT:    vcvt.s32.f32 q0, q0
+; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #1
 ; CHECK-NEXT:    bx lr
   %2 = fmul fast <4 x float> %0, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
   %3 = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %2)
   ret <4 x i32> %3
 }
 
 define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_1(<4 x float> %0) {
 ; CHECK-LABEL: vcvt_sat_u32_1:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vadd.f32 q0, q0, q0
-; CHECK-NEXT:    vcvt.u32.f32 q0, q0
+; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #1
 ; CHECK-NEXT:    bx lr
   %2 = fmul fast <4 x float> %0, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
   %3 = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %2)
   ret <4 x i32> %3
 }
 
 define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_11(<4 x float> %0) {
 ; CHECK-LABEL: vcvt_sat_u32_11:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov.i32 q1, #0x45000000
-; CHECK-NEXT:    vmul.f32 q0, q0, q1
-; CHECK-NEXT:    vcvt.s32.f32 q0, q0
+; CHECK-NEXT:    vcvt.s32.f32 q0, q0, #11
 ; CHECK-NEXT:    bx lr
   %2 = fmul fast <4 x float> %0, <float 2.048000e+03, float 2.048000e+03, float 2.048000e+03, float 2.048000e+03>
   %3 = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %2)
   ret <4 x i32> %3
 }
 
 define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_7(<4 x float> %0) {
 ; CHECK-LABEL: vcvt_sat_u32_7:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov.i32 q1, #0x4b000000
-; CHECK-NEXT:    vmul.f32 q0, q0, q1
-; CHECK-NEXT:    vcvt.u32.f32 q0, q0
+; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #23
 ; CHECK-NEXT:    bx lr
   %2 = fmul fast <4 x float> %0, <float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000>
   %3 = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %2)
   ret <4 x i32> %3
 }
 
 define arm_aapcs_vfpcc <4 x i32> @vcvt_sat_u32_7_24(<4 x float> %0) {
 ; CHECK-LABEL: vcvt_sat_u32_7_24:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov.i32 q2, #0x4b000000
 ; CHECK-NEXT:    vmov.i32 q1, #0xffffff
-; CHECK-NEXT:    vmul.f32 q0, q0, q2
-; CHECK-NEXT:    vcvt.u32.f32 q0, q0
+; CHECK-NEXT:    vcvt.u32.f32 q0, q0, #23
 ; CHECK-NEXT:    vmin.u32 q0, q0, q1
 ; CHECK-NEXT:    vbic.i32 q0, #0xff000000
 ; CHECK-NEXT:    bx lr
   %2 = fmul fast <4 x float> %0, <float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000, float 0x4160000000000000>
   %3 = call <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float> %2)
   %4 = zext <4 x i24> %3 to <4 x i32>
   ret <4 x i32> %4
 }
 
 declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float>)
 declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float>)
 declare <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float>)
 declare <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half>)
 declare <8 x i16> @llvm.fptoui.sat.v8i16.v8f16(<8 x half>)