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Differential D114353

[AMDGPU] Allow VOP3 source modifiers in fpow expansion
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Authored by foad on Nov 22 2021, 2:54 AM.

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Reviewers
arsenm
rampitec
Commits
rG44a3916f78b0: [AMDGPU] Allow VOP3 source modifiers in fpow expansion

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Event Timeline

foad created this revision.Nov 22 2021, 2:54 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 6 others. · View Herald TranscriptNov 22 2021, 2:54 AM
foad requested review of this revision.Nov 22 2021, 2:54 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 22 2021, 2:54 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B135371: Diff 388840.Nov 22 2021, 3:33 AM
rampitec accepted this revision.Nov 22 2021, 11:25 AM

LGTM. Thanks!

This revision is now accepted and ready to land.Nov 22 2021, 11:25 AM
Closed by commit rG44a3916f78b0: [AMDGPU] Allow VOP3 source modifiers in fpow expansion (authored by foad). · Explain WhyNov 22 2021, 12:40 PM
This revision was automatically updated to reflect the committed changes.
foad added a commit: rG44a3916f78b0: [AMDGPU] Allow VOP3 source modifiers in fpow expansion.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
9 lines
test/
CodeGen/
AMDGPU/
200 lines

Diff 388840

llvm/lib/Target/AMDGPU/SIInstructions.td

Show First 20 Lines • Show All 1,675 Lines • ▼ Show 20 Linesdef : GCNPat <
(f64 InlineImmFP64:$imm), (f64 InlineImmFP64:$imm),
(S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineImmFP64:$imm))) (S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineImmFP64:$imm)))
>; >;
/********** ================== **********/ /********** ================== **********/
/********** Intrinsic Patterns **********/ /********** Intrinsic Patterns **********/
/********** ================== **********/ /********** ================== **********/
let OtherPredicates = [isNotGFX90APlus] in
// FIXME: Should use _e64 and select source modifiers.
def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
let OtherPredicates = [isGFX90APlus] in
def : GCNPat < def : GCNPat <
(fpow f32:$src0, f32:$src1), (f32 (fpow (VOP3Mods f32:$src0, i32:$src0_mods), (VOP3Mods f32:$src1, i32:$src1_mods))),
(V_EXP_F32_e32 (V_MUL_LEGACY_F32_e64 0, f32:$src1, SRCMODS.NONE, (V_LOG_F32_e32 f32:$src0), 0, 0)) (V_EXP_F32_e64 SRCMODS.NONE, (V_MUL_LEGACY_F32_e64 $src1_mods, $src1, SRCMODS.NONE, (V_LOG_F32_e64 $src0_mods, $src0), 0, 0))
>; >;
def : GCNPat < def : GCNPat <
(i32 (sext i1:$src0)), (i32 (sext i1:$src0)),
(V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0), (V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
/*src1mod*/(i32 0), /*src1*/(i32 -1), $src0) /*src1mod*/(i32 0), /*src1*/(i32 -1), $src0)
>; >;
▲ Show 20 Lines • Show All 1,263 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fpow.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s ; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GFX6 %s
; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s ; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -march=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefix=GFX90A %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
define float @v_pow_f32(float %x, float %y) { define float @v_pow_f32(float %x, float %y) {
; GFX6-LABEL: v_pow_f32: ; GFX6-LABEL: v_pow_f32:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_log_f32_e32 v0, v0 ; GFX6-NEXT: v_log_f32_e32 v0, v0
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
Show All 11 Lines
; GFX9-LABEL: v_pow_f32: ; GFX9-LABEL: v_pow_f32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_log_f32_e32 v0, v0
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX90A-LABEL: v_pow_f32:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_log_f32_e32 v0, v0
; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32: ; GFX10-LABEL: v_pow_f32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_log_f32_e32 v0, v0
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
Show All 30 Lines
; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_log_f32_e32 v0, v0
; GFX9-NEXT: v_log_f32_e32 v1, v1 ; GFX9-NEXT: v_log_f32_e32 v1, v1
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v2, v0
; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 ; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v3, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: v_exp_f32_e32 v1, v1 ; GFX9-NEXT: v_exp_f32_e32 v1, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX90A-LABEL: v_pow_v2f32:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_log_f32_e32 v0, v0
; GFX90A-NEXT: v_log_f32_e32 v1, v1
; GFX90A-NEXT: v_mul_legacy_f32 v0, v2, v0
; GFX90A-NEXT: v_mul_legacy_f32 v1, v3, v1
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: v_exp_f32_e32 v1, v1
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f32: ; GFX10-LABEL: v_pow_v2f32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_log_f32_e32 v0, v0
; GFX10-NEXT: v_log_f32_e32 v1, v1 ; GFX10-NEXT: v_log_f32_e32 v1, v1
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v2, v0 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v2, v0
; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v3, v1 ; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v3, v1
Show All 34 Lines
; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_log_f32_e32 v0, v0
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX90A-LABEL: v_pow_f16:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX90A-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX90A-NEXT: v_log_f32_e32 v0, v0
; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f16: ; GFX10-LABEL: v_pow_f16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_log_f32_e32 v0, v0
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX9-NEXT: v_exp_f32_e32 v2, v2 ; GFX9-NEXT: v_exp_f32_e32 v2, v2
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2 ; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX90A-LABEL: v_pow_v2f16:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX90A-NEXT: v_log_f32_e32 v2, v2
; GFX90A-NEXT: v_log_f32_e32 v0, v0
; GFX90A-NEXT: v_mul_legacy_f32 v2, v3, v2
; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
; GFX90A-NEXT: v_exp_f32_e32 v2, v2
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: v_cvt_f16_f32_e32 v1, v2
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f16: ; GFX10-LABEL: v_pow_v2f16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX9-NEXT: v_exp_f32_e32 v2, v2 ; GFX9-NEXT: v_exp_f32_e32 v2, v2
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2 ; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX90A-LABEL: v_pow_v2f16_fneg_lhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e64 v0, -v0
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX90A-NEXT: v_log_f32_e32 v2, v2
; GFX90A-NEXT: v_log_f32_e32 v0, v0
; GFX90A-NEXT: v_mul_legacy_f32 v2, v3, v2
; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
; GFX90A-NEXT: v_exp_f32_e32 v2, v2
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: v_cvt_f16_f32_e32 v1, v2
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f16_fneg_lhs: ; GFX10-LABEL: v_pow_v2f16_fneg_lhs:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e64 v0, -v0 ; GFX10-NEXT: v_cvt_f32_f16_e64 v0, -v0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v1
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX9-NEXT: v_exp_f32_e32 v2, v2 ; GFX9-NEXT: v_exp_f32_e32 v2, v2
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2 ; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX90A-LABEL: v_pow_v2f16_fneg_rhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e64 v1, -v1
; GFX90A-NEXT: v_log_f32_e32 v2, v2
; GFX90A-NEXT: v_log_f32_e32 v0, v0
; GFX90A-NEXT: v_mul_legacy_f32 v2, v3, v2
; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
; GFX90A-NEXT: v_exp_f32_e32 v2, v2
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: v_cvt_f16_f32_e32 v1, v2
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f16_fneg_rhs: ; GFX10-LABEL: v_pow_v2f16_fneg_rhs:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e64 v1, -v1 ; GFX10-NEXT: v_cvt_f32_f16_e64 v1, -v1
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX9-NEXT: v_exp_f32_e32 v2, v2 ; GFX9-NEXT: v_exp_f32_e32 v2, v2
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2 ; GFX9-NEXT: v_cvt_f16_f32_e32 v1, v2
; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX90A-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e64 v0, -v0
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e64 v1, -v1
; GFX90A-NEXT: v_log_f32_e32 v2, v2
; GFX90A-NEXT: v_log_f32_e32 v0, v0
; GFX90A-NEXT: v_mul_legacy_f32 v2, v3, v2
; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
; GFX90A-NEXT: v_exp_f32_e32 v2, v2
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: v_cvt_f16_f32_e32 v1, v2
; GFX90A-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX90A-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f16_fneg_lhs_rhs: ; GFX10-LABEL: v_pow_v2f16_fneg_lhs_rhs:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-NEXT: v_cvt_f32_f16_sdwa v2, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e64 v0, -v0 ; GFX10-NEXT: v_cvt_f32_f16_e64 v0, -v0
; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_f16_e64 v1, -v1 ; GFX10-NEXT: v_cvt_f32_f16_e64 v1, -v1
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; %pow = call double @llvm.pow.f64(double %x, double %y) ; %pow = call double @llvm.pow.f64(double %x, double %y)
; ret double %pow ; ret double %pow
; } ; }
define float @v_pow_f32_fabs_lhs(float %x, float %y) { define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX6-LABEL: v_pow_f32_fabs_lhs: ; GFX6-LABEL: v_pow_f32_fabs_lhs:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GFX6-NEXT: v_log_f32_e64 v0, |v0|
; GFX6-NEXT: v_log_f32_e32 v0, v0
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: v_exp_f32_e32 v0, v0
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_pow_f32_fabs_lhs: ; GFX8-LABEL: v_pow_f32_fabs_lhs:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GFX8-NEXT: v_log_f32_e64 v0, |v0|
; GFX8-NEXT: v_log_f32_e32 v0, v0
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: v_exp_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_pow_f32_fabs_lhs: ; GFX9-LABEL: v_pow_f32_fabs_lhs:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GFX9-NEXT: v_log_f32_e64 v0, |v0|
; GFX9-NEXT: v_log_f32_e32 v0, v0
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX90A-LABEL: v_pow_f32_fabs_lhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_log_f32_e64 v0, |v0|
; GFX90A-NEXT: v_mul_legacy_f32 v0, v1, v0
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_lhs: ; GFX10-LABEL: v_pow_f32_fabs_lhs:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GFX10-NEXT: v_log_f32_e64 v0, |v0|
; GFX10-NEXT: v_log_f32_e32 v0, v0
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x) %fabs.x = call float @llvm.fabs.f32(float %x)
%pow = call float @llvm.pow.f32(float %fabs.x, float %y) %pow = call float @llvm.pow.f32(float %fabs.x, float %y)
ret float %pow ret float %pow
} }
define float @v_pow_f32_fabs_rhs(float %x, float %y) { define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX6-LABEL: v_pow_f32_fabs_rhs: ; GFX6-LABEL: v_pow_f32_fabs_rhs:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_log_f32_e32 v0, v0 ; GFX6-NEXT: v_log_f32_e32 v0, v0
; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 ; GFX6-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: v_exp_f32_e32 v0, v0
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_pow_f32_fabs_rhs: ; GFX8-LABEL: v_pow_f32_fabs_rhs:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_log_f32_e32 v0, v0 ; GFX8-NEXT: v_log_f32_e32 v0, v0
; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 ; GFX8-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: v_exp_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_pow_f32_fabs_rhs: ; GFX9-LABEL: v_pow_f32_fabs_rhs:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_log_f32_e32 v0, v0
; GFX9-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 ; GFX9-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX90A-LABEL: v_pow_f32_fabs_rhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_log_f32_e32 v0, v0
; GFX90A-NEXT: v_mul_legacy_f32 v0, |v1|, v0
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_rhs: ; GFX10-LABEL: v_pow_f32_fabs_rhs:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_log_f32_e32 v0, v0
; GFX10-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 ; GFX10-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y) %fabs.y = call float @llvm.fabs.f32(float %y)
%pow = call float @llvm.pow.f32(float %x, float %fabs.y) %pow = call float @llvm.pow.f32(float %x, float %fabs.y)
ret float %pow ret float %pow
} }
define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) { define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX6-LABEL: v_pow_f32_fabs_lhs_rhs: ; GFX6-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_brev_b32 s4, -2 ; GFX6-NEXT: v_log_f32_e64 v0, |v0|
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 ; GFX6-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
; GFX6-NEXT: v_log_f32_e32 v0, v0
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX6-NEXT: v_exp_f32_e32 v0, v0 ; GFX6-NEXT: v_exp_f32_e32 v0, v0
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs: ; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_brev_b32 s4, -2 ; GFX8-NEXT: v_log_f32_e64 v0, |v0|
; GFX8-NEXT: v_and_b32_e32 v0, s4, v0 ; GFX8-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
; GFX8-NEXT: v_log_f32_e32 v0, v0
; GFX8-NEXT: v_and_b32_e32 v1, s4, v1
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX8-NEXT: v_exp_f32_e32 v0, v0 ; GFX8-NEXT: v_exp_f32_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs: ; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_brev_b32 s4, -2 ; GFX9-NEXT: v_log_f32_e64 v0, |v0|
; GFX9-NEXT: v_and_b32_e32 v0, s4, v0 ; GFX9-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
; GFX9-NEXT: v_log_f32_e32 v0, v0
; GFX9-NEXT: v_and_b32_e32 v1, s4, v1
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX90A-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX90A-NEXT: v_log_f32_e64 v0, |v0|
; GFX90A-NEXT: v_mul_legacy_f32 v0, |v1|, v0
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs: ; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_brev_b32 s4, -2 ; GFX10-NEXT: v_log_f32_e64 v0, |v0|
; GFX10-NEXT: v_and_b32_e32 v0, s4, v0 ; GFX10-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
; GFX10-NEXT: v_and_b32_e32 v1, s4, v1
; GFX10-NEXT: v_log_f32_e32 v0, v0
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x) %fabs.x = call float @llvm.fabs.f32(float %x)
%fabs.y = call float @llvm.fabs.f32(float %y) %fabs.y = call float @llvm.fabs.f32(float %y)
%pow = call float @llvm.pow.f32(float %fabs.x, float %fabs.y) %pow = call float @llvm.pow.f32(float %fabs.x, float %fabs.y)
ret float %pow ret float %pow
} }
Show All 14 Lines
; ;
; GFX9-LABEL: v_pow_f32_sgpr_vgpr: ; GFX9-LABEL: v_pow_f32_sgpr_vgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_log_f32_e32 v1, s0 ; GFX9-NEXT: v_log_f32_e32 v1, s0
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX90A-LABEL: v_pow_f32_sgpr_vgpr:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: v_log_f32_e32 v1, s0
; GFX90A-NEXT: v_mul_legacy_f32 v0, v0, v1
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_pow_f32_sgpr_vgpr: ; GFX10-LABEL: v_pow_f32_sgpr_vgpr:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_log_f32_e32 v1, s0 ; GFX10-NEXT: v_log_f32_e32 v1, s0
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y) %pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow ret float %pow
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; ;
; GFX9-LABEL: v_pow_f32_vgpr_sgpr: ; GFX9-LABEL: v_pow_f32_vgpr_sgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_log_f32_e32 v0, v0 ; GFX9-NEXT: v_log_f32_e32 v0, v0
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX90A-LABEL: v_pow_f32_vgpr_sgpr:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: v_log_f32_e32 v0, v0
; GFX90A-NEXT: v_mul_legacy_f32 v0, s0, v0
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_pow_f32_vgpr_sgpr: ; GFX10-LABEL: v_pow_f32_vgpr_sgpr:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_log_f32_e32 v0, v0 ; GFX10-NEXT: v_log_f32_e32 v0, v0
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s0, v0 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y) %pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow ret float %pow
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; ;
; GFX9-LABEL: v_pow_f32_sgpr_sgpr: ; GFX9-LABEL: v_pow_f32_sgpr_sgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_log_f32_e32 v0, s0 ; GFX9-NEXT: v_log_f32_e32 v0, s0
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 ; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
; GFX9-NEXT: v_exp_f32_e32 v0, v0 ; GFX9-NEXT: v_exp_f32_e32 v0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX90A-LABEL: v_pow_f32_sgpr_sgpr:
; GFX90A: ; %bb.0:
; GFX90A-NEXT: v_log_f32_e32 v0, s0
; GFX90A-NEXT: v_mul_legacy_f32 v0, s1, v0
; GFX90A-NEXT: v_exp_f32_e32 v0, v0
; GFX90A-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_pow_f32_sgpr_sgpr: ; GFX10-LABEL: v_pow_f32_sgpr_sgpr:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_log_f32_e32 v0, s0 ; GFX10-NEXT: v_log_f32_e32 v0, s0
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0 ; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
; GFX10-NEXT: v_exp_f32_e32 v0, v0 ; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y) %pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow ret float %pow
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