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Differential D114349

[ARM] CSINC/CSINV patterns from CMOV
ClosedPublic

Authored by dmgreen on Nov 22 2021, 12:10 AM.

Details

Reviewers
SjoerdMeijer
samtebbs
ostannard
simon_tatham
sjarus
Commits
rG5c64d8ef8cc0: [ARM] CSINC/CSINV patterns from CMOV
Summary

We sometimes end up generating CMOV with constant operands that can be simplified to CSINC or CSINV under Arm-8.1m. This adds some simple patterns for them.

Diff Detail

Event Timeline

dmgreen created this revision.Nov 22 2021, 12:10 AM
Herald added a reviewer: sjarus. · View Herald TranscriptNov 22 2021, 12:10 AM
Herald added subscribers: armkevincheng, jsmolens, eric-k256 and 2 others. · View Herald Transcript
dmgreen requested review of this revision.Nov 22 2021, 12:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 22 2021, 12:10 AM
Harbormaster completed remote builds in B135345: Diff 388806.Nov 22 2021, 12:11 AM
dmgreen added a parent revision: D114013: [ARM] Fold away unnecessary CSET/CMPZ.Nov 23 2021, 3:04 AM
dmgreen added a child revision: D114449: [ARM] Make v2i1 legal.Nov 23 2021, 2:13 PM
samtebbs accepted this revision.Nov 26 2021, 7:12 AM

👍

This revision is now accepted and ready to land.Nov 26 2021, 7:12 AM
This revision was landed with ongoing or failed builds.Nov 27 2021, 12:21 PM
Closed by commit rG5c64d8ef8cc0: [ARM] CSINC/CSINV patterns from CMOV (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG5c64d8ef8cc0: [ARM] CSINC/CSINV patterns from CMOV.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
9 lines
test/
CodeGen/
Thumb2/
84 lines
552 lines
1371 lines
464 lines
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128 lines
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Diff 390171

llvm/lib/Target/ARM/ARMInstrThumb2.td

Show First 20 Lines • Show All 5,597 Lines • ▼ Show 20 Lines multiclass CSPats<SDNode Node, Instruction Insn> {
def : T2Pat<(Node (i32 0), (i32 0), imm0_31:$imm), def : T2Pat<(Node (i32 0), (i32 0), imm0_31:$imm),
(Insn ZR, ZR, imm0_31:$imm)>; (Insn ZR, ZR, imm0_31:$imm)>;
} }
defm : CSPats<ARMcsinc, t2CSINC>; defm : CSPats<ARMcsinc, t2CSINC>;
defm : CSPats<ARMcsinv, t2CSINV>; defm : CSPats<ARMcsinv, t2CSINV>;
defm : CSPats<ARMcsneg, t2CSNEG>; defm : CSPats<ARMcsneg, t2CSNEG>;
def : T2Pat<(ARMcmov (i32 1), (i32 0), cmovpred:$imm),
(t2CSINC ZR, ZR, imm0_31:$imm)>;
def : T2Pat<(ARMcmov (i32 -1), (i32 0), cmovpred:$imm),
(t2CSINV ZR, ZR, imm0_31:$imm)>;
def : T2Pat<(ARMcmov (i32 0), (i32 1), cmovpred:$imm),
(t2CSINC ZR, ZR, (inv_cond_XFORM imm:$imm))>;
def : T2Pat<(ARMcmov (i32 0), (i32 -1), cmovpred:$imm),
(t2CSINV ZR, ZR, (inv_cond_XFORM imm:$imm))>;
multiclass ModifiedV8_1CSEL<Instruction Insn, dag modvalue> { multiclass ModifiedV8_1CSEL<Instruction Insn, dag modvalue> {
def : T2Pat<(ARMcmov modvalue, GPRwithZR:$tval, cmovpred:$imm), def : T2Pat<(ARMcmov modvalue, GPRwithZR:$tval, cmovpred:$imm),
(Insn GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>; (Insn GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>;
def : T2Pat<(ARMcmov GPRwithZR:$tval, modvalue, cmovpred:$imm), def : T2Pat<(ARMcmov GPRwithZR:$tval, modvalue, cmovpred:$imm),
(Insn GPRwithZR:$tval, GPRwithZR:$fval, (Insn GPRwithZR:$tval, GPRwithZR:$fval,
(i32 (inv_cond_XFORM imm:$imm)))>; (i32 (inv_cond_XFORM imm:$imm)))>;
} }
defm : ModifiedV8_1CSEL<t2CSINC, (add rGPR:$fval, 1)>; defm : ModifiedV8_1CSEL<t2CSINC, (add rGPR:$fval, 1)>;
Show All 21 Lines

llvm/test/CodeGen/Thumb2/active_lane_mask.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve %s -o - | FileCheck %s
define <2 x i64> @v2i64(i32 %index, i32 %TC, <2 x i64> %V1, <2 x i64> %V2) { define <2 x i64> @v2i64(i32 %index, i32 %TC, <2 x i64> %V1, <2 x i64> %V2) {
; CHECK-LABEL: v2i64: ; CHECK-LABEL: v2i64:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: vmov q0[2], q0[0], r0, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r0
; CHECK-NEXT: vmov.i64 q1, #0xffffffff ; CHECK-NEXT: vmov.i64 q1, #0xffffffff
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vmov q2[2], q2[0], r1, r1 ; CHECK-NEXT: vmov q2[2], q2[0], r1, r1
; CHECK-NEXT: vmov r0, r12, d1 ; CHECK-NEXT: vmov r0, r12, d1
; CHECK-NEXT: movs r7, #0 ; CHECK-NEXT: vmov lr, s0
; CHECK-NEXT: adds.w r8, r0, #1 ; CHECK-NEXT: adds r0, #1
; CHECK-NEXT: adc lr, r12, #0 ; CHECK-NEXT: vmov q0[2], q0[0], lr, r0
; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: adc r12, r12, #0
; CHECK-NEXT: vmov q0[2], q0[0], r12, r8
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vand q1, q2, q1 ; CHECK-NEXT: vand q1, q2, q1
; CHECK-NEXT: vmov r4, r5, d1 ; CHECK-NEXT: vmov r4, r5, d1
; CHECK-NEXT: vmov.i32 q2, #0x1 ; CHECK-NEXT: vmov.i32 q2, #0x1
; CHECK-NEXT: vmov r1, r6, d3 ; CHECK-NEXT: vmov r1, r6, d3
; CHECK-NEXT: eors r0, r4
; CHECK-NEXT: subs r1, r4, r1 ; CHECK-NEXT: subs r1, r4, r1
; CHECK-NEXT: sbcs.w r1, r5, r6 ; CHECK-NEXT: sbcs.w r1, r5, r6
; CHECK-NEXT: vmov r5, r6, d0 ; CHECK-NEXT: vmov r5, r6, d0
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r1, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmov r0, r1, d2 ; CHECK-NEXT: vmov r7, r1, d2
; CHECK-NEXT: csetm r9, ne ; CHECK-NEXT: csetm r8, ne
; CHECK-NEXT: subs r0, r5, r0 ; CHECK-NEXT: subs r7, r5, r7
; CHECK-NEXT: sbcs.w r0, r6, r1 ; CHECK-NEXT: sbcs.w r1, r6, r1
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r1, lo
; CHECK-NEXT: movlo r7, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: orrs.w r0, r0, r12
; CHECK-NEXT: vmov q0[2], q0[0], r0, r9
; CHECK-NEXT: eor.w r0, r4, r8
; CHECK-NEXT: orrs.w r0, r0, lr
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: teq.w r5, r12 ; CHECK-NEXT: teq.w r5, lr
; CHECK-NEXT: vmov q0[2], q0[0], r1, r8
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: veor q1, q1, q2 ; CHECK-NEXT: veor q1, q1, q2
; CHECK-NEXT: vldr d5, [sp, #32] ; CHECK-NEXT: vldr d5, [sp, #24]
; CHECK-NEXT: vand q0, q1, q0 ; CHECK-NEXT: vand q0, q1, q0
; CHECK-NEXT: vmov d4, r2, r3 ; CHECK-NEXT: vmov d4, r2, r3
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: and r1, r1, #1 ; CHECK-NEXT: and r1, r1, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: add r0, sp, #40 ; CHECK-NEXT: add r0, sp, #32
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vbic q1, q1, q0 ; CHECK-NEXT: vbic q1, q1, q0
; CHECK-NEXT: vand q0, q2, q0 ; CHECK-NEXT: vand q0, q2, q0
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: vmov r0, r1, d0 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
%active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %TC) %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %TC)
%select = select <2 x i1> %active.lane.mask, <2 x i64> %V1, <2 x i64> %V2 %select = select <2 x i1> %active.lane.mask, <2 x i64> %V1, <2 x i64> %V2
ret <2 x i64> %select ret <2 x i64> %select
} }
define <4 x i32> @v4i32(i32 %index, i32 %TC, <4 x i32> %V1, <4 x i32> %V2) { define <4 x i32> @v4i32(i32 %index, i32 %TC, <4 x i32> %V1, <4 x i32> %V2) {
; CHECK-LABEL: v4i32: ; CHECK-LABEL: v4i32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
▲ Show 20 Lines • Show All 387 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov q1[2], q1[0], r2, r2 ; CHECK-NEXT: vmov q1[2], q1[0], r2, r2
; CHECK-NEXT: bic r0, r0, #1 ; CHECK-NEXT: bic r0, r0, #1
; CHECK-NEXT: adr r2, .LCPI5_0 ; CHECK-NEXT: adr r2, .LCPI5_0
; CHECK-NEXT: subs r0, #2 ; CHECK-NEXT: subs r0, #2
; CHECK-NEXT: movs r3, #1 ; CHECK-NEXT: movs r3, #1
; CHECK-NEXT: vmov.i64 q0, #0xffffffff ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
; CHECK-NEXT: vldrw.u32 q2, [r2] ; CHECK-NEXT: vldrw.u32 q2, [r2]
; CHECK-NEXT: add.w lr, r3, r0, lsr #1 ; CHECK-NEXT: add.w lr, r3, r0, lsr #1
; CHECK-NEXT: mov.w r12, #0 ; CHECK-NEXT: mov.w r8, #0
; CHECK-NEXT: vand q1, q1, q0 ; CHECK-NEXT: vand q1, q1, q0
; CHECK-NEXT: .LBB5_2: @ %vector.body ; CHECK-NEXT: .LBB5_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmov q3[2], q3[0], r12, r12 ; CHECK-NEXT: vmov q3[2], q3[0], r8, r8
; CHECK-NEXT: vmov r6, r7, d3 ; CHECK-NEXT: vmov r6, r7, d3
; CHECK-NEXT: vand q3, q3, q0 ; CHECK-NEXT: vand q3, q3, q0
; CHECK-NEXT: add.w r12, r12, #2 ; CHECK-NEXT: add.w r8, r8, #2
; CHECK-NEXT: vmov r2, r3, d7 ; CHECK-NEXT: vmov r2, r3, d7
; CHECK-NEXT: vmov r9, s12 ; CHECK-NEXT: vmov r9, s12
; CHECK-NEXT: adds r0, r2, #1 ; CHECK-NEXT: adds r2, #1
; CHECK-NEXT: vmov q3[2], q3[0], r9, r0 ; CHECK-NEXT: vmov q3[2], q3[0], r9, r2
; CHECK-NEXT: adc r8, r3, #0 ; CHECK-NEXT: adc r12, r3, #0
; CHECK-NEXT: vand q3, q3, q0 ; CHECK-NEXT: vand q3, q3, q0
; CHECK-NEXT: vmov r3, r2, d2 ; CHECK-NEXT: vmov r0, r3, d2
; CHECK-NEXT: vmov r4, r5, d7 ; CHECK-NEXT: vmov r4, r5, d7
; CHECK-NEXT: subs r6, r4, r6 ; CHECK-NEXT: subs r6, r4, r6
; CHECK-NEXT: eor.w r0, r0, r4
; CHECK-NEXT: sbcs r5, r7 ; CHECK-NEXT: sbcs r5, r7
; CHECK-NEXT: vmov r6, r7, d6 ; CHECK-NEXT: vmov r6, r7, d6
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csetm r5, ne ; CHECK-NEXT: csetm r5, ne
; CHECK-NEXT: subs r3, r6, r3 ; CHECK-NEXT: subs r0, r6, r0
; CHECK-NEXT: sbcs.w r2, r7, r2 ; CHECK-NEXT: sbcs.w r0, r7, r3
; CHECK-NEXT: mov.w r2, #0 ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: it lo ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: movlo r2, #1 ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: vmov q3[2], q3[0], r0, r5
; CHECK-NEXT: csetm r2, ne ; CHECK-NEXT: vmov q3[3], q3[1], r0, r5
; CHECK-NEXT: orrs.w r0, r0, r8 ; CHECK-NEXT: eor.w r0, r4, r2
; CHECK-NEXT: vmov q3[2], q3[0], r2, r5 ; CHECK-NEXT: orrs.w r0, r0, r12
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: teq.w r6, r9 ; CHECK-NEXT: teq.w r6, r9
; CHECK-NEXT: vmov q3[3], q3[1], r2, r5
; CHECK-NEXT: csetm r2, ne ; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov q4[2], q4[0], r2, r0 ; CHECK-NEXT: vmov q4[2], q4[0], r2, r0
; CHECK-NEXT: vmov q4[3], q4[1], r2, r0 ; CHECK-NEXT: vmov q4[3], q4[1], r2, r0
; CHECK-NEXT: veor q4, q4, q2 ; CHECK-NEXT: veor q4, q4, q2
; CHECK-NEXT: vand q4, q4, q3 ; CHECK-NEXT: vand q4, q4, q3
; CHECK-NEXT: @ implicit-def: $q3 ; CHECK-NEXT: @ implicit-def: $q3
; CHECK-NEXT: vmov r2, s16 ; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vmov r0, s18 ; CHECK-NEXT: vmov r0, s18
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-fmas.ll

Show First 20 Lines • Show All 398 Lines • ▼ Show 20 Lines
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_v1_pred: ; CHECK-MVE-LABEL: vfma16_v1_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s14, s4 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmovx.f16 s13, s0 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s0 ; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14 ; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14
; CHECK-MVE-NEXT: vmovx.f16 s8, s5 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vins.f16 s0, s12 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s1 ; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmov.f32 s14, s12 ; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14 ; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
; CHECK-MVE-NEXT: vmov.f32 s8, s1 ; CHECK-MVE-NEXT: vmov.f32 s8, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmla.f16 s8, s5, s9 ; CHECK-MVE-NEXT: vmla.f16 s8, s5, s9
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8 ; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s6 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vcmp.f16 s8, #0 ; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4 ; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vmov.f32 s8, s2 ; CHECK-MVE-NEXT: vmov.f32 s8, s2
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10 ; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s6, s7 ; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8 ; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s3 ; CHECK-MVE-NEXT: vmovx.f16 s8, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmov.f32 s10, s8 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4 ; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0 ; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vmov.f32 s6, s3 ; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: vmla.f16 s6, s7, s11
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmla.f16 s6, s7, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6 ; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %src1, %0 %1 = fadd <8 x half> %src1, %0
%c = fcmp olt <8 x half> %src2, zeroinitializer %c = fcmp olt <8 x half> %src2, zeroinitializer
Show All 16 Lines
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_v2_pred: ; CHECK-MVE-LABEL: vfma16_v2_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s14, s4 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmovx.f16 s13, s0 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmla.f16 s15, s14, s12
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s0 ; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vmla.f16 s14, s4, s8 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14 ; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14
; CHECK-MVE-NEXT: vmovx.f16 s8, s5 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vins.f16 s0, s12 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s1 ; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmov.f32 s14, s12 ; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14 ; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
; CHECK-MVE-NEXT: vmov.f32 s8, s1 ; CHECK-MVE-NEXT: vmov.f32 s8, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmla.f16 s8, s5, s9 ; CHECK-MVE-NEXT: vmla.f16 s8, s5, s9
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8 ; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s6 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vcmp.f16 s8, #0 ; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4 ; CHECK-MVE-NEXT: vmla.f16 s14, s8, s4
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vmov.f32 s8, s2 ; CHECK-MVE-NEXT: vmov.f32 s8, s2
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10 ; CHECK-MVE-NEXT: vmla.f16 s8, s6, s10
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s6, s7 ; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8 ; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s3 ; CHECK-MVE-NEXT: vmovx.f16 s8, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmov.f32 s10, s8 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4 ; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0 ; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vmov.f32 s6, s3 ; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: vmla.f16 s6, s7, s11
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmla.f16 s6, s7, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6 ; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fadd <8 x half> %0, %src1 %1 = fadd <8 x half> %0, %src1
%c = fcmp olt <8 x half> %src2, zeroinitializer %c = fcmp olt <8 x half> %src2, zeroinitializer
Show All 16 Lines
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfms16_pred: ; CHECK-MVE-LABEL: vfms16_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s14, s4 ; CHECK-MVE-NEXT: vmovx.f16 s14, s4
; CHECK-MVE-NEXT: vmovx.f16 s13, s0 ; CHECK-MVE-NEXT: vmovx.f16 s13, s0
; CHECK-MVE-NEXT: vcmp.f16 s14, #0 ; CHECK-MVE-NEXT: vcmp.f16 s14, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s8 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8
; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmov.f32 s15, s13
; CHECK-MVE-NEXT: vmls.f16 s15, s14, s12 ; CHECK-MVE-NEXT: vmls.f16 s15, s14, s12
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s0 ; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: vmls.f16 s14, s4, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s5
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15 ; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s15
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vmls.f16 s14, s4, s8 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14 ; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s14
; CHECK-MVE-NEXT: vmovx.f16 s8, s5 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vins.f16 s0, s12 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s1 ; CHECK-MVE-NEXT: vmovx.f16 s12, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmov.f32 s14, s12 ; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14 ; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4
; CHECK-MVE-NEXT: vmov.f32 s8, s1 ; CHECK-MVE-NEXT: vmov.f32 s8, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmls.f16 s8, s5, s9 ; CHECK-MVE-NEXT: vmls.f16 s8, s5, s9
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8 ; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s6 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmovx.f16 s12, s2
; CHECK-MVE-NEXT: vcmp.f16 s8, #0 ; CHECK-MVE-NEXT: vcmp.f16 s8, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4 ; CHECK-MVE-NEXT: vmls.f16 s14, s8, s4
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vmov.f32 s8, s2 ; CHECK-MVE-NEXT: vmov.f32 s8, s2
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmls.f16 s8, s6, s10 ; CHECK-MVE-NEXT: vmls.f16 s8, s6, s10
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s6, s7 ; CHECK-MVE-NEXT: vmovx.f16 s6, s7
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s14
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8 ; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s3 ; CHECK-MVE-NEXT: vmovx.f16 s8, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmov.f32 s10, s8 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmls.f16 s10, s6, s4 ; CHECK-MVE-NEXT: vmls.f16 s10, s6, s4
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s7, #0 ; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vmov.f32 s6, s3 ; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: vmls.f16 s6, s7, s11
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s10
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmls.f16 s6, s7, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6 ; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <8 x half> %src2, %src3 %0 = fmul <8 x half> %src2, %src3
%1 = fsub <8 x half> %src1, %0 %1 = fsub <8 x half> %src1, %0
%c = fcmp olt <8 x half> %src2, zeroinitializer %c = fcmp olt <8 x half> %src2, zeroinitializer
Show All 21 Lines
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmar16_pred: ; CHECK-MVE-LABEL: vfmar16_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s10, s4 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: vcmp.f16 s10, #0 ; CHECK-MVE-NEXT: vcmp.f16 s10, #0
; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmov.f32 s14, s12
; CHECK-MVE-NEXT: vmla.f16 s14, s10, s8 ; CHECK-MVE-NEXT: vmla.f16 s14, s10, s8
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s10, s12, s14 ; CHECK-MVE-NEXT: vseleq.f16 s10, s12, s14
; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8 ; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vins.f16 s0, s10 ; CHECK-MVE-NEXT: vins.f16 s0, s10
; CHECK-MVE-NEXT: vmovx.f16 s10, s1 ; CHECK-MVE-NEXT: vmovx.f16 s10, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s10 ; CHECK-MVE-NEXT: vmov.f32 s12, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12 ; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
; CHECK-MVE-NEXT: vmov.f32 s10, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmov.f32 s10, s1
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s10, s5, s8 ; CHECK-MVE-NEXT: vmla.f16 s10, s5, s8
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s10 ; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s10
; CHECK-MVE-NEXT: vmovx.f16 s10, s2 ; CHECK-MVE-NEXT: vmovx.f16 s10, s2
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s10 ; CHECK-MVE-NEXT: vmov.f32 s12, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8 ; CHECK-MVE-NEXT: vmla.f16 s12, s4, s8
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12 ; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
; CHECK-MVE-NEXT: vmov.f32 s10, s2
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmov.f32 s10, s2
; CHECK-MVE-NEXT: vmla.f16 s10, s6, s8 ; CHECK-MVE-NEXT: vmla.f16 s10, s6, s8
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10
; CHECK-MVE-NEXT: vmov.f32 s10, s6
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmla.f16 s10, s4, s8 ; CHECK-MVE-NEXT: vmla.f16 s10, s4, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s7, #0 ; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10
; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: vmov.f32 s6, s3
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmla.f16 s6, s7, s8 ; CHECK-MVE-NEXT: vmla.f16 s6, s7, s8
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6 ; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s6
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%src3 = fptrunc float %src3o to half %src3 = fptrunc float %src3o to half
%i = insertelement <8 x half> undef, half %src3, i32 0 %i = insertelement <8 x half> undef, half %src3, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
Show All 23 Lines
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_pred: ; CHECK-MVE-LABEL: vfma16_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s10, s4 ; CHECK-MVE-NEXT: vmovx.f16 s10, s4
; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-NEXT: vcmp.f16 s10, #0 ; CHECK-MVE-NEXT: vcmp.f16 s10, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: vmov.f32 s14, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmov.f32 s14, s8
; CHECK-MVE-NEXT: vmla.f16 s14, s12, s10 ; CHECK-MVE-NEXT: vmla.f16 s14, s12, s10
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s10, s12, s14 ; CHECK-MVE-NEXT: vseleq.f16 s10, s12, s14
; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: vmla.f16 s12, s0, s4 ; CHECK-MVE-NEXT: vmla.f16 s12, s0, s4
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vins.f16 s0, s10 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s0, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vins.f16 s0, s10
; CHECK-MVE-NEXT: vmovx.f16 s10, s1 ; CHECK-MVE-NEXT: vmovx.f16 s10, s1
; CHECK-MVE-NEXT: vmov.f32 s12, s8 ; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4
; CHECK-MVE-NEXT: vcmp.f16 s5, #0 ; CHECK-MVE-NEXT: vcmp.f16 s5, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12 ; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s10, s1, s5 ; CHECK-MVE-NEXT: vmla.f16 s10, s1, s5
; CHECK-MVE-NEXT: vmov.f32 s12, s8 ; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s10 ; CHECK-MVE-NEXT: vseleq.f16 s1, s1, s10
; CHECK-MVE-NEXT: vmovx.f16 s10, s2 ; CHECK-MVE-NEXT: vmovx.f16 s10, s2
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4 ; CHECK-MVE-NEXT: vmla.f16 s12, s10, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s6, #0 ; CHECK-MVE-NEXT: vcmp.f16 s6, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12 ; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s12
; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmla.f16 s10, s2, s6 ; CHECK-MVE-NEXT: vmla.f16 s10, s2, s6
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s2, s10
; CHECK-MVE-NEXT: vmov.f32 s10, s8 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4 ; CHECK-MVE-NEXT: vmla.f16 s10, s6, s4
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s7, #0 ; CHECK-MVE-NEXT: vcmp.f16 s7, #0
; CHECK-MVE-NEXT: vmla.f16 s8, s3, s7
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s10
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmla.f16 s8, s3, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s8 ; CHECK-MVE-NEXT: vseleq.f16 s3, s3, s8
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%src3 = fptrunc float %src3o to half %src3 = fptrunc float %src3o to half
%i = insertelement <8 x half> undef, half %src3, i32 0 %i = insertelement <8 x half> undef, half %src3, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
Show All 15 Lines
; CHECK-MVE-VMLA-LABEL: vfma32_v1_pred: ; CHECK-MVE-VMLA-LABEL: vfma32_v1_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma32_v1_pred: ; CHECK-MVE-LABEL: vfma32_v1_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0 ; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: vmov.f32 s12, s1 ; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8 ; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vmov.f32 s4, s3 ; CHECK-MVE-NEXT: vmov.f32 s4, s3
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vmov.f32 s8, s2 ; CHECK-MVE-NEXT: vmov.f32 s8, s2
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9 ; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9
; CHECK-MVE-NEXT: vmla.f32 s4, s7, s11 ; CHECK-MVE-NEXT: vmla.f32 s4, s7, s11
; CHECK-MVE-NEXT: vmla.f32 s8, s6, s10 ; CHECK-MVE-NEXT: vmla.f32 s8, s6, s10
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4 ; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8 ; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12 ; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14 ; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <4 x float> %src2, %src3 %0 = fmul <4 x float> %src2, %src3
%1 = fadd <4 x float> %src1, %0 %1 = fadd <4 x float> %src1, %0
%c = fcmp olt <4 x float> %src2, zeroinitializer %c = fcmp olt <4 x float> %src2, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1
ret <4 x float> %s ret <4 x float> %s
Show All 10 Lines
; CHECK-MVE-VMLA-LABEL: vfma32_v2_pred: ; CHECK-MVE-VMLA-LABEL: vfma32_v2_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma32_v2_pred: ; CHECK-MVE-LABEL: vfma32_v2_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0 ; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: vmov.f32 s12, s1 ; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8 ; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vmov.f32 s4, s3 ; CHECK-MVE-NEXT: vmov.f32 s4, s3
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vmov.f32 s8, s2 ; CHECK-MVE-NEXT: vmov.f32 s8, s2
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9 ; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9
; CHECK-MVE-NEXT: vmla.f32 s4, s7, s11 ; CHECK-MVE-NEXT: vmla.f32 s4, s7, s11
; CHECK-MVE-NEXT: vmla.f32 s8, s6, s10 ; CHECK-MVE-NEXT: vmla.f32 s8, s6, s10
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4 ; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8 ; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12 ; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14 ; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <4 x float> %src2, %src3 %0 = fmul <4 x float> %src2, %src3
%1 = fadd <4 x float> %0, %src1 %1 = fadd <4 x float> %0, %src1
%c = fcmp olt <4 x float> %src2, zeroinitializer %c = fcmp olt <4 x float> %src2, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1
ret <4 x float> %s ret <4 x float> %s
Show All 10 Lines
; CHECK-MVE-VMLA-LABEL: vfms32_pred: ; CHECK-MVE-VMLA-LABEL: vfms32_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmst.f32 q0, q1, q2 ; CHECK-MVE-VMLA-NEXT: vfmst.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfms32_pred: ; CHECK-MVE-LABEL: vfms32_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0 ; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s0
; CHECK-MVE-NEXT: vmov.f32 s12, s1 ; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmls.f32 s14, s4, s8 ; CHECK-MVE-NEXT: vmls.f32 s14, s4, s8
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vmov.f32 s4, s3 ; CHECK-MVE-NEXT: vmov.f32 s4, s3
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vmov.f32 s8, s2 ; CHECK-MVE-NEXT: vmov.f32 s8, s2
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vmls.f32 s12, s5, s9 ; CHECK-MVE-NEXT: vmls.f32 s12, s5, s9
; CHECK-MVE-NEXT: vmls.f32 s4, s7, s11 ; CHECK-MVE-NEXT: vmls.f32 s4, s7, s11
; CHECK-MVE-NEXT: vmls.f32 s8, s6, s10 ; CHECK-MVE-NEXT: vmls.f32 s8, s6, s10
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4 ; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8 ; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12 ; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14 ; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%0 = fmul <4 x float> %src2, %src3 %0 = fmul <4 x float> %src2, %src3
%1 = fsub <4 x float> %src1, %0 %1 = fsub <4 x float> %src1, %0
%c = fcmp olt <4 x float> %src2, zeroinitializer %c = fcmp olt <4 x float> %src2, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1
ret <4 x float> %s ret <4 x float> %s
Show All 13 Lines
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov r0, s8
; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmar32_pred: ; CHECK-MVE-LABEL: vfmar32_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0 ; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s0
; CHECK-MVE-NEXT: vmov.f32 s14, s2 ; CHECK-MVE-NEXT: vmov.f32 s14, s2
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmov.f32 s10, s1 ; CHECK-MVE-NEXT: vmov.f32 s10, s1
; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8
; CHECK-MVE-NEXT: vmov.f32 s4, s3
; CHECK-MVE-NEXT: vmla.f32 s14, s6, s8
; CHECK-MVE-NEXT: vmla.f32 s10, s5, s8
; CHECK-MVE-NEXT: vmla.f32 s4, s7, s8
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0 ; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.f32 s4, s3
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s6, #0 ; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vmla.f32 s10, s5, s8
; CHECK-MVE-NEXT: vmla.f32 s14, s6, s8
; CHECK-MVE-NEXT: vmla.f32 s4, s7, s8
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4 ; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s14 ; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s14
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10 ; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s12 ; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s12
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src3, i32 0 %i = insertelement <4 x float> undef, float %src3, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%0 = fmul <4 x float> %src2, %sp %0 = fmul <4 x float> %src2, %sp
%1 = fadd <4 x float> %src1, %0 %1 = fadd <4 x float> %src1, %0
%c = fcmp olt <4 x float> %src2, zeroinitializer %c = fcmp olt <4 x float> %src2, zeroinitializer
Show All 14 Lines
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov r0, s8
; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmast.f32 q0, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfmast.f32 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmas32_pred: ; CHECK-MVE-LABEL: vfmas32_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0 ; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: vmov.f32 s10, s8 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: vmla.f32 s12, s0, s4
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: vmov.f32 s4, s8
; CHECK-MVE-NEXT: vmla.f32 s8, s2, s6
; CHECK-MVE-NEXT: vmla.f32 s10, s1, s5
; CHECK-MVE-NEXT: vmla.f32 s4, s3, s7
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0 ; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmla.f32 s12, s0, s4
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vmov.f32 s4, s8
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s6, #0 ; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vmla.f32 s10, s1, s5
; CHECK-MVE-NEXT: vmla.f32 s8, s2, s6
; CHECK-MVE-NEXT: vmla.f32 s4, s3, s7
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4 ; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8 ; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10 ; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s12 ; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s12
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src3, i32 0 %i = insertelement <4 x float> undef, float %src3, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%0 = fmul <4 x float> %src1, %src2 %0 = fmul <4 x float> %src1, %src2
%1 = fadd <4 x float> %sp, %0 %1 = fadd <4 x float> %sp, %0
%c = fcmp olt <4 x float> %src2, zeroinitializer %c = fcmp olt <4 x float> %src2, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1 %s = select <4 x i1> %c, <4 x float> %1, <4 x float> %src1
ret <4 x float> %s ret <4 x float> %s
} }

llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll

Show All 12 Lines
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov r0, r1, d9 ; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r5, r1 ; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: vmov r0, r1, d8 ; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: adr r3, .LCPI0_0 ; CHECK-NEXT: adr r3, .LCPI0_0
; CHECK-NEXT: mvn r12, #-2147483648 ; CHECK-NEXT: mvn r2, #-2147483648
; CHECK-NEXT: vldrw.u32 q0, [r3] ; CHECK-NEXT: vldrw.u32 q0, [r3]
; CHECK-NEXT: subs.w r3, r4, r12 ; CHECK-NEXT: subs r3, r4, r2
; CHECK-NEXT: sbcs r3, r5, #0 ; CHECK-NEXT: sbcs r3, r5, #0
; CHECK-NEXT: vmov q1[2], q1[0], r0, r4 ; CHECK-NEXT: vmov q1[2], q1[0], r0, r4
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: vmov q1[3], q1[1], r1, r5 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r5
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: mov.w r5, #-1
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: subs.w r0, r0, r12 ; CHECK-NEXT: subs r0, r0, r2
; CHECK-NEXT: sbcs r0, r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov.w r12, #-1 ; CHECK-NEXT: adr r4, .LCPI0_1
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: mov.w r2, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: adr r4, .LCPI0_1
; CHECK-NEXT: vmov q2[2], q2[0], r0, r3 ; CHECK-NEXT: vmov q2[2], q2[0], r0, r3
; CHECK-NEXT: vmov q2[3], q2[1], r0, r3 ; CHECK-NEXT: vmov q2[3], q2[1], r0, r3
; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vbic q0, q0, q2 ; CHECK-NEXT: vbic q0, q0, q2
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: vldrw.u32 q1, [r4] ; CHECK-NEXT: vldrw.u32 q1, [r4]
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: vmov r3, r5, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: rsbs.w r0, r0, #-2147483648 ; CHECK-NEXT: rsbs.w r0, r0, #-2147483648
; CHECK-NEXT: sbcs.w r0, r12, r1 ; CHECK-NEXT: sbcs.w r0, r5, r1
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs.w r1, r3, #-2147483648 ; CHECK-NEXT: rsbs.w r1, r2, #-2147483648
; CHECK-NEXT: sbcs.w r1, r12, r5 ; CHECK-NEXT: sbcs.w r1, r5, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt r2, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 ; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0 ; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
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; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov r0, r1, d9 ; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r5, r1 ; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: vmov r0, r1, d8 ; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: subs.w r3, r4, #-1 ; CHECK-NEXT: subs.w r2, r4, #-1
; CHECK-NEXT: vmov q1[2], q1[0], r0, r4 ; CHECK-NEXT: vmov q1[2], q1[0], r0, r4
; CHECK-NEXT: sbcs r3, r5, #0 ; CHECK-NEXT: sbcs r2, r5, #0
; CHECK-NEXT: mov.w r2, #0
; CHECK-NEXT: mov.w r3, #0
; CHECK-NEXT: vmov.i64 q0, #0xffffffff ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r2, lo
; CHECK-NEXT: movlo r3, #1 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r5
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: subs.w r0, r0, #-1 ; CHECK-NEXT: subs.w r0, r0, #-1
; CHECK-NEXT: sbcs r0, r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: movlo r2, #1 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r5
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q2[2], q2[0], r0, r3 ; CHECK-NEXT: vmov q2[2], q2[0], r0, r2
; CHECK-NEXT: vmov q2[3], q2[1], r0, r3 ; CHECK-NEXT: vmov q2[3], q2[1], r0, r2
; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vbic q0, q0, q2 ; CHECK-NEXT: vbic q0, q0, q2
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%conv = fptoui <2 x double> %x to <2 x i64> %conv = fptoui <2 x double> %x to <2 x i64>
%0 = icmp ult <2 x i64> %conv, <i64 4294967295, i64 4294967295> %0 = icmp ult <2 x i64> %conv, <i64 4294967295, i64 4294967295>
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; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov r0, r1, d9 ; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r5, r1 ; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: vmov r0, r1, d8 ; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: subs.w r3, r4, #-1 ; CHECK-NEXT: subs.w r2, r4, #-1
; CHECK-NEXT: vmov q1[2], q1[0], r0, r4 ; CHECK-NEXT: vmov q1[2], q1[0], r0, r4
; CHECK-NEXT: sbcs r3, r5, #0 ; CHECK-NEXT: sbcs r2, r5, #0
; CHECK-NEXT: vmov.i64 q0, #0xffffffff
; CHECK-NEXT: mov.w r3, #0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r5 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r5
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: movlt r3, #1 ; CHECK-NEXT: vmov.i64 q0, #0xffffffff
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: mov.w r5, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: subs.w r0, r0, #-1 ; CHECK-NEXT: subs.w r0, r0, #-1
; CHECK-NEXT: sbcs r0, r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov.w r2, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q2[2], q2[0], r0, r3 ; CHECK-NEXT: vmov q2[2], q2[0], r0, r2
; CHECK-NEXT: vmov q2[3], q2[1], r0, r3 ; CHECK-NEXT: vmov q2[3], q2[1], r0, r2
; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vbic q0, q0, q2 ; CHECK-NEXT: vbic q0, q0, q2
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: vmov r3, r5, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: sbcs.w r0, r2, r1 ; CHECK-NEXT: sbcs.w r0, r5, r1
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs r1, r3, #0 ; CHECK-NEXT: rsbs r1, r2, #0
; CHECK-NEXT: sbcs.w r1, r2, r5 ; CHECK-NEXT: sbcs.w r1, r5, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt r2, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%conv = fptosi <2 x double> %x to <2 x i64> %conv = fptosi <2 x double> %x to <2 x i64>
%0 = icmp slt <2 x i64> %conv, <i64 4294967295, i64 4294967295> %0 = icmp slt <2 x i64> %conv, <i64 4294967295, i64 4294967295>
%spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295> %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>
%1 = icmp sgt <2 x i64> %spec.store.select, zeroinitializer %1 = icmp sgt <2 x i64> %spec.store.select, zeroinitializer
%spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> zeroinitializer %spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> zeroinitializer
%conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32> %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
ret <2 x i32> %conv6 ret <2 x i32> %conv6
} }
define arm_aapcs_vfpcc <4 x i32> @stest_f32i32(<4 x float> %x) { define arm_aapcs_vfpcc <4 x i32> @stest_f32i32(<4 x float> %x) {
; CHECK-LABEL: stest_f32i32: ; CHECK-LABEL: stest_f32i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: .pad #8
; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov r0, r6, d8 ; CHECK-NEXT: vmov r4, r0, d8
; CHECK-NEXT: bl __aeabi_f2lz ; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: mov r9, r0 ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mvn r0, #-2147483648 ; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: subs.w r0, r9, r0 ; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: str r1, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mvn r4, #-2147483648
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: csetm r11, ne
; CHECK-NEXT: bl __aeabi_f2lz ; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: mov r6, r0 ; CHECK-NEXT: vmov r4, r2, d9
; CHECK-NEXT: subs r0, r0, r4 ; CHECK-NEXT: adr r3, .LCPI3_0
; CHECK-NEXT: mvn r7, #-2147483648
; CHECK-NEXT: vldrw.u32 q5, [r3]
; CHECK-NEXT: subs r3, r5, r7
; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: sbcs r3, r6, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r6
; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: subs r0, r0, r7
; CHECK-NEXT: sbcs r0, r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov r10, r1 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov r4, r0, d9 ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: csetm r8, ne ; CHECK-NEXT: vmov q1[2], q1[0], r0, r3
; CHECK-NEXT: vmov q1[3], q1[1], r0, r3
; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vbic q1, q5, q1
; CHECK-NEXT: vorr q4, q0, q1
; CHECK-NEXT: vmov r9, r8, d8
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: bl __aeabi_f2lz ; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: mov r5, r0 ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: mov r7, r1 ; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: bl __aeabi_f2lz ; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: adr r2, .LCPI3_0 ; CHECK-NEXT: adr r3, .LCPI3_1
; CHECK-NEXT: mvn r4, #-2147483648 ; CHECK-NEXT: vmov q1[2], q1[0], r0, r5
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r3]
; CHECK-NEXT: adr r2, .LCPI3_1 ; CHECK-NEXT: subs r3, r5, r7
; CHECK-NEXT: vldrw.u32 q2, [r2] ; CHECK-NEXT: sbcs r3, r6, #0
; CHECK-NEXT: subs r2, r5, r4 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r6
; CHECK-NEXT: ldr r2, [sp, #4] @ 4-byte Reload ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: vmov q1[2], q1[0], r9, r6 ; CHECK-NEXT: mov.w r2, #-1
; CHECK-NEXT: vmov q4[2], q4[0], r11, r8
; CHECK-NEXT: vmov q3[2], q3[0], r0, r5
; CHECK-NEXT: vmov q1[3], q1[1], r2, r10
; CHECK-NEXT: vmov q4[3], q4[1], r11, r8
; CHECK-NEXT: vand q1, q1, q4
; CHECK-NEXT: vbic q4, q2, q4
; CHECK-NEXT: vorr q1, q1, q4
; CHECK-NEXT: vmov q3[3], q3[1], r1, r7
; CHECK-NEXT: vmov r2, r3, d2
; CHECK-NEXT: sbcs r7, r7, #0
; CHECK-NEXT: vmov r6, r5, d3
; CHECK-NEXT: mov.w r7, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r7, #1
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csetm r7, ne
; CHECK-NEXT: subs r0, r0, r4
; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: mov.w r0, #-1
; CHECK-NEXT: vmov q4[2], q4[0], r1, r7
; CHECK-NEXT: vmov q4[3], q4[1], r1, r7
; CHECK-NEXT: vand q3, q3, q4
; CHECK-NEXT: vbic q2, q2, q4
; CHECK-NEXT: vorr q2, q3, q2
; CHECK-NEXT: vmov r1, r7, d5
; CHECK-NEXT: rsbs.w r2, r2, #-2147483648
; CHECK-NEXT: sbcs.w r2, r0, r3
; CHECK-NEXT: mov.w r2, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: rsbs.w r3, r6, #-2147483648
; CHECK-NEXT: sbcs.w r3, r0, r5
; CHECK-NEXT: vmov r6, r5, d4
; CHECK-NEXT: mov.w r3, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: subs r0, r0, r7
; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov r1, r7, d9
; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs.w r6, r9, #-2147483648
; CHECK-NEXT: vmov q2[2], q2[0], r0, r3
; CHECK-NEXT: sbcs.w r6, r2, r8
; CHECK-NEXT: vmov q2[3], q2[1], r0, r3
; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vbic q2, q5, q2
; CHECK-NEXT: vorr q1, q1, q2
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: vmov r0, r3, d3
; CHECK-NEXT: csetm r6, ne
; CHECK-NEXT: vmov r5, r4, d2
; CHECK-NEXT: rsbs.w r1, r1, #-2147483648 ; CHECK-NEXT: rsbs.w r1, r1, #-2147483648
; CHECK-NEXT: sbcs.w r1, r0, r7 ; CHECK-NEXT: sbcs.w r1, r2, r7
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: rsbs.w r7, r6, #-2147483648 ; CHECK-NEXT: rsbs.w r0, r0, #-2147483648
; CHECK-NEXT: sbcs r0, r5 ; CHECK-NEXT: sbcs.w r0, r2, r3
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: rsbs.w r3, r5, #-2147483648
; CHECK-NEXT: vmov q3[2], q3[0], r0, r1 ; CHECK-NEXT: sbcs r2, r4
; CHECK-NEXT: vbic q4, q0, q3 ; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: vand q2, q2, q3 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vmov.32 q3[1], r2 ; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vorr q2, q2, q4 ; CHECK-NEXT: vmov.32 q2[1], r2
; CHECK-NEXT: vmov q3[2], q3[0], r2, r3 ; CHECK-NEXT: vmov q2[2], q2[0], r2, r0
; CHECK-NEXT: vbic q0, q0, q3 ; CHECK-NEXT: vbic q3, q0, q2
; CHECK-NEXT: vand q1, q1, q3 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vmov.32 q2[1], r6
; CHECK-NEXT: vorr q1, q1, q3
; CHECK-NEXT: vmov q2[2], q2[0], r6, r1
; CHECK-NEXT: vbic q0, q0, q2
; CHECK-NEXT: vand q2, q4, q2
; CHECK-NEXT: vorr q0, q2, q0
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s10 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: add sp, #8 ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI3_0: ; CHECK-NEXT: .LCPI3_0:
; CHECK-NEXT: .long 2147483648 @ 0x80000000
; CHECK-NEXT: .long 4294967295 @ 0xffffffff
; CHECK-NEXT: .long 2147483648 @ 0x80000000
; CHECK-NEXT: .long 4294967295 @ 0xffffffff
; CHECK-NEXT: .LCPI3_1:
; CHECK-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
; CHECK-NEXT: .long 0 @ 0x0 ; CHECK-NEXT: .long 0 @ 0x0
; CHECK-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
; CHECK-NEXT: .long 0 @ 0x0 ; CHECK-NEXT: .long 0 @ 0x0
; CHECK-NEXT: .LCPI3_1:
; CHECK-NEXT: .long 2147483648 @ 0x80000000
; CHECK-NEXT: .long 4294967295 @ 0xffffffff
; CHECK-NEXT: .long 2147483648 @ 0x80000000
; CHECK-NEXT: .long 4294967295 @ 0xffffffff
entry: entry:
%conv = fptosi <4 x float> %x to <4 x i64> %conv = fptosi <4 x float> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647> %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
%spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647> %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
%1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648> %1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
%spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648> %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
ret <4 x i32> %conv6 ret <4 x i32> %conv6
Show All 16 Lines
; CHECK-NEXT: mov r6, r0 ; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: vmov r5, r0, d8 ; CHECK-NEXT: vmov r5, r0, d8
; CHECK-NEXT: mov r9, r1 ; CHECK-NEXT: mov r9, r1
; CHECK-NEXT: bl __aeabi_f2ulz ; CHECK-NEXT: bl __aeabi_f2ulz
; CHECK-NEXT: mov r7, r0 ; CHECK-NEXT: mov r7, r0
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r4, r1 ; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: bl __aeabi_f2ulz ; CHECK-NEXT: bl __aeabi_f2ulz
; CHECK-NEXT: subs.w r3, r7, #-1 ; CHECK-NEXT: subs.w r2, r7, #-1
; CHECK-NEXT: vmov q0[2], q0[0], r0, r7 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r7
; CHECK-NEXT: sbcs r3, r4, #0 ; CHECK-NEXT: sbcs r2, r4, #0
; CHECK-NEXT: mov.w r2, #0
; CHECK-NEXT: mov.w r3, #0
; CHECK-NEXT: vmov q1[2], q1[0], r10, r6 ; CHECK-NEXT: vmov q1[2], q1[0], r10, r6
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r2, lo
; CHECK-NEXT: movlo r3, #1 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: subs.w r0, r0, #-1 ; CHECK-NEXT: subs.w r0, r0, #-1
; CHECK-NEXT: sbcs r0, r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs.w r1, r6, #-1 ; CHECK-NEXT: subs.w r1, r6, #-1
; CHECK-NEXT: sbcs r1, r9, #0 ; CHECK-NEXT: sbcs r1, r9, #0
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r1, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs.w r7, r10, #-1 ; CHECK-NEXT: subs.w r3, r10, #-1
; CHECK-NEXT: sbcs r7, r8, #0 ; CHECK-NEXT: sbcs r3, r8, #0
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r3, lo
; CHECK-NEXT: movlo r2, #1 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: csetm r2, ne ; CHECK-NEXT: vmov.32 q2[1], r3
; CHECK-NEXT: vmov.32 q2[1], r2 ; CHECK-NEXT: vmov q2[2], q2[0], r3, r1
; CHECK-NEXT: vmov q2[2], q2[0], r2, r1
; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vorn q1, q1, q2 ; CHECK-NEXT: vorn q1, q1, q2
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov q2[2], q2[0], r0, r3 ; CHECK-NEXT: vmov q2[2], q2[0], r0, r2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorn q0, q0, q2 ; CHECK-NEXT: vorn q0, q0, q2
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s6 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
entry: entry:
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; CHECK-NEXT: mov r5, r0 ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: mov r6, r1 ; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: bl __aeabi_f2lz ; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: vmov r4, r2, d8 ; CHECK-NEXT: vmov r4, r2, d8
; CHECK-NEXT: subs.w r3, r5, #-1 ; CHECK-NEXT: subs.w r3, r5, #-1
; CHECK-NEXT: sbcs r3, r6, #0 ; CHECK-NEXT: sbcs r3, r6, #0
; CHECK-NEXT: vmov q0[2], q0[0], r0, r5 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: vmov.i64 q5, #0xffffffff ; CHECK-NEXT: vmov.i64 q5, #0xffffffff
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r6
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: subs.w r0, r0, #-1 ; CHECK-NEXT: subs.w r0, r0, #-1
; CHECK-NEXT: sbcs r0, r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r6 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: mov.w r7, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q1[2], q1[0], r0, r3 ; CHECK-NEXT: vmov q1[2], q1[0], r0, r3
; CHECK-NEXT: vmov q1[3], q1[1], r0, r3 ; CHECK-NEXT: vmov q1[3], q1[1], r0, r3
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vbic q1, q5, q1 ; CHECK-NEXT: vbic q1, q5, q1
; CHECK-NEXT: vorr q4, q0, q1 ; CHECK-NEXT: vorr q4, q0, q1
; CHECK-NEXT: vmov r9, r8, d9 ; CHECK-NEXT: vmov r9, r8, d9
; CHECK-NEXT: mov r0, r2 ; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: bl __aeabi_f2lz ; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: mov r5, r0 ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: subs.w r0, r0, #-1
; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov r6, r1 ; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: csetm r7, ne
; CHECK-NEXT: bl __aeabi_f2lz ; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: subs.w r2, r5, #-1 ; CHECK-NEXT: subs.w r3, r0, #-1
; CHECK-NEXT: vmov q0[2], q0[0], r0, r5 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: sbcs r2, r6, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r6
; CHECK-NEXT: mov.w r2, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: subs.w r0, r0, #-1
; CHECK-NEXT: sbcs r0, r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r6
; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: vmov r1, r3, d8 ; CHECK-NEXT: vmov r1, r3, d8
; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mov.w r2, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs.w r6, r9, #0 ; CHECK-NEXT: rsbs.w r6, r9, #0
; CHECK-NEXT: vmov q1[2], q1[0], r0, r2 ; CHECK-NEXT: vmov q1[2], q1[0], r0, r7
; CHECK-NEXT: sbcs.w r6, r7, r8 ; CHECK-NEXT: sbcs.w r6, r2, r8
; CHECK-NEXT: vmov q1[3], q1[1], r0, r2 ; CHECK-NEXT: vmov q1[3], q1[1], r0, r7
; CHECK-NEXT: mov.w r6, #0 ; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vbic q1, q5, q1 ; CHECK-NEXT: vbic q1, q5, q1
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r6, #1
; CHECK-NEXT: vmov r0, r2, d1
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: vmov r5, r4, d0 ; CHECK-NEXT: vmov r0, r7, d1
; CHECK-NEXT: csetm r6, ne ; CHECK-NEXT: csetm r6, ne
; CHECK-NEXT: vmov r5, r4, d0
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: sbcs.w r1, r7, r3 ; CHECK-NEXT: sbcs.w r1, r2, r3
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r6 ; CHECK-NEXT: vmov q2[2], q2[0], r1, r6
; CHECK-NEXT: vand q2, q4, q2 ; CHECK-NEXT: vand q2, q4, q2
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: sbcs.w r0, r7, r2 ; CHECK-NEXT: sbcs.w r0, r2, r7
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs r2, r5, #0 ; CHECK-NEXT: rsbs r3, r5, #0
; CHECK-NEXT: sbcs.w r2, r7, r4 ; CHECK-NEXT: sbcs r2, r4
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: movlt r7, #1 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csetm r2, ne ; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov q1[2], q1[0], r2, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r2, r0
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s10 ; CHECK-NEXT: vmov.f32 s3, s10
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
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; CHECK-NEXT: mov r5, r0 ; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: vmov.u16 r0, q4[0] ; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: mov r7, r1 ; CHECK-NEXT: mov r7, r1
; CHECK-NEXT: bl __fixhfdi ; CHECK-NEXT: bl __fixhfdi
; CHECK-NEXT: rsbs r3, r5, #0 ; CHECK-NEXT: rsbs r3, r5, #0
; CHECK-NEXT: mov.w r2, #0 ; CHECK-NEXT: mov.w r2, #0
; CHECK-NEXT: sbcs.w r3, r2, r7 ; CHECK-NEXT: sbcs.w r3, r2, r7
; CHECK-NEXT: vmov q0[2], q0[0], r0, r6 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r6
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: vmov q1[2], q1[0], r4, r5 ; CHECK-NEXT: vmov q1[2], q1[0], r4, r5
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: rsbs r7, r4, #0 ; CHECK-NEXT: rsbs r7, r4, #0
; CHECK-NEXT: sbcs.w r7, r2, r8 ; CHECK-NEXT: sbcs.w r7, r2, r8
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: cset r7, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r7, #1
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csetm r7, ne ; CHECK-NEXT: csetm r7, ne
; CHECK-NEXT: rsbs r6, r6, #0 ; CHECK-NEXT: rsbs r6, r6, #0
; CHECK-NEXT: sbcs.w r6, r2, r9 ; CHECK-NEXT: sbcs.w r6, r2, r9
; CHECK-NEXT: vmov q3[2], q3[0], r7, r3 ; CHECK-NEXT: vmov q3[2], q3[0], r7, r3
; CHECK-NEXT: mov.w r6, #0 ; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: vand q1, q1, q3 ; CHECK-NEXT: vand q1, q1, q3
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r6, #1
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csetm r6, ne ; CHECK-NEXT: csetm r6, ne
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: sbcs.w r0, r2, r1 ; CHECK-NEXT: sbcs.w r0, r2, r1
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: movlt r2, #1 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q2[2], q2[0], r0, r6 ; CHECK-NEXT: vmov q2[2], q2[0], r0, r6
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s6 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
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; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r5, r1 ; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: vmov r0, r1, d8 ; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: vmov q0[2], q0[0], r0, r4 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
; CHECK-NEXT: movw r4, #32767 ; CHECK-NEXT: movw r4, #32767
; CHECK-NEXT: vmov q0[3], q0[1], r1, r5 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
; CHECK-NEXT: adr.w r12, .LCPI9_0 ; CHECK-NEXT: adr r5, .LCPI9_0
; CHECK-NEXT: vmov r1, r2, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: vldrw.u32 q1, [r12] ; CHECK-NEXT: vldrw.u32 q1, [r5]
; CHECK-NEXT: vmov r3, r5, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: movw lr, #32768
; CHECK-NEXT: movt lr, #65535
; CHECK-NEXT: mov.w r12, #-1 ; CHECK-NEXT: mov.w r12, #-1
; CHECK-NEXT: movs r0, #0 ; CHECK-NEXT: adr r5, .LCPI9_1
; CHECK-NEXT: subs r1, r1, r4 ; CHECK-NEXT: subs r0, r0, r4
; CHECK-NEXT: sbcs r1, r2, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs r1, r2, r4
; CHECK-NEXT: sbcs r1, r3, #0
; CHECK-NEXT: movw r4, #32768
; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movt r4, #65535
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r4 ; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: sbcs r2, r5, #0 ; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: adr r4, .LCPI9_1
; CHECK-NEXT: mov.w r2, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov q2[2], q2[0], r2, r1
; CHECK-NEXT: vmov q2[3], q2[1], r2, r1
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: vldrw.u32 q1, [r4] ; CHECK-NEXT: vldrw.u32 q1, [r5]
; CHECK-NEXT: vmov r1, r2, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: vmov r3, r5, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: subs.w r1, lr, r1 ; CHECK-NEXT: subs r0, r4, r0
; CHECK-NEXT: sbcs.w r1, r12, r2 ; CHECK-NEXT: sbcs.w r0, r12, r1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs.w r2, lr, r3
; CHECK-NEXT: sbcs.w r2, r12, r5
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q2[2], q2[0], r0, r1 ; CHECK-NEXT: subs r1, r4, r2
; CHECK-NEXT: vmov q2[3], q2[1], r0, r1 ; CHECK-NEXT: sbcs.w r1, r12, r3
; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI9_0: ; CHECK-NEXT: .LCPI9_0:
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; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov r0, r1, d9 ; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r5, r1 ; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: vmov r0, r1, d8 ; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: bl __aeabi_d2ulz
; CHECK-NEXT: vmov q0[2], q0[0], r0, r4 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
; CHECK-NEXT: movw r4, #65535 ; CHECK-NEXT: vmov.i64 q1, #0xffff
; CHECK-NEXT: vmov q0[3], q0[1], r1, r5 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
; CHECK-NEXT: movs r5, #0 ; CHECK-NEXT: movw r5, #65535
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: vmov.i64 q1, #0xffff
; CHECK-NEXT: vmov r2, r3, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: subs r0, r0, r4 ; CHECK-NEXT: subs r0, r0, r5
; CHECK-NEXT: sbcs r0, r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs r1, r2, r4 ; CHECK-NEXT: subs r1, r2, r5
; CHECK-NEXT: sbcs r1, r3, #0 ; CHECK-NEXT: sbcs r1, r3, #0
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r1, lo
; CHECK-NEXT: movlo r5, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 ; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0 ; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
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; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov r0, r1, d9 ; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: mov r5, r1 ; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: vmov r0, r1, d8 ; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: vmov q0[2], q0[0], r0, r4 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
; CHECK-NEXT: movw r4, #65535
; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
; CHECK-NEXT: vmov.i64 q1, #0xffff ; CHECK-NEXT: vmov.i64 q1, #0xffff
; CHECK-NEXT: vmov r1, r2, d1 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
; CHECK-NEXT: movs r0, #0 ; CHECK-NEXT: movw r5, #65535
; CHECK-NEXT: vmov r3, r5, d0 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: subs r1, r1, r4 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: sbcs r1, r2, #0 ; CHECK-NEXT: subs r0, r0, r5
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs r1, r2, r5
; CHECK-NEXT: sbcs r1, r3, #0
; CHECK-NEXT: mov.w r5, #0
; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r4 ; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: sbcs r2, r5, #0 ; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: mov.w r2, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov q2[2], q2[0], r2, r1
; CHECK-NEXT: vmov q2[3], q2[1], r2, r1
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: vmov r1, r2, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: vmov r3, r5, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: sbcs.w r1, r0, r2 ; CHECK-NEXT: sbcs.w r0, r5, r1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: rsbs r2, r3, #0
; CHECK-NEXT: sbcs.w r2, r0, r5
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q1[2], q1[0], r0, r1 ; CHECK-NEXT: rsbs r1, r2, #0
; CHECK-NEXT: vmov q1[3], q1[1], r0, r1 ; CHECK-NEXT: sbcs.w r1, r5, r3
; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%conv = fptosi <2 x double> %x to <2 x i32> %conv = fptosi <2 x double> %x to <2 x i32>
%0 = icmp slt <2 x i32> %conv, <i32 65535, i32 65535> %0 = icmp slt <2 x i32> %conv, <i32 65535, i32 65535>
%spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535> %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>
%1 = icmp sgt <2 x i32> %spec.store.select, zeroinitializer %1 = icmp sgt <2 x i32> %spec.store.select, zeroinitializer
▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Linesentry:
ret <8 x i16> %conv6 ret <8 x i16> %conv6
} }
; i64 saturate ; i64 saturate
define arm_aapcs_vfpcc <2 x i64> @stest_f64i64(<2 x double> %x) { define arm_aapcs_vfpcc <2 x i64> @stest_f64i64(<2 x double> %x) {
; CHECK-LABEL: stest_f64i64: ; CHECK-LABEL: stest_f64i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: movs r4, #0
; CHECK-NEXT: vmov r0, r1, d9 ; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: mvn r9, #-2147483648
; CHECK-NEXT: bl __fixdfti ; CHECK-NEXT: bl __fixdfti
; CHECK-NEXT: subs.w r7, r0, #-1 ; CHECK-NEXT: vmov r12, lr, d8
; CHECK-NEXT: mov.w r5, #-1 ; CHECK-NEXT: subs.w r4, r0, #-1
; CHECK-NEXT: sbcs.w r7, r1, r9 ; CHECK-NEXT: mvn r9, #-2147483648
; CHECK-NEXT: sbcs.w r4, r1, r9
; CHECK-NEXT: sbcs r4, r2, #0
; CHECK-NEXT: mov.w r7, #-1
; CHECK-NEXT: sbcs r4, r3, #0
; CHECK-NEXT: mov.w r10, #-2147483648 ; CHECK-NEXT: mov.w r10, #-2147483648
; CHECK-NEXT: sbcs r7, r2, #0 ; CHECK-NEXT: cset r4, lt
; CHECK-NEXT: sbcs r7, r3, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: csel r3, r3, r4, ne
; CHECK-NEXT: it lt ; CHECK-NEXT: csel r2, r2, r4, ne
; CHECK-NEXT: movlt r7, #1 ; CHECK-NEXT: csel r4, r0, r7, ne
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r11, r0, r5, ne
; CHECK-NEXT: csel r3, r3, r7, ne
; CHECK-NEXT: csel r2, r2, r7, ne
; CHECK-NEXT: csel r1, r1, r9, ne ; CHECK-NEXT: csel r1, r1, r9, ne
; CHECK-NEXT: rsbs.w r0, r11, #0 ; CHECK-NEXT: rsbs r0, r4, #0
; CHECK-NEXT: mov.w r7, #0
; CHECK-NEXT: sbcs.w r0, r10, r1 ; CHECK-NEXT: sbcs.w r0, r10, r1
; CHECK-NEXT: sbcs.w r0, r5, r2 ; CHECK-NEXT: sbcs.w r0, r7, r2
; CHECK-NEXT: sbcs.w r0, r5, r3 ; CHECK-NEXT: sbcs.w r0, r7, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: movlt r7, #1 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r8, r1, r10, ne ; CHECK-NEXT: csel r8, r1, r10, ne
; CHECK-NEXT: vmov r0, r1, d8 ; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: mov r1, lr
; CHECK-NEXT: bl __fixdfti ; CHECK-NEXT: bl __fixdfti
; CHECK-NEXT: subs.w r6, r0, #-1 ; CHECK-NEXT: subs.w r6, r0, #-1
; CHECK-NEXT: sbcs.w r6, r1, r9 ; CHECK-NEXT: sbcs.w r6, r1, r9
; CHECK-NEXT: sbcs r6, r2, #0 ; CHECK-NEXT: sbcs r6, r2, #0
; CHECK-NEXT: sbcs r6, r3, #0 ; CHECK-NEXT: sbcs r6, r3, #0
; CHECK-NEXT: mov.w r6, #0 ; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r6, #1
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r0, r0, r5, ne ; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: csel r1, r1, r9, ne ; CHECK-NEXT: csel r1, r1, r9, ne
; CHECK-NEXT: csel r3, r3, r6, ne ; CHECK-NEXT: csel r3, r3, r6, ne
; CHECK-NEXT: csel r2, r2, r6, ne ; CHECK-NEXT: csel r2, r2, r6, ne
; CHECK-NEXT: rsbs r6, r0, #0 ; CHECK-NEXT: rsbs r6, r0, #0
; CHECK-NEXT: sbcs.w r6, r10, r1 ; CHECK-NEXT: sbcs.w r6, r10, r1
; CHECK-NEXT: sbcs.w r2, r5, r2 ; CHECK-NEXT: sbcs.w r2, r7, r2
; CHECK-NEXT: sbcs.w r2, r5, r3 ; CHECK-NEXT: sbcs.w r2, r7, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: movlt r4, #1 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r1, r1, r10, ne ; CHECK-NEXT: csel r1, r1, r10, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r2, r11, r7, ne ; CHECK-NEXT: csel r3, r4, r5, ne
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r0, r0, r4, ne ; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r3
; CHECK-NEXT: vmov q0[3], q0[1], r1, r8 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r8
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
entry: entry:
%conv = fptosi <2 x double> %x to <2 x i128> %conv = fptosi <2 x double> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807> %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807> %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>
%1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808> %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>
%spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808> %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define arm_aapcs_vfpcc <2 x i64> @utest_f64i64(<2 x double> %x) { define arm_aapcs_vfpcc <2 x i64> @utest_f64i64(<2 x double> %x) {
; CHECK-LABEL: utest_f64i64: ; CHECK-LABEL: utest_f64i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov r0, r1, d9 ; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: bl __fixunsdfti ; CHECK-NEXT: bl __fixunsdfti
; CHECK-NEXT: mov r8, r1 ; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: vmov r4, r1, d8 ; CHECK-NEXT: vmov r4, r1, d8
; CHECK-NEXT: subs r2, #1 ; CHECK-NEXT: subs r2, #1
; CHECK-NEXT: mov.w r7, #0
; CHECK-NEXT: sbcs r2, r3, #0 ; CHECK-NEXT: sbcs r2, r3, #0
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r6, lo
; CHECK-NEXT: movlo r7, #1 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: csel r7, r0, r6, ne
; CHECK-NEXT: mov.w r6, #0
; CHECK-NEXT: csel r5, r0, r7, ne
; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: bl __fixunsdfti ; CHECK-NEXT: bl __fixunsdfti
; CHECK-NEXT: subs r2, #1 ; CHECK-NEXT: subs r2, #1
; CHECK-NEXT: sbcs r2, r3, #0 ; CHECK-NEXT: sbcs r2, r3, #0
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r2, lo
; CHECK-NEXT: movlo r6, #1 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: csel r0, r0, r6, ne
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r2, r8, r7, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r1, r1, r6, ne ; CHECK-NEXT: csel r3, r5, r6, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r5 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r2 ; CHECK-NEXT: csel r1, r1, r2, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r7
; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc} ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
entry: entry:
%conv = fptoui <2 x double> %x to <2 x i128> %conv = fptoui <2 x double> %x to <2 x i128>
%0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616> %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616> %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define arm_aapcs_vfpcc <2 x i64> @ustest_f64i64(<2 x double> %x) { define arm_aapcs_vfpcc <2 x i64> @ustest_f64i64(<2 x double> %x) {
; CHECK-LABEL: ustest_f64i64: ; CHECK-LABEL: ustest_f64i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov r0, r1, d9 ; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: bl __fixdfti ; CHECK-NEXT: bl __fixdfti
; CHECK-NEXT: vmov r12, lr, d8 ; CHECK-NEXT: vmov r12, lr, d8
; CHECK-NEXT: subs r5, r2, #1 ; CHECK-NEXT: subs r4, r2, #1
; CHECK-NEXT: sbcs r5, r3, #0 ; CHECK-NEXT: sbcs r4, r3, #0
; CHECK-NEXT: mov.w r6, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: mov.w r8, #1 ; CHECK-NEXT: mov.w r8, #1
; CHECK-NEXT: csel r0, r0, r6, ne ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: csel r3, r3, r6, ne ; CHECK-NEXT: movs r7, #0
; CHECK-NEXT: csel r5, r1, r6, ne ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: csel r3, r3, r5, ne
; CHECK-NEXT: csel r2, r2, r8, ne ; CHECK-NEXT: csel r2, r2, r8, ne
; CHECK-NEXT: csel r4, r1, r5, ne
; CHECK-NEXT: rsbs r1, r0, #0 ; CHECK-NEXT: rsbs r1, r0, #0
; CHECK-NEXT: mov.w r4, #0 ; CHECK-NEXT: sbcs.w r1, r7, r4
; CHECK-NEXT: sbcs.w r1, r4, r5 ; CHECK-NEXT: sbcs.w r1, r7, r2
; CHECK-NEXT: sbcs.w r1, r4, r2 ; CHECK-NEXT: sbcs.w r1, r7, r3
; CHECK-NEXT: mov.w r6, #0 ; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: sbcs.w r1, r4, r3
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r6, #1
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r9, r0, r6, ne ; CHECK-NEXT: csel r9, r0, r6, ne
; CHECK-NEXT: mov r0, r12 ; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: mov r1, lr ; CHECK-NEXT: mov r1, lr
; CHECK-NEXT: bl __fixdfti ; CHECK-NEXT: bl __fixdfti
; CHECK-NEXT: subs r7, r2, #1 ; CHECK-NEXT: subs r5, r2, #1
; CHECK-NEXT: sbcs r7, r3, #0 ; CHECK-NEXT: sbcs r5, r3, #0
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: it lt ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: movlt r7, #1 ; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: csel r2, r2, r8, ne ; CHECK-NEXT: csel r2, r2, r8, ne
; CHECK-NEXT: csel r3, r3, r7, ne ; CHECK-NEXT: csel r3, r3, r5, ne
; CHECK-NEXT: csel r1, r1, r7, ne ; CHECK-NEXT: csel r1, r1, r5, ne
; CHECK-NEXT: rsbs r7, r0, #0 ; CHECK-NEXT: rsbs r5, r0, #0
; CHECK-NEXT: sbcs.w r7, r4, r1 ; CHECK-NEXT: sbcs.w r5, r7, r1
; CHECK-NEXT: sbcs.w r2, r4, r2 ; CHECK-NEXT: sbcs.w r2, r7, r2
; CHECK-NEXT: sbcs.w r2, r4, r3 ; CHECK-NEXT: sbcs.w r2, r7, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: movlt r4, #1 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: csel r0, r0, r4, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r2, r5, r6, ne ; CHECK-NEXT: csel r3, r4, r6, ne
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r1, r1, r4, ne ; CHECK-NEXT: csel r1, r1, r2, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r9 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r9
; CHECK-NEXT: vmov q0[3], q0[1], r1, r2 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
entry: entry:
%conv = fptosi <2 x double> %x to <2 x i128> %conv = fptosi <2 x double> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616> %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616> %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
%1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer
%spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define arm_aapcs_vfpcc <2 x i64> @stest_f32i64(<2 x float> %x) { define arm_aapcs_vfpcc <2 x i64> @stest_f32i64(<2 x float> %x) {
; CHECK-LABEL: stest_f32i64: ; CHECK-LABEL: stest_f32i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: vmov r8, r0, d0 ; CHECK-NEXT: vmov r9, r0, d0
; CHECK-NEXT: bl __fixsfti ; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: subs.w r7, r0, #-1 ; CHECK-NEXT: subs.w r7, r0, #-1
; CHECK-NEXT: mvn r10, #-2147483648 ; CHECK-NEXT: mvn r10, #-2147483648
; CHECK-NEXT: sbcs.w r7, r1, r10 ; CHECK-NEXT: sbcs.w r7, r1, r10
; CHECK-NEXT: mov.w r11, #-2147483648 ; CHECK-NEXT: mov.w r4, #-1
; CHECK-NEXT: sbcs r7, r2, #0 ; CHECK-NEXT: sbcs r7, r2, #0
; CHECK-NEXT: mov.w r4, #0 ; CHECK-NEXT: mov.w r11, #-2147483648
; CHECK-NEXT: sbcs r7, r3, #0 ; CHECK-NEXT: sbcs r7, r3, #0
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r7, lt
; CHECK-NEXT: mov.w r7, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r7, #1
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r5, r0, r4, ne
; CHECK-NEXT: csel r3, r3, r7, ne ; CHECK-NEXT: csel r3, r3, r7, ne
; CHECK-NEXT: csel r2, r2, r7, ne ; CHECK-NEXT: csel r2, r2, r7, ne
; CHECK-NEXT: mov.w r7, #-1
; CHECK-NEXT: csel r1, r1, r10, ne ; CHECK-NEXT: csel r1, r1, r10, ne
; CHECK-NEXT: csel r9, r0, r7, ne ; CHECK-NEXT: rsbs r0, r5, #0
; CHECK-NEXT: rsbs.w r0, r9, #0
; CHECK-NEXT: sbcs.w r0, r11, r1 ; CHECK-NEXT: sbcs.w r0, r11, r1
; CHECK-NEXT: sbcs.w r0, r7, r2 ; CHECK-NEXT: sbcs.w r0, r4, r2
; CHECK-NEXT: sbcs.w r0, r7, r3 ; CHECK-NEXT: sbcs.w r0, r4, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: movlt r4, #1 ; CHECK-NEXT: mov r0, r9
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r0, r1, r11, ne
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: subs.w r6, r0, #-1
; CHECK-NEXT: sbcs.w r6, r1, r10
; CHECK-NEXT: sbcs r6, r2, #0
; CHECK-NEXT: sbcs r6, r3, #0
; CHECK-NEXT: mov.w r6, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r6, #1
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r0, r0, r7, ne ; CHECK-NEXT: csel r8, r1, r11, ne
; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: subs.w r7, r0, #-1
; CHECK-NEXT: sbcs.w r7, r1, r10
; CHECK-NEXT: sbcs r7, r2, #0
; CHECK-NEXT: sbcs r7, r3, #0
; CHECK-NEXT: cset r7, lt
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r0, r0, r4, ne
; CHECK-NEXT: csel r1, r1, r10, ne ; CHECK-NEXT: csel r1, r1, r10, ne
; CHECK-NEXT: csel r3, r3, r6, ne ; CHECK-NEXT: csel r3, r3, r7, ne
; CHECK-NEXT: csel r2, r2, r6, ne ; CHECK-NEXT: csel r2, r2, r7, ne
; CHECK-NEXT: rsbs r6, r0, #0 ; CHECK-NEXT: rsbs r7, r0, #0
; CHECK-NEXT: sbcs.w r6, r11, r1 ; CHECK-NEXT: sbcs.w r7, r11, r1
; CHECK-NEXT: sbcs.w r2, r7, r2 ; CHECK-NEXT: sbcs.w r2, r4, r2
; CHECK-NEXT: sbcs.w r2, r7, r3 ; CHECK-NEXT: sbcs.w r2, r4, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: movlt r5, #1 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r1, r1, r11, ne ; CHECK-NEXT: csel r1, r1, r11, ne
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r2, r9, r4, ne ; CHECK-NEXT: csel r3, r5, r6, ne
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r0, r0, r5, ne ; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r3
; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload ; CHECK-NEXT: vmov q0[3], q0[1], r1, r8
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
entry: entry:
%conv = fptosi <2 x float> %x to <2 x i128> %conv = fptosi <2 x float> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807> %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807> %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>
%1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808> %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>
%spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808> %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define arm_aapcs_vfpcc <2 x i64> @utest_f32i64(<2 x float> %x) { define arm_aapcs_vfpcc <2 x i64> @utest_f32i64(<2 x float> %x) {
; CHECK-LABEL: utest_f32i64: ; CHECK-LABEL: utest_f32i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr} ; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: vmov r4, r0, d0 ; CHECK-NEXT: vmov r4, r0, d0
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: mov r8, r1 ; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: subs r1, r2, #1 ; CHECK-NEXT: subs r1, r2, #1
; CHECK-NEXT: sbcs r1, r3, #0 ; CHECK-NEXT: sbcs r1, r3, #0
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: cset r6, lo
; CHECK-NEXT: it lo ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: movlo r7, #1 ; CHECK-NEXT: csel r7, r0, r6, ne
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r5, r0, r7, ne
; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: movs r6, #0
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: subs r2, #1 ; CHECK-NEXT: subs r2, #1
; CHECK-NEXT: sbcs r2, r3, #0 ; CHECK-NEXT: sbcs r2, r3, #0
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r2, lo
; CHECK-NEXT: movlo r6, #1 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: csel r0, r0, r6, ne
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r2, r8, r7, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r1, r1, r6, ne ; CHECK-NEXT: csel r3, r5, r6, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r5 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r2 ; CHECK-NEXT: csel r1, r1, r2, ne
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc} ; CHECK-NEXT: vmov q0[2], q0[0], r0, r7
; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
entry: entry:
%conv = fptoui <2 x float> %x to <2 x i128> %conv = fptoui <2 x float> %x to <2 x i128>
%0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616> %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616> %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define arm_aapcs_vfpcc <2 x i64> @ustest_f32i64(<2 x float> %x) { define arm_aapcs_vfpcc <2 x i64> @ustest_f32i64(<2 x float> %x) {
; CHECK-LABEL: ustest_f32i64: ; CHECK-LABEL: ustest_f32i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: vmov r4, r0, d0 ; CHECK-NEXT: vmov r6, r0, d0
; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: subs r7, r2, #1
; CHECK-NEXT: mov.w r9, #1
; CHECK-NEXT: sbcs r7, r3, #0
; CHECK-NEXT: mov.w r5, #0
; CHECK-NEXT: mov.w r7, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r7, #1
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: csel r3, r3, r7, ne
; CHECK-NEXT: csel r6, r1, r7, ne
; CHECK-NEXT: csel r2, r2, r9, ne
; CHECK-NEXT: rsbs r1, r0, #0
; CHECK-NEXT: mov.w r7, #0
; CHECK-NEXT: sbcs.w r1, r5, r6
; CHECK-NEXT: sbcs.w r1, r5, r2
; CHECK-NEXT: sbcs.w r1, r5, r3
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r7, #1
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r8, r0, r7, ne
; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: bl __fixsfti ; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: subs r4, r2, #1 ; CHECK-NEXT: subs r5, r2, #1
; CHECK-NEXT: sbcs r4, r3, #0 ; CHECK-NEXT: mov.w r8, #1
; CHECK-NEXT: mov.w r4, #0 ; CHECK-NEXT: sbcs r5, r3, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r4, lt
; CHECK-NEXT: movlt r4, #1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r0, r0, r4, ne ; CHECK-NEXT: csel r0, r0, r4, ne
; CHECK-NEXT: csel r2, r2, r9, ne
; CHECK-NEXT: csel r3, r3, r4, ne ; CHECK-NEXT: csel r3, r3, r4, ne
; CHECK-NEXT: csel r1, r1, r4, ne ; CHECK-NEXT: csel r5, r1, r4, ne
; CHECK-NEXT: rsbs r4, r0, #0 ; CHECK-NEXT: csel r2, r2, r8, ne
; CHECK-NEXT: sbcs.w r4, r5, r1 ; CHECK-NEXT: rsbs r1, r0, #0
; CHECK-NEXT: sbcs.w r2, r5, r2 ; CHECK-NEXT: mov.w r4, #0
; CHECK-NEXT: sbcs.w r2, r5, r3 ; CHECK-NEXT: sbcs.w r1, r4, r5
; CHECK-NEXT: it lt ; CHECK-NEXT: sbcs.w r1, r4, r2
; CHECK-NEXT: movlt r5, #1 ; CHECK-NEXT: sbcs.w r1, r4, r3
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cset r7, lt
; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r2, r6, r7, ne ; CHECK-NEXT: csel r9, r0, r7, ne
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: csel r1, r1, r5, ne ; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: vmov q0[2], q0[0], r0, r8 ; CHECK-NEXT: subs r6, r2, #1
; CHECK-NEXT: vmov q0[3], q0[1], r1, r2 ; CHECK-NEXT: sbcs r6, r3, #0
; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r0, r0, r6, ne
; CHECK-NEXT: csel r2, r2, r8, ne
; CHECK-NEXT: csel r3, r3, r6, ne
; CHECK-NEXT: csel r1, r1, r6, ne
; CHECK-NEXT: rsbs r6, r0, #0
; CHECK-NEXT: sbcs.w r6, r4, r1
; CHECK-NEXT: sbcs.w r2, r4, r2
; CHECK-NEXT: sbcs.w r2, r4, r3
; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r3, r5, r7, ne
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r1, r1, r2, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r9
; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
entry: entry:
%conv = fptosi <2 x float> %x to <2 x i128> %conv = fptosi <2 x float> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616> %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616> %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
%1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer
%spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define arm_aapcs_vfpcc <2 x i64> @stest_f16i64(<2 x half> %x) { define arm_aapcs_vfpcc <2 x i64> @stest_f16i64(<2 x half> %x) {
; CHECK-LABEL: stest_f16i64: ; CHECK-LABEL: stest_f16i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.u16 r0, q0[1] ; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: bl __fixhfti ; CHECK-NEXT: bl __fixhfti
; CHECK-NEXT: subs.w r7, r0, #-1 ; CHECK-NEXT: subs.w r7, r0, #-1
; CHECK-NEXT: mvn r9, #-2147483648 ; CHECK-NEXT: mvn r9, #-2147483648
; CHECK-NEXT: sbcs.w r7, r1, r9 ; CHECK-NEXT: sbcs.w r7, r1, r9
; CHECK-NEXT: mov.w r6, #-1
; CHECK-NEXT: sbcs r7, r2, #0
; CHECK-NEXT: mov.w r10, #-2147483648 ; CHECK-NEXT: mov.w r10, #-2147483648
; CHECK-NEXT: sbcs r7, r2, #0
; CHECK-NEXT: sbcs r7, r3, #0 ; CHECK-NEXT: sbcs r7, r3, #0
; CHECK-NEXT: mov.w r4, #0 ; CHECK-NEXT: cset r7, lt
; CHECK-NEXT: mov.w r7, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r7, #1
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r11, r0, r6, ne
; CHECK-NEXT: csel r3, r3, r7, ne ; CHECK-NEXT: csel r3, r3, r7, ne
; CHECK-NEXT: csel r2, r2, r7, ne ; CHECK-NEXT: csel r2, r2, r7, ne
; CHECK-NEXT: mov.w r7, #-1
; CHECK-NEXT: csel r1, r1, r9, ne ; CHECK-NEXT: csel r1, r1, r9, ne
; CHECK-NEXT: rsbs.w r0, r11, #0 ; CHECK-NEXT: csel r4, r0, r7, ne
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: rsbs r0, r4, #0
; CHECK-NEXT: sbcs.w r0, r10, r1 ; CHECK-NEXT: sbcs.w r0, r10, r1
; CHECK-NEXT: sbcs.w r0, r6, r2 ; CHECK-NEXT: sbcs.w r0, r7, r2
; CHECK-NEXT: sbcs.w r0, r6, r3 ; CHECK-NEXT: sbcs.w r0, r7, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: movlt r7, #1
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: vmov.u16 r0, q4[0] ; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r8, r1, r10, ne ; CHECK-NEXT: csel r8, r1, r10, ne
; CHECK-NEXT: bl __fixhfti ; CHECK-NEXT: bl __fixhfti
; CHECK-NEXT: subs.w r5, r0, #-1 ; CHECK-NEXT: subs.w r6, r0, #-1
; CHECK-NEXT: sbcs.w r5, r1, r9 ; CHECK-NEXT: sbcs.w r6, r1, r9
; CHECK-NEXT: sbcs r5, r2, #0 ; CHECK-NEXT: sbcs r6, r2, #0
; CHECK-NEXT: sbcs r5, r3, #0 ; CHECK-NEXT: sbcs r6, r3, #0
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: it lt ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: movlt r5, #1 ; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r0, r0, r6, ne
; CHECK-NEXT: csel r1, r1, r9, ne ; CHECK-NEXT: csel r1, r1, r9, ne
; CHECK-NEXT: csel r3, r3, r5, ne ; CHECK-NEXT: csel r3, r3, r6, ne
; CHECK-NEXT: csel r2, r2, r5, ne ; CHECK-NEXT: csel r2, r2, r6, ne
; CHECK-NEXT: rsbs r5, r0, #0 ; CHECK-NEXT: rsbs r6, r0, #0
; CHECK-NEXT: sbcs.w r5, r10, r1 ; CHECK-NEXT: sbcs.w r6, r10, r1
; CHECK-NEXT: sbcs.w r2, r6, r2 ; CHECK-NEXT: sbcs.w r2, r7, r2
; CHECK-NEXT: sbcs.w r2, r6, r3 ; CHECK-NEXT: sbcs.w r2, r7, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: movlt r4, #1 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r1, r1, r10, ne ; CHECK-NEXT: csel r1, r1, r10, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r2, r11, r7, ne ; CHECK-NEXT: csel r3, r4, r5, ne
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r0, r0, r4, ne ; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r3
; CHECK-NEXT: vmov q0[3], q0[1], r1, r8 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r8
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
entry: entry:
%conv = fptosi <2 x half> %x to <2 x i128> %conv = fptosi <2 x half> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807> %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807> %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>
%1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808> %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>
%spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808> %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
Show All 32 Lines
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.u16 r0, q0[1] ; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: bl __fixhfti ; CHECK-NEXT: bl __fixhfti
; CHECK-NEXT: subs r7, r2, #1 ; CHECK-NEXT: subs r5, r2, #1
; CHECK-NEXT: mov.w r8, #1 ; CHECK-NEXT: mov.w r8, #1
; CHECK-NEXT: sbcs r7, r3, #0 ; CHECK-NEXT: sbcs r5, r3, #0
; CHECK-NEXT: mov.w r4, #0
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: mov.w r7, #0
; CHECK-NEXT: mov.w r6, #0 ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: it lt ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: movlt r7, #1 ; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: csel r3, r3, r5, ne
; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: csel r3, r3, r7, ne
; CHECK-NEXT: csel r2, r2, r8, ne ; CHECK-NEXT: csel r2, r2, r8, ne
; CHECK-NEXT: csel r5, r1, r7, ne ; CHECK-NEXT: csel r4, r1, r5, ne
; CHECK-NEXT: rsbs r1, r0, #0 ; CHECK-NEXT: rsbs r1, r0, #0
; CHECK-NEXT: sbcs.w r1, r4, r5 ; CHECK-NEXT: sbcs.w r1, r7, r4
; CHECK-NEXT: sbcs.w r1, r4, r2 ; CHECK-NEXT: sbcs.w r1, r7, r2
; CHECK-NEXT: sbcs.w r1, r4, r3 ; CHECK-NEXT: sbcs.w r1, r7, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: movlt r6, #1
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r9, r0, r6, ne ; CHECK-NEXT: csel r9, r0, r6, ne
; CHECK-NEXT: vmov.u16 r0, q4[0] ; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: bl __fixhfti ; CHECK-NEXT: bl __fixhfti
; CHECK-NEXT: subs r7, r2, #1 ; CHECK-NEXT: subs r5, r2, #1
; CHECK-NEXT: sbcs r7, r3, #0 ; CHECK-NEXT: sbcs r5, r3, #0
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: it lt ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: movlt r7, #1 ; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: csel r2, r2, r8, ne ; CHECK-NEXT: csel r2, r2, r8, ne
; CHECK-NEXT: csel r3, r3, r7, ne ; CHECK-NEXT: csel r3, r3, r5, ne
; CHECK-NEXT: csel r1, r1, r7, ne ; CHECK-NEXT: csel r1, r1, r5, ne
; CHECK-NEXT: rsbs r7, r0, #0 ; CHECK-NEXT: rsbs r5, r0, #0
; CHECK-NEXT: sbcs.w r7, r4, r1 ; CHECK-NEXT: sbcs.w r5, r7, r1
; CHECK-NEXT: sbcs.w r2, r4, r2 ; CHECK-NEXT: sbcs.w r2, r7, r2
; CHECK-NEXT: sbcs.w r2, r4, r3 ; CHECK-NEXT: sbcs.w r2, r7, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: movlt r4, #1 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: csel r0, r0, r4, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r2, r5, r6, ne ; CHECK-NEXT: csel r3, r4, r6, ne
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r1, r1, r4, ne ; CHECK-NEXT: csel r1, r1, r2, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r9 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r9
; CHECK-NEXT: vmov q0[3], q0[1], r1, r2 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
entry: entry:
%conv = fptosi <2 x half> %x to <2 x i128> %conv = fptosi <2 x half> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616> %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616> %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
%1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer
▲ Show 20 Lines • Show All 1,089 Lines • ▼ Show 20 Linesentry:
%spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>) %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define arm_aapcs_vfpcc <2 x i64> @utest_f64i64_mm(<2 x double> %x) { define arm_aapcs_vfpcc <2 x i64> @utest_f64i64_mm(<2 x double> %x) {
; CHECK-LABEL: utest_f64i64_mm: ; CHECK-LABEL: utest_f64i64_mm:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov r0, r1, d9 ; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: bl __fixunsdfti ; CHECK-NEXT: bl __fixunsdfti
; CHECK-NEXT: mov r8, r1 ; CHECK-NEXT: mov r8, r1
; CHECK-NEXT: vmov r4, r1, d8 ; CHECK-NEXT: vmov r4, r1, d8
; CHECK-NEXT: eor r7, r2, #1 ; CHECK-NEXT: eor r6, r2, #1
; CHECK-NEXT: subs r2, #1 ; CHECK-NEXT: subs r2, #1
; CHECK-NEXT: sbcs r2, r3, #0 ; CHECK-NEXT: sbcs r2, r3, #0
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: orr.w r6, r6, r3
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r7, lo
; CHECK-NEXT: movlo r5, #1
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: orr.w r7, r7, r3
; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: mov.w r6, #0 ; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: csel r9, r0, r7, ne ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r5, r0, r6, ne
; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: bl __fixunsdfti ; CHECK-NEXT: bl __fixunsdfti
; CHECK-NEXT: eor r4, r2, #1 ; CHECK-NEXT: eor r4, r2, #1
; CHECK-NEXT: subs r2, #1 ; CHECK-NEXT: subs r2, #1
; CHECK-NEXT: sbcs r2, r3, #0 ; CHECK-NEXT: sbcs r2, r3, #0
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: orr.w r4, r4, r3 ; CHECK-NEXT: orr.w r4, r4, r3
; CHECK-NEXT: csel r0, r0, r6, ne ; CHECK-NEXT: cset r2, lo
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r0, r0, r4, ne ; CHECK-NEXT: csel r0, r0, r4, ne
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r2, r8, r5, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r2, r2, r7, ne ; CHECK-NEXT: csel r3, r8, r7, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r1, r1, r6, ne ; CHECK-NEXT: csel r3, r3, r6, ne
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r1, r1, r2, ne
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r1, r1, r4, ne ; CHECK-NEXT: csel r1, r1, r4, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r9 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: vmov q0[3], q0[1], r1, r2 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
entry: entry:
%conv = fptoui <2 x double> %x to <2 x i128> %conv = fptoui <2 x double> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>) %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define arm_aapcs_vfpcc <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { define arm_aapcs_vfpcc <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {
; CHECK-LABEL: ustest_f64i64_mm: ; CHECK-LABEL: ustest_f64i64_mm:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov r0, r1, d9 ; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: bl __fixdfti ; CHECK-NEXT: bl __fixdfti
; CHECK-NEXT: subs r6, r2, #1 ; CHECK-NEXT: subs r6, r2, #1
; CHECK-NEXT: eor r7, r2, #1 ; CHECK-NEXT: eor r7, r2, #1
; CHECK-NEXT: sbcs r6, r3, #0 ; CHECK-NEXT: sbcs r6, r3, #0
; CHECK-NEXT: orr.w r7, r7, r3 ; CHECK-NEXT: orr.w r7, r7, r3
; CHECK-NEXT: mov.w r6, #0 ; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: mov.w r10, #1 ; CHECK-NEXT: mov.w r10, #1
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r6, #1
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: mov.w r11, #0
; CHECK-NEXT: csel r0, r0, r6, ne ; CHECK-NEXT: csel r0, r0, r6, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r0, r0, r7, ne ; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r1, r1, r6, ne ; CHECK-NEXT: csel r1, r1, r6, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r11, r1, r7, ne ; CHECK-NEXT: csel r4, r1, r7, ne
; CHECK-NEXT: movs r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: cmp.w r11, #0 ; CHECK-NEXT: csel r1, r0, r4, ne
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: csel r7, r0, r1, eq
; CHECK-NEXT: csel r1, r0, r11, ne
; CHECK-NEXT: csel r6, r0, r1, eq
; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: csel r1, r2, r10, lo ; CHECK-NEXT: csel r1, r2, r10, lo
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csel r2, r2, r10, mi ; CHECK-NEXT: csel r2, r2, r10, mi
; CHECK-NEXT: csel r1, r1, r2, eq ; CHECK-NEXT: csel r1, r1, r2, eq
; CHECK-NEXT: csel r2, r3, r4, mi ; CHECK-NEXT: csel r2, r3, r11, mi
; CHECK-NEXT: rsbs r3, r1, #0 ; CHECK-NEXT: rsbs r3, r1, #0
; CHECK-NEXT: sbcs.w r3, r4, r2 ; CHECK-NEXT: sbcs.w r3, r11, r2
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: movlt r7, #1 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: csel r3, r0, r6, ne
; CHECK-NEXT: csel r3, r0, r7, ne
; CHECK-NEXT: orrs.w r9, r1, r2 ; CHECK-NEXT: orrs.w r9, r1, r2
; CHECK-NEXT: vmov r0, r1, d8 ; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: csel r8, r6, r3, eq ; CHECK-NEXT: csel r8, r7, r3, eq
; CHECK-NEXT: bl __fixdfti ; CHECK-NEXT: bl __fixdfti
; CHECK-NEXT: subs r5, r2, #1 ; CHECK-NEXT: subs r5, r2, #1
; CHECK-NEXT: eor r6, r2, #1 ; CHECK-NEXT: eor r7, r2, #1
; CHECK-NEXT: sbcs r5, r3, #0 ; CHECK-NEXT: sbcs r5, r3, #0
; CHECK-NEXT: orr.w r6, r6, r3 ; CHECK-NEXT: orr.w r7, r7, r3
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r0, r0, r5, ne ; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r0, r0, r6, ne ; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r1, r1, r5, ne ; CHECK-NEXT: csel r1, r1, r5, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r1, r1, r6, ne ; CHECK-NEXT: csel r1, r1, r7, ne
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csel r6, r0, r1, ne ; CHECK-NEXT: csel r7, r0, r1, ne
; CHECK-NEXT: csel r6, r0, r6, eq ; CHECK-NEXT: csel r7, r0, r7, eq
; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: csel r5, r2, r10, lo ; CHECK-NEXT: csel r5, r2, r10, lo
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csel r2, r2, r10, mi ; CHECK-NEXT: csel r2, r2, r10, mi
; CHECK-NEXT: csel r3, r3, r4, mi ; CHECK-NEXT: csel r3, r3, r11, mi
; CHECK-NEXT: csel r2, r5, r2, eq ; CHECK-NEXT: csel r2, r5, r2, eq
; CHECK-NEXT: rsbs r5, r2, #0 ; CHECK-NEXT: rsbs r5, r2, #0
; CHECK-NEXT: sbcs.w r5, r4, r3 ; CHECK-NEXT: sbcs.w r5, r11, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: movlt r4, #1 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: csel r0, r0, r4, ne
; CHECK-NEXT: orrs r2, r3 ; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: csel r0, r6, r0, eq ; CHECK-NEXT: csel r0, r7, r0, eq
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r3, r11, r7, ne ; CHECK-NEXT: csel r3, r4, r6, ne
; CHECK-NEXT: cmp.w r9, #0 ; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: csel r3, r11, r3, eq ; CHECK-NEXT: csel r3, r4, r3, eq
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r7, r1, r4, ne ; CHECK-NEXT: csel r7, r1, r5, ne
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r1, r1, r7, eq ; CHECK-NEXT: csel r1, r1, r7, eq
; CHECK-NEXT: vmov q0[2], q0[0], r0, r8 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r8
; CHECK-NEXT: vmov q0[3], q0[1], r1, r3 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
entry: entry:
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Linesentry:
%spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>) %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define arm_aapcs_vfpcc <2 x i64> @utest_f32i64_mm(<2 x float> %x) { define arm_aapcs_vfpcc <2 x i64> @utest_f32i64_mm(<2 x float> %x) {
; CHECK-LABEL: utest_f32i64_mm: ; CHECK-LABEL: utest_f32i64_mm:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: vmov r5, r0, d0 ; CHECK-NEXT: vmov r5, r0, d0
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: mov r8, r1 ; CHECK-NEXT: mov r8, r1
; CHECK-NEXT: eor r1, r2, #1 ; CHECK-NEXT: eor r1, r2, #1
; CHECK-NEXT: orr.w r7, r1, r3 ; CHECK-NEXT: orr.w r6, r1, r3
; CHECK-NEXT: subs r1, r2, #1 ; CHECK-NEXT: subs r1, r2, #1
; CHECK-NEXT: sbcs r1, r3, #0 ; CHECK-NEXT: sbcs r1, r3, #0
; CHECK-NEXT: mov.w r4, #0 ; CHECK-NEXT: cset r7, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r4, #1
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r0, r0, r4, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r9, r0, r7, ne ; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r4, r0, r6, ne
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: movs r6, #0
; CHECK-NEXT: bl __fixunssfti ; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: eor r5, r2, #1 ; CHECK-NEXT: eor r5, r2, #1
; CHECK-NEXT: subs r2, #1 ; CHECK-NEXT: subs r2, #1
; CHECK-NEXT: sbcs r2, r3, #0 ; CHECK-NEXT: sbcs r2, r3, #0
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: orr.w r5, r5, r3 ; CHECK-NEXT: orr.w r5, r5, r3
; CHECK-NEXT: csel r0, r0, r6, ne ; CHECK-NEXT: cset r2, lo
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r0, r0, r5, ne ; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r2, r8, r4, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r2, r2, r7, ne ; CHECK-NEXT: csel r3, r8, r7, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r1, r1, r6, ne ; CHECK-NEXT: csel r3, r3, r6, ne
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r1, r1, r2, ne
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r1, r1, r5, ne ; CHECK-NEXT: csel r1, r1, r5, ne
; CHECK-NEXT: vmov q0[2], q0[0], r0, r9 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
; CHECK-NEXT: vmov q0[3], q0[1], r1, r2 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
entry: entry:
%conv = fptoui <2 x float> %x to <2 x i128> %conv = fptoui <2 x float> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>) %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define arm_aapcs_vfpcc <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { define arm_aapcs_vfpcc <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {
; CHECK-LABEL: ustest_f32i64_mm: ; CHECK-LABEL: ustest_f32i64_mm:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: vmov r9, r0, d0 ; CHECK-NEXT: vmov r10, r0, d0
; CHECK-NEXT: bl __fixsfti ; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: subs r6, r2, #1 ; CHECK-NEXT: subs r6, r2, #1
; CHECK-NEXT: eor r7, r2, #1 ; CHECK-NEXT: eor r7, r2, #1
; CHECK-NEXT: sbcs r6, r3, #0 ; CHECK-NEXT: sbcs r6, r3, #0
; CHECK-NEXT: orr.w r7, r7, r3 ; CHECK-NEXT: orr.w r7, r7, r3
; CHECK-NEXT: mov.w r6, #0 ; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: mov.w r11, #1 ; CHECK-NEXT: mov.w r11, #1
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r6, #1
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: mov.w r8, #0
; CHECK-NEXT: csel r0, r0, r6, ne ; CHECK-NEXT: csel r0, r0, r6, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r0, r0, r7, ne ; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r1, r1, r6, ne ; CHECK-NEXT: csel r1, r1, r6, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r8, r1, r7, ne ; CHECK-NEXT: csel r5, r1, r7, ne
; CHECK-NEXT: movs r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: cmp.w r8, #0 ; CHECK-NEXT: csel r1, r0, r5, ne
; CHECK-NEXT: csel r1, r0, r8, ne
; CHECK-NEXT: csel r1, r0, r1, eq ; CHECK-NEXT: csel r1, r0, r1, eq
; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: csel r7, r2, r11, lo ; CHECK-NEXT: csel r7, r2, r11, lo
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csel r2, r2, r11, mi ; CHECK-NEXT: csel r2, r2, r11, mi
; CHECK-NEXT: csel r3, r3, r5, mi ; CHECK-NEXT: csel r3, r3, r8, mi
; CHECK-NEXT: csel r2, r7, r2, eq ; CHECK-NEXT: csel r2, r7, r2, eq
; CHECK-NEXT: rsbs r7, r2, #0 ; CHECK-NEXT: rsbs r7, r2, #0
; CHECK-NEXT: sbcs.w r7, r5, r3 ; CHECK-NEXT: sbcs.w r7, r8, r3
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: cset r7, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r7, #1
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r0, r0, r7, ne ; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: orrs.w r10, r2, r3 ; CHECK-NEXT: orrs.w r9, r2, r3
; CHECK-NEXT: csel r0, r1, r0, eq ; CHECK-NEXT: csel r0, r1, r0, eq
; CHECK-NEXT: str r0, [sp] @ 4-byte Spill ; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
; CHECK-NEXT: mov r0, r9 ; CHECK-NEXT: mov r0, r10
; CHECK-NEXT: bl __fixsfti ; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: subs r6, r2, #1 ; CHECK-NEXT: subs r4, r2, #1
; CHECK-NEXT: eor r4, r2, #1 ; CHECK-NEXT: eor r6, r2, #1
; CHECK-NEXT: sbcs r6, r3, #0 ; CHECK-NEXT: sbcs r4, r3, #0
; CHECK-NEXT: orr.w r4, r4, r3 ; CHECK-NEXT: orr.w r6, r6, r3
; CHECK-NEXT: mov.w r6, #0 ; CHECK-NEXT: cset r4, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r0, r0, r6, ne
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r0, r0, r4, ne ; CHECK-NEXT: csel r0, r0, r4, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r1, r1, r6, ne ; CHECK-NEXT: csel r0, r0, r6, ne
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r1, r1, r4, ne ; CHECK-NEXT: csel r1, r1, r4, ne
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r1, r1, r6, ne
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csel r6, r0, r1, ne ; CHECK-NEXT: csel r6, r0, r1, ne
; CHECK-NEXT: csel r6, r0, r6, eq ; CHECK-NEXT: csel r6, r0, r6, eq
; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: csel r4, r2, r11, lo ; CHECK-NEXT: csel r4, r2, r11, lo
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csel r2, r2, r11, mi ; CHECK-NEXT: csel r2, r2, r11, mi
; CHECK-NEXT: csel r3, r3, r5, mi ; CHECK-NEXT: csel r3, r3, r8, mi
; CHECK-NEXT: csel r2, r4, r2, eq ; CHECK-NEXT: csel r2, r4, r2, eq
; CHECK-NEXT: rsbs r4, r2, #0 ; CHECK-NEXT: rsbs r4, r2, #0
; CHECK-NEXT: sbcs.w r4, r5, r3 ; CHECK-NEXT: sbcs.w r4, r8, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r4, lt
; CHECK-NEXT: movlt r5, #1 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: csel r0, r0, r4, ne
; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: orrs r2, r3 ; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: csel r0, r6, r0, eq ; CHECK-NEXT: csel r0, r6, r0, eq
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r3, r8, r7, ne ; CHECK-NEXT: csel r3, r5, r7, ne
; CHECK-NEXT: cmp.w r10, #0 ; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: csel r3, r8, r3, eq ; CHECK-NEXT: csel r3, r5, r3, eq
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r7, r1, r5, ne ; CHECK-NEXT: csel r7, r1, r4, ne
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload ; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
; CHECK-NEXT: csel r1, r1, r7, eq ; CHECK-NEXT: csel r1, r1, r7, eq
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r2
; CHECK-NEXT: vmov q0[3], q0[1], r1, r3 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
entry: entry:
▲ Show 20 Lines • Show All 161 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov.u16 r0, q0[1] ; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: bl __fixhfti ; CHECK-NEXT: bl __fixhfti
; CHECK-NEXT: subs r6, r2, #1 ; CHECK-NEXT: subs r6, r2, #1
; CHECK-NEXT: eor r7, r2, #1 ; CHECK-NEXT: eor r7, r2, #1
; CHECK-NEXT: sbcs r6, r3, #0 ; CHECK-NEXT: sbcs r6, r3, #0
; CHECK-NEXT: orr.w r7, r7, r3 ; CHECK-NEXT: orr.w r7, r7, r3
; CHECK-NEXT: mov.w r6, #0 ; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: mov.w r10, #1 ; CHECK-NEXT: mov.w r10, #1
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r6, #1
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: mov.w r11, #0
; CHECK-NEXT: csel r0, r0, r6, ne ; CHECK-NEXT: csel r0, r0, r6, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r0, r0, r7, ne ; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r1, r1, r6, ne ; CHECK-NEXT: csel r1, r1, r6, ne
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r11, r1, r7, ne ; CHECK-NEXT: csel r4, r1, r7, ne
; CHECK-NEXT: movs r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: cmp.w r11, #0 ; CHECK-NEXT: csel r1, r0, r4, ne
; CHECK-NEXT: csel r1, r0, r11, ne
; CHECK-NEXT: csel r1, r0, r1, eq ; CHECK-NEXT: csel r1, r0, r1, eq
; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: csel r7, r2, r10, lo ; CHECK-NEXT: csel r6, r2, r10, lo
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csel r2, r2, r10, mi ; CHECK-NEXT: csel r2, r2, r10, mi
; CHECK-NEXT: csel r3, r3, r4, mi ; CHECK-NEXT: csel r3, r3, r11, mi
; CHECK-NEXT: csel r2, r7, r2, eq ; CHECK-NEXT: csel r2, r6, r2, eq
; CHECK-NEXT: rsbs r7, r2, #0 ; CHECK-NEXT: rsbs r6, r2, #0
; CHECK-NEXT: sbcs.w r7, r4, r3 ; CHECK-NEXT: sbcs.w r6, r11, r3
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: cset r6, lt
; CHECK-NEXT: it lt ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: movlt r7, #1 ; CHECK-NEXT: csel r0, r0, r6, ne
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: orrs.w r9, r2, r3 ; CHECK-NEXT: orrs.w r9, r2, r3
; CHECK-NEXT: csel r8, r1, r0, eq ; CHECK-NEXT: csel r8, r1, r0, eq
; CHECK-NEXT: vmov.u16 r0, q4[0] ; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: bl __fixhfti ; CHECK-NEXT: bl __fixhfti
; CHECK-NEXT: subs r5, r2, #1 ; CHECK-NEXT: subs r5, r2, #1
; CHECK-NEXT: eor r6, r2, #1 ; CHECK-NEXT: eor r7, r2, #1
; CHECK-NEXT: sbcs r5, r3, #0 ; CHECK-NEXT: sbcs r5, r3, #0
; CHECK-NEXT: orr.w r6, r6, r3 ; CHECK-NEXT: orr.w r7, r7, r3
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r0, r0, r5, ne ; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r0, r0, r6, ne ; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r1, r1, r5, ne ; CHECK-NEXT: csel r1, r1, r5, ne
; CHECK-NEXT: cmp r6, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r1, r1, r6, ne ; CHECK-NEXT: csel r1, r1, r7, ne
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csel r6, r0, r1, ne ; CHECK-NEXT: csel r7, r0, r1, ne
; CHECK-NEXT: csel r6, r0, r6, eq ; CHECK-NEXT: csel r7, r0, r7, eq
; CHECK-NEXT: cmp r2, #1 ; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: csel r5, r2, r10, lo ; CHECK-NEXT: csel r5, r2, r10, lo
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csel r2, r2, r10, mi ; CHECK-NEXT: csel r2, r2, r10, mi
; CHECK-NEXT: csel r3, r3, r4, mi ; CHECK-NEXT: csel r3, r3, r11, mi
; CHECK-NEXT: csel r2, r5, r2, eq ; CHECK-NEXT: csel r2, r5, r2, eq
; CHECK-NEXT: rsbs r5, r2, #0 ; CHECK-NEXT: rsbs r5, r2, #0
; CHECK-NEXT: sbcs.w r5, r4, r3 ; CHECK-NEXT: sbcs.w r5, r11, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: movlt r4, #1 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: csel r0, r0, r4, ne
; CHECK-NEXT: orrs r2, r3 ; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: csel r0, r6, r0, eq ; CHECK-NEXT: csel r0, r7, r0, eq
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csel r3, r11, r7, ne ; CHECK-NEXT: csel r3, r4, r6, ne
; CHECK-NEXT: cmp.w r9, #0 ; CHECK-NEXT: cmp.w r9, #0
; CHECK-NEXT: csel r3, r11, r3, eq ; CHECK-NEXT: csel r3, r4, r3, eq
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r7, r1, r4, ne ; CHECK-NEXT: csel r7, r1, r5, ne
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r1, r1, r7, eq ; CHECK-NEXT: csel r1, r1, r7, eq
; CHECK-NEXT: vmov q0[2], q0[0], r0, r8 ; CHECK-NEXT: vmov q0[2], q0[0], r0, r8
; CHECK-NEXT: vmov q0[3], q0[1], r1, r3 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
entry: entry:
Show All 25 Lines

llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
define void @foo_sext_v2i64_v2i32(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32> *%src) { define void @foo_sext_v2i64_v2i32(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32> *%src) {
; CHECK-LE-LABEL: foo_sext_v2i64_v2i32: ; CHECK-LE-LABEL: foo_sext_v2i64_v2i32:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r4, r5, r7, lr} ; CHECK-LE-NEXT: .save {r4, r5, r7, lr}
; CHECK-LE-NEXT: push {r4, r5, r7, lr} ; CHECK-LE-NEXT: push {r4, r5, r7, lr}
; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: .pad #4
; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: ldrd lr, r5, [r1] ; CHECK-LE-NEXT: ldrd lr, r1, [r1]
; CHECK-LE-NEXT: movs r3, #0 ; CHECK-LE-NEXT: rsbs r3, r1, #0
; CHECK-LE-NEXT: @ implicit-def: $q0 ; CHECK-LE-NEXT: mov.w r12, #0
; CHECK-LE-NEXT: rsbs.w r1, lr, #0 ; CHECK-LE-NEXT: sbcs.w r3, r12, r1, asr #31
; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r5 ; CHECK-LE-NEXT: cset r3, lt
; CHECK-LE-NEXT: sbcs.w r1, r3, lr, asr #31 ; CHECK-LE-NEXT: @ implicit-def: $q1
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: vmov q0[2], q0[0], lr, r1
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r1, #1
; CHECK-LE-NEXT: rsbs r4, r5, #0
; CHECK-LE-NEXT: sbcs.w r4, r3, r5, asr #31
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r3, #1
; CHECK-LE-NEXT: cmp r3, #0 ; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r3, #1 ; CHECK-LE-NEXT: mvnne r3, #1
; CHECK-LE-NEXT: bfi r3, r1, #0, #1 ; CHECK-LE-NEXT: rsbs.w r4, lr, #0
; CHECK-LE-NEXT: vmov r4, s4 ; CHECK-LE-NEXT: sbcs.w r4, r12, lr, asr #31
; CHECK-LE-NEXT: mov.w lr, #0
; CHECK-LE-NEXT: cset r4, lt
; CHECK-LE-NEXT: bfi r3, r4, #0, #1
; CHECK-LE-NEXT: and r12, r3, #3 ; CHECK-LE-NEXT: and r12, r3, #3
; CHECK-LE-NEXT: lsls r1, r3, #31 ; CHECK-LE-NEXT: lsls r3, r3, #31
; CHECK-LE-NEXT: itt ne ; CHECK-LE-NEXT: itt ne
; CHECK-LE-NEXT: ldrne r1, [r2] ; CHECK-LE-NEXT: ldrne r3, [r2]
; CHECK-LE-NEXT: vmovne.32 q0[0], r1 ; CHECK-LE-NEXT: vmovne.32 q1[0], r3
; CHECK-LE-NEXT: lsls.w r1, r12, #30 ; CHECK-LE-NEXT: lsls.w r1, r12, #30
; CHECK-LE-NEXT: itt mi ; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: ldrmi r1, [r2, #4] ; CHECK-LE-NEXT: ldrmi r1, [r2, #4]
; CHECK-LE-NEXT: vmovmi.32 q0[2], r1 ; CHECK-LE-NEXT: vmovmi.32 q1[2], r1
; CHECK-LE-NEXT: vmov r3, s0 ; CHECK-LE-NEXT: vmov r1, s6
; CHECK-LE-NEXT: movs r2, #0 ; CHECK-LE-NEXT: vmov r2, s2
; CHECK-LE-NEXT: vmov r1, s2 ; CHECK-LE-NEXT: vmov r3, s4
; CHECK-LE-NEXT: vmov q0[2], q0[0], r3, r1 ; CHECK-LE-NEXT: vmov q1[2], q1[0], r3, r1
; CHECK-LE-NEXT: rsbs r5, r4, #0 ; CHECK-LE-NEXT: rsbs r5, r2, #0
; CHECK-LE-NEXT: asr.w lr, r3, #31
; CHECK-LE-NEXT: vmov r3, s6
; CHECK-LE-NEXT: asr.w r12, r1, #31 ; CHECK-LE-NEXT: asr.w r12, r1, #31
; CHECK-LE-NEXT: sbcs.w r1, r2, r4, asr #31 ; CHECK-LE-NEXT: sbcs.w r1, lr, r2, asr #31
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: vmov r1, s0
; CHECK-LE-NEXT: vmov q0[3], q0[1], lr, r12 ; CHECK-LE-NEXT: cset r2, lt
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r1, #1
; CHECK-LE-NEXT: rsbs r5, r3, #0
; CHECK-LE-NEXT: sbcs.w r3, r2, r3, asr #31
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r2, #1
; CHECK-LE-NEXT: cmp r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: asr.w r4, r3, #31
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r2, #1 ; CHECK-LE-NEXT: mvnne r2, #1
; CHECK-LE-NEXT: vmov q1[3], q1[1], r4, r12
; CHECK-LE-NEXT: rsbs r3, r1, #0
; CHECK-LE-NEXT: sbcs.w r1, lr, r1, asr #31
; CHECK-LE-NEXT: cset r1, lt
; CHECK-LE-NEXT: bfi r2, r1, #0, #1 ; CHECK-LE-NEXT: bfi r2, r1, #0, #1
; CHECK-LE-NEXT: and r1, r2, #3 ; CHECK-LE-NEXT: and r1, r2, #3
; CHECK-LE-NEXT: lsls r2, r2, #31 ; CHECK-LE-NEXT: lsls r2, r2, #31
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: vstrne d0, [r0] ; CHECK-LE-NEXT: vstrne d2, [r0]
; CHECK-LE-NEXT: lsls r1, r1, #30 ; CHECK-LE-NEXT: lsls r1, r1, #30
; CHECK-LE-NEXT: it mi ; CHECK-LE-NEXT: it mi
; CHECK-LE-NEXT: vstrmi d1, [r0, #8] ; CHECK-LE-NEXT: vstrmi d3, [r0, #8]
; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: pop {r4, r5, r7, pc} ; CHECK-LE-NEXT: pop {r4, r5, r7, pc}
; ;
; CHECK-BE-LABEL: foo_sext_v2i64_v2i32: ; CHECK-BE-LABEL: foo_sext_v2i64_v2i32:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r4, r5, r7, lr} ; CHECK-BE-NEXT: .save {r4, r5, r7, lr}
; CHECK-BE-NEXT: push {r4, r5, r7, lr} ; CHECK-BE-NEXT: push {r4, r5, r7, lr}
; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: .pad #4
; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: sub sp, #4
; CHECK-BE-NEXT: ldrd r12, lr, [r1] ; CHECK-BE-NEXT: ldrd r3, lr, [r1]
; CHECK-BE-NEXT: rsbs.w r1, lr, #0 ; CHECK-BE-NEXT: mov.w r12, #0
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: @ implicit-def: $q2
; CHECK-BE-NEXT: sbcs.w r1, r3, lr, asr #31 ; CHECK-BE-NEXT: rsbs r1, r3, #0
; CHECK-BE-NEXT: vmov q0[3], q0[1], r12, lr ; CHECK-BE-NEXT: vmov q0[3], q0[1], r3, lr
; CHECK-BE-NEXT: mov.w lr, #0 ; CHECK-BE-NEXT: sbcs.w r1, r12, r3, asr #31
; CHECK-BE-NEXT: it lt ; CHECK-BE-NEXT: cset r3, lt
; CHECK-BE-NEXT: movlt.w lr, #1
; CHECK-BE-NEXT: rsbs.w r1, r12, #0
; CHECK-BE-NEXT: sbcs.w r1, r3, r12, asr #31
; CHECK-BE-NEXT: it lt
; CHECK-BE-NEXT: movlt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r3, #1 ; CHECK-BE-NEXT: mvnne r3, #1
; CHECK-BE-NEXT: bfi r3, lr, #0, #1 ; CHECK-BE-NEXT: rsbs.w r1, lr, #0
; CHECK-BE-NEXT: @ implicit-def: $q2 ; CHECK-BE-NEXT: sbcs.w r1, r12, lr, asr #31
; CHECK-BE-NEXT: cset r1, lt
; CHECK-BE-NEXT: bfi r3, r1, #0, #1
; CHECK-BE-NEXT: and r1, r3, #3 ; CHECK-BE-NEXT: and r1, r3, #3
; CHECK-BE-NEXT: lsls r3, r3, #30 ; CHECK-BE-NEXT: lsls r3, r3, #30
; CHECK-BE-NEXT: bpl .LBB5_2 ; CHECK-BE-NEXT: bpl .LBB5_2
; CHECK-BE-NEXT: @ %bb.1: @ %cond.load ; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
; CHECK-BE-NEXT: ldr r3, [r2] ; CHECK-BE-NEXT: ldr r3, [r2]
; CHECK-BE-NEXT: vmov.32 q1[1], r3 ; CHECK-BE-NEXT: vmov.32 q1[1], r3
; CHECK-BE-NEXT: vrev64.32 q2, q1 ; CHECK-BE-NEXT: vrev64.32 q2, q1
; CHECK-BE-NEXT: .LBB5_2: @ %else ; CHECK-BE-NEXT: .LBB5_2: @ %else
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: beq .LBB5_4 ; CHECK-BE-NEXT: beq .LBB5_4
; CHECK-BE-NEXT: @ %bb.3: @ %cond.load1 ; CHECK-BE-NEXT: @ %bb.3: @ %cond.load1
; CHECK-BE-NEXT: ldr r1, [r2, #4] ; CHECK-BE-NEXT: ldr r1, [r2, #4]
; CHECK-BE-NEXT: vrev64.32 q0, q2 ; CHECK-BE-NEXT: vrev64.32 q0, q2
; CHECK-BE-NEXT: vmov.32 q0[3], r1 ; CHECK-BE-NEXT: vmov.32 q0[3], r1
; CHECK-BE-NEXT: vrev64.32 q2, q0 ; CHECK-BE-NEXT: vrev64.32 q2, q0
; CHECK-BE-NEXT: .LBB5_4: @ %else2 ; CHECK-BE-NEXT: .LBB5_4: @ %else2
; CHECK-BE-NEXT: vrev64.32 q0, q2 ; CHECK-BE-NEXT: vrev64.32 q0, q2
; CHECK-BE-NEXT: vrev64.32 q2, q1 ; CHECK-BE-NEXT: vrev64.32 q2, q1
; CHECK-BE-NEXT: vmov r2, s11
; CHECK-BE-NEXT: movs r4, #0
; CHECK-BE-NEXT: vmov r1, s3 ; CHECK-BE-NEXT: vmov r1, s3
; CHECK-BE-NEXT: movs r4, #0
; CHECK-BE-NEXT: vmov r3, s1 ; CHECK-BE-NEXT: vmov r3, s1
; CHECK-BE-NEXT: rsbs r5, r2, #0
; CHECK-BE-NEXT: sbcs.w r2, r4, r2, asr #31
; CHECK-BE-NEXT: vmov r2, s9 ; CHECK-BE-NEXT: vmov r2, s9
; CHECK-BE-NEXT: asr.w r12, r1, #31 ; CHECK-BE-NEXT: asr.w r12, r1, #31
; CHECK-BE-NEXT: asr.w lr, r3, #31 ; CHECK-BE-NEXT: asr.w lr, r3, #31
; CHECK-BE-NEXT: rsbs r5, r2, #0
; CHECK-BE-NEXT: vmov q1[2], q1[0], lr, r12 ; CHECK-BE-NEXT: vmov q1[2], q1[0], lr, r12
; CHECK-BE-NEXT: sbcs.w r2, r4, r2, asr #31
; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, r1 ; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, r1
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: vmov r1, s11
; CHECK-BE-NEXT: it lt ; CHECK-BE-NEXT: cset r2, lt
; CHECK-BE-NEXT: movlt r1, #1
; CHECK-BE-NEXT: vrev64.32 q0, q1 ; CHECK-BE-NEXT: vrev64.32 q0, q1
; CHECK-BE-NEXT: rsbs r3, r2, #0 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: sbcs.w r2, r4, r2, asr #31
; CHECK-BE-NEXT: it lt
; CHECK-BE-NEXT: movlt r4, #1
; CHECK-BE-NEXT: cmp r4, #0
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r4, #1 ; CHECK-BE-NEXT: mvnne r2, #1
; CHECK-BE-NEXT: bfi r4, r1, #0, #1 ; CHECK-BE-NEXT: rsbs r3, r1, #0
; CHECK-BE-NEXT: and r1, r4, #3 ; CHECK-BE-NEXT: sbcs.w r1, r4, r1, asr #31
; CHECK-BE-NEXT: lsls r2, r4, #30 ; CHECK-BE-NEXT: cset r1, lt
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
; CHECK-BE-NEXT: and r1, r2, #3
; CHECK-BE-NEXT: lsls r2, r2, #30
; CHECK-BE-NEXT: it mi ; CHECK-BE-NEXT: it mi
; CHECK-BE-NEXT: vstrmi d0, [r0] ; CHECK-BE-NEXT: vstrmi d0, [r0]
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: vstrne d1, [r0, #8] ; CHECK-BE-NEXT: vstrne d1, [r0, #8]
; CHECK-BE-NEXT: add sp, #4 ; CHECK-BE-NEXT: add sp, #4
; CHECK-BE-NEXT: pop {r4, r5, r7, pc} ; CHECK-BE-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%0 = load <2 x i32>, <2 x i32>* %mask, align 4 %0 = load <2 x i32>, <2 x i32>* %mask, align 4
%1 = icmp sgt <2 x i32> %0, zeroinitializer %1 = icmp sgt <2 x i32> %0, zeroinitializer
%2 = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %src, i32 4, <2 x i1> %1, <2 x i32> undef) %2 = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %src, i32 4, <2 x i1> %1, <2 x i32> undef)
%3 = sext <2 x i32> %2 to <2 x i64> %3 = sext <2 x i32> %2 to <2 x i64>
call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %3, <2 x i64>* %dest, i32 8, <2 x i1> %1) call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %3, <2 x i64>* %dest, i32 8, <2 x i1> %1)
ret void ret void
} }
define void @foo_sext_v2i64_v2i32_unaligned(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32> *%src) { define void @foo_sext_v2i64_v2i32_unaligned(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32> *%src) {
; CHECK-LE-LABEL: foo_sext_v2i64_v2i32_unaligned: ; CHECK-LE-LABEL: foo_sext_v2i64_v2i32_unaligned:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r4, r5, r7, lr} ; CHECK-LE-NEXT: .save {r4, r5, r7, lr}
; CHECK-LE-NEXT: push {r4, r5, r7, lr} ; CHECK-LE-NEXT: push {r4, r5, r7, lr}
; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: .pad #4
; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: ldrd lr, r5, [r1] ; CHECK-LE-NEXT: ldrd lr, r1, [r1]
; CHECK-LE-NEXT: movs r3, #0 ; CHECK-LE-NEXT: rsbs r3, r1, #0
; CHECK-LE-NEXT: mov.w r12, #0
; CHECK-LE-NEXT: sbcs.w r3, r12, r1, asr #31
; CHECK-LE-NEXT: cset r3, lt
; CHECK-LE-NEXT: @ implicit-def: $q0 ; CHECK-LE-NEXT: @ implicit-def: $q0
; CHECK-LE-NEXT: rsbs.w r1, lr, #0 ; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r1
; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r5
; CHECK-LE-NEXT: sbcs.w r1, r3, lr, asr #31
; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r1, #1
; CHECK-LE-NEXT: rsbs r4, r5, #0
; CHECK-LE-NEXT: sbcs.w r4, r3, r5, asr #31
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r3, #1
; CHECK-LE-NEXT: cmp r3, #0 ; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r3, #1 ; CHECK-LE-NEXT: mvnne r3, #1
; CHECK-LE-NEXT: bfi r3, r1, #0, #1 ; CHECK-LE-NEXT: rsbs.w r4, lr, #0
; CHECK-LE-NEXT: vmov r4, s4 ; CHECK-LE-NEXT: sbcs.w r4, r12, lr, asr #31
; CHECK-LE-NEXT: mov.w lr, #0
; CHECK-LE-NEXT: cset r4, lt
; CHECK-LE-NEXT: bfi r3, r4, #0, #1
; CHECK-LE-NEXT: and r12, r3, #3 ; CHECK-LE-NEXT: and r12, r3, #3
; CHECK-LE-NEXT: lsls r1, r3, #31 ; CHECK-LE-NEXT: lsls r3, r3, #31
; CHECK-LE-NEXT: itt ne ; CHECK-LE-NEXT: itt ne
; CHECK-LE-NEXT: ldrne r1, [r2] ; CHECK-LE-NEXT: ldrne r3, [r2]
; CHECK-LE-NEXT: vmovne.32 q0[0], r1 ; CHECK-LE-NEXT: vmovne.32 q0[0], r3
; CHECK-LE-NEXT: lsls.w r1, r12, #30 ; CHECK-LE-NEXT: lsls.w r1, r12, #30
; CHECK-LE-NEXT: itt mi ; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: ldrmi r1, [r2, #4] ; CHECK-LE-NEXT: ldrmi r1, [r2, #4]
; CHECK-LE-NEXT: vmovmi.32 q0[2], r1 ; CHECK-LE-NEXT: vmovmi.32 q0[2], r1
; CHECK-LE-NEXT: vmov r3, s0
; CHECK-LE-NEXT: movs r2, #0
; CHECK-LE-NEXT: vmov r1, s2 ; CHECK-LE-NEXT: vmov r1, s2
; CHECK-LE-NEXT: vmov r2, s6
; CHECK-LE-NEXT: vmov r3, s0
; CHECK-LE-NEXT: vmov q0[2], q0[0], r3, r1 ; CHECK-LE-NEXT: vmov q0[2], q0[0], r3, r1
; CHECK-LE-NEXT: rsbs r5, r4, #0 ; CHECK-LE-NEXT: rsbs r5, r2, #0
; CHECK-LE-NEXT: asr.w lr, r3, #31
; CHECK-LE-NEXT: vmov r3, s6
; CHECK-LE-NEXT: asr.w r12, r1, #31 ; CHECK-LE-NEXT: asr.w r12, r1, #31
; CHECK-LE-NEXT: sbcs.w r1, r2, r4, asr #31 ; CHECK-LE-NEXT: sbcs.w r1, lr, r2, asr #31
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: vmov r1, s4
; CHECK-LE-NEXT: vmov q0[3], q0[1], lr, r12 ; CHECK-LE-NEXT: cset r2, lt
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r1, #1
; CHECK-LE-NEXT: rsbs r5, r3, #0
; CHECK-LE-NEXT: sbcs.w r3, r2, r3, asr #31
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r2, #1
; CHECK-LE-NEXT: cmp r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: asr.w r4, r3, #31
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r2, #1 ; CHECK-LE-NEXT: mvnne r2, #1
; CHECK-LE-NEXT: vmov q0[3], q0[1], r4, r12
; CHECK-LE-NEXT: rsbs r3, r1, #0
; CHECK-LE-NEXT: sbcs.w r1, lr, r1, asr #31
; CHECK-LE-NEXT: cset r1, lt
; CHECK-LE-NEXT: bfi r2, r1, #0, #1 ; CHECK-LE-NEXT: bfi r2, r1, #0, #1
; CHECK-LE-NEXT: and r1, r2, #3 ; CHECK-LE-NEXT: and r1, r2, #3
; CHECK-LE-NEXT: lsls r2, r2, #31 ; CHECK-LE-NEXT: lsls r2, r2, #31
; CHECK-LE-NEXT: itt ne ; CHECK-LE-NEXT: itt ne
; CHECK-LE-NEXT: vmovne r2, r3, d0 ; CHECK-LE-NEXT: vmovne r2, r3, d0
; CHECK-LE-NEXT: strdne r2, r3, [r0] ; CHECK-LE-NEXT: strdne r2, r3, [r0]
; CHECK-LE-NEXT: lsls r1, r1, #30 ; CHECK-LE-NEXT: lsls r1, r1, #30
; CHECK-LE-NEXT: itt mi ; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: vmovmi r1, r2, d1 ; CHECK-LE-NEXT: vmovmi r1, r2, d1
; CHECK-LE-NEXT: strdmi r1, r2, [r0, #8] ; CHECK-LE-NEXT: strdmi r1, r2, [r0, #8]
; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: pop {r4, r5, r7, pc} ; CHECK-LE-NEXT: pop {r4, r5, r7, pc}
; ;
; CHECK-BE-LABEL: foo_sext_v2i64_v2i32_unaligned: ; CHECK-BE-LABEL: foo_sext_v2i64_v2i32_unaligned:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r4, r5, r7, lr} ; CHECK-BE-NEXT: .save {r4, r5, r7, lr}
; CHECK-BE-NEXT: push {r4, r5, r7, lr} ; CHECK-BE-NEXT: push {r4, r5, r7, lr}
; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: .pad #4
; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: sub sp, #4
; CHECK-BE-NEXT: ldrd r12, lr, [r1] ; CHECK-BE-NEXT: ldrd r3, lr, [r1]
; CHECK-BE-NEXT: rsbs.w r1, lr, #0 ; CHECK-BE-NEXT: mov.w r12, #0
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: @ implicit-def: $q2
; CHECK-BE-NEXT: sbcs.w r1, r3, lr, asr #31 ; CHECK-BE-NEXT: rsbs r1, r3, #0
; CHECK-BE-NEXT: vmov q0[3], q0[1], r12, lr ; CHECK-BE-NEXT: vmov q0[3], q0[1], r3, lr
; CHECK-BE-NEXT: mov.w lr, #0 ; CHECK-BE-NEXT: sbcs.w r1, r12, r3, asr #31
; CHECK-BE-NEXT: it lt ; CHECK-BE-NEXT: cset r3, lt
; CHECK-BE-NEXT: movlt.w lr, #1
; CHECK-BE-NEXT: rsbs.w r1, r12, #0
; CHECK-BE-NEXT: sbcs.w r1, r3, r12, asr #31
; CHECK-BE-NEXT: it lt
; CHECK-BE-NEXT: movlt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r3, #1 ; CHECK-BE-NEXT: mvnne r3, #1
; CHECK-BE-NEXT: bfi r3, lr, #0, #1 ; CHECK-BE-NEXT: rsbs.w r1, lr, #0
; CHECK-BE-NEXT: @ implicit-def: $q2 ; CHECK-BE-NEXT: sbcs.w r1, r12, lr, asr #31
; CHECK-BE-NEXT: cset r1, lt
; CHECK-BE-NEXT: bfi r3, r1, #0, #1
; CHECK-BE-NEXT: and r1, r3, #3 ; CHECK-BE-NEXT: and r1, r3, #3
; CHECK-BE-NEXT: lsls r3, r3, #30 ; CHECK-BE-NEXT: lsls r3, r3, #30
; CHECK-BE-NEXT: bpl .LBB6_2 ; CHECK-BE-NEXT: bpl .LBB6_2
; CHECK-BE-NEXT: @ %bb.1: @ %cond.load ; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
; CHECK-BE-NEXT: ldr r3, [r2] ; CHECK-BE-NEXT: ldr r3, [r2]
; CHECK-BE-NEXT: vmov.32 q1[1], r3 ; CHECK-BE-NEXT: vmov.32 q1[1], r3
; CHECK-BE-NEXT: vrev64.32 q2, q1 ; CHECK-BE-NEXT: vrev64.32 q2, q1
; CHECK-BE-NEXT: .LBB6_2: @ %else ; CHECK-BE-NEXT: .LBB6_2: @ %else
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: beq .LBB6_4 ; CHECK-BE-NEXT: beq .LBB6_4
; CHECK-BE-NEXT: @ %bb.3: @ %cond.load1 ; CHECK-BE-NEXT: @ %bb.3: @ %cond.load1
; CHECK-BE-NEXT: ldr r1, [r2, #4] ; CHECK-BE-NEXT: ldr r1, [r2, #4]
; CHECK-BE-NEXT: vrev64.32 q0, q2 ; CHECK-BE-NEXT: vrev64.32 q0, q2
; CHECK-BE-NEXT: vmov.32 q0[3], r1 ; CHECK-BE-NEXT: vmov.32 q0[3], r1
; CHECK-BE-NEXT: vrev64.32 q2, q0 ; CHECK-BE-NEXT: vrev64.32 q2, q0
; CHECK-BE-NEXT: .LBB6_4: @ %else2 ; CHECK-BE-NEXT: .LBB6_4: @ %else2
; CHECK-BE-NEXT: vrev64.32 q0, q2 ; CHECK-BE-NEXT: vrev64.32 q0, q2
; CHECK-BE-NEXT: vrev64.32 q2, q1 ; CHECK-BE-NEXT: vrev64.32 q2, q1
; CHECK-BE-NEXT: vmov r2, s11
; CHECK-BE-NEXT: movs r4, #0
; CHECK-BE-NEXT: vmov r1, s3 ; CHECK-BE-NEXT: vmov r1, s3
; CHECK-BE-NEXT: movs r4, #0
; CHECK-BE-NEXT: vmov r3, s1 ; CHECK-BE-NEXT: vmov r3, s1
; CHECK-BE-NEXT: rsbs r5, r2, #0
; CHECK-BE-NEXT: sbcs.w r2, r4, r2, asr #31
; CHECK-BE-NEXT: vmov r2, s9 ; CHECK-BE-NEXT: vmov r2, s9
; CHECK-BE-NEXT: asr.w r12, r1, #31 ; CHECK-BE-NEXT: asr.w r12, r1, #31
; CHECK-BE-NEXT: asr.w lr, r3, #31 ; CHECK-BE-NEXT: asr.w lr, r3, #31
; CHECK-BE-NEXT: rsbs r5, r2, #0
; CHECK-BE-NEXT: vmov q1[2], q1[0], lr, r12 ; CHECK-BE-NEXT: vmov q1[2], q1[0], lr, r12
; CHECK-BE-NEXT: sbcs.w r2, r4, r2, asr #31
; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, r1 ; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, r1
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: vmov r1, s11
; CHECK-BE-NEXT: it lt ; CHECK-BE-NEXT: cset r2, lt
; CHECK-BE-NEXT: movlt r1, #1
; CHECK-BE-NEXT: vrev64.32 q0, q1 ; CHECK-BE-NEXT: vrev64.32 q0, q1
; CHECK-BE-NEXT: rsbs r3, r2, #0 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: sbcs.w r2, r4, r2, asr #31
; CHECK-BE-NEXT: it lt
; CHECK-BE-NEXT: movlt r4, #1
; CHECK-BE-NEXT: cmp r4, #0
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r4, #1 ; CHECK-BE-NEXT: mvnne r2, #1
; CHECK-BE-NEXT: bfi r4, r1, #0, #1 ; CHECK-BE-NEXT: rsbs r3, r1, #0
; CHECK-BE-NEXT: and r1, r4, #3 ; CHECK-BE-NEXT: sbcs.w r1, r4, r1, asr #31
; CHECK-BE-NEXT: lsls r2, r4, #30 ; CHECK-BE-NEXT: cset r1, lt
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
; CHECK-BE-NEXT: and r1, r2, #3
; CHECK-BE-NEXT: lsls r2, r2, #30
; CHECK-BE-NEXT: itt mi ; CHECK-BE-NEXT: itt mi
; CHECK-BE-NEXT: vmovmi r2, r3, d0 ; CHECK-BE-NEXT: vmovmi r2, r3, d0
; CHECK-BE-NEXT: strdmi r3, r2, [r0] ; CHECK-BE-NEXT: strdmi r3, r2, [r0]
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: itt ne ; CHECK-BE-NEXT: itt ne
; CHECK-BE-NEXT: vmovne r1, r2, d1 ; CHECK-BE-NEXT: vmovne r1, r2, d1
; CHECK-BE-NEXT: strdne r2, r1, [r0, #8] ; CHECK-BE-NEXT: strdne r2, r1, [r0, #8]
; CHECK-BE-NEXT: add sp, #4 ; CHECK-BE-NEXT: add sp, #4
; CHECK-BE-NEXT: pop {r4, r5, r7, pc} ; CHECK-BE-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%0 = load <2 x i32>, <2 x i32>* %mask, align 4 %0 = load <2 x i32>, <2 x i32>* %mask, align 4
%1 = icmp sgt <2 x i32> %0, zeroinitializer %1 = icmp sgt <2 x i32> %0, zeroinitializer
%2 = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %src, i32 2, <2 x i1> %1, <2 x i32> undef) %2 = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %src, i32 2, <2 x i1> %1, <2 x i32> undef)
%3 = sext <2 x i32> %2 to <2 x i64> %3 = sext <2 x i32> %2 to <2 x i64>
call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %3, <2 x i64>* %dest, i32 4, <2 x i1> %1) call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %3, <2 x i64>* %dest, i32 4, <2 x i1> %1)
ret void ret void
} }
define void @foo_zext_v2i64_v2i32(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32> *%src) { define void @foo_zext_v2i64_v2i32(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32> *%src) {
; CHECK-LE-LABEL: foo_zext_v2i64_v2i32: ; CHECK-LE-LABEL: foo_zext_v2i64_v2i32:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r4, r5, r7, lr} ; CHECK-LE-NEXT: .save {r4, lr}
; CHECK-LE-NEXT: push {r4, r5, r7, lr} ; CHECK-LE-NEXT: push {r4, lr}
; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: .pad #4
; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: ldrd lr, r5, [r1] ; CHECK-LE-NEXT: ldrd lr, r1, [r1]
; CHECK-LE-NEXT: movs r3, #0 ; CHECK-LE-NEXT: rsbs r3, r1, #0
; CHECK-LE-NEXT: mov.w r12, #0
; CHECK-LE-NEXT: sbcs.w r3, r12, r1, asr #31
; CHECK-LE-NEXT: cset r3, lt
; CHECK-LE-NEXT: @ implicit-def: $q0 ; CHECK-LE-NEXT: @ implicit-def: $q0
; CHECK-LE-NEXT: vmov.i64 q2, #0xffffffff ; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r1
; CHECK-LE-NEXT: rsbs.w r1, lr, #0
; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r5
; CHECK-LE-NEXT: sbcs.w r1, r3, lr, asr #31
; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r1, #1
; CHECK-LE-NEXT: rsbs r4, r5, #0
; CHECK-LE-NEXT: sbcs.w r4, r3, r5, asr #31
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r3, #1
; CHECK-LE-NEXT: cmp r3, #0 ; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r3, #1 ; CHECK-LE-NEXT: mvnne r3, #1
; CHECK-LE-NEXT: bfi r3, r1, #0, #1 ; CHECK-LE-NEXT: rsbs.w r4, lr, #0
; CHECK-LE-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-LE-NEXT: sbcs.w r4, r12, lr, asr #31
; CHECK-LE-NEXT: cset r4, lt
; CHECK-LE-NEXT: bfi r3, r4, #0, #1
; CHECK-LE-NEXT: and r12, r3, #3 ; CHECK-LE-NEXT: and r12, r3, #3
; CHECK-LE-NEXT: lsls r1, r3, #31 ; CHECK-LE-NEXT: lsls r3, r3, #31
; CHECK-LE-NEXT: itt ne ; CHECK-LE-NEXT: itt ne
; CHECK-LE-NEXT: ldrne r1, [r2] ; CHECK-LE-NEXT: ldrne r3, [r2]
; CHECK-LE-NEXT: vmovne.32 q0[0], r1 ; CHECK-LE-NEXT: vmovne.32 q0[0], r3
; CHECK-LE-NEXT: lsls.w r1, r12, #30 ; CHECK-LE-NEXT: lsls.w r1, r12, #30
; CHECK-LE-NEXT: itt mi ; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: ldrmi r1, [r2, #4] ; CHECK-LE-NEXT: ldrmi r1, [r2, #4]
; CHECK-LE-NEXT: vmovmi.32 q0[2], r1 ; CHECK-LE-NEXT: vmovmi.32 q0[2], r1
; CHECK-LE-NEXT: vmov r1, s4 ; CHECK-LE-NEXT: vmov r2, s6
; CHECK-LE-NEXT: movs r2, #0 ; CHECK-LE-NEXT: movs r1, #0
; CHECK-LE-NEXT: vand q0, q0, q2 ; CHECK-LE-NEXT: vand q0, q0, q2
; CHECK-LE-NEXT: rsbs r3, r1, #0 ; CHECK-LE-NEXT: rsbs r3, r2, #0
; CHECK-LE-NEXT: vmov r3, s6 ; CHECK-LE-NEXT: vmov r3, s4
; CHECK-LE-NEXT: sbcs.w r1, r2, r1, asr #31 ; CHECK-LE-NEXT: sbcs.w r2, r1, r2, asr #31
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: cset r2, lt
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r1, #1
; CHECK-LE-NEXT: rsbs r5, r3, #0
; CHECK-LE-NEXT: sbcs.w r3, r2, r3, asr #31
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r2, #1
; CHECK-LE-NEXT: cmp r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r2, #1 ; CHECK-LE-NEXT: mvnne r2, #1
; CHECK-LE-NEXT: rsbs r4, r3, #0
; CHECK-LE-NEXT: sbcs.w r1, r1, r3, asr #31
; CHECK-LE-NEXT: cset r1, lt
; CHECK-LE-NEXT: bfi r2, r1, #0, #1 ; CHECK-LE-NEXT: bfi r2, r1, #0, #1
; CHECK-LE-NEXT: and r1, r2, #3 ; CHECK-LE-NEXT: and r1, r2, #3
; CHECK-LE-NEXT: lsls r2, r2, #31 ; CHECK-LE-NEXT: lsls r2, r2, #31
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: vstrne d0, [r0] ; CHECK-LE-NEXT: vstrne d0, [r0]
; CHECK-LE-NEXT: lsls r1, r1, #30 ; CHECK-LE-NEXT: lsls r1, r1, #30
; CHECK-LE-NEXT: it mi ; CHECK-LE-NEXT: it mi
; CHECK-LE-NEXT: vstrmi d1, [r0, #8] ; CHECK-LE-NEXT: vstrmi d1, [r0, #8]
; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: pop {r4, r5, r7, pc} ; CHECK-LE-NEXT: pop {r4, pc}
; ;
; CHECK-BE-LABEL: foo_zext_v2i64_v2i32: ; CHECK-BE-LABEL: foo_zext_v2i64_v2i32:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r7, lr} ; CHECK-BE-NEXT: .save {r7, lr}
; CHECK-BE-NEXT: push {r7, lr} ; CHECK-BE-NEXT: push {r7, lr}
; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: .pad #4
; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: sub sp, #4
; CHECK-BE-NEXT: ldrd r12, lr, [r1] ; CHECK-BE-NEXT: ldrd r3, lr, [r1]
; CHECK-BE-NEXT: rsbs.w r1, lr, #0 ; CHECK-BE-NEXT: mov.w r12, #0
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: @ implicit-def: $q0
; CHECK-BE-NEXT: sbcs.w r1, r3, lr, asr #31 ; CHECK-BE-NEXT: rsbs r1, r3, #0
; CHECK-BE-NEXT: vmov q0[3], q0[1], r12, lr ; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, lr
; CHECK-BE-NEXT: mov.w lr, #0 ; CHECK-BE-NEXT: sbcs.w r1, r12, r3, asr #31
; CHECK-BE-NEXT: it lt ; CHECK-BE-NEXT: cset r3, lt
; CHECK-BE-NEXT: movlt.w lr, #1
; CHECK-BE-NEXT: rsbs.w r1, r12, #0
; CHECK-BE-NEXT: sbcs.w r1, r3, r12, asr #31
; CHECK-BE-NEXT: it lt
; CHECK-BE-NEXT: movlt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r3, #1 ; CHECK-BE-NEXT: mvnne r3, #1
; CHECK-BE-NEXT: bfi r3, lr, #0, #1 ; CHECK-BE-NEXT: rsbs.w r1, lr, #0
; CHECK-BE-NEXT: @ implicit-def: $q1 ; CHECK-BE-NEXT: sbcs.w r1, r12, lr, asr #31
; CHECK-BE-NEXT: cset r1, lt
; CHECK-BE-NEXT: bfi r3, r1, #0, #1
; CHECK-BE-NEXT: and r1, r3, #3 ; CHECK-BE-NEXT: and r1, r3, #3
; CHECK-BE-NEXT: lsls r3, r3, #30 ; CHECK-BE-NEXT: lsls r3, r3, #30
; CHECK-BE-NEXT: bpl .LBB7_2 ; CHECK-BE-NEXT: bpl .LBB7_2
; CHECK-BE-NEXT: @ %bb.1: @ %cond.load ; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
; CHECK-BE-NEXT: ldr r3, [r2] ; CHECK-BE-NEXT: ldr r3, [r2]
; CHECK-BE-NEXT: vmov.32 q2[1], r3 ; CHECK-BE-NEXT: vmov.32 q2[1], r3
; CHECK-BE-NEXT: vrev64.32 q1, q2 ; CHECK-BE-NEXT: vrev64.32 q0, q2
; CHECK-BE-NEXT: .LBB7_2: @ %else ; CHECK-BE-NEXT: .LBB7_2: @ %else
; CHECK-BE-NEXT: vrev64.32 q2, q0 ; CHECK-BE-NEXT: vrev64.32 q2, q1
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: beq .LBB7_4 ; CHECK-BE-NEXT: beq .LBB7_4
; CHECK-BE-NEXT: @ %bb.3: @ %cond.load1 ; CHECK-BE-NEXT: @ %bb.3: @ %cond.load1
; CHECK-BE-NEXT: ldr r1, [r2, #4] ; CHECK-BE-NEXT: ldr r1, [r2, #4]
; CHECK-BE-NEXT: vrev64.32 q0, q1
; CHECK-BE-NEXT: vmov.32 q0[3], r1
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: vmov.32 q1[3], r1
; CHECK-BE-NEXT: vrev64.32 q0, q1
; CHECK-BE-NEXT: .LBB7_4: @ %else2 ; CHECK-BE-NEXT: .LBB7_4: @ %else2
; CHECK-BE-NEXT: vrev64.32 q3, q2 ; CHECK-BE-NEXT: vrev64.32 q3, q2
; CHECK-BE-NEXT: movs r2, #0
; CHECK-BE-NEXT: vmov r1, s15
; CHECK-BE-NEXT: mov.w r12, #0 ; CHECK-BE-NEXT: mov.w r12, #0
; CHECK-BE-NEXT: vmov.i64 q0, #0xffffffff ; CHECK-BE-NEXT: vmov r2, s13
; CHECK-BE-NEXT: vand q0, q1, q0 ; CHECK-BE-NEXT: vmov.i64 q1, #0xffffffff
; CHECK-BE-NEXT: rsbs r3, r1, #0 ; CHECK-BE-NEXT: vand q0, q0, q1
; CHECK-BE-NEXT: vmov r3, s13 ; CHECK-BE-NEXT: rsbs r3, r2, #0
; CHECK-BE-NEXT: sbcs.w r1, r2, r1, asr #31 ; CHECK-BE-NEXT: vmov r3, s15
; CHECK-BE-NEXT: it lt ; CHECK-BE-NEXT: sbcs.w r2, r12, r2, asr #31
; CHECK-BE-NEXT: movlt.w r12, #1 ; CHECK-BE-NEXT: cset r2, lt
; CHECK-BE-NEXT: rsbs r1, r3, #0
; CHECK-BE-NEXT: sbcs.w r1, r2, r3, asr #31
; CHECK-BE-NEXT: it lt
; CHECK-BE-NEXT: movlt r2, #1
; CHECK-BE-NEXT: cmp r2, #0 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r2, #1 ; CHECK-BE-NEXT: mvnne r2, #1
; CHECK-BE-NEXT: bfi r2, r12, #0, #1 ; CHECK-BE-NEXT: rsbs r1, r3, #0
; CHECK-BE-NEXT: sbcs.w r1, r12, r3, asr #31
; CHECK-BE-NEXT: cset r1, lt
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
; CHECK-BE-NEXT: and r1, r2, #3 ; CHECK-BE-NEXT: and r1, r2, #3
; CHECK-BE-NEXT: lsls r2, r2, #30 ; CHECK-BE-NEXT: lsls r2, r2, #30
; CHECK-BE-NEXT: it mi ; CHECK-BE-NEXT: it mi
; CHECK-BE-NEXT: vstrmi d0, [r0] ; CHECK-BE-NEXT: vstrmi d0, [r0]
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: vstrne d1, [r0, #8] ; CHECK-BE-NEXT: vstrne d1, [r0, #8]
; CHECK-BE-NEXT: add sp, #4 ; CHECK-BE-NEXT: add sp, #4
; CHECK-BE-NEXT: pop {r7, pc} ; CHECK-BE-NEXT: pop {r7, pc}
entry: entry:
%0 = load <2 x i32>, <2 x i32>* %mask, align 4 %0 = load <2 x i32>, <2 x i32>* %mask, align 4
%1 = icmp sgt <2 x i32> %0, zeroinitializer %1 = icmp sgt <2 x i32> %0, zeroinitializer
%2 = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %src, i32 4, <2 x i1> %1, <2 x i32> undef) %2 = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %src, i32 4, <2 x i1> %1, <2 x i32> undef)
%3 = zext <2 x i32> %2 to <2 x i64> %3 = zext <2 x i32> %2 to <2 x i64>
call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %3, <2 x i64>* %dest, i32 8, <2 x i1> %1) call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %3, <2 x i64>* %dest, i32 8, <2 x i1> %1)
ret void ret void
} }
define void @foo_zext_v2i64_v2i32_unaligned(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32> *%src) { define void @foo_zext_v2i64_v2i32_unaligned(<2 x i64> *%dest, <2 x i32> *%mask, <2 x i32> *%src) {
; CHECK-LE-LABEL: foo_zext_v2i64_v2i32_unaligned: ; CHECK-LE-LABEL: foo_zext_v2i64_v2i32_unaligned:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r4, r5, r7, lr} ; CHECK-LE-NEXT: .save {r4, lr}
; CHECK-LE-NEXT: push {r4, r5, r7, lr} ; CHECK-LE-NEXT: push {r4, lr}
; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: .pad #4
; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: ldrd lr, r5, [r1] ; CHECK-LE-NEXT: ldrd lr, r1, [r1]
; CHECK-LE-NEXT: movs r3, #0 ; CHECK-LE-NEXT: rsbs r3, r1, #0
; CHECK-LE-NEXT: mov.w r12, #0
; CHECK-LE-NEXT: sbcs.w r3, r12, r1, asr #31
; CHECK-LE-NEXT: cset r3, lt
; CHECK-LE-NEXT: @ implicit-def: $q0 ; CHECK-LE-NEXT: @ implicit-def: $q0
; CHECK-LE-NEXT: vmov.i64 q2, #0xffffffff ; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r1
; CHECK-LE-NEXT: rsbs.w r1, lr, #0
; CHECK-LE-NEXT: vmov q1[2], q1[0], lr, r5
; CHECK-LE-NEXT: sbcs.w r1, r3, lr, asr #31
; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r1, #1
; CHECK-LE-NEXT: rsbs r4, r5, #0
; CHECK-LE-NEXT: sbcs.w r4, r3, r5, asr #31
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r3, #1
; CHECK-LE-NEXT: cmp r3, #0 ; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r3, #1 ; CHECK-LE-NEXT: mvnne r3, #1
; CHECK-LE-NEXT: bfi r3, r1, #0, #1 ; CHECK-LE-NEXT: rsbs.w r4, lr, #0
; CHECK-LE-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-LE-NEXT: sbcs.w r4, r12, lr, asr #31
; CHECK-LE-NEXT: cset r4, lt
; CHECK-LE-NEXT: bfi r3, r4, #0, #1
; CHECK-LE-NEXT: and r12, r3, #3 ; CHECK-LE-NEXT: and r12, r3, #3
; CHECK-LE-NEXT: lsls r1, r3, #31 ; CHECK-LE-NEXT: lsls r3, r3, #31
; CHECK-LE-NEXT: itt ne ; CHECK-LE-NEXT: itt ne
; CHECK-LE-NEXT: ldrne r1, [r2] ; CHECK-LE-NEXT: ldrne r3, [r2]
; CHECK-LE-NEXT: vmovne.32 q0[0], r1 ; CHECK-LE-NEXT: vmovne.32 q0[0], r3
; CHECK-LE-NEXT: lsls.w r1, r12, #30 ; CHECK-LE-NEXT: lsls.w r1, r12, #30
; CHECK-LE-NEXT: itt mi ; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: ldrmi r1, [r2, #4] ; CHECK-LE-NEXT: ldrmi r1, [r2, #4]
; CHECK-LE-NEXT: vmovmi.32 q0[2], r1 ; CHECK-LE-NEXT: vmovmi.32 q0[2], r1
; CHECK-LE-NEXT: vmov r1, s4 ; CHECK-LE-NEXT: vmov r2, s6
; CHECK-LE-NEXT: movs r2, #0 ; CHECK-LE-NEXT: movs r1, #0
; CHECK-LE-NEXT: vand q0, q0, q2 ; CHECK-LE-NEXT: vand q0, q0, q2
; CHECK-LE-NEXT: rsbs r3, r1, #0 ; CHECK-LE-NEXT: rsbs r3, r2, #0
; CHECK-LE-NEXT: vmov r3, s6 ; CHECK-LE-NEXT: vmov r3, s4
; CHECK-LE-NEXT: sbcs.w r1, r2, r1, asr #31 ; CHECK-LE-NEXT: sbcs.w r2, r1, r2, asr #31
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: cset r2, lt
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r1, #1
; CHECK-LE-NEXT: rsbs r5, r3, #0
; CHECK-LE-NEXT: sbcs.w r3, r2, r3, asr #31
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r2, #1
; CHECK-LE-NEXT: cmp r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r2, #1 ; CHECK-LE-NEXT: mvnne r2, #1
; CHECK-LE-NEXT: rsbs r4, r3, #0
; CHECK-LE-NEXT: sbcs.w r1, r1, r3, asr #31
; CHECK-LE-NEXT: cset r1, lt
; CHECK-LE-NEXT: bfi r2, r1, #0, #1 ; CHECK-LE-NEXT: bfi r2, r1, #0, #1
; CHECK-LE-NEXT: and r1, r2, #3 ; CHECK-LE-NEXT: and r1, r2, #3
; CHECK-LE-NEXT: lsls r2, r2, #31 ; CHECK-LE-NEXT: lsls r2, r2, #31
; CHECK-LE-NEXT: itt ne ; CHECK-LE-NEXT: itt ne
; CHECK-LE-NEXT: vmovne r2, r3, d0 ; CHECK-LE-NEXT: vmovne r2, r3, d0
; CHECK-LE-NEXT: strdne r2, r3, [r0] ; CHECK-LE-NEXT: strdne r2, r3, [r0]
; CHECK-LE-NEXT: lsls r1, r1, #30 ; CHECK-LE-NEXT: lsls r1, r1, #30
; CHECK-LE-NEXT: itt mi ; CHECK-LE-NEXT: itt mi
; CHECK-LE-NEXT: vmovmi r1, r2, d1 ; CHECK-LE-NEXT: vmovmi r1, r2, d1
; CHECK-LE-NEXT: strdmi r1, r2, [r0, #8] ; CHECK-LE-NEXT: strdmi r1, r2, [r0, #8]
; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: pop {r4, r5, r7, pc} ; CHECK-LE-NEXT: pop {r4, pc}
; ;
; CHECK-BE-LABEL: foo_zext_v2i64_v2i32_unaligned: ; CHECK-BE-LABEL: foo_zext_v2i64_v2i32_unaligned:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r7, lr} ; CHECK-BE-NEXT: .save {r7, lr}
; CHECK-BE-NEXT: push {r7, lr} ; CHECK-BE-NEXT: push {r7, lr}
; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: .pad #4
; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: sub sp, #4
; CHECK-BE-NEXT: ldrd r12, lr, [r1] ; CHECK-BE-NEXT: ldrd r3, lr, [r1]
; CHECK-BE-NEXT: rsbs.w r1, lr, #0 ; CHECK-BE-NEXT: mov.w r12, #0
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: @ implicit-def: $q0
; CHECK-BE-NEXT: sbcs.w r1, r3, lr, asr #31 ; CHECK-BE-NEXT: rsbs r1, r3, #0
; CHECK-BE-NEXT: vmov q0[3], q0[1], r12, lr ; CHECK-BE-NEXT: vmov q1[3], q1[1], r3, lr
; CHECK-BE-NEXT: mov.w lr, #0 ; CHECK-BE-NEXT: sbcs.w r1, r12, r3, asr #31
; CHECK-BE-NEXT: it lt ; CHECK-BE-NEXT: cset r3, lt
; CHECK-BE-NEXT: movlt.w lr, #1
; CHECK-BE-NEXT: rsbs.w r1, r12, #0
; CHECK-BE-NEXT: sbcs.w r1, r3, r12, asr #31
; CHECK-BE-NEXT: it lt
; CHECK-BE-NEXT: movlt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r3, #1 ; CHECK-BE-NEXT: mvnne r3, #1
; CHECK-BE-NEXT: bfi r3, lr, #0, #1 ; CHECK-BE-NEXT: rsbs.w r1, lr, #0
; CHECK-BE-NEXT: @ implicit-def: $q1 ; CHECK-BE-NEXT: sbcs.w r1, r12, lr, asr #31
; CHECK-BE-NEXT: cset r1, lt
; CHECK-BE-NEXT: bfi r3, r1, #0, #1
; CHECK-BE-NEXT: and r1, r3, #3 ; CHECK-BE-NEXT: and r1, r3, #3
; CHECK-BE-NEXT: lsls r3, r3, #30 ; CHECK-BE-NEXT: lsls r3, r3, #30
; CHECK-BE-NEXT: bpl .LBB8_2 ; CHECK-BE-NEXT: bpl .LBB8_2
; CHECK-BE-NEXT: @ %bb.1: @ %cond.load ; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
; CHECK-BE-NEXT: ldr r3, [r2] ; CHECK-BE-NEXT: ldr r3, [r2]
; CHECK-BE-NEXT: vmov.32 q2[1], r3 ; CHECK-BE-NEXT: vmov.32 q2[1], r3
; CHECK-BE-NEXT: vrev64.32 q1, q2 ; CHECK-BE-NEXT: vrev64.32 q0, q2
; CHECK-BE-NEXT: .LBB8_2: @ %else ; CHECK-BE-NEXT: .LBB8_2: @ %else
; CHECK-BE-NEXT: vrev64.32 q2, q0 ; CHECK-BE-NEXT: vrev64.32 q2, q1
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: beq .LBB8_4 ; CHECK-BE-NEXT: beq .LBB8_4
; CHECK-BE-NEXT: @ %bb.3: @ %cond.load1 ; CHECK-BE-NEXT: @ %bb.3: @ %cond.load1
; CHECK-BE-NEXT: ldr r1, [r2, #4] ; CHECK-BE-NEXT: ldr r1, [r2, #4]
; CHECK-BE-NEXT: vrev64.32 q0, q1
; CHECK-BE-NEXT: vmov.32 q0[3], r1
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: vmov.32 q1[3], r1
; CHECK-BE-NEXT: vrev64.32 q0, q1
; CHECK-BE-NEXT: .LBB8_4: @ %else2 ; CHECK-BE-NEXT: .LBB8_4: @ %else2
; CHECK-BE-NEXT: vrev64.32 q3, q2 ; CHECK-BE-NEXT: vrev64.32 q3, q2
; CHECK-BE-NEXT: movs r2, #0
; CHECK-BE-NEXT: vmov r1, s15
; CHECK-BE-NEXT: mov.w r12, #0 ; CHECK-BE-NEXT: mov.w r12, #0
; CHECK-BE-NEXT: vmov.i64 q0, #0xffffffff ; CHECK-BE-NEXT: vmov r2, s13
; CHECK-BE-NEXT: vand q0, q1, q0 ; CHECK-BE-NEXT: vmov.i64 q1, #0xffffffff
; CHECK-BE-NEXT: rsbs r3, r1, #0 ; CHECK-BE-NEXT: vand q0, q0, q1
; CHECK-BE-NEXT: vmov r3, s13 ; CHECK-BE-NEXT: rsbs r3, r2, #0
; CHECK-BE-NEXT: sbcs.w r1, r2, r1, asr #31 ; CHECK-BE-NEXT: vmov r3, s15
; CHECK-BE-NEXT: it lt ; CHECK-BE-NEXT: sbcs.w r2, r12, r2, asr #31
; CHECK-BE-NEXT: movlt.w r12, #1 ; CHECK-BE-NEXT: cset r2, lt
; CHECK-BE-NEXT: rsbs r1, r3, #0
; CHECK-BE-NEXT: sbcs.w r1, r2, r3, asr #31
; CHECK-BE-NEXT: it lt
; CHECK-BE-NEXT: movlt r2, #1
; CHECK-BE-NEXT: cmp r2, #0 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r2, #1 ; CHECK-BE-NEXT: mvnne r2, #1
; CHECK-BE-NEXT: bfi r2, r12, #0, #1 ; CHECK-BE-NEXT: rsbs r1, r3, #0
; CHECK-BE-NEXT: sbcs.w r1, r12, r3, asr #31
; CHECK-BE-NEXT: cset r1, lt
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
; CHECK-BE-NEXT: and r1, r2, #3 ; CHECK-BE-NEXT: and r1, r2, #3
; CHECK-BE-NEXT: lsls r2, r2, #30 ; CHECK-BE-NEXT: lsls r2, r2, #30
; CHECK-BE-NEXT: itt mi ; CHECK-BE-NEXT: itt mi
; CHECK-BE-NEXT: vmovmi r2, r3, d0 ; CHECK-BE-NEXT: vmovmi r2, r3, d0
; CHECK-BE-NEXT: strdmi r3, r2, [r0] ; CHECK-BE-NEXT: strdmi r3, r2, [r0]
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: itt ne ; CHECK-BE-NEXT: itt ne
; CHECK-BE-NEXT: vmovne r1, r2, d1 ; CHECK-BE-NEXT: vmovne r1, r2, d1
▲ Show 20 Lines • Show All 563 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-masked-load.ll

Show First 20 Lines • Show All 1,748 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <2 x i64> @masked_v2i64_align4_zero(<2 x i64> *%dest, <2 x i64> %a) { define arm_aapcs_vfpcc <2 x i64> @masked_v2i64_align4_zero(<2 x i64> *%dest, <2 x i64> %a) {
; CHECK-LE-LABEL: masked_v2i64_align4_zero: ; CHECK-LE-LABEL: masked_v2i64_align4_zero:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r7, lr} ; CHECK-LE-NEXT: .save {r7, lr}
; CHECK-LE-NEXT: push {r7, lr} ; CHECK-LE-NEXT: push {r7, lr}
; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: .pad #4
; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: vmov r1, r2, d0 ; CHECK-LE-NEXT: vmov r1, r2, d1
; CHECK-LE-NEXT: movs r3, #0 ; CHECK-LE-NEXT: mov.w lr, #0
; CHECK-LE-NEXT: vmov lr, r12, d1 ; CHECK-LE-NEXT: vmov r3, r12, d0
; CHECK-LE-NEXT: rsbs r1, r1, #0 ; CHECK-LE-NEXT: rsbs r1, r1, #0
; CHECK-LE-NEXT: sbcs.w r1, r3, r2 ; CHECK-LE-NEXT: sbcs.w r1, lr, r2
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: cset r2, lt
; CHECK-LE-NEXT: it lt ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: movlt r1, #1
; CHECK-LE-NEXT: rsbs.w r2, lr, #0
; CHECK-LE-NEXT: sbcs.w r2, r3, r12
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r3, #1 ; CHECK-LE-NEXT: mvnne r2, #1
; CHECK-LE-NEXT: bfi r3, r1, #0, #1 ; CHECK-LE-NEXT: rsbs r1, r3, #0
; CHECK-LE-NEXT: and r1, r3, #3 ; CHECK-LE-NEXT: sbcs.w r1, lr, r12
; CHECK-LE-NEXT: lsls r2, r3, #31 ; CHECK-LE-NEXT: cset r1, lt
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
; CHECK-LE-NEXT: and r1, r2, #3
; CHECK-LE-NEXT: lsls r2, r2, #31
; CHECK-LE-NEXT: beq .LBB49_2 ; CHECK-LE-NEXT: beq .LBB49_2
; CHECK-LE-NEXT: @ %bb.1: @ %cond.load ; CHECK-LE-NEXT: @ %bb.1: @ %cond.load
; CHECK-LE-NEXT: vldr d1, .LCPI49_0 ; CHECK-LE-NEXT: vldr d1, .LCPI49_0
; CHECK-LE-NEXT: vldr d0, [r0] ; CHECK-LE-NEXT: vldr d0, [r0]
; CHECK-LE-NEXT: b .LBB49_3 ; CHECK-LE-NEXT: b .LBB49_3
; CHECK-LE-NEXT: .LBB49_2: ; CHECK-LE-NEXT: .LBB49_2:
; CHECK-LE-NEXT: vmov.i32 q0, #0x0 ; CHECK-LE-NEXT: vmov.i32 q0, #0x0
; CHECK-LE-NEXT: .LBB49_3: @ %else ; CHECK-LE-NEXT: .LBB49_3: @ %else
Show All 10 Lines
; ;
; CHECK-BE-LABEL: masked_v2i64_align4_zero: ; CHECK-BE-LABEL: masked_v2i64_align4_zero:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r7, lr} ; CHECK-BE-NEXT: .save {r7, lr}
; CHECK-BE-NEXT: push {r7, lr} ; CHECK-BE-NEXT: push {r7, lr}
; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: .pad #4
; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: sub sp, #4
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: movs r3, #0 ; CHECK-BE-NEXT: mov.w lr, #0
; CHECK-BE-NEXT: vmov r1, r2, d3 ; CHECK-BE-NEXT: vmov r1, r2, d2
; CHECK-BE-NEXT: vmov r12, lr, d2 ; CHECK-BE-NEXT: vmov r12, r3, d3
; CHECK-BE-NEXT: rsbs r2, r2, #0 ; CHECK-BE-NEXT: rsbs r2, r2, #0
; CHECK-BE-NEXT: sbcs.w r1, r3, r1 ; CHECK-BE-NEXT: sbcs.w r1, lr, r1
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: cset r2, lt
; CHECK-BE-NEXT: it lt ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: movlt r1, #1
; CHECK-BE-NEXT: rsbs.w r2, lr, #0
; CHECK-BE-NEXT: sbcs.w r2, r3, r12
; CHECK-BE-NEXT: it lt
; CHECK-BE-NEXT: movlt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r3, #1 ; CHECK-BE-NEXT: mvnne r2, #1
; CHECK-BE-NEXT: bfi r3, r1, #0, #1 ; CHECK-BE-NEXT: rsbs r1, r3, #0
; CHECK-BE-NEXT: and r1, r3, #3 ; CHECK-BE-NEXT: sbcs.w r1, lr, r12
; CHECK-BE-NEXT: lsls r2, r3, #30 ; CHECK-BE-NEXT: cset r1, lt
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
; CHECK-BE-NEXT: and r1, r2, #3
; CHECK-BE-NEXT: lsls r2, r2, #30
; CHECK-BE-NEXT: bpl .LBB49_2 ; CHECK-BE-NEXT: bpl .LBB49_2
; CHECK-BE-NEXT: @ %bb.1: @ %cond.load ; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
; CHECK-BE-NEXT: vldr d1, .LCPI49_0 ; CHECK-BE-NEXT: vldr d1, .LCPI49_0
; CHECK-BE-NEXT: vldr d0, [r0] ; CHECK-BE-NEXT: vldr d0, [r0]
; CHECK-BE-NEXT: b .LBB49_3 ; CHECK-BE-NEXT: b .LBB49_3
; CHECK-BE-NEXT: .LBB49_2: ; CHECK-BE-NEXT: .LBB49_2:
; CHECK-BE-NEXT: vmov.i32 q0, #0x0 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
; CHECK-BE-NEXT: .LBB49_3: @ %else ; CHECK-BE-NEXT: .LBB49_3: @ %else
Show All 15 Lines
define arm_aapcs_vfpcc <2 x double> @masked_v2f64_align4_zero(<2 x double> *%dest, <2 x double> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x double> @masked_v2f64_align4_zero(<2 x double> *%dest, <2 x double> %a, <2 x i64> %b) {
; CHECK-LE-LABEL: masked_v2f64_align4_zero: ; CHECK-LE-LABEL: masked_v2f64_align4_zero:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r7, lr} ; CHECK-LE-NEXT: .save {r7, lr}
; CHECK-LE-NEXT: push {r7, lr} ; CHECK-LE-NEXT: push {r7, lr}
; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: .pad #4
; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: vmov r1, r2, d2 ; CHECK-LE-NEXT: vmov r1, r2, d3
; CHECK-LE-NEXT: movs r3, #0 ; CHECK-LE-NEXT: mov.w lr, #0
; CHECK-LE-NEXT: vmov lr, r12, d3 ; CHECK-LE-NEXT: vmov r3, r12, d2
; CHECK-LE-NEXT: rsbs r1, r1, #0 ; CHECK-LE-NEXT: rsbs r1, r1, #0
; CHECK-LE-NEXT: sbcs.w r1, r3, r2 ; CHECK-LE-NEXT: sbcs.w r1, lr, r2
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: cset r2, lt
; CHECK-LE-NEXT: it lt ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: movlt r1, #1
; CHECK-LE-NEXT: rsbs.w r2, lr, #0
; CHECK-LE-NEXT: sbcs.w r2, r3, r12
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r3, #1 ; CHECK-LE-NEXT: mvnne r2, #1
; CHECK-LE-NEXT: bfi r3, r1, #0, #1 ; CHECK-LE-NEXT: rsbs r1, r3, #0
; CHECK-LE-NEXT: and r1, r3, #3 ; CHECK-LE-NEXT: sbcs.w r1, lr, r12
; CHECK-LE-NEXT: lsls r2, r3, #31 ; CHECK-LE-NEXT: cset r1, lt
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
; CHECK-LE-NEXT: and r1, r2, #3
; CHECK-LE-NEXT: lsls r2, r2, #31
; CHECK-LE-NEXT: beq .LBB50_2 ; CHECK-LE-NEXT: beq .LBB50_2
; CHECK-LE-NEXT: @ %bb.1: @ %cond.load ; CHECK-LE-NEXT: @ %bb.1: @ %cond.load
; CHECK-LE-NEXT: vldr d1, .LCPI50_0 ; CHECK-LE-NEXT: vldr d1, .LCPI50_0
; CHECK-LE-NEXT: vldr d0, [r0] ; CHECK-LE-NEXT: vldr d0, [r0]
; CHECK-LE-NEXT: b .LBB50_3 ; CHECK-LE-NEXT: b .LBB50_3
; CHECK-LE-NEXT: .LBB50_2: ; CHECK-LE-NEXT: .LBB50_2:
; CHECK-LE-NEXT: vmov.i32 q0, #0x0 ; CHECK-LE-NEXT: vmov.i32 q0, #0x0
; CHECK-LE-NEXT: .LBB50_3: @ %else ; CHECK-LE-NEXT: .LBB50_3: @ %else
Show All 10 Lines
; ;
; CHECK-BE-LABEL: masked_v2f64_align4_zero: ; CHECK-BE-LABEL: masked_v2f64_align4_zero:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r7, lr} ; CHECK-BE-NEXT: .save {r7, lr}
; CHECK-BE-NEXT: push {r7, lr} ; CHECK-BE-NEXT: push {r7, lr}
; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: .pad #4
; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: sub sp, #4
; CHECK-BE-NEXT: vrev64.32 q0, q1 ; CHECK-BE-NEXT: vrev64.32 q0, q1
; CHECK-BE-NEXT: movs r3, #0 ; CHECK-BE-NEXT: mov.w lr, #0
; CHECK-BE-NEXT: vmov r1, r2, d1 ; CHECK-BE-NEXT: vmov r1, r2, d0
; CHECK-BE-NEXT: vmov r12, lr, d0 ; CHECK-BE-NEXT: vmov r12, r3, d1
; CHECK-BE-NEXT: rsbs r2, r2, #0 ; CHECK-BE-NEXT: rsbs r2, r2, #0
; CHECK-BE-NEXT: sbcs.w r1, r3, r1 ; CHECK-BE-NEXT: sbcs.w r1, lr, r1
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: cset r2, lt
; CHECK-BE-NEXT: it lt ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: movlt r1, #1
; CHECK-BE-NEXT: rsbs.w r2, lr, #0
; CHECK-BE-NEXT: sbcs.w r2, r3, r12
; CHECK-BE-NEXT: it lt
; CHECK-BE-NEXT: movlt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r3, #1 ; CHECK-BE-NEXT: mvnne r2, #1
; CHECK-BE-NEXT: bfi r3, r1, #0, #1 ; CHECK-BE-NEXT: rsbs r1, r3, #0
; CHECK-BE-NEXT: and r1, r3, #3 ; CHECK-BE-NEXT: sbcs.w r1, lr, r12
; CHECK-BE-NEXT: lsls r2, r3, #30 ; CHECK-BE-NEXT: cset r1, lt
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
; CHECK-BE-NEXT: and r1, r2, #3
; CHECK-BE-NEXT: lsls r2, r2, #30
; CHECK-BE-NEXT: bpl .LBB50_2 ; CHECK-BE-NEXT: bpl .LBB50_2
; CHECK-BE-NEXT: @ %bb.1: @ %cond.load ; CHECK-BE-NEXT: @ %bb.1: @ %cond.load
; CHECK-BE-NEXT: vldr d1, .LCPI50_0 ; CHECK-BE-NEXT: vldr d1, .LCPI50_0
; CHECK-BE-NEXT: vldr d0, [r0] ; CHECK-BE-NEXT: vldr d0, [r0]
; CHECK-BE-NEXT: b .LBB50_3 ; CHECK-BE-NEXT: b .LBB50_3
; CHECK-BE-NEXT: .LBB50_2: ; CHECK-BE-NEXT: .LBB50_2:
; CHECK-BE-NEXT: vmov.i32 q0, #0x0 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
; CHECK-BE-NEXT: .LBB50_3: @ %else ; CHECK-BE-NEXT: .LBB50_3: @ %else
▲ Show 20 Lines • Show All 267 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-masked-store.ll

Show First 20 Lines • Show All 933 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc void @masked_v2i64(<2 x i64> *%dest, <2 x i64> %a) { define arm_aapcs_vfpcc void @masked_v2i64(<2 x i64> *%dest, <2 x i64> %a) {
; CHECK-LE-LABEL: masked_v2i64: ; CHECK-LE-LABEL: masked_v2i64:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r7, lr} ; CHECK-LE-NEXT: .save {r7, lr}
; CHECK-LE-NEXT: push {r7, lr} ; CHECK-LE-NEXT: push {r7, lr}
; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: .pad #4
; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: vmov r1, r2, d0 ; CHECK-LE-NEXT: vmov r1, r2, d1
; CHECK-LE-NEXT: movs r3, #0 ; CHECK-LE-NEXT: mov.w lr, #0
; CHECK-LE-NEXT: vmov lr, r12, d1 ; CHECK-LE-NEXT: vmov r3, r12, d0
; CHECK-LE-NEXT: rsbs r1, r1, #0 ; CHECK-LE-NEXT: rsbs r1, r1, #0
; CHECK-LE-NEXT: sbcs.w r1, r3, r2 ; CHECK-LE-NEXT: sbcs.w r1, lr, r2
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: cset r2, lt
; CHECK-LE-NEXT: it lt ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: movlt r1, #1
; CHECK-LE-NEXT: rsbs.w r2, lr, #0
; CHECK-LE-NEXT: sbcs.w r2, r3, r12
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r3, #1 ; CHECK-LE-NEXT: mvnne r2, #1
; CHECK-LE-NEXT: bfi r3, r1, #0, #1 ; CHECK-LE-NEXT: rsbs r1, r3, #0
; CHECK-LE-NEXT: and r1, r3, #3 ; CHECK-LE-NEXT: sbcs.w r1, lr, r12
; CHECK-LE-NEXT: lsls r2, r3, #31 ; CHECK-LE-NEXT: cset r1, lt
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
; CHECK-LE-NEXT: and r1, r2, #3
; CHECK-LE-NEXT: lsls r2, r2, #31
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: vstrne d0, [r0] ; CHECK-LE-NEXT: vstrne d0, [r0]
; CHECK-LE-NEXT: lsls r1, r1, #30 ; CHECK-LE-NEXT: lsls r1, r1, #30
; CHECK-LE-NEXT: it mi ; CHECK-LE-NEXT: it mi
; CHECK-LE-NEXT: vstrmi d1, [r0, #8] ; CHECK-LE-NEXT: vstrmi d1, [r0, #8]
; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: pop {r7, pc} ; CHECK-LE-NEXT: pop {r7, pc}
; ;
; CHECK-BE-LABEL: masked_v2i64: ; CHECK-BE-LABEL: masked_v2i64:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r7, lr} ; CHECK-BE-NEXT: .save {r7, lr}
; CHECK-BE-NEXT: push {r7, lr} ; CHECK-BE-NEXT: push {r7, lr}
; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: .pad #4
; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: sub sp, #4
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: movs r3, #0 ; CHECK-BE-NEXT: mov.w lr, #0
; CHECK-BE-NEXT: vmov r1, r2, d3 ; CHECK-BE-NEXT: vmov r1, r2, d2
; CHECK-BE-NEXT: vmov r12, lr, d2 ; CHECK-BE-NEXT: vmov r12, r3, d3
; CHECK-BE-NEXT: rsbs r2, r2, #0 ; CHECK-BE-NEXT: rsbs r2, r2, #0
; CHECK-BE-NEXT: sbcs.w r1, r3, r1 ; CHECK-BE-NEXT: sbcs.w r1, lr, r1
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: cset r2, lt
; CHECK-BE-NEXT: it lt ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: movlt r1, #1
; CHECK-BE-NEXT: rsbs.w r2, lr, #0
; CHECK-BE-NEXT: sbcs.w r2, r3, r12
; CHECK-BE-NEXT: it lt
; CHECK-BE-NEXT: movlt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r3, #1 ; CHECK-BE-NEXT: mvnne r2, #1
; CHECK-BE-NEXT: bfi r3, r1, #0, #1 ; CHECK-BE-NEXT: rsbs r1, r3, #0
; CHECK-BE-NEXT: and r1, r3, #3 ; CHECK-BE-NEXT: sbcs.w r1, lr, r12
; CHECK-BE-NEXT: lsls r2, r3, #30 ; CHECK-BE-NEXT: cset r1, lt
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
; CHECK-BE-NEXT: and r1, r2, #3
; CHECK-BE-NEXT: lsls r2, r2, #30
; CHECK-BE-NEXT: it mi ; CHECK-BE-NEXT: it mi
; CHECK-BE-NEXT: vstrmi d0, [r0] ; CHECK-BE-NEXT: vstrmi d0, [r0]
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: vstrne d1, [r0, #8] ; CHECK-BE-NEXT: vstrne d1, [r0, #8]
; CHECK-BE-NEXT: add sp, #4 ; CHECK-BE-NEXT: add sp, #4
; CHECK-BE-NEXT: pop {r7, pc} ; CHECK-BE-NEXT: pop {r7, pc}
entry: entry:
%c = icmp sgt <2 x i64> %a, zeroinitializer %c = icmp sgt <2 x i64> %a, zeroinitializer
call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %a, <2 x i64>* %dest, i32 8, <2 x i1> %c) call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %a, <2 x i64>* %dest, i32 8, <2 x i1> %c)
ret void ret void
} }
define arm_aapcs_vfpcc void @masked_v2f64(<2 x double> *%dest, <2 x double> %a, <2 x i64> %b) { define arm_aapcs_vfpcc void @masked_v2f64(<2 x double> *%dest, <2 x double> %a, <2 x i64> %b) {
; CHECK-LE-LABEL: masked_v2f64: ; CHECK-LE-LABEL: masked_v2f64:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .save {r7, lr} ; CHECK-LE-NEXT: .save {r7, lr}
; CHECK-LE-NEXT: push {r7, lr} ; CHECK-LE-NEXT: push {r7, lr}
; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: .pad #4
; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: vmov r1, r2, d2 ; CHECK-LE-NEXT: vmov r1, r2, d3
; CHECK-LE-NEXT: movs r3, #0 ; CHECK-LE-NEXT: mov.w lr, #0
; CHECK-LE-NEXT: vmov lr, r12, d3 ; CHECK-LE-NEXT: vmov r3, r12, d2
; CHECK-LE-NEXT: rsbs r1, r1, #0 ; CHECK-LE-NEXT: rsbs r1, r1, #0
; CHECK-LE-NEXT: sbcs.w r1, r3, r2 ; CHECK-LE-NEXT: sbcs.w r1, lr, r2
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: cset r2, lt
; CHECK-LE-NEXT: it lt ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: movlt r1, #1
; CHECK-LE-NEXT: rsbs.w r2, lr, #0
; CHECK-LE-NEXT: sbcs.w r2, r3, r12
; CHECK-LE-NEXT: it lt
; CHECK-LE-NEXT: movlt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r3, #1 ; CHECK-LE-NEXT: mvnne r2, #1
; CHECK-LE-NEXT: bfi r3, r1, #0, #1 ; CHECK-LE-NEXT: rsbs r1, r3, #0
; CHECK-LE-NEXT: and r1, r3, #3 ; CHECK-LE-NEXT: sbcs.w r1, lr, r12
; CHECK-LE-NEXT: lsls r2, r3, #31 ; CHECK-LE-NEXT: cset r1, lt
; CHECK-LE-NEXT: bfi r2, r1, #0, #1
; CHECK-LE-NEXT: and r1, r2, #3
; CHECK-LE-NEXT: lsls r2, r2, #31
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: vstrne d0, [r0] ; CHECK-LE-NEXT: vstrne d0, [r0]
; CHECK-LE-NEXT: lsls r1, r1, #30 ; CHECK-LE-NEXT: lsls r1, r1, #30
; CHECK-LE-NEXT: it mi ; CHECK-LE-NEXT: it mi
; CHECK-LE-NEXT: vstrmi d1, [r0, #8] ; CHECK-LE-NEXT: vstrmi d1, [r0, #8]
; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: pop {r7, pc} ; CHECK-LE-NEXT: pop {r7, pc}
; ;
; CHECK-BE-LABEL: masked_v2f64: ; CHECK-BE-LABEL: masked_v2f64:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .save {r7, lr} ; CHECK-BE-NEXT: .save {r7, lr}
; CHECK-BE-NEXT: push {r7, lr} ; CHECK-BE-NEXT: push {r7, lr}
; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: .pad #4
; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: sub sp, #4
; CHECK-BE-NEXT: vrev64.32 q2, q1 ; CHECK-BE-NEXT: vrev64.32 q2, q1
; CHECK-BE-NEXT: movs r3, #0 ; CHECK-BE-NEXT: mov.w lr, #0
; CHECK-BE-NEXT: vmov r1, r2, d5 ; CHECK-BE-NEXT: vmov r1, r2, d4
; CHECK-BE-NEXT: vmov r12, lr, d4 ; CHECK-BE-NEXT: vmov r12, r3, d5
; CHECK-BE-NEXT: rsbs r2, r2, #0 ; CHECK-BE-NEXT: rsbs r2, r2, #0
; CHECK-BE-NEXT: sbcs.w r1, r3, r1 ; CHECK-BE-NEXT: sbcs.w r1, lr, r1
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: cset r2, lt
; CHECK-BE-NEXT: it lt ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: movlt r1, #1
; CHECK-BE-NEXT: rsbs.w r2, lr, #0
; CHECK-BE-NEXT: sbcs.w r2, r3, r12
; CHECK-BE-NEXT: it lt
; CHECK-BE-NEXT: movlt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r3, #1 ; CHECK-BE-NEXT: mvnne r2, #1
; CHECK-BE-NEXT: bfi r3, r1, #0, #1 ; CHECK-BE-NEXT: rsbs r1, r3, #0
; CHECK-BE-NEXT: and r1, r3, #3 ; CHECK-BE-NEXT: sbcs.w r1, lr, r12
; CHECK-BE-NEXT: lsls r2, r3, #30 ; CHECK-BE-NEXT: cset r1, lt
; CHECK-BE-NEXT: bfi r2, r1, #0, #1
; CHECK-BE-NEXT: and r1, r2, #3
; CHECK-BE-NEXT: lsls r2, r2, #30
; CHECK-BE-NEXT: it mi ; CHECK-BE-NEXT: it mi
; CHECK-BE-NEXT: vstrmi d0, [r0] ; CHECK-BE-NEXT: vstrmi d0, [r0]
; CHECK-BE-NEXT: lsls r1, r1, #31 ; CHECK-BE-NEXT: lsls r1, r1, #31
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: vstrne d1, [r0, #8] ; CHECK-BE-NEXT: vstrne d1, [r0, #8]
; CHECK-BE-NEXT: add sp, #4 ; CHECK-BE-NEXT: add sp, #4
; CHECK-BE-NEXT: pop {r7, pc} ; CHECK-BE-NEXT: pop {r7, pc}
entry: entry:
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
} }
define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float> %a) { define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float> %a) {
; CHECK-LE-LABEL: masked_v4f16_align4: ; CHECK-LE-LABEL: masked_v4f16_align4:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: .pad #4
; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: vcmp.f32 s0, #0 ; CHECK-LE-NEXT: vcmp.f32 s0, #0
; CHECK-LE-NEXT: movs r1, #0 ; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: vcmp.f32 s1, #0
; CHECK-LE-NEXT: movgt r1, #1 ; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-LE-NEXT: cset r1, gt
; CHECK-LE-NEXT: cmp r1, #0 ; CHECK-LE-NEXT: cmp r1, #0
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: csetm r3, ne ; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: vcmp.f32 s1, #0
; CHECK-LE-NEXT: bfi r1, r3, #0, #1
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: mov.w r3, #0 ; CHECK-LE-NEXT: bfi r1, r2, #0, #1
; CHECK-LE-NEXT: vcmp.f32 s2, #0 ; CHECK-LE-NEXT: vcmp.f32 s2, #0
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: cset r2, gt
; CHECK-LE-NEXT: movgt r3, #1 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: cmp r3, #0 ; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: csetm r3, ne
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: bfi r1, r3, #1, #1 ; CHECK-LE-NEXT: bfi r1, r2, #1, #1
; CHECK-LE-NEXT: mov.w r3, #0
; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: vcmp.f32 s3, #0 ; CHECK-LE-NEXT: vcmp.f32 s3, #0
; CHECK-LE-NEXT: csetm r3, ne ; CHECK-LE-NEXT: cset r2, gt
; CHECK-LE-NEXT: movs r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: bfi r1, r2, #2, #1
; CHECK-LE-NEXT: movgt r2, #1 ; CHECK-LE-NEXT: cset r2, gt
; CHECK-LE-NEXT: cmp r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: bfi r1, r3, #2, #1
; CHECK-LE-NEXT: csetm r2, ne ; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: bfi r1, r2, #3, #1 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-LE-NEXT: lsls r2, r1, #31 ; CHECK-LE-NEXT: lsls r2, r1, #31
; CHECK-LE-NEXT: bne .LBB25_5 ; CHECK-LE-NEXT: bne .LBB25_5
; CHECK-LE-NEXT: @ %bb.1: @ %else ; CHECK-LE-NEXT: @ %bb.1: @ %else
; CHECK-LE-NEXT: lsls r2, r1, #30 ; CHECK-LE-NEXT: lsls r2, r1, #30
; CHECK-LE-NEXT: bmi .LBB25_6 ; CHECK-LE-NEXT: bmi .LBB25_6
; CHECK-LE-NEXT: .LBB25_2: @ %else2 ; CHECK-LE-NEXT: .LBB25_2: @ %else2
; CHECK-LE-NEXT: lsls r2, r1, #29 ; CHECK-LE-NEXT: lsls r2, r1, #29
; CHECK-LE-NEXT: bmi .LBB25_7 ; CHECK-LE-NEXT: bmi .LBB25_7
Show All 22 Lines
; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v4f16_align4: ; CHECK-BE-LABEL: masked_v4f16_align4:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: .pad #4
; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: sub sp, #4
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: movs r1, #0
; CHECK-BE-NEXT: vcmp.f32 s7, #0 ; CHECK-BE-NEXT: vcmp.f32 s7, #0
; CHECK-BE-NEXT: movs r2, #0 ; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: vcmp.f32 s6, #0
; CHECK-BE-NEXT: movgt r1, #1 ; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
; CHECK-BE-NEXT: cset r1, gt
; CHECK-BE-NEXT: cmp r1, #0 ; CHECK-BE-NEXT: cmp r1, #0
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: mov.w r1, #0
; CHECK-BE-NEXT: csetm r3, ne ; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: vcmp.f32 s6, #0
; CHECK-BE-NEXT: bfi r1, r3, #0, #1
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: bfi r1, r2, #0, #1
; CHECK-BE-NEXT: vcmp.f32 s5, #0 ; CHECK-BE-NEXT: vcmp.f32 s5, #0
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: cset r2, gt
; CHECK-BE-NEXT: movgt r3, #1 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: csetm r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: bfi r1, r3, #1, #1 ; CHECK-BE-NEXT: bfi r1, r2, #1, #1
; CHECK-BE-NEXT: mov.w r3, #0
; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: vcmp.f32 s4, #0 ; CHECK-BE-NEXT: vcmp.f32 s4, #0
; CHECK-BE-NEXT: csetm r3, ne ; CHECK-BE-NEXT: cset r2, gt
; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: bfi r1, r2, #2, #1
; CHECK-BE-NEXT: movgt r2, #1 ; CHECK-BE-NEXT: cset r2, gt
; CHECK-BE-NEXT: cmp r2, #0 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: bfi r1, r3, #2, #1
; CHECK-BE-NEXT: csetm r2, ne ; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r2, #3, #1 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
; CHECK-BE-NEXT: lsls r2, r1, #28 ; CHECK-BE-NEXT: lsls r2, r1, #28
; CHECK-BE-NEXT: bmi .LBB25_5 ; CHECK-BE-NEXT: bmi .LBB25_5
; CHECK-BE-NEXT: @ %bb.1: @ %else ; CHECK-BE-NEXT: @ %bb.1: @ %else
; CHECK-BE-NEXT: lsls r2, r1, #29 ; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: bmi .LBB25_6 ; CHECK-BE-NEXT: bmi .LBB25_6
; CHECK-BE-NEXT: .LBB25_2: @ %else2 ; CHECK-BE-NEXT: .LBB25_2: @ %else2
; CHECK-BE-NEXT: lsls r2, r1, #30 ; CHECK-BE-NEXT: lsls r2, r1, #30
; CHECK-BE-NEXT: bmi .LBB25_7 ; CHECK-BE-NEXT: bmi .LBB25_7
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} }
define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float> %a) { define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float> %a) {
; CHECK-LE-LABEL: masked_v4f16_align2: ; CHECK-LE-LABEL: masked_v4f16_align2:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: .pad #4
; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: vcmp.f32 s0, #0 ; CHECK-LE-NEXT: vcmp.f32 s0, #0
; CHECK-LE-NEXT: movs r1, #0 ; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: vcmp.f32 s1, #0
; CHECK-LE-NEXT: movgt r1, #1 ; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-LE-NEXT: cset r1, gt
; CHECK-LE-NEXT: cmp r1, #0 ; CHECK-LE-NEXT: cmp r1, #0
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: csetm r3, ne ; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: vcmp.f32 s1, #0
; CHECK-LE-NEXT: bfi r1, r3, #0, #1
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: mov.w r3, #0 ; CHECK-LE-NEXT: bfi r1, r2, #0, #1
; CHECK-LE-NEXT: vcmp.f32 s2, #0 ; CHECK-LE-NEXT: vcmp.f32 s2, #0
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: cset r2, gt
; CHECK-LE-NEXT: movgt r3, #1 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: cmp r3, #0 ; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: csetm r3, ne
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: bfi r1, r3, #1, #1 ; CHECK-LE-NEXT: bfi r1, r2, #1, #1
; CHECK-LE-NEXT: mov.w r3, #0
; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: vcmp.f32 s3, #0 ; CHECK-LE-NEXT: vcmp.f32 s3, #0
; CHECK-LE-NEXT: csetm r3, ne ; CHECK-LE-NEXT: cset r2, gt
; CHECK-LE-NEXT: movs r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: bfi r1, r2, #2, #1
; CHECK-LE-NEXT: movgt r2, #1 ; CHECK-LE-NEXT: cset r2, gt
; CHECK-LE-NEXT: cmp r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: bfi r1, r3, #2, #1
; CHECK-LE-NEXT: csetm r2, ne ; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: bfi r1, r2, #3, #1 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-LE-NEXT: lsls r2, r1, #31 ; CHECK-LE-NEXT: lsls r2, r1, #31
; CHECK-LE-NEXT: bne .LBB26_5 ; CHECK-LE-NEXT: bne .LBB26_5
; CHECK-LE-NEXT: @ %bb.1: @ %else ; CHECK-LE-NEXT: @ %bb.1: @ %else
; CHECK-LE-NEXT: lsls r2, r1, #30 ; CHECK-LE-NEXT: lsls r2, r1, #30
; CHECK-LE-NEXT: bmi .LBB26_6 ; CHECK-LE-NEXT: bmi .LBB26_6
; CHECK-LE-NEXT: .LBB26_2: @ %else2 ; CHECK-LE-NEXT: .LBB26_2: @ %else2
; CHECK-LE-NEXT: lsls r2, r1, #29 ; CHECK-LE-NEXT: lsls r2, r1, #29
; CHECK-LE-NEXT: bmi .LBB26_7 ; CHECK-LE-NEXT: bmi .LBB26_7
Show All 22 Lines
; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v4f16_align2: ; CHECK-BE-LABEL: masked_v4f16_align2:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: .pad #4
; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: sub sp, #4
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: movs r1, #0
; CHECK-BE-NEXT: vcmp.f32 s7, #0 ; CHECK-BE-NEXT: vcmp.f32 s7, #0
; CHECK-BE-NEXT: movs r2, #0 ; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: vcmp.f32 s6, #0
; CHECK-BE-NEXT: movgt r1, #1 ; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
; CHECK-BE-NEXT: cset r1, gt
; CHECK-BE-NEXT: cmp r1, #0 ; CHECK-BE-NEXT: cmp r1, #0
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: mov.w r1, #0
; CHECK-BE-NEXT: csetm r3, ne ; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: vcmp.f32 s6, #0
; CHECK-BE-NEXT: bfi r1, r3, #0, #1
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: bfi r1, r2, #0, #1
; CHECK-BE-NEXT: vcmp.f32 s5, #0 ; CHECK-BE-NEXT: vcmp.f32 s5, #0
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: cset r2, gt
; CHECK-BE-NEXT: movgt r3, #1 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: csetm r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: bfi r1, r3, #1, #1 ; CHECK-BE-NEXT: bfi r1, r2, #1, #1
; CHECK-BE-NEXT: mov.w r3, #0
; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: vcmp.f32 s4, #0 ; CHECK-BE-NEXT: vcmp.f32 s4, #0
; CHECK-BE-NEXT: csetm r3, ne ; CHECK-BE-NEXT: cset r2, gt
; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: bfi r1, r2, #2, #1
; CHECK-BE-NEXT: movgt r2, #1 ; CHECK-BE-NEXT: cset r2, gt
; CHECK-BE-NEXT: cmp r2, #0 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: bfi r1, r3, #2, #1
; CHECK-BE-NEXT: csetm r2, ne ; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r2, #3, #1 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
; CHECK-BE-NEXT: lsls r2, r1, #28 ; CHECK-BE-NEXT: lsls r2, r1, #28
; CHECK-BE-NEXT: bmi .LBB26_5 ; CHECK-BE-NEXT: bmi .LBB26_5
; CHECK-BE-NEXT: @ %bb.1: @ %else ; CHECK-BE-NEXT: @ %bb.1: @ %else
; CHECK-BE-NEXT: lsls r2, r1, #29 ; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: bmi .LBB26_6 ; CHECK-BE-NEXT: bmi .LBB26_6
; CHECK-BE-NEXT: .LBB26_2: @ %else2 ; CHECK-BE-NEXT: .LBB26_2: @ %else2
; CHECK-BE-NEXT: lsls r2, r1, #30 ; CHECK-BE-NEXT: lsls r2, r1, #30
; CHECK-BE-NEXT: bmi .LBB26_7 ; CHECK-BE-NEXT: bmi .LBB26_7
Show All 29 Lines
} }
define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float> %a) { define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float> %a) {
; CHECK-LE-LABEL: masked_v4f16_align1: ; CHECK-LE-LABEL: masked_v4f16_align1:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .pad #20 ; CHECK-LE-NEXT: .pad #20
; CHECK-LE-NEXT: sub sp, #20 ; CHECK-LE-NEXT: sub sp, #20
; CHECK-LE-NEXT: vcmp.f32 s0, #0 ; CHECK-LE-NEXT: vcmp.f32 s0, #0
; CHECK-LE-NEXT: movs r1, #0 ; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: vcmp.f32 s1, #0
; CHECK-LE-NEXT: movgt r1, #1 ; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-LE-NEXT: cset r1, gt
; CHECK-LE-NEXT: cmp r1, #0 ; CHECK-LE-NEXT: cmp r1, #0
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: csetm r3, ne ; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: vcmp.f32 s1, #0
; CHECK-LE-NEXT: bfi r1, r3, #0, #1
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: mov.w r3, #0 ; CHECK-LE-NEXT: bfi r1, r2, #0, #1
; CHECK-LE-NEXT: vcmp.f32 s2, #0 ; CHECK-LE-NEXT: vcmp.f32 s2, #0
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: cset r2, gt
; CHECK-LE-NEXT: movgt r3, #1 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: cmp r3, #0 ; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: csetm r3, ne
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: bfi r1, r3, #1, #1 ; CHECK-LE-NEXT: bfi r1, r2, #1, #1
; CHECK-LE-NEXT: mov.w r3, #0
; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r3, #1
; CHECK-LE-NEXT: cmp r3, #0
; CHECK-LE-NEXT: vcmp.f32 s3, #0 ; CHECK-LE-NEXT: vcmp.f32 s3, #0
; CHECK-LE-NEXT: csetm r3, ne ; CHECK-LE-NEXT: cset r2, gt
; CHECK-LE-NEXT: movs r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: bfi r1, r2, #2, #1
; CHECK-LE-NEXT: movgt r2, #1 ; CHECK-LE-NEXT: cset r2, gt
; CHECK-LE-NEXT: cmp r2, #0 ; CHECK-LE-NEXT: cmp r2, #0
; CHECK-LE-NEXT: bfi r1, r3, #2, #1
; CHECK-LE-NEXT: csetm r2, ne ; CHECK-LE-NEXT: csetm r2, ne
; CHECK-LE-NEXT: bfi r1, r2, #3, #1 ; CHECK-LE-NEXT: bfi r1, r2, #3, #1
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: vcvtb.f16.f32 s6, s2
; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-LE-NEXT: lsls r2, r1, #31 ; CHECK-LE-NEXT: lsls r2, r1, #31
; CHECK-LE-NEXT: bne .LBB27_5 ; CHECK-LE-NEXT: bne .LBB27_5
; CHECK-LE-NEXT: @ %bb.1: @ %else ; CHECK-LE-NEXT: @ %bb.1: @ %else
; CHECK-LE-NEXT: lsls r2, r1, #30 ; CHECK-LE-NEXT: lsls r2, r1, #30
; CHECK-LE-NEXT: bmi .LBB27_6 ; CHECK-LE-NEXT: bmi .LBB27_6
; CHECK-LE-NEXT: .LBB27_2: @ %else2 ; CHECK-LE-NEXT: .LBB27_2: @ %else2
; CHECK-LE-NEXT: lsls r2, r1, #29 ; CHECK-LE-NEXT: lsls r2, r1, #29
; CHECK-LE-NEXT: bmi .LBB27_7 ; CHECK-LE-NEXT: bmi .LBB27_7
Show All 30 Lines
; CHECK-LE-NEXT: add sp, #20 ; CHECK-LE-NEXT: add sp, #20
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v4f16_align1: ; CHECK-BE-LABEL: masked_v4f16_align1:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .pad #20 ; CHECK-BE-NEXT: .pad #20
; CHECK-BE-NEXT: sub sp, #20 ; CHECK-BE-NEXT: sub sp, #20
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: movs r1, #0
; CHECK-BE-NEXT: vcmp.f32 s7, #0 ; CHECK-BE-NEXT: vcmp.f32 s7, #0
; CHECK-BE-NEXT: movs r2, #0 ; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: vcmp.f32 s6, #0
; CHECK-BE-NEXT: movgt r1, #1 ; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
; CHECK-BE-NEXT: cset r1, gt
; CHECK-BE-NEXT: cmp r1, #0 ; CHECK-BE-NEXT: cmp r1, #0
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: mov.w r1, #0
; CHECK-BE-NEXT: csetm r3, ne ; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: vcmp.f32 s6, #0
; CHECK-BE-NEXT: bfi r1, r3, #0, #1
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: bfi r1, r2, #0, #1
; CHECK-BE-NEXT: vcmp.f32 s5, #0 ; CHECK-BE-NEXT: vcmp.f32 s5, #0
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: cset r2, gt
; CHECK-BE-NEXT: movgt r3, #1 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: csetm r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: bfi r1, r3, #1, #1 ; CHECK-BE-NEXT: bfi r1, r2, #1, #1
; CHECK-BE-NEXT: mov.w r3, #0
; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: vcmp.f32 s4, #0 ; CHECK-BE-NEXT: vcmp.f32 s4, #0
; CHECK-BE-NEXT: csetm r3, ne ; CHECK-BE-NEXT: cset r2, gt
; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: bfi r1, r2, #2, #1
; CHECK-BE-NEXT: movgt r2, #1 ; CHECK-BE-NEXT: cset r2, gt
; CHECK-BE-NEXT: cmp r2, #0 ; CHECK-BE-NEXT: cmp r2, #0
; CHECK-BE-NEXT: bfi r1, r3, #2, #1
; CHECK-BE-NEXT: csetm r2, ne ; CHECK-BE-NEXT: csetm r2, ne
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: bfi r1, r2, #3, #1 ; CHECK-BE-NEXT: bfi r1, r2, #3, #1
; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
; CHECK-BE-NEXT: vcvtb.f16.f32 s2, s6
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
; CHECK-BE-NEXT: lsls r2, r1, #28 ; CHECK-BE-NEXT: lsls r2, r1, #28
; CHECK-BE-NEXT: bmi .LBB27_5 ; CHECK-BE-NEXT: bmi .LBB27_5
; CHECK-BE-NEXT: @ %bb.1: @ %else ; CHECK-BE-NEXT: @ %bb.1: @ %else
; CHECK-BE-NEXT: lsls r2, r1, #29 ; CHECK-BE-NEXT: lsls r2, r1, #29
; CHECK-BE-NEXT: bmi .LBB27_6 ; CHECK-BE-NEXT: bmi .LBB27_6
; CHECK-BE-NEXT: .LBB27_2: @ %else2 ; CHECK-BE-NEXT: .LBB27_2: @ %else2
; CHECK-BE-NEXT: lsls r2, r1, #30 ; CHECK-BE-NEXT: lsls r2, r1, #30
; CHECK-BE-NEXT: bmi .LBB27_7 ; CHECK-BE-NEXT: bmi .LBB27_7
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-minmax.ll

Show All 32 Linesentry:
%0 = icmp slt <4 x i32> %s1, %s2 %0 = icmp slt <4 x i32> %s1, %s2
%1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2 %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
ret <4 x i32> %1 ret <4 x i32> %1
} }
define arm_aapcs_vfpcc <2 x i64> @smin_v2i64(<2 x i64> %s1, <2 x i64> %s2) { define arm_aapcs_vfpcc <2 x i64> @smin_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
; CHECK-LABEL: smin_v2i64: ; CHECK-LABEL: smin_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vmov r0, r1, d3 ; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: movs r6, #0
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: vmov r12, lr, d2 ; CHECK-NEXT: vmov r12, lr, d2
; CHECK-NEXT: vmov r4, r5, d0 ; CHECK-NEXT: vmov r4, r5, d0
; CHECK-NEXT: subs r0, r2, r0 ; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs.w r0, r3, r1 ; CHECK-NEXT: sbcs.w r0, r3, r1
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs.w r1, r4, r12 ; CHECK-NEXT: subs.w r1, r4, r12
; CHECK-NEXT: sbcs.w r1, r5, lr ; CHECK-NEXT: sbcs.w r1, r5, lr
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt r6, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 ; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0 ; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%0 = icmp slt <2 x i64> %s1, %s2 %0 = icmp slt <2 x i64> %s1, %s2
%1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2 %1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2
ret <2 x i64> %1 ret <2 x i64> %1
} }
define arm_aapcs_vfpcc <16 x i8> @umin_v16i8(<16 x i8> %s1, <16 x i8> %s2) { define arm_aapcs_vfpcc <16 x i8> @umin_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
; CHECK-LABEL: umin_v16i8: ; CHECK-LABEL: umin_v16i8:
Show All 26 Linesentry:
%0 = icmp ult <4 x i32> %s1, %s2 %0 = icmp ult <4 x i32> %s1, %s2
%1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2 %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
ret <4 x i32> %1 ret <4 x i32> %1
} }
define arm_aapcs_vfpcc <2 x i64> @umin_v2i64(<2 x i64> %s1, <2 x i64> %s2) { define arm_aapcs_vfpcc <2 x i64> @umin_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
; CHECK-LABEL: umin_v2i64: ; CHECK-LABEL: umin_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vmov r0, r1, d3 ; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: movs r6, #0
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: vmov r12, lr, d2 ; CHECK-NEXT: vmov r12, lr, d2
; CHECK-NEXT: vmov r4, r5, d0 ; CHECK-NEXT: vmov r4, r5, d0
; CHECK-NEXT: subs r0, r2, r0 ; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs.w r0, r3, r1 ; CHECK-NEXT: sbcs.w r0, r3, r1
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs.w r1, r4, r12 ; CHECK-NEXT: subs.w r1, r4, r12
; CHECK-NEXT: sbcs.w r1, r5, lr ; CHECK-NEXT: sbcs.w r1, r5, lr
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r1, lo
; CHECK-NEXT: movlo r6, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 ; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0 ; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%0 = icmp ult <2 x i64> %s1, %s2 %0 = icmp ult <2 x i64> %s1, %s2
%1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2 %1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2
ret <2 x i64> %1 ret <2 x i64> %1
} }
define arm_aapcs_vfpcc <16 x i8> @smax_v16i8(<16 x i8> %s1, <16 x i8> %s2) { define arm_aapcs_vfpcc <16 x i8> @smax_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
Show All 27 Linesentry:
%0 = icmp sgt <4 x i32> %s1, %s2 %0 = icmp sgt <4 x i32> %s1, %s2
%1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2 %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
ret <4 x i32> %1 ret <4 x i32> %1
} }
define arm_aapcs_vfpcc <2 x i64> @smax_v2i64(<2 x i64> %s1, <2 x i64> %s2) { define arm_aapcs_vfpcc <2 x i64> @smax_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
; CHECK-LABEL: smax_v2i64: ; CHECK-LABEL: smax_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: movs r6, #0
; CHECK-NEXT: vmov r2, r3, d3 ; CHECK-NEXT: vmov r2, r3, d3
; CHECK-NEXT: vmov r12, lr, d0 ; CHECK-NEXT: vmov r12, lr, d0
; CHECK-NEXT: vmov r4, r5, d2 ; CHECK-NEXT: vmov r4, r5, d2
; CHECK-NEXT: subs r0, r2, r0 ; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs.w r0, r3, r1 ; CHECK-NEXT: sbcs.w r0, r3, r1
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs.w r1, r4, r12 ; CHECK-NEXT: subs.w r1, r4, r12
; CHECK-NEXT: sbcs.w r1, r5, lr ; CHECK-NEXT: sbcs.w r1, r5, lr
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt r6, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 ; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0 ; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%0 = icmp sgt <2 x i64> %s1, %s2 %0 = icmp sgt <2 x i64> %s1, %s2
%1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2 %1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2
ret <2 x i64> %1 ret <2 x i64> %1
} }
define arm_aapcs_vfpcc <16 x i8> @umax_v16i8(<16 x i8> %s1, <16 x i8> %s2) { define arm_aapcs_vfpcc <16 x i8> @umax_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
; CHECK-LABEL: umax_v16i8: ; CHECK-LABEL: umax_v16i8:
Show All 26 Linesentry:
%0 = icmp ugt <4 x i32> %s1, %s2 %0 = icmp ugt <4 x i32> %s1, %s2
%1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2 %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
ret <4 x i32> %1 ret <4 x i32> %1
} }
define arm_aapcs_vfpcc <2 x i64> @umax_v2i64(<2 x i64> %s1, <2 x i64> %s2) { define arm_aapcs_vfpcc <2 x i64> @umax_v2i64(<2 x i64> %s1, <2 x i64> %s2) {
; CHECK-LABEL: umax_v2i64: ; CHECK-LABEL: umax_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: movs r6, #0
; CHECK-NEXT: vmov r2, r3, d3 ; CHECK-NEXT: vmov r2, r3, d3
; CHECK-NEXT: vmov r12, lr, d0 ; CHECK-NEXT: vmov r12, lr, d0
; CHECK-NEXT: vmov r4, r5, d2 ; CHECK-NEXT: vmov r4, r5, d2
; CHECK-NEXT: subs r0, r2, r0 ; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs.w r0, r3, r1 ; CHECK-NEXT: sbcs.w r0, r3, r1
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs.w r1, r4, r12 ; CHECK-NEXT: subs.w r1, r4, r12
; CHECK-NEXT: sbcs.w r1, r5, lr ; CHECK-NEXT: sbcs.w r1, r5, lr
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r1, lo
; CHECK-NEXT: movlo r6, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 ; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0 ; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%0 = icmp ugt <2 x i64> %s1, %s2 %0 = icmp ugt <2 x i64> %s1, %s2
%1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2 %1 = select <2 x i1> %0, <2 x i64> %s1, <2 x i64> %s2
ret <2 x i64> %1 ret <2 x i64> %1
} }
define arm_aapcs_vfpcc <4 x float> @maxnm_float32_t(<4 x float> %src1, <4 x float> %src2) { define arm_aapcs_vfpcc <4 x float> @maxnm_float32_t(<4 x float> %src1, <4 x float> %src2) {
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llvm/test/CodeGen/Thumb2/mve-pred-ext.ll

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Linesentry:
%0 = sext <16 x i1> %c to <16 x i8> %0 = sext <16 x i1> %c to <16 x i8>
ret <16 x i8> %0 ret <16 x i8> %0
} }
define arm_aapcs_vfpcc <2 x i64> @sext_v2i1_v2i64(<2 x i64> %src) { define arm_aapcs_vfpcc <2 x i64> @sext_v2i1_v2i64(<2 x i64> %src) {
; CHECK-LABEL: sext_v2i1_v2i64: ; CHECK-LABEL: sext_v2i1_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: vmov r2, r12, d0 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: sbcs.w r0, r3, r1 ; CHECK-NEXT: sbcs.w r0, r12, r1
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs r1, r2, #0 ; CHECK-NEXT: rsbs r1, r2, #0
; CHECK-NEXT: sbcs.w r1, r3, r12 ; CHECK-NEXT: sbcs.w r1, r12, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt r3, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp sgt <2 x i64> %src, zeroinitializer %c = icmp sgt <2 x i64> %src, zeroinitializer
%0 = sext <2 x i1> %c to <2 x i64> %0 = sext <2 x i1> %c to <2 x i64>
ret <2 x i64> %0 ret <2 x i64> %0
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} }
define arm_aapcs_vfpcc <2 x i64> @zext_v2i1_v2i64(<2 x i64> %src) { define arm_aapcs_vfpcc <2 x i64> @zext_v2i1_v2i64(<2 x i64> %src) {
; CHECK-LABEL: zext_v2i1_v2i64: ; CHECK-LABEL: zext_v2i1_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: vmov lr, r12, d0 ; CHECK-NEXT: vmov r2, lr, d0
; CHECK-NEXT: adr r2, .LCPI12_0 ; CHECK-NEXT: adr r3, .LCPI12_0
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r3]
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: sbcs.w r0, r3, r1 ; CHECK-NEXT: sbcs.w r0, r12, r1
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs.w r1, lr, #0 ; CHECK-NEXT: rsbs r1, r2, #0
; CHECK-NEXT: sbcs.w r1, r3, r12 ; CHECK-NEXT: sbcs.w r1, r12, lr
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt r3, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vand q0, q1, q0 ; CHECK-NEXT: vand q0, q1, q0
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI12_0: ; CHECK-NEXT: .LCPI12_0:
; CHECK-NEXT: .long 1 @ 0x1 ; CHECK-NEXT: .long 1 @ 0x1
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define arm_aapcs_vfpcc <2 x double> @uitofp_v2i1_v2f64(<2 x i64> %src) { define arm_aapcs_vfpcc <2 x double> @uitofp_v2i1_v2f64(<2 x i64> %src) {
; CHECK-LABEL: uitofp_v2i1_v2f64: ; CHECK-LABEL: uitofp_v2i1_v2f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: vmov lr, r12, d0 ; CHECK-NEXT: vmov r2, lr, d0
; CHECK-NEXT: adr r2, .LCPI26_0 ; CHECK-NEXT: adr r3, .LCPI26_0
; CHECK-NEXT: vldrw.u32 q0, [r2] ; CHECK-NEXT: vldrw.u32 q0, [r3]
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: sbcs.w r0, r3, r1 ; CHECK-NEXT: sbcs.w r0, r12, r1
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs.w r1, lr, #0 ; CHECK-NEXT: rsbs r1, r2, #0
; CHECK-NEXT: sbcs.w r1, r3, r12 ; CHECK-NEXT: sbcs.w r1, r12, lr
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt r3, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vand q4, q1, q0 ; CHECK-NEXT: vand q4, q1, q0
; CHECK-NEXT: vmov r0, r1, d9 ; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: bl __aeabi_ul2d ; CHECK-NEXT: bl __aeabi_ul2d
; CHECK-NEXT: vmov r2, r3, d8 ; CHECK-NEXT: vmov r2, r3, d8
; CHECK-NEXT: vmov d9, r0, r1 ; CHECK-NEXT: vmov d9, r0, r1
; CHECK-NEXT: mov r0, r2 ; CHECK-NEXT: mov r0, r2
Show All 19 Lines
define arm_aapcs_vfpcc <2 x double> @sitofp_v2i1_v2f64(<2 x i64> %src) { define arm_aapcs_vfpcc <2 x double> @sitofp_v2i1_v2f64(<2 x i64> %src) {
; CHECK-LABEL: sitofp_v2i1_v2f64: ; CHECK-LABEL: sitofp_v2i1_v2f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov r0, r1, d0 ; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: vmov r2, r12, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: movs r4, #0
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: sbcs.w r0, r3, r1 ; CHECK-NEXT: sbcs.w r0, r12, r1
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r4, lt
; CHECK-NEXT: movlt r4, #1
; CHECK-NEXT: rsbs r0, r2, #0 ; CHECK-NEXT: rsbs r0, r2, #0
; CHECK-NEXT: sbcs.w r0, r3, r12 ; CHECK-NEXT: sbcs.w r0, r12, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: movlt r3, #1 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: mov r1, r0 ; CHECK-NEXT: mov r1, r0
; CHECK-NEXT: bl __aeabi_l2d ; CHECK-NEXT: bl __aeabi_l2d
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: vmov d9, r0, r1 ; CHECK-NEXT: vmov d9, r0, r1
; CHECK-NEXT: csetm r2, ne ; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: mov r0, r2 ; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: mov r1, r2 ; CHECK-NEXT: mov r1, r2
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll

Show All 40 Lines
; CHECK-NEXT: ldrd r5, r4, [r0], #8 ; CHECK-NEXT: ldrd r5, r4, [r0], #8
; CHECK-NEXT: mov.w r3, #-1 ; CHECK-NEXT: mov.w r3, #-1
; CHECK-NEXT: ldrd r8, r7, [r1], #8 ; CHECK-NEXT: ldrd r8, r7, [r1], #8
; CHECK-NEXT: smull r4, r7, r7, r4 ; CHECK-NEXT: smull r4, r7, r7, r4
; CHECK-NEXT: asrl r4, r7, #31 ; CHECK-NEXT: asrl r4, r7, #31
; CHECK-NEXT: smull r6, r5, r8, r5 ; CHECK-NEXT: smull r6, r5, r8, r5
; CHECK-NEXT: rsbs.w r9, r4, #-2147483648 ; CHECK-NEXT: rsbs.w r9, r4, #-2147483648
; CHECK-NEXT: sbcs r3, r7 ; CHECK-NEXT: sbcs r3, r7
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: asrl r6, r5, #31 ; CHECK-NEXT: asrl r6, r5, #31
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: vmov q4[2], q4[0], r6, r4
; CHECK-NEXT: csetm r9, ne ; CHECK-NEXT: csetm r9, ne
; CHECK-NEXT: rsbs.w r3, r6, #-2147483648 ; CHECK-NEXT: rsbs.w r3, r6, #-2147483648
; CHECK-NEXT: mov.w r3, #-1 ; CHECK-NEXT: mov.w r3, #-1
; CHECK-NEXT: vmov q4[2], q4[0], r6, r4
; CHECK-NEXT: sbcs r3, r5
; CHECK-NEXT: vmov q4[3], q4[1], r5, r7 ; CHECK-NEXT: vmov q4[3], q4[1], r5, r7
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: sbcs r3, r5
; CHECK-NEXT: mvn r6, #-2147483648 ; CHECK-NEXT: mvn r6, #-2147483648
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q2[2], q2[0], r3, r9 ; CHECK-NEXT: vmov q2[2], q2[0], r3, r9
; CHECK-NEXT: vmov q2[3], q2[1], r3, r9 ; CHECK-NEXT: vmov q2[3], q2[1], r3, r9
; CHECK-NEXT: vbic q3, q0, q2 ; CHECK-NEXT: vbic q3, q0, q2
; CHECK-NEXT: vand q2, q4, q2 ; CHECK-NEXT: vand q2, q4, q2
; CHECK-NEXT: vorr q2, q2, q3 ; CHECK-NEXT: vorr q2, q2, q3
; CHECK-NEXT: vmov r3, r4, d4 ; CHECK-NEXT: vmov r3, r4, d4
; CHECK-NEXT: subs r3, r3, r6 ; CHECK-NEXT: subs r3, r3, r6
; CHECK-NEXT: sbcs r3, r4, #0 ; CHECK-NEXT: sbcs r3, r4, #0
; CHECK-NEXT: vmov r4, r5, d5 ; CHECK-NEXT: vmov r4, r5, d5
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov.32 q3[1], r3 ; CHECK-NEXT: vmov.32 q3[1], r3
; CHECK-NEXT: subs r4, r4, r6 ; CHECK-NEXT: subs r4, r4, r6
; CHECK-NEXT: sbcs r4, r5, #0 ; CHECK-NEXT: sbcs r4, r5, #0
; CHECK-NEXT: mov.w r4, #0 ; CHECK-NEXT: cset r4, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r4, #1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csetm r4, ne ; CHECK-NEXT: csetm r4, ne
; CHECK-NEXT: vmov q3[2], q3[0], r3, r4 ; CHECK-NEXT: vmov q3[2], q3[0], r3, r4
; CHECK-NEXT: vbic q4, q1, q3 ; CHECK-NEXT: vbic q4, q1, q3
; CHECK-NEXT: vand q2, q2, q3 ; CHECK-NEXT: vand q2, q2, q3
; CHECK-NEXT: vorr q2, q2, q4 ; CHECK-NEXT: vorr q2, q2, q4
; CHECK-NEXT: vmov r3, s10 ; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: vmov r4, s8 ; CHECK-NEXT: vmov r4, s8
Show All 11 Lines
; CHECK-NEXT: .LBB0_7: @ %for.body ; CHECK-NEXT: .LBB0_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr r3, [r12], #4 ; CHECK-NEXT: ldr r3, [r12], #4
; CHECK-NEXT: ldr r4, [r10], #4 ; CHECK-NEXT: ldr r4, [r10], #4
; CHECK-NEXT: smull r4, r3, r4, r3 ; CHECK-NEXT: smull r4, r3, r4, r3
; CHECK-NEXT: asrl r4, r3, #31 ; CHECK-NEXT: asrl r4, r3, #31
; CHECK-NEXT: subs r5, r1, r4 ; CHECK-NEXT: subs r5, r1, r4
; CHECK-NEXT: sbcs.w r5, r0, r3 ; CHECK-NEXT: sbcs.w r5, r0, r3
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r4, r4, r1, ne ; CHECK-NEXT: csel r4, r4, r1, ne
; CHECK-NEXT: csel r3, r3, r0, ne ; CHECK-NEXT: csel r3, r3, r0, ne
; CHECK-NEXT: subs r5, r4, r2 ; CHECK-NEXT: subs r5, r4, r2
; CHECK-NEXT: sbcs r3, r3, #0 ; CHECK-NEXT: sbcs r3, r3, #0
; CHECK-NEXT: csel r3, r4, r2, lt ; CHECK-NEXT: csel r3, r4, r2, lt
; CHECK-NEXT: str r3, [r11], #4 ; CHECK-NEXT: str r3, [r11], #4
; CHECK-NEXT: le lr, .LBB0_7 ; CHECK-NEXT: le lr, .LBB0_7
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: .pad #16 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: beq.w .LBB1_8 ; CHECK-NEXT: beq.w .LBB1_8
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader ; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: movs r7, #0
; CHECK-NEXT: cmp r3, #3 ; CHECK-NEXT: cmp r3, #3
; CHECK-NEXT: bhi .LBB1_3 ; CHECK-NEXT: bhi .LBB1_3
; CHECK-NEXT: @ %bb.2: ; CHECK-NEXT: @ %bb.2:
; CHECK-NEXT: movs r7, #0
; CHECK-NEXT: mov r12, r0 ; CHECK-NEXT: mov r12, r0
; CHECK-NEXT: mov r9, r1 ; CHECK-NEXT: mov r9, r1
; CHECK-NEXT: mov r11, r2 ; CHECK-NEXT: mov r11, r2
; CHECK-NEXT: b .LBB1_6 ; CHECK-NEXT: b .LBB1_6
; CHECK-NEXT: .LBB1_3: @ %vector.ph ; CHECK-NEXT: .LBB1_3: @ %vector.ph
; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill ; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: bic r3, r3, #3 ; CHECK-NEXT: bic r3, r3, #3
; CHECK-NEXT: subs r7, r3, #4 ; CHECK-NEXT: subs r7, r3, #4
Show All 20 Lines
; CHECK-NEXT: vmov.f32 s22, s15 ; CHECK-NEXT: vmov.f32 s22, s15
; CHECK-NEXT: vmullb.s32 q6, q5, q4 ; CHECK-NEXT: vmullb.s32 q6, q5, q4
; CHECK-NEXT: vmov.f32 s10, s9 ; CHECK-NEXT: vmov.f32 s10, s9
; CHECK-NEXT: vmov r4, r7, d13 ; CHECK-NEXT: vmov r4, r7, d13
; CHECK-NEXT: asrl r4, r7, #31 ; CHECK-NEXT: asrl r4, r7, #31
; CHECK-NEXT: vmov r6, s12 ; CHECK-NEXT: vmov r6, s12
; CHECK-NEXT: rsbs.w r5, r4, #-2147483648 ; CHECK-NEXT: rsbs.w r5, r4, #-2147483648
; CHECK-NEXT: sbcs.w r5, r2, r7 ; CHECK-NEXT: sbcs.w r5, r2, r7
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: vmov r10, r5, d12 ; CHECK-NEXT: vmov r10, r5, d12
; CHECK-NEXT: csetm r8, ne
; CHECK-NEXT: asrl r10, r5, #31 ; CHECK-NEXT: asrl r10, r5, #31
; CHECK-NEXT: csetm r8, ne
; CHECK-NEXT: rsbs.w r3, r10, #-2147483648 ; CHECK-NEXT: rsbs.w r3, r10, #-2147483648
; CHECK-NEXT: vmov q6[2], q6[0], r10, r4 ; CHECK-NEXT: vmov q6[2], q6[0], r10, r4
; CHECK-NEXT: sbcs.w r3, r2, r5 ; CHECK-NEXT: sbcs.w r3, r2, r5
; CHECK-NEXT: vmov q6[3], q6[1], r5, r7 ; CHECK-NEXT: vmov q6[3], q6[1], r5, r7
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q4[2], q4[0], r3, r8 ; CHECK-NEXT: vmov q4[2], q4[0], r3, r8
; CHECK-NEXT: vmov q4[3], q4[1], r3, r8 ; CHECK-NEXT: vmov q4[3], q4[1], r3, r8
; CHECK-NEXT: mvn r8, #-2147483648 ; CHECK-NEXT: mvn r8, #-2147483648
; CHECK-NEXT: vbic q5, q0, q4 ; CHECK-NEXT: vbic q5, q0, q4
; CHECK-NEXT: vand q4, q6, q4 ; CHECK-NEXT: vand q4, q6, q4
; CHECK-NEXT: vorr q4, q4, q5 ; CHECK-NEXT: vorr q4, q4, q5
; CHECK-NEXT: vmov r3, r4, d8 ; CHECK-NEXT: vmov r3, r4, d8
; CHECK-NEXT: subs.w r3, r3, r8 ; CHECK-NEXT: subs.w r3, r3, r8
; CHECK-NEXT: sbcs r3, r4, #0 ; CHECK-NEXT: sbcs r3, r4, #0
; CHECK-NEXT: vmov r4, r5, d9 ; CHECK-NEXT: vmov r4, r5, d9
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov.32 q5[1], r3 ; CHECK-NEXT: vmov.32 q5[1], r3
; CHECK-NEXT: subs.w r4, r4, r8 ; CHECK-NEXT: subs.w r4, r4, r8
; CHECK-NEXT: sbcs r4, r5, #0 ; CHECK-NEXT: sbcs r4, r5, #0
; CHECK-NEXT: vmov r5, s8 ; CHECK-NEXT: vmov r5, s8
; CHECK-NEXT: mov.w r4, #0 ; CHECK-NEXT: cset r4, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r4, #1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csetm r4, ne ; CHECK-NEXT: csetm r4, ne
; CHECK-NEXT: vmov q5[2], q5[0], r3, r4 ; CHECK-NEXT: vmov q5[2], q5[0], r3, r4
; CHECK-NEXT: vmov r3, s10 ; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: vmov.f32 s10, s13 ; CHECK-NEXT: vmov.f32 s10, s13
; CHECK-NEXT: vbic q6, q1, q5 ; CHECK-NEXT: vbic q6, q1, q5
; CHECK-NEXT: vand q4, q4, q5 ; CHECK-NEXT: vand q4, q4, q5
; CHECK-NEXT: vorr q4, q4, q6 ; CHECK-NEXT: vorr q4, q4, q6
; CHECK-NEXT: vmov r4, s10 ; CHECK-NEXT: vmov r4, s10
; CHECK-NEXT: smull r6, r5, r6, r5 ; CHECK-NEXT: smull r6, r5, r6, r5
; CHECK-NEXT: asrl r6, r5, #31 ; CHECK-NEXT: asrl r6, r5, #31
; CHECK-NEXT: smull r4, r7, r4, r3 ; CHECK-NEXT: smull r4, r7, r4, r3
; CHECK-NEXT: asrl r4, r7, #31 ; CHECK-NEXT: asrl r4, r7, #31
; CHECK-NEXT: rsbs.w r3, r4, #-2147483648 ; CHECK-NEXT: rsbs.w r3, r4, #-2147483648
; CHECK-NEXT: vmov q5[2], q5[0], r6, r4 ; CHECK-NEXT: vmov q5[2], q5[0], r6, r4
; CHECK-NEXT: sbcs.w r3, r2, r7 ; CHECK-NEXT: sbcs.w r3, r2, r7
; CHECK-NEXT: vmov q5[3], q5[1], r5, r7 ; CHECK-NEXT: vmov q5[3], q5[1], r5, r7
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: rsbs.w r1, r6, #-2147483648 ; CHECK-NEXT: rsbs.w r1, r6, #-2147483648
; CHECK-NEXT: sbcs.w r1, r2, r5 ; CHECK-NEXT: sbcs.w r1, r2, r5
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q2[2], q2[0], r1, r3 ; CHECK-NEXT: vmov q2[2], q2[0], r1, r3
; CHECK-NEXT: vmov q2[3], q2[1], r1, r3 ; CHECK-NEXT: vmov q2[3], q2[1], r1, r3
; CHECK-NEXT: ldrd r1, r2, [sp, #8] @ 8-byte Folded Reload ; CHECK-NEXT: ldrd r1, r2, [sp, #8] @ 8-byte Folded Reload
; CHECK-NEXT: vbic q3, q0, q2 ; CHECK-NEXT: vbic q3, q0, q2
; CHECK-NEXT: vand q2, q5, q2 ; CHECK-NEXT: vand q2, q5, q2
; CHECK-NEXT: vorr q2, q2, q3 ; CHECK-NEXT: vorr q2, q2, q3
; CHECK-NEXT: vmov r4, r3, d4 ; CHECK-NEXT: vmov r4, r3, d4
; CHECK-NEXT: subs.w r4, r4, r8 ; CHECK-NEXT: subs.w r4, r4, r8
; CHECK-NEXT: sbcs r3, r3, #0 ; CHECK-NEXT: sbcs r3, r3, #0
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: vmov r3, r4, d5 ; CHECK-NEXT: vmov r3, r4, d5
; CHECK-NEXT: csetm r5, ne ; CHECK-NEXT: csetm r5, ne
; CHECK-NEXT: vmov.32 q3[1], r5 ; CHECK-NEXT: vmov.32 q3[1], r5
; CHECK-NEXT: subs.w r3, r3, r8 ; CHECK-NEXT: subs.w r3, r3, r8
; CHECK-NEXT: sbcs r3, r4, #0 ; CHECK-NEXT: sbcs r3, r4, #0
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q3[2], q3[0], r5, r3 ; CHECK-NEXT: vmov q3[2], q3[0], r5, r3
; CHECK-NEXT: vbic q5, q1, q3 ; CHECK-NEXT: vbic q5, q1, q3
; CHECK-NEXT: vand q2, q2, q3 ; CHECK-NEXT: vand q2, q2, q3
; CHECK-NEXT: vorr q2, q2, q5 ; CHECK-NEXT: vorr q2, q2, q5
; CHECK-NEXT: vmov.f32 s9, s10 ; CHECK-NEXT: vmov.f32 s9, s10
; CHECK-NEXT: vmov.f32 s10, s16 ; CHECK-NEXT: vmov.f32 s10, s16
Show All 12 Lines
; CHECK-NEXT: .LBB1_7: @ %for.body ; CHECK-NEXT: .LBB1_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr r1, [r12], #4 ; CHECK-NEXT: ldr r1, [r12], #4
; CHECK-NEXT: ldr r4, [r9], #4 ; CHECK-NEXT: ldr r4, [r9], #4
; CHECK-NEXT: smull r4, r1, r4, r1 ; CHECK-NEXT: smull r4, r1, r4, r1
; CHECK-NEXT: asrl r4, r1, #31 ; CHECK-NEXT: asrl r4, r1, #31
; CHECK-NEXT: subs r5, r3, r4 ; CHECK-NEXT: subs r5, r3, r4
; CHECK-NEXT: sbcs.w r5, r0, r1 ; CHECK-NEXT: sbcs.w r5, r0, r1
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r4, r4, r3, ne ; CHECK-NEXT: csel r4, r4, r3, ne
; CHECK-NEXT: csel r1, r1, r0, ne ; CHECK-NEXT: csel r1, r1, r0, ne
; CHECK-NEXT: subs r5, r4, r2 ; CHECK-NEXT: subs r5, r4, r2
; CHECK-NEXT: sbcs r1, r1, #0 ; CHECK-NEXT: sbcs r1, r1, #0
; CHECK-NEXT: csel r1, r4, r2, lt ; CHECK-NEXT: csel r1, r4, r2, lt
; CHECK-NEXT: str r1, [r11], #4 ; CHECK-NEXT: str r1, [r11], #4
; CHECK-NEXT: le lr, .LBB1_7 ; CHECK-NEXT: le lr, .LBB1_7
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov.f32 s26, s19 ; CHECK-NEXT: vmov.f32 s26, s19
; CHECK-NEXT: vmov.f32 s28, s22 ; CHECK-NEXT: vmov.f32 s28, s22
; CHECK-NEXT: vmov.f32 s30, s23 ; CHECK-NEXT: vmov.f32 s30, s23
; CHECK-NEXT: vmullb.s32 q0, q7, q6 ; CHECK-NEXT: vmullb.s32 q0, q7, q6
; CHECK-NEXT: vmov r6, r5, d1 ; CHECK-NEXT: vmov r6, r5, d1
; CHECK-NEXT: asrl r6, r5, #31 ; CHECK-NEXT: asrl r6, r5, #31
; CHECK-NEXT: rsbs.w r7, r6, #-2147483648 ; CHECK-NEXT: rsbs.w r7, r6, #-2147483648
; CHECK-NEXT: sbcs.w r7, r12, r5 ; CHECK-NEXT: sbcs.w r7, r12, r5
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: cset r7, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r7, #1
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: vmov r4, r7, d0 ; CHECK-NEXT: vmov r4, r7, d0
; CHECK-NEXT: csetm r10, ne
; CHECK-NEXT: asrl r4, r7, #31 ; CHECK-NEXT: asrl r4, r7, #31
; CHECK-NEXT: csetm r10, ne
; CHECK-NEXT: rsbs.w r3, r4, #-2147483648 ; CHECK-NEXT: rsbs.w r3, r4, #-2147483648
; CHECK-NEXT: vmov q7[2], q7[0], r4, r6 ; CHECK-NEXT: vmov q7[2], q7[0], r4, r6
; CHECK-NEXT: sbcs.w r3, r12, r7 ; CHECK-NEXT: sbcs.w r3, r12, r7
; CHECK-NEXT: vmov q7[3], q7[1], r7, r5 ; CHECK-NEXT: vmov q7[3], q7[1], r7, r5
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: vmov r7, s20 ; CHECK-NEXT: vmov r7, s20
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q0[2], q0[0], r3, r10 ; CHECK-NEXT: vmov q0[2], q0[0], r3, r10
; CHECK-NEXT: vmov q0[3], q0[1], r3, r10 ; CHECK-NEXT: vmov q0[3], q0[1], r3, r10
; CHECK-NEXT: vbic q6, q2, q0 ; CHECK-NEXT: vbic q6, q2, q0
; CHECK-NEXT: vand q0, q7, q0 ; CHECK-NEXT: vand q0, q7, q0
; CHECK-NEXT: vorr q6, q0, q6 ; CHECK-NEXT: vorr q6, q0, q6
; CHECK-NEXT: vmov r3, r4, d12 ; CHECK-NEXT: vmov r3, r4, d12
; CHECK-NEXT: subs.w r3, r3, r8 ; CHECK-NEXT: subs.w r3, r3, r8
; CHECK-NEXT: sbcs r3, r4, #0 ; CHECK-NEXT: sbcs r3, r4, #0
; CHECK-NEXT: vmov r4, r5, d13 ; CHECK-NEXT: vmov r4, r5, d13
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov.32 q0[1], r3 ; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: subs.w r4, r4, r8 ; CHECK-NEXT: subs.w r4, r4, r8
; CHECK-NEXT: sbcs r4, r5, #0 ; CHECK-NEXT: sbcs r4, r5, #0
; CHECK-NEXT: mov.w r4, #0 ; CHECK-NEXT: cset r4, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r4, #1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csetm r4, ne ; CHECK-NEXT: csetm r4, ne
; CHECK-NEXT: vmov q0[2], q0[0], r3, r4 ; CHECK-NEXT: vmov q0[2], q0[0], r3, r4
; CHECK-NEXT: vbic q7, q3, q0 ; CHECK-NEXT: vbic q7, q3, q0
; CHECK-NEXT: vand q0, q6, q0 ; CHECK-NEXT: vand q0, q6, q0
; CHECK-NEXT: vorr q6, q0, q7 ; CHECK-NEXT: vorr q6, q0, q7
; CHECK-NEXT: vmov.f32 s2, s17 ; CHECK-NEXT: vmov.f32 s2, s17
; CHECK-NEXT: vmov r3, s2 ; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: vmov.f32 s2, s21 ; CHECK-NEXT: vmov.f32 s2, s21
; CHECK-NEXT: vmov r4, s2 ; CHECK-NEXT: vmov r4, s2
; CHECK-NEXT: smull r6, r5, r4, r3 ; CHECK-NEXT: smull r6, r5, r4, r3
; CHECK-NEXT: vmov r4, s16 ; CHECK-NEXT: vmov r4, s16
; CHECK-NEXT: asrl r6, r5, #31 ; CHECK-NEXT: asrl r6, r5, #31
; CHECK-NEXT: rsbs.w r3, r6, #-2147483648 ; CHECK-NEXT: rsbs.w r3, r6, #-2147483648
; CHECK-NEXT: sbcs.w r3, r12, r5 ; CHECK-NEXT: sbcs.w r3, r12, r5
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r10, ne ; CHECK-NEXT: csetm r10, ne
; CHECK-NEXT: smull r4, r7, r7, r4 ; CHECK-NEXT: smull r4, r7, r7, r4
; CHECK-NEXT: asrl r4, r7, #31 ; CHECK-NEXT: asrl r4, r7, #31
; CHECK-NEXT: rsbs.w r3, r4, #-2147483648 ; CHECK-NEXT: rsbs.w r3, r4, #-2147483648
; CHECK-NEXT: vmov q5[2], q5[0], r4, r6 ; CHECK-NEXT: vmov q5[2], q5[0], r4, r6
; CHECK-NEXT: sbcs.w r3, r12, r7 ; CHECK-NEXT: sbcs.w r3, r12, r7
; CHECK-NEXT: vmov q5[3], q5[1], r7, r5 ; CHECK-NEXT: vmov q5[3], q5[1], r7, r5
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov q0[2], q0[0], r3, r10 ; CHECK-NEXT: vmov q0[2], q0[0], r3, r10
; CHECK-NEXT: vmov q0[3], q0[1], r3, r10 ; CHECK-NEXT: vmov q0[3], q0[1], r3, r10
; CHECK-NEXT: vbic q4, q2, q0 ; CHECK-NEXT: vbic q4, q2, q0
; CHECK-NEXT: vand q0, q5, q0 ; CHECK-NEXT: vand q0, q5, q0
; CHECK-NEXT: vorr q4, q0, q4 ; CHECK-NEXT: vorr q4, q0, q4
; CHECK-NEXT: vmov r3, r4, d8 ; CHECK-NEXT: vmov r3, r4, d8
; CHECK-NEXT: subs.w r3, r3, r8 ; CHECK-NEXT: subs.w r3, r3, r8
; CHECK-NEXT: sbcs r3, r4, #0 ; CHECK-NEXT: sbcs r3, r4, #0
; CHECK-NEXT: vmov r4, r5, d9 ; CHECK-NEXT: vmov r4, r5, d9
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: vmov.32 q0[1], r3 ; CHECK-NEXT: vmov.32 q0[1], r3
; CHECK-NEXT: subs.w r4, r4, r8 ; CHECK-NEXT: subs.w r4, r4, r8
; CHECK-NEXT: sbcs r4, r5, #0 ; CHECK-NEXT: sbcs r4, r5, #0
; CHECK-NEXT: mov.w r4, #0 ; CHECK-NEXT: cset r4, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r4, #1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csetm r4, ne ; CHECK-NEXT: csetm r4, ne
; CHECK-NEXT: vmov q0[2], q0[0], r3, r4 ; CHECK-NEXT: vmov q0[2], q0[0], r3, r4
; CHECK-NEXT: vbic q5, q3, q0 ; CHECK-NEXT: vbic q5, q3, q0
; CHECK-NEXT: vand q0, q4, q0 ; CHECK-NEXT: vand q0, q4, q0
; CHECK-NEXT: vorr q0, q0, q5 ; CHECK-NEXT: vorr q0, q0, q5
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s2, s24 ; CHECK-NEXT: vmov.f32 s2, s24
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrd r4, r7, [r0], #8 ; CHECK-NEXT: ldrd r4, r7, [r0], #8
; CHECK-NEXT: ldrd r5, r10, [r1], #8 ; CHECK-NEXT: ldrd r5, r10, [r1], #8
; CHECK-NEXT: umull r4, r5, r5, r4 ; CHECK-NEXT: umull r4, r5, r5, r4
; CHECK-NEXT: lsrl r4, r5, #31 ; CHECK-NEXT: lsrl r4, r5, #31
; CHECK-NEXT: subs.w r6, r4, #-1 ; CHECK-NEXT: subs.w r6, r4, #-1
; CHECK-NEXT: umull r6, r7, r10, r7 ; CHECK-NEXT: umull r6, r7, r10, r7
; CHECK-NEXT: sbcs r5, r5, #0 ; CHECK-NEXT: sbcs r5, r5, #0
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: lsrl r6, r7, #31 ; CHECK-NEXT: lsrl r6, r7, #31
; CHECK-NEXT: csetm r9, ne ; CHECK-NEXT: csetm r9, ne
; CHECK-NEXT: subs.w r5, r6, #-1 ; CHECK-NEXT: subs.w r5, r6, #-1
; CHECK-NEXT: vmov.32 q0[1], r9 ; CHECK-NEXT: vmov.32 q0[1], r9
; CHECK-NEXT: sbcs r5, r7, #0 ; CHECK-NEXT: sbcs r5, r7, #0
; CHECK-NEXT: vmov q1[2], q1[0], r4, r6 ; CHECK-NEXT: vmov q1[2], q1[0], r4, r6
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csetm r5, ne ; CHECK-NEXT: csetm r5, ne
; CHECK-NEXT: vmov q0[2], q0[0], r9, r5 ; CHECK-NEXT: vmov q0[2], q0[0], r9, r5
; CHECK-NEXT: vand q1, q1, q0 ; CHECK-NEXT: vand q1, q1, q0
; CHECK-NEXT: vorn q0, q1, q0 ; CHECK-NEXT: vorn q0, q1, q0
; CHECK-NEXT: vmov r4, s2 ; CHECK-NEXT: vmov r4, s2
; CHECK-NEXT: vmov r5, s0 ; CHECK-NEXT: vmov r5, s0
; CHECK-NEXT: strd r5, r4, [r2], #8 ; CHECK-NEXT: strd r5, r4, [r2], #8
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: beq.w .LBB4_8 ; CHECK-NEXT: beq.w .LBB4_8
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader ; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: mov.w r8, #0
; CHECK-NEXT: cmp r3, #3 ; CHECK-NEXT: cmp r3, #3
; CHECK-NEXT: bhi .LBB4_3 ; CHECK-NEXT: bhi .LBB4_3
; CHECK-NEXT: @ %bb.2: ; CHECK-NEXT: @ %bb.2:
; CHECK-NEXT: mov.w r8, #0
; CHECK-NEXT: mov r12, r0 ; CHECK-NEXT: mov r12, r0
; CHECK-NEXT: mov r9, r1 ; CHECK-NEXT: mov r9, r1
; CHECK-NEXT: mov r10, r2 ; CHECK-NEXT: mov r10, r2
; CHECK-NEXT: b .LBB4_6 ; CHECK-NEXT: b .LBB4_6
; CHECK-NEXT: .LBB4_3: @ %vector.ph ; CHECK-NEXT: .LBB4_3: @ %vector.ph
; CHECK-NEXT: bic r8, r3, #3 ; CHECK-NEXT: bic r8, r3, #3
; CHECK-NEXT: movs r6, #1 ; CHECK-NEXT: movs r6, #1
; CHECK-NEXT: sub.w r7, r8, #4 ; CHECK-NEXT: sub.w r7, r8, #4
Show All 12 Lines
; CHECK-NEXT: vmullb.u32 q4, q3, q1 ; CHECK-NEXT: vmullb.u32 q4, q3, q1
; CHECK-NEXT: vmov.f32 s2, s1 ; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vmov r4, r5, d8 ; CHECK-NEXT: vmov r4, r5, d8
; CHECK-NEXT: lsrl r4, r5, #31 ; CHECK-NEXT: lsrl r4, r5, #31
; CHECK-NEXT: vmov.f32 s10, s9 ; CHECK-NEXT: vmov.f32 s10, s9
; CHECK-NEXT: subs.w r6, r4, #-1 ; CHECK-NEXT: subs.w r6, r4, #-1
; CHECK-NEXT: sbcs r5, r5, #0 ; CHECK-NEXT: sbcs r5, r5, #0
; CHECK-NEXT: vmov r6, r7, d9 ; CHECK-NEXT: vmov r6, r7, d9
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lo
; CHECK-NEXT: lsrl r6, r7, #31 ; CHECK-NEXT: lsrl r6, r7, #31
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: vmov q3[2], q3[0], r4, r6
; CHECK-NEXT: csetm r11, ne ; CHECK-NEXT: csetm r11, ne
; CHECK-NEXT: subs.w r5, r6, #-1 ; CHECK-NEXT: subs.w r5, r6, #-1
; CHECK-NEXT: sbcs r5, r7, #0 ; CHECK-NEXT: sbcs r5, r7, #0
; CHECK-NEXT: vmov.32 q1[1], r11 ; CHECK-NEXT: vmov.32 q1[1], r11
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lo
; CHECK-NEXT: vmov q3[2], q3[0], r4, r6
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csetm r5, ne ; CHECK-NEXT: csetm r5, ne
; CHECK-NEXT: vmov q1[2], q1[0], r11, r5 ; CHECK-NEXT: vmov q1[2], q1[0], r11, r5
; CHECK-NEXT: vand q3, q3, q1 ; CHECK-NEXT: vand q3, q3, q1
; CHECK-NEXT: vorn q1, q3, q1 ; CHECK-NEXT: vorn q1, q3, q1
; CHECK-NEXT: vmullb.u32 q3, q2, q0 ; CHECK-NEXT: vmullb.u32 q3, q2, q0
; CHECK-NEXT: vmov r4, r5, d6 ; CHECK-NEXT: vmov r4, r5, d6
; CHECK-NEXT: lsrl r4, r5, #31 ; CHECK-NEXT: lsrl r4, r5, #31
; CHECK-NEXT: subs.w r6, r4, #-1 ; CHECK-NEXT: subs.w r6, r4, #-1
; CHECK-NEXT: sbcs r5, r5, #0 ; CHECK-NEXT: sbcs r5, r5, #0
; CHECK-NEXT: vmov r6, r7, d7 ; CHECK-NEXT: vmov r6, r7, d7
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lo
; CHECK-NEXT: lsrl r6, r7, #31 ; CHECK-NEXT: lsrl r6, r7, #31
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: vmov q2[2], q2[0], r4, r6
; CHECK-NEXT: csetm r11, ne ; CHECK-NEXT: csetm r11, ne
; CHECK-NEXT: subs.w r5, r6, #-1 ; CHECK-NEXT: subs.w r5, r6, #-1
; CHECK-NEXT: sbcs r5, r7, #0 ; CHECK-NEXT: sbcs r5, r7, #0
; CHECK-NEXT: vmov.32 q0[1], r11 ; CHECK-NEXT: vmov.32 q0[1], r11
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lo
; CHECK-NEXT: vmov q2[2], q2[0], r4, r6
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csetm r5, ne ; CHECK-NEXT: csetm r5, ne
; CHECK-NEXT: vmov q0[2], q0[0], r11, r5 ; CHECK-NEXT: vmov q0[2], q0[0], r11, r5
; CHECK-NEXT: vand q2, q2, q0 ; CHECK-NEXT: vand q2, q2, q0
; CHECK-NEXT: vorn q0, q2, q0 ; CHECK-NEXT: vorn q0, q2, q0
; CHECK-NEXT: vmov.f32 s1, s2 ; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s2, s4 ; CHECK-NEXT: vmov.f32 s2, s4
; CHECK-NEXT: vmov.f32 s3, s6 ; CHECK-NEXT: vmov.f32 s3, s6
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llvm/test/CodeGen/Thumb2/mve-vcmp.ll

Show First 20 Lines • Show All 388 Lines • ▼ Show 20 Linesentry:
%c = icmp eq <2 x i64> %src, %srcb %c = icmp eq <2 x i64> %src, %srcb
%s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }
define arm_aapcs_vfpcc <2 x i64> @vcmp_slt_v2i64(<2 x i64> %src, <2 x i64> %srcb, <2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @vcmp_slt_v2i64(<2 x i64> %src, <2 x i64> %srcb, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: vcmp_slt_v2i64: ; CHECK-LABEL: vcmp_slt_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vmov r0, r1, d3
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: vmov r0, r12, d3
; CHECK-NEXT: movs r1, #0
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d1
; CHECK-NEXT: subs r0, r2, r0 ; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs.w r0, r3, r12 ; CHECK-NEXT: sbcs.w r0, r3, r1
; CHECK-NEXT: vmov lr, r12, d2 ; CHECK-NEXT: vmov r1, r12, d2
; CHECK-NEXT: vmov r3, r2, d0 ; CHECK-NEXT: vmov r3, r2, d0
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs.w r3, r3, lr ; CHECK-NEXT: subs r1, r3, r1
; CHECK-NEXT: sbcs.w r2, r2, r12 ; CHECK-NEXT: sbcs.w r1, r2, r12
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: vbic q1, q3, q0 ; CHECK-NEXT: vbic q1, q3, q0
; CHECK-NEXT: vand q0, q2, q0 ; CHECK-NEXT: vand q0, q2, q0
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp slt <2 x i64> %src, %srcb %c = icmp slt <2 x i64> %src, %srcb
%s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }
define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, <2 x i64> %srcb, <2 x i32> %a, <2 x i32> %b) { define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, <2 x i64> %srcb, <2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: vcmp_eq_v2i32: ; CHECK-LABEL: vcmp_eq_v2i32:
Show All 20 Linesentry:
%c = icmp eq <2 x i64> %src, %srcb %c = icmp eq <2 x i64> %src, %srcb
%s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %s ret <2 x i32> %s
} }
define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) { define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
; CHECK-LABEL: vcmp_multi_v2i32: ; CHECK-LABEL: vcmp_multi_v2i32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, r2, d0 ; CHECK-NEXT: vmov r1, r2, d0
; CHECK-NEXT: csetm r0, eq ; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: orrs r1, r2 ; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s10 ; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: csetm r1, eq ; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: vbic q0, q2, q0 ; CHECK-NEXT: vbic q0, q2, q0
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: subs r1, r0, r2 ; CHECK-NEXT: subs r3, r0, r2
; CHECK-NEXT: asr.w r12, r0, #31 ; CHECK-NEXT: asr.w r1, r0, #31
; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31 ; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: sbcs.w r1, r1, r2, asr #31
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: csetm lr, ne ; CHECK-NEXT: csetm lr, ne
; CHECK-NEXT: subs r1, r2, r3
; CHECK-NEXT: asr.w r12, r2, #31 ; CHECK-NEXT: asr.w r12, r2, #31
; CHECK-NEXT: subs r4, r2, r1 ; CHECK-NEXT: sbcs.w r1, r12, r3, asr #31
; CHECK-NEXT: sbcs.w r1, r12, r1, asr #31 ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: it lt ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov q3[2], q3[0], r1, lr ; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vmov q3[3], q3[1], r1, lr ; CHECK-NEXT: vmov q3[3], q3[1], r1, lr
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0 ; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0 ; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: vand q1, q1, q4 ; CHECK-NEXT: vand q1, q1, q4
; CHECK-NEXT: vand q1, q3, q1 ; CHECK-NEXT: vand q1, q3, q1
; CHECK-NEXT: vbic q0, q0, q1 ; CHECK-NEXT: vbic q0, q0, q1
; CHECK-NEXT: vand q1, q2, q1 ; CHECK-NEXT: vand q1, q2, q1
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
%a4 = icmp eq <2 x i64> %a, zeroinitializer %a4 = icmp eq <2 x i64> %a, zeroinitializer
%a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c
%a6 = icmp ne <2 x i32> %b, zeroinitializer %a6 = icmp ne <2 x i32> %b, zeroinitializer
%a7 = icmp slt <2 x i32> %a5, %c %a7 = icmp slt <2 x i32> %a5, %c
%a8 = icmp ne <2 x i32> %a5, zeroinitializer %a8 = icmp ne <2 x i32> %a5, zeroinitializer
%a9 = and <2 x i1> %a6, %a8 %a9 = and <2 x i1> %a6, %a8
%a10 = and <2 x i1> %a7, %a9 %a10 = and <2 x i1> %a7, %a9
%a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5 %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5
ret <2 x i32> %a11 ret <2 x i32> %a11
} }

llvm/test/CodeGen/Thumb2/mve-vcmpf.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVEFP ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVEFP
define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v4f32: ; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32: ; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oeq <4 x float> %src, %src2 %c = fcmp oeq <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_one_v4f32: ; CHECK-MVE-LABEL: vcmp_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v4f32: ; CHECK-MVEFP-LABEL: vcmp_one_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f32 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp one <4 x float> %src, %src2 %c = fcmp one <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v4f32: ; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r1, gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r2, gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r3, gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ogt <4 x float> %src, %src2 %c = fcmp ogt <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v4f32: ; CHECK-MVE-LABEL: vcmp_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r1, ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r2, ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r3, ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oge_v4f32: ; CHECK-MVEFP-LABEL: vcmp_oge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oge <4 x float> %src, %src2 %c = fcmp oge <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v4f32: ; CHECK-MVE-LABEL: vcmp_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_olt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_olt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp olt <4 x float> %src, %src2 %c = fcmp olt <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v4f32: ; CHECK-MVE-LABEL: vcmp_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r1, ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r2, ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r3, ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ole_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ole_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ole <4 x float> %src, %src2 %c = fcmp ole <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v4f32: ; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f32 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ueq <4 x float> %src, %src2 %c = fcmp ueq <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_une_v4f32: ; CHECK-MVE-LABEL: vcmp_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_une_v4f32: ; CHECK-MVEFP-LABEL: vcmp_une_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp une <4 x float> %src, %src2 %c = fcmp une <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v4f32: ; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r1, hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r2, hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r3, hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ugt <4 x float> %src, %src2 %c = fcmp ugt <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v4f32: ; CHECK-MVE-LABEL: vcmp_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r1, pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r2, pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r3, pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uge_v4f32: ; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 le, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f32 le, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uge <4 x float> %src, %src2 %c = fcmp uge <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v4f32: ; CHECK-MVE-LABEL: vcmp_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r1, lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r2, lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r3, lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ult_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ult <4 x float> %src, %src2 %c = fcmp ult <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v4f32: ; CHECK-MVE-LABEL: vcmp_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r1, le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r2, le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r3, le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ule_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ule <4 x float> %src, %src2 %c = fcmp ule <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v4f32: ; CHECK-MVE-LABEL: vcmp_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r1, vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r2, vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r3, vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ord_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f32 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ord <4 x float> %src, %src2 %c = fcmp ord <4 x float> %src, %src2
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v4f32: ; CHECK-MVE-LABEL: vcmp_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r1, vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r2, vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r3, vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v4f32: ; CHECK-MVEFP-LABEL: vcmp_uno_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f32 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
Show All 9 Lines
define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v8f16: ; CHECK-MVE-LABEL: vcmp_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oeq <8 x half> %src, %src2 %c = fcmp oeq <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_one_v8f16: ; CHECK-MVE-LABEL: vcmp_one_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 12 Lines
define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v8f16: ; CHECK-MVE-LABEL: vcmp_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ogt <8 x half> %src, %src2 %c = fcmp ogt <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v8f16: ; CHECK-MVE-LABEL: vcmp_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oge <8 x half> %src, %src2 %c = fcmp oge <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v8f16: ; CHECK-MVE-LABEL: vcmp_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp olt <8 x half> %src, %src2 %c = fcmp olt <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v8f16: ; CHECK-MVE-LABEL: vcmp_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ole <8 x half> %src, %src2 %c = fcmp ole <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v8f16: ; CHECK-MVE-LABEL: vcmp_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 12 Lines
define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_une_v8f16: ; CHECK-MVE-LABEL: vcmp_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp une <8 x half> %src, %src2 %c = fcmp une <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v8f16: ; CHECK-MVE-LABEL: vcmp_ugt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ugt <8 x half> %src, %src2 %c = fcmp ugt <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v8f16: ; CHECK-MVE-LABEL: vcmp_uge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uge <8 x half> %src, %src2 %c = fcmp uge <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v8f16: ; CHECK-MVE-LABEL: vcmp_ult_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ult <8 x half> %src, %src2 %c = fcmp ult <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v8f16: ; CHECK-MVE-LABEL: vcmp_ule_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, q1 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ule <8 x half> %src, %src2 %c = fcmp ule <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v8f16: ; CHECK-MVE-LABEL: vcmp_ord_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0
Show All 9 Lines
define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v8f16: ; CHECK-MVE-LABEL: vcmp_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: .vsave {d8, d9}
; CHECK-MVE-NEXT: vpush {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4 ; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1 ; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s9 ; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s13 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s2 ; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4 ; CHECK-MVE-NEXT: vcmp.f16 s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s10 ; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s4, s11 ; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s6, s15 ; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s16
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q1, q0
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q1 ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, q1
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uno <8 x half> %src, %src2 %c = fcmp uno <8 x half> %src, %src2
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }

llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVEFP ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVEFP
define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v4f32: ; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32: ; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp oeq <4 x float> %src, %sp %c = fcmp oeq <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_one_v4f32: ; CHECK-MVE-LABEL: vcmp_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v4f32: ; CHECK-MVEFP-LABEL: vcmp_one_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp one <4 x float> %src, %sp %c = fcmp one <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v4f32: ; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r1, gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r2, gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r3, gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ogt <4 x float> %src, %sp %c = fcmp ogt <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v4f32: ; CHECK-MVE-LABEL: vcmp_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r1, ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r2, ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r3, ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oge_v4f32: ; CHECK-MVEFP-LABEL: vcmp_oge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp oge <4 x float> %src, %sp %c = fcmp oge <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v4f32: ; CHECK-MVE-LABEL: vcmp_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_olt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_olt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp olt <4 x float> %src, %sp %c = fcmp olt <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v4f32: ; CHECK-MVE-LABEL: vcmp_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r1, ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r2, ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r3, ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ole_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ole_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ole <4 x float> %src, %sp %c = fcmp ole <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v4f32: ; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ueq <4 x float> %src, %sp %c = fcmp ueq <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_une_v4f32: ; CHECK-MVE-LABEL: vcmp_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_une_v4f32: ; CHECK-MVEFP-LABEL: vcmp_une_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp une <4 x float> %src, %sp %c = fcmp une <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v4f32: ; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r1, hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r2, hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r3, hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ugt <4 x float> %src, %sp %c = fcmp ugt <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v4f32: ; CHECK-MVE-LABEL: vcmp_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r1, pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r2, pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r3, pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uge_v4f32: ; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp uge <4 x float> %src, %sp %c = fcmp uge <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v4f32: ; CHECK-MVE-LABEL: vcmp_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r1, lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r2, lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r3, lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ult_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ult <4 x float> %src, %sp %c = fcmp ult <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v4f32: ; CHECK-MVE-LABEL: vcmp_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r1, le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r2, le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r3, le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ule_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ule <4 x float> %src, %sp %c = fcmp ule <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v4f32: ; CHECK-MVE-LABEL: vcmp_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r1, vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r2, vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r3, vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ord_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ord <4 x float> %src, %sp %c = fcmp ord <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v4f32: ; CHECK-MVE-LABEL: vcmp_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r1, vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r2, vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r3, vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v4f32: ; CHECK-MVEFP-LABEL: vcmp_uno_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp uno <4 x float> %src, %sp %c = fcmp uno <4 x float> %src, %sp
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v8f16: ; CHECK-MVE-LABEL: vcmp_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp oeq <8 x half> %src, %sp %c = fcmp oeq <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_one_v8f16: ; CHECK-MVE-LABEL: vcmp_one_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s8, s15 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
Show All 10 Linesentry:
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v8f16: ; CHECK-MVE-LABEL: vcmp_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ogt <8 x half> %src, %sp %c = fcmp ogt <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v8f16: ; CHECK-MVE-LABEL: vcmp_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp oge <8 x half> %src, %sp %c = fcmp oge <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v8f16: ; CHECK-MVE-LABEL: vcmp_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp olt <8 x half> %src, %sp %c = fcmp olt <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v8f16: ; CHECK-MVE-LABEL: vcmp_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ole <8 x half> %src, %sp %c = fcmp ole <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v8f16: ; CHECK-MVE-LABEL: vcmp_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s8, s15 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
Show All 10 Linesentry:
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_une_v8f16: ; CHECK-MVE-LABEL: vcmp_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp une <8 x half> %src, %sp %c = fcmp une <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v8f16: ; CHECK-MVE-LABEL: vcmp_ugt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ugt <8 x half> %src, %sp %c = fcmp ugt <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v8f16: ; CHECK-MVE-LABEL: vcmp_uge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp uge <8 x half> %src, %sp %c = fcmp uge <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v8f16: ; CHECK-MVE-LABEL: vcmp_ult_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ult <8 x half> %src, %sp %c = fcmp ult <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v8f16: ; CHECK-MVE-LABEL: vcmp_ule_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ule <8 x half> %src, %sp %c = fcmp ule <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v8f16: ; CHECK-MVE-LABEL: vcmp_ord_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ord <8 x half> %src, %sp %c = fcmp ord <8 x half> %src, %sp
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v8f16: ; CHECK-MVE-LABEL: vcmp_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
Show All 11 Lines
; Reversed ; Reversed
define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32: ; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oeq_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_oeq_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp oeq <4 x float> %sp, %src %c = fcmp oeq <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_one_v4f32: ; CHECK-MVE-LABEL: vcmp_r_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_one_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_one_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp one <4 x float> %sp, %src %c = fcmp one <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r1, gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r2, gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r3, gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ogt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ogt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ogt <4 x float> %sp, %src %c = fcmp ogt <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_oge_v4f32: ; CHECK-MVE-LABEL: vcmp_r_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r1, ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r2, ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r3, ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oge_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_oge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp oge <4 x float> %sp, %src %c = fcmp oge <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_olt_v4f32: ; CHECK-MVE-LABEL: vcmp_r_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_olt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_olt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp olt <4 x float> %sp, %src %c = fcmp olt <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ole_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r1, ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r2, ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r3, ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ole_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ole_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ole <4 x float> %sp, %src %c = fcmp ole <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ueq <4 x float> %sp, %src %c = fcmp ueq <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_une_v4f32: ; CHECK-MVE-LABEL: vcmp_r_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_une_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_une_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp une <4 x float> %sp, %src %c = fcmp une <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r1, hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r2, hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r3, hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ugt <4 x float> %sp, %src %c = fcmp ugt <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_uge_v4f32: ; CHECK-MVE-LABEL: vcmp_r_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r1, pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r2, pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r3, pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp uge <4 x float> %sp, %src %c = fcmp uge <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ult_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r1, lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r2, lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r3, lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ult <4 x float> %sp, %src %c = fcmp ult <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ule_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r1, le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r2, le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r3, le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ule <4 x float> %sp, %src %c = fcmp ule <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ord_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r1, vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r2, vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r3, vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ord_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ord_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp ord <4 x float> %sp, %src %c = fcmp ord <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_uno_v4f32: ; CHECK-MVE-LABEL: vcmp_r_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1 ; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0 ; CHECK-MVE-NEXT: vcmp.f32 s4, s0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s3 ; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r1, vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s4, s2 ; CHECK-MVE-NEXT: vcmp.f32 s4, s2
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r2, vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r3, vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uno_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_uno_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov r0, s4 ; CHECK-MVEFP-NEXT: vmov r0, s4
; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f32 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <4 x float> undef, float %src2, i32 0 %i = insertelement <4 x float> undef, float %src2, i32 0
%sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer %sp = shufflevector <4 x float> %i, <4 x float> undef, <4 x i32> zeroinitializer
%c = fcmp uno <4 x float> %sp, %src %c = fcmp uno <4 x float> %sp, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16: ; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp oeq <8 x half> %sp, %src %c = fcmp oeq <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_one_v8f16: ; CHECK-MVE-LABEL: vcmp_r_one_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s8, s15 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16:
Show All 10 Linesentry:
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ogt <8 x half> %sp, %src %c = fcmp ogt <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_oge_v8f16: ; CHECK-MVE-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp oge <8 x half> %sp, %src %c = fcmp oge <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_olt_v8f16: ; CHECK-MVE-LABEL: vcmp_r_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp olt <8 x half> %sp, %src %c = fcmp olt <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ole_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ole <8 x half> %sp, %src %c = fcmp ole <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmovx.f16 s8, s15 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16:
Show All 10 Linesentry:
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_une_v8f16: ; CHECK-MVE-LABEL: vcmp_r_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp une <8 x half> %sp, %src %c = fcmp une <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ugt <8 x half> %sp, %src %c = fcmp ugt <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_uge_v8f16: ; CHECK-MVE-LABEL: vcmp_r_uge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp uge <8 x half> %sp, %src %c = fcmp uge <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ult_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ult <8 x half> %sp, %src %c = fcmp ult <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ule_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0 ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q2, q3 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q3
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ule <8 x half> %sp, %src %c = fcmp ule <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ord_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ord_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0 ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, r0
; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, r0 ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, r0
; CHECK-MVEFP-NEXT: vpsel q0, q3, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%i = insertelement <8 x half> undef, half %src2, i32 0 %i = insertelement <8 x half> undef, half %src2, i32 0
%sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer %sp = shufflevector <8 x half> %i, <8 x half> undef, <8 x i32> zeroinitializer
%c = fcmp ord <8 x half> %sp, %src %c = fcmp ord <8 x half> %sp, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_uno_v8f16: ; CHECK-MVE-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s0 ; CHECK-MVE-NEXT: vcmp.f16 s4, s0
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s4, s1 ; CHECK-MVE-NEXT: vcmp.f16 s4, s1
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s4, s2 ; CHECK-MVE-NEXT: vcmp.f16 s4, s2
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6 ; CHECK-MVE-NEXT: vcmp.f16 s4, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s4, s3 ; CHECK-MVE-NEXT: vcmp.f16 s4, s3
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
Show All 10 Lines
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16_bc(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16_bc(<8 x half> %src, half %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v8f16_bc: ; CHECK-MVE-LABEL: vcmp_oeq_v8f16_bc:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s8 ; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6 ; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1 ; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s9 ; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s4 ; CHECK-MVE-NEXT: vcmp.f16 s1, s4
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s6 ; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2 ; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s10 ; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s4 ; CHECK-MVE-NEXT: vcmp.f16 s2, s4
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s2, s6 ; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3 ; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4 ; CHECK-MVE-NEXT: vcmp.f16 s6, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s11 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s4 ; CHECK-MVE-NEXT: vcmp.f16 s3, s4
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6 ; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6 ; CHECK-MVE-NEXT: vins.f16 s3, s6
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16_bc: ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16_bc:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vmov.f16 r0, s4 ; CHECK-MVEFP-NEXT: vmov.f16 r0, s4
Show All 12 Lines

llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVEFP ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-MVEFP
define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v4f32: ; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32: ; CHECK-MVEFP-LABEL: vcmp_oeq_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oeq <4 x float> %src, zeroinitializer %c = fcmp oeq <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_one_v4f32: ; CHECK-MVE-LABEL: vcmp_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v4f32: ; CHECK-MVEFP-LABEL: vcmp_one_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp one <4 x float> %src, zeroinitializer %c = fcmp one <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v4f32: ; CHECK-MVE-LABEL: vcmp_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r1, gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r2, gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r3, gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ogt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ogt <4 x float> %src, zeroinitializer %c = fcmp ogt <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v4f32: ; CHECK-MVE-LABEL: vcmp_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r1, ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r2, ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r3, ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oge_v4f32: ; CHECK-MVEFP-LABEL: vcmp_oge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oge <4 x float> %src, zeroinitializer %c = fcmp oge <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v4f32: ; CHECK-MVE-LABEL: vcmp_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_olt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_olt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp olt <4 x float> %src, zeroinitializer %c = fcmp olt <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v4f32: ; CHECK-MVE-LABEL: vcmp_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r1, ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r2, ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r3, ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ole_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ole_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ole <4 x float> %src, zeroinitializer %c = fcmp ole <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v4f32: ; CHECK-MVE-LABEL: vcmp_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ueq_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f32 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ueq <4 x float> %src, zeroinitializer %c = fcmp ueq <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_une_v4f32: ; CHECK-MVE-LABEL: vcmp_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_une_v4f32: ; CHECK-MVEFP-LABEL: vcmp_une_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp une <4 x float> %src, zeroinitializer %c = fcmp une <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v4f32: ; CHECK-MVE-LABEL: vcmp_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r1, hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r2, hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r3, hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ugt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ugt <4 x float> %src, zeroinitializer %c = fcmp ugt <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v4f32: ; CHECK-MVE-LABEL: vcmp_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r1, pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r2, pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r3, pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uge_v4f32: ; CHECK-MVEFP-LABEL: vcmp_uge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uge <4 x float> %src, zeroinitializer %c = fcmp uge <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v4f32: ; CHECK-MVE-LABEL: vcmp_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r1, lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r2, lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r3, lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ult_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ult_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ult <4 x float> %src, zeroinitializer %c = fcmp ult <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v4f32: ; CHECK-MVE-LABEL: vcmp_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r1, le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r2, le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r3, le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ule_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ule_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ule <4 x float> %src, zeroinitializer %c = fcmp ule <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v4f32: ; CHECK-MVE-LABEL: vcmp_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r1, vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r2, vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r3, vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v4f32: ; CHECK-MVEFP-LABEL: vcmp_ord_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ord <4 x float> %src, zeroinitializer %c = fcmp ord <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v4f32: ; CHECK-MVE-LABEL: vcmp_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r1, vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r2, vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r3, vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v4f32: ; CHECK-MVEFP-LABEL: vcmp_uno_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f32 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f32 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uno <4 x float> %src, zeroinitializer %c = fcmp uno <4 x float> %src, zeroinitializer
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v8f16: ; CHECK-MVE-LABEL: vcmp_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oeq <8 x half> %src, zeroinitializer %c = fcmp oeq <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_one_v8f16: ; CHECK-MVE-LABEL: vcmp_one_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp one <8 x half> %src, zeroinitializer %c = fcmp one <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ogt_v8f16: ; CHECK-MVE-LABEL: vcmp_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ogt <8 x half> %src, zeroinitializer %c = fcmp ogt <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_oge_v8f16: ; CHECK-MVE-LABEL: vcmp_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oge <8 x half> %src, zeroinitializer %c = fcmp oge <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_olt_v8f16: ; CHECK-MVE-LABEL: vcmp_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp olt <8 x half> %src, zeroinitializer %c = fcmp olt <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ole_v8f16: ; CHECK-MVE-LABEL: vcmp_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ole <8 x half> %src, zeroinitializer %c = fcmp ole <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ueq_v8f16: ; CHECK-MVE-LABEL: vcmp_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ueq <8 x half> %src, zeroinitializer %c = fcmp ueq <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_une_v8f16: ; CHECK-MVE-LABEL: vcmp_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp une <8 x half> %src, zeroinitializer %c = fcmp une <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ugt_v8f16: ; CHECK-MVE-LABEL: vcmp_ugt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ugt <8 x half> %src, zeroinitializer %c = fcmp ugt <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uge_v8f16: ; CHECK-MVE-LABEL: vcmp_uge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uge <8 x half> %src, zeroinitializer %c = fcmp uge <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ult_v8f16: ; CHECK-MVE-LABEL: vcmp_ult_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ult <8 x half> %src, zeroinitializer %c = fcmp ult <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ule_v8f16: ; CHECK-MVE-LABEL: vcmp_ule_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ule <8 x half> %src, zeroinitializer %c = fcmp ule <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_ord_v8f16: ; CHECK-MVE-LABEL: vcmp_ord_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, s12 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, s0 ; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, s1 ; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2 ; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3 ; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ord <8 x half> %src, zeroinitializer %c = fcmp ord <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_uno_v8f16: ; CHECK-MVE-LABEL: vcmp_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, s12 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, s0 ; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, s1 ; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2 ; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3 ; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uno <8 x half> %src, zeroinitializer %c = fcmp uno <8 x half> %src, zeroinitializer
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
; Reversed ; Reversed
define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32: ; CHECK-MVE-LABEL: vcmp_r_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oeq_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_oeq_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 eq, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oeq <4 x float> zeroinitializer, %src %c = fcmp oeq <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_one_v4f32: ; CHECK-MVE-LABEL: vcmp_r_one_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_one_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_one_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp one <4 x float> zeroinitializer, %src %c = fcmp one <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ogt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ogt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ogt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ogt <4 x float> zeroinitializer, %src %c = fcmp ogt <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_oge_v4f32: ; CHECK-MVE-LABEL: vcmp_r_oge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r1, ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r2, ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r3, ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oge_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_oge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oge <4 x float> zeroinitializer, %src %c = fcmp oge <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_olt_v4f32: ; CHECK-MVE-LABEL: vcmp_r_olt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r1, gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r2, gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r3, gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_olt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_olt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp olt <4 x float> zeroinitializer, %src %c = fcmp olt <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ole_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ole_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r1, ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r2, ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r3, ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ole_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ole_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ole <4 x float> zeroinitializer, %src %c = fcmp ole <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ueq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: cset r1, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: cset r2, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r3, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f32 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ueq <4 x float> zeroinitializer, %src %c = fcmp ueq <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_une_v4f32: ; CHECK-MVE-LABEL: vcmp_r_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_une_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_une_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp une <4 x float> zeroinitializer, %src %c = fcmp une <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ugt_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r1, lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r2, lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r3, lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ugt_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ugt <4 x float> zeroinitializer, %src %c = fcmp ugt <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_uge_v4f32: ; CHECK-MVE-LABEL: vcmp_r_uge_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r1, le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r2, le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r3, le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_uge_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uge <4 x float> zeroinitializer, %src %c = fcmp uge <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ult_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ult_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r1, hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r2, hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r3, hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ult_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ult <4 x float> zeroinitializer, %src %c = fcmp ult <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ule_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ule_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r1, pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r2, pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r3, pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ule_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f32 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ule <4 x float> zeroinitializer, %src %c = fcmp ule <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_ord_v4f32: ; CHECK-MVE-LABEL: vcmp_r_ord_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r1, vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r2, vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r3, vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ord_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_ord_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ord <4 x float> zeroinitializer, %src %c = fcmp ord <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_r_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_uno_v4f32: ; CHECK-MVE-LABEL: vcmp_r_uno_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s1 ; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s0 ; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s3 ; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r1, vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s2 ; CHECK-MVE-NEXT: vcmp.f32 s2, s2
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r2, vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r3, vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uno_v4f32: ; CHECK-MVEFP-LABEL: vcmp_r_uno_v4f32:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f32 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f32 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uno <4 x float> zeroinitializer, %src %c = fcmp uno <4 x float> zeroinitializer, %src
%s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b %s = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
ret <4 x float> %s ret <4 x float> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_oeq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16: ; CHECK-MVE-LABEL: vcmp_r_oeq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_oeq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 eq, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oeq <8 x half> zeroinitializer, %src %c = fcmp oeq <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_one_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_one_v8f16: ; CHECK-MVE-LABEL: vcmp_r_one_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_one_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp one <8 x half> zeroinitializer, %src %c = fcmp one <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ogt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ogt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ogt <8 x half> zeroinitializer, %src %c = fcmp ogt <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_oge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_oge_v8f16: ; CHECK-MVE-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: cset r0, ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_oge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp oge <8 x half> zeroinitializer, %src %c = fcmp oge <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_olt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_olt_v8f16: ; CHECK-MVE-LABEL: vcmp_r_olt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: cset r0, gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_olt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp olt <8 x half> zeroinitializer, %src %c = fcmp olt <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ole_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ole_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ole_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: cset r0, ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ole_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ole <8 x half> zeroinitializer, %src %c = fcmp ole <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ueq_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ueq_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ueq <8 x half> zeroinitializer, %src %c = fcmp ueq <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_une_v8f16: ; CHECK-MVE-LABEL: vcmp_r_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_une_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp une <8 x half> zeroinitializer, %src %c = fcmp une <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ugt_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ugt_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: cset r0, lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ugt_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 lt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ugt <8 x half> zeroinitializer, %src %c = fcmp ugt <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_uge_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_uge_v8f16: ; CHECK-MVE-LABEL: vcmp_r_uge_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: cset r0, le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uge_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uge <8 x half> zeroinitializer, %src %c = fcmp uge <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ult_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ult_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: cset r0, hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ult_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ult <8 x half> zeroinitializer, %src %c = fcmp ult <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ule_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ule_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: cset r0, pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ule_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr ; CHECK-MVEFP-NEXT: vcmp.f16 ge, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ule <8 x half> zeroinitializer, %src %c = fcmp ule <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_ord_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_ord_v8f16: ; CHECK-MVE-LABEL: vcmp_r_ord_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, s12 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, s0 ; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, s1 ; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2 ; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3 ; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: cset r0, vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_ord_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q2, q1 ; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp ord <8 x half> zeroinitializer, %src %c = fcmp ord <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }
define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) { define arm_aapcs_vfpcc <8 x half> @vcmp_r_uno_v8f16(<8 x half> %src, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_r_uno_v8f16: ; CHECK-MVE-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0 ; CHECK-MVE-NEXT: vmovx.f16 s12, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, s12 ; CHECK-MVE-NEXT: vcmp.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s0, s0 ; CHECK-MVE-NEXT: vcmp.f16 s0, s0
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1 ; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s4, s5 ; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmovx.f16 s8, s9 ; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, s1 ; CHECK-MVE-NEXT: vcmp.f16 s1, s1
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmovx.f16 s8, s10 ; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vins.f16 s1, s4 ; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2 ; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6 ; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s2, s2 ; CHECK-MVE-NEXT: vcmp.f16 s2, s2
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4 ; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3 ; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s4 ; CHECK-MVE-NEXT: vcmp.f16 s4, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s3, s3 ; CHECK-MVE-NEXT: vcmp.f16 s3, s3
; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4 ; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: cset r0, vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vins.f16 s0, s12
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4 ; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16: ; CHECK-MVEFP-LABEL: vcmp_r_uno_v8f16:
; CHECK-MVEFP: @ %bb.0: @ %entry ; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr ; CHECK-MVEFP-NEXT: vpt.f16 le, q0, zr
; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr ; CHECK-MVEFP-NEXT: vcmpt.f16 gt, q0, zr
; CHECK-MVEFP-NEXT: vpsel q0, q1, q2 ; CHECK-MVEFP-NEXT: vpsel q0, q1, q2
; CHECK-MVEFP-NEXT: bx lr ; CHECK-MVEFP-NEXT: bx lr
entry: entry:
%c = fcmp uno <8 x half> zeroinitializer, %src %c = fcmp uno <8 x half> zeroinitializer, %src
%s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b %s = select <8 x i1> %c, <8 x half> %a, <8 x half> %b
ret <8 x half> %s ret <8 x half> %s
} }

llvm/test/CodeGen/Thumb2/mve-vcmpr.ll

Show First 20 Lines • Show All 481 Lines • ▼ Show 20 Linesentry:
%c = icmp eq <2 x i64> %src, %sp %c = icmp eq <2 x i64> %src, %sp
%s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %s ret <2 x i32> %s
} }
define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) { define arm_aapcs_vfpcc <2 x i32> @vcmp_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
; CHECK-LABEL: vcmp_multi_v2i32: ; CHECK-LABEL: vcmp_multi_v2i32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, r2, d0 ; CHECK-NEXT: vmov r1, r2, d0
; CHECK-NEXT: csetm r0, eq ; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: orrs r1, r2 ; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s10 ; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: csetm r1, eq ; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: vbic q0, q2, q0 ; CHECK-NEXT: vbic q0, q2, q0
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: subs r1, r0, r2 ; CHECK-NEXT: subs r3, r0, r2
; CHECK-NEXT: asr.w r12, r0, #31 ; CHECK-NEXT: asr.w r1, r0, #31
; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31 ; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: sbcs.w r1, r1, r2, asr #31
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: csetm lr, ne ; CHECK-NEXT: csetm lr, ne
; CHECK-NEXT: subs r1, r2, r3
; CHECK-NEXT: asr.w r12, r2, #31 ; CHECK-NEXT: asr.w r12, r2, #31
; CHECK-NEXT: subs r4, r2, r1 ; CHECK-NEXT: sbcs.w r1, r12, r3, asr #31
; CHECK-NEXT: sbcs.w r1, r12, r1, asr #31 ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: it lt ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov q3[2], q3[0], r1, lr ; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vmov q3[3], q3[1], r1, lr ; CHECK-NEXT: vmov q3[3], q3[1], r1, lr
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0 ; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0 ; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: vand q1, q1, q4 ; CHECK-NEXT: vand q1, q1, q4
; CHECK-NEXT: vand q1, q3, q1 ; CHECK-NEXT: vand q1, q3, q1
; CHECK-NEXT: vbic q0, q0, q1 ; CHECK-NEXT: vbic q0, q0, q1
; CHECK-NEXT: vand q1, q2, q1 ; CHECK-NEXT: vand q1, q2, q1
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
%a4 = icmp eq <2 x i64> %a, zeroinitializer %a4 = icmp eq <2 x i64> %a, zeroinitializer
%a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c
%a6 = icmp ne <2 x i32> %b, zeroinitializer %a6 = icmp ne <2 x i32> %b, zeroinitializer
%a7 = icmp slt <2 x i32> %a5, %c %a7 = icmp slt <2 x i32> %a5, %c
%a8 = icmp ne <2 x i32> %a5, zeroinitializer %a8 = icmp ne <2 x i32> %a5, zeroinitializer
%a9 = and <2 x i1> %a6, %a8 %a9 = and <2 x i1> %a6, %a8
%a10 = and <2 x i1> %a7, %a9 %a10 = and <2 x i1> %a7, %a9
%a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5 %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5
▲ Show 20 Lines • Show All 483 Lines • ▼ Show 20 Linesentry:
%c = icmp eq <2 x i64> %sp, %src %c = icmp eq <2 x i64> %sp, %src
%s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %s ret <2 x i32> %s
} }
define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) { define arm_aapcs_vfpcc <2 x i32> @vcmp_r_multi_v2i32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
; CHECK-LABEL: vcmp_r_multi_v2i32: ; CHECK-LABEL: vcmp_r_multi_v2i32:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, r2, d0 ; CHECK-NEXT: vmov r1, r2, d0
; CHECK-NEXT: csetm r0, eq ; CHECK-NEXT: csetm r0, eq
; CHECK-NEXT: orrs r1, r2 ; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: vmov r2, s10 ; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: csetm r1, eq ; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: vmov q0[2], q0[0], r1, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0 ; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: vbic q0, q2, q0 ; CHECK-NEXT: vbic q0, q2, q0
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: subs r1, r0, r2 ; CHECK-NEXT: subs r3, r0, r2
; CHECK-NEXT: asr.w r12, r0, #31 ; CHECK-NEXT: asr.w r1, r0, #31
; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31 ; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: sbcs.w r1, r1, r2, asr #31
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: csetm lr, ne ; CHECK-NEXT: csetm lr, ne
; CHECK-NEXT: subs r1, r2, r3
; CHECK-NEXT: asr.w r12, r2, #31 ; CHECK-NEXT: asr.w r12, r2, #31
; CHECK-NEXT: subs r4, r2, r1 ; CHECK-NEXT: sbcs.w r1, r12, r3, asr #31
; CHECK-NEXT: sbcs.w r1, r12, r1, asr #31 ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: it lt ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov q3[2], q3[0], r1, lr ; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vmov q3[3], q3[1], r1, lr ; CHECK-NEXT: vmov q3[3], q3[1], r1, lr
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q4[2], q4[0], r1, r0 ; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
; CHECK-NEXT: vmov q4[3], q4[1], r1, r0 ; CHECK-NEXT: vmov q4[3], q4[1], r1, r0
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: vand q1, q1, q4 ; CHECK-NEXT: vand q1, q1, q4
; CHECK-NEXT: vand q1, q3, q1 ; CHECK-NEXT: vand q1, q3, q1
; CHECK-NEXT: vbic q0, q0, q1 ; CHECK-NEXT: vbic q0, q0, q1
; CHECK-NEXT: vand q1, q2, q1 ; CHECK-NEXT: vand q1, q2, q1
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
%a4 = icmp eq <2 x i64> %a, zeroinitializer %a4 = icmp eq <2 x i64> %a, zeroinitializer
%a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c %a5 = select <2 x i1> %a4, <2 x i32> zeroinitializer, <2 x i32> %c
%a6 = icmp ne <2 x i32> %b, zeroinitializer %a6 = icmp ne <2 x i32> %b, zeroinitializer
%a7 = icmp slt <2 x i32> %a5, %c %a7 = icmp slt <2 x i32> %a5, %c
%a8 = icmp ne <2 x i32> %a5, zeroinitializer %a8 = icmp ne <2 x i32> %a5, zeroinitializer
%a9 = and <2 x i1> %a6, %a8 %a9 = and <2 x i1> %a6, %a8
%a10 = and <2 x i1> %a7, %a9 %a10 = and <2 x i1> %a7, %a9
%a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5 %a11 = select <2 x i1> %a10, <2 x i32> %c, <2 x i32> %a5
ret <2 x i32> %a11 ret <2 x i32> %a11
} }

llvm/test/CodeGen/Thumb2/mve-vctp.ll

Show First 20 Lines • Show All 172 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <2 x i64> @vcmp_ult_v2i64(i64 %n, <2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @vcmp_ult_v2i64(i64 %n, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: vcmp_ult_v2i64: ; CHECK-LABEL: vcmp_ult_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: rsbs.w r3, r0, #1 ; CHECK-NEXT: rsbs.w r3, r0, #1
; CHECK-NEXT: mov.w r2, #0 ; CHECK-NEXT: mov.w r2, #0
; CHECK-NEXT: sbcs.w r3, r2, r1 ; CHECK-NEXT: sbcs.w r3, r2, r1
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csetm r3, ne ; CHECK-NEXT: csetm r3, ne
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: sbcs.w r0, r2, r1 ; CHECK-NEXT: sbcs.w r0, r2, r1
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: movlo r2, #1 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q2[2], q2[0], r0, r3 ; CHECK-NEXT: vmov q2[2], q2[0], r0, r3
; CHECK-NEXT: vmov q2[3], q2[1], r0, r3 ; CHECK-NEXT: vmov q2[3], q2[1], r0, r3
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%i = insertelement <2 x i64> undef, i64 %n, i32 0 %i = insertelement <2 x i64> undef, i64 %n, i32 0
%ns = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer %ns = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer
%c = icmp ult <2 x i64> <i64 0, i64 1>, %ns %c = icmp ult <2 x i64> <i64 0, i64 1>, %ns
%s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }
define arm_aapcs_vfpcc <2 x i64> @vcmp_uge_v2i64(i64 %n, <2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @vcmp_uge_v2i64(i64 %n, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: vcmp_uge_v2i64: ; CHECK-LABEL: vcmp_uge_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: subs r0, #1 ; CHECK-NEXT: subs r0, #1
; CHECK-NEXT: mov.w r2, #0
; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: it hs
; CHECK-NEXT: movhs r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: vldr s8, .LCPI11_0 ; CHECK-NEXT: vldr s8, .LCPI11_0
; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: cset r0, hs
; CHECK-NEXT: vmov.f32 s9, s8
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov s10, r0 ; CHECK-NEXT: vmov s10, r0
; CHECK-NEXT: vmov.f32 s9, s8
; CHECK-NEXT: vmov.f32 s11, s10 ; CHECK-NEXT: vmov.f32 s11, s10
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI11_0: ; CHECK-NEXT: .LCPI11_0:
Show All 13 Lines

llvm/test/CodeGen/Thumb2/mve-vmaxv-vminv-scalar.ll

Show First 20 Lines • Show All 487 Lines • ▼ Show 20 Lines; CHECK-NEXT: bx lr
%mt = trunc i32 %max to i16 %mt = trunc i32 %max to i16
%1 = select i1 %cmp, i16 %mt, i16 %x %1 = select i1 %cmp, i16 %mt, i16 %x
ret i16 %1 ret i16 %1
} }
define arm_aapcs_vfpcc i64 @uminv2i64(<2 x i64> %vec, i64 %min) { define arm_aapcs_vfpcc i64 @uminv2i64(<2 x i64> %vec, i64 %min) {
; CHECK-LABEL: uminv2i64: ; CHECK-LABEL: uminv2i64:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: vmov r2, r12, d1 ; CHECK-NEXT: vmov r2, r12, d1
; CHECK-NEXT: vmov r3, lr, d0 ; CHECK-NEXT: vmov r3, lr, d0
; CHECK-NEXT: cmp r3, r2 ; CHECK-NEXT: cmp r3, r2
; CHECK-NEXT: csel r4, r3, r2, lo ; CHECK-NEXT: csel r4, r3, r2, lo
; CHECK-NEXT: cmp lr, r12 ; CHECK-NEXT: cmp lr, r12
; CHECK-NEXT: csel r2, r3, r2, lo ; CHECK-NEXT: csel r2, r3, r2, lo
; CHECK-NEXT: csel r3, lr, r12, lo ; CHECK-NEXT: csel r3, lr, r12, lo
; CHECK-NEXT: csel r5, r4, r2, eq ; CHECK-NEXT: csel r2, r4, r2, eq
; CHECK-NEXT: movs r4, #0 ; CHECK-NEXT: subs r4, r2, r0
; CHECK-NEXT: subs r2, r5, r0 ; CHECK-NEXT: sbcs.w r4, r3, r1
; CHECK-NEXT: sbcs.w r2, r3, r1 ; CHECK-NEXT: cset r4, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r4, #1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r0, r5, r0, ne ; CHECK-NEXT: csel r0, r2, r0, ne
; CHECK-NEXT: csel r1, r3, r1, ne ; CHECK-NEXT: csel r1, r3, r1, ne
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, pc}
%x = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %vec) %x = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %vec)
%cmp = icmp ult i64 %x, %min %cmp = icmp ult i64 %x, %min
%1 = select i1 %cmp, i64 %x, i64 %min %1 = select i1 %cmp, i64 %x, i64 %min
ret i64 %1 ret i64 %1
} }
define arm_aapcs_vfpcc i64 @sminv2i64(<2 x i64> %vec, i64 %min) { define arm_aapcs_vfpcc i64 @sminv2i64(<2 x i64> %vec, i64 %min) {
; CHECK-LABEL: sminv2i64: ; CHECK-LABEL: sminv2i64:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: vmov r2, r12, d1 ; CHECK-NEXT: vmov r2, r12, d1
; CHECK-NEXT: vmov r3, lr, d0 ; CHECK-NEXT: vmov r3, lr, d0
; CHECK-NEXT: cmp r3, r2 ; CHECK-NEXT: cmp r3, r2
; CHECK-NEXT: csel r4, r3, r2, lo ; CHECK-NEXT: csel r4, r3, r2, lo
; CHECK-NEXT: cmp lr, r12 ; CHECK-NEXT: cmp lr, r12
; CHECK-NEXT: csel r2, r3, r2, lt ; CHECK-NEXT: csel r2, r3, r2, lt
; CHECK-NEXT: csel r3, lr, r12, lt ; CHECK-NEXT: csel r3, lr, r12, lt
; CHECK-NEXT: csel r5, r4, r2, eq ; CHECK-NEXT: csel r2, r4, r2, eq
; CHECK-NEXT: movs r4, #0 ; CHECK-NEXT: subs r4, r2, r0
; CHECK-NEXT: subs r2, r5, r0 ; CHECK-NEXT: sbcs.w r4, r3, r1
; CHECK-NEXT: sbcs.w r2, r3, r1 ; CHECK-NEXT: cset r4, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r4, #1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r0, r5, r0, ne ; CHECK-NEXT: csel r0, r2, r0, ne
; CHECK-NEXT: csel r1, r3, r1, ne ; CHECK-NEXT: csel r1, r3, r1, ne
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, pc}
%x = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %vec) %x = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %vec)
%cmp = icmp slt i64 %x, %min %cmp = icmp slt i64 %x, %min
%1 = select i1 %cmp, i64 %x, i64 %min %1 = select i1 %cmp, i64 %x, i64 %min
ret i64 %1 ret i64 %1
} }
define arm_aapcs_vfpcc i64 @umaxv2i64(<2 x i64> %vec, i64 %max) { define arm_aapcs_vfpcc i64 @umaxv2i64(<2 x i64> %vec, i64 %max) {
; CHECK-LABEL: umaxv2i64: ; CHECK-LABEL: umaxv2i64:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: vmov r2, r12, d1 ; CHECK-NEXT: vmov r2, r12, d1
; CHECK-NEXT: vmov r3, lr, d0 ; CHECK-NEXT: vmov r3, lr, d0
; CHECK-NEXT: cmp r3, r2 ; CHECK-NEXT: cmp r3, r2
; CHECK-NEXT: csel r4, r3, r2, hi ; CHECK-NEXT: csel r4, r3, r2, hi
; CHECK-NEXT: cmp lr, r12 ; CHECK-NEXT: cmp lr, r12
; CHECK-NEXT: csel r2, r3, r2, hi ; CHECK-NEXT: csel r2, r3, r2, hi
; CHECK-NEXT: csel r3, lr, r12, hi ; CHECK-NEXT: csel r3, lr, r12, hi
; CHECK-NEXT: csel r5, r4, r2, eq ; CHECK-NEXT: csel r2, r4, r2, eq
; CHECK-NEXT: movs r4, #0 ; CHECK-NEXT: subs r4, r0, r2
; CHECK-NEXT: subs r2, r0, r5 ; CHECK-NEXT: sbcs.w r4, r1, r3
; CHECK-NEXT: sbcs.w r2, r1, r3 ; CHECK-NEXT: cset r4, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r4, #1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r0, r5, r0, ne ; CHECK-NEXT: csel r0, r2, r0, ne
; CHECK-NEXT: csel r1, r3, r1, ne ; CHECK-NEXT: csel r1, r3, r1, ne
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, pc}
%x = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %vec) %x = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %vec)
%cmp = icmp ugt i64 %x, %max %cmp = icmp ugt i64 %x, %max
%1 = select i1 %cmp, i64 %x, i64 %max %1 = select i1 %cmp, i64 %x, i64 %max
ret i64 %1 ret i64 %1
} }
define arm_aapcs_vfpcc i64 @smaxv2i64(<2 x i64> %vec, i64 %max) { define arm_aapcs_vfpcc i64 @smaxv2i64(<2 x i64> %vec, i64 %max) {
; CHECK-LABEL: smaxv2i64: ; CHECK-LABEL: smaxv2i64:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: vmov r2, r12, d1 ; CHECK-NEXT: vmov r2, r12, d1
; CHECK-NEXT: vmov r3, lr, d0 ; CHECK-NEXT: vmov r3, lr, d0
; CHECK-NEXT: cmp r3, r2 ; CHECK-NEXT: cmp r3, r2
; CHECK-NEXT: csel r4, r3, r2, hi ; CHECK-NEXT: csel r4, r3, r2, hi
; CHECK-NEXT: cmp lr, r12 ; CHECK-NEXT: cmp lr, r12
; CHECK-NEXT: csel r2, r3, r2, gt ; CHECK-NEXT: csel r2, r3, r2, gt
; CHECK-NEXT: csel r3, lr, r12, gt ; CHECK-NEXT: csel r3, lr, r12, gt
; CHECK-NEXT: csel r5, r4, r2, eq ; CHECK-NEXT: csel r2, r4, r2, eq
; CHECK-NEXT: movs r4, #0 ; CHECK-NEXT: subs r4, r0, r2
; CHECK-NEXT: subs r2, r0, r5 ; CHECK-NEXT: sbcs.w r4, r1, r3
; CHECK-NEXT: sbcs.w r2, r1, r3 ; CHECK-NEXT: cset r4, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r4, #1
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: csel r0, r5, r0, ne ; CHECK-NEXT: csel r0, r2, r0, ne
; CHECK-NEXT: csel r1, r3, r1, ne ; CHECK-NEXT: csel r1, r3, r1, ne
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, pc}
%x = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %vec) %x = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %vec)
%cmp = icmp sgt i64 %x, %max %cmp = icmp sgt i64 %x, %max
%1 = select i1 %cmp, i64 %x, i64 %max %1 = select i1 %cmp, i64 %x, i64 %max
ret i64 %1 ret i64 %1
} }
declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>) declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
Show All 29 Lines

llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll

Show First 20 Lines • Show All 507 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: mov r8, r3 ; CHECK-NEXT: mov r8, r3
; CHECK-NEXT: mov r5, r2 ; CHECK-NEXT: mov r5, r2
; CHECK-NEXT: bl __fixdfti ; CHECK-NEXT: bl __fixdfti
; CHECK-NEXT: subs r7, r2, #1 ; CHECK-NEXT: subs r7, r2, #1
; CHECK-NEXT: mov.w r9, #1 ; CHECK-NEXT: mov.w r9, #1
; CHECK-NEXT: sbcs r7, r3, #0 ; CHECK-NEXT: sbcs r7, r3, #0
; CHECK-NEXT: mov.w r4, #0 ; CHECK-NEXT: mov.w r4, #0
; CHECK-NEXT: mov.w r7, #0 ; CHECK-NEXT: cset r7, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r7, #1
; CHECK-NEXT: cmp r7, #0 ; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: csel r0, r0, r7, ne ; CHECK-NEXT: csel r0, r0, r7, ne
; CHECK-NEXT: csel r3, r3, r7, ne ; CHECK-NEXT: csel r3, r3, r7, ne
; CHECK-NEXT: csel r2, r2, r9, ne ; CHECK-NEXT: csel r2, r2, r9, ne
; CHECK-NEXT: csel r1, r1, r7, ne ; CHECK-NEXT: csel r1, r1, r7, ne
; CHECK-NEXT: rsbs r7, r0, #0 ; CHECK-NEXT: rsbs r7, r0, #0
; CHECK-NEXT: sbcs.w r7, r4, r1 ; CHECK-NEXT: sbcs.w r7, r4, r1
; CHECK-NEXT: sbcs.w r2, r4, r2 ; CHECK-NEXT: sbcs.w r2, r4, r2
; CHECK-NEXT: sbcs.w r2, r4, r3 ; CHECK-NEXT: sbcs.w r2, r4, r3
; CHECK-NEXT: mov.w r2, #0 ; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #1
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csel r6, r0, r2, ne ; CHECK-NEXT: csel r6, r0, r2, ne
; CHECK-NEXT: csel r7, r1, r2, ne ; CHECK-NEXT: csel r7, r1, r2, ne
; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: mov r1, r8 ; CHECK-NEXT: mov r1, r8
; CHECK-NEXT: bl __fixdfti ; CHECK-NEXT: bl __fixdfti
; CHECK-NEXT: subs r5, r2, #1 ; CHECK-NEXT: subs r5, r2, #1
; CHECK-NEXT: sbcs r5, r3, #0 ; CHECK-NEXT: sbcs r5, r3, #0
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r5, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r5, #1
; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csel r0, r0, r5, ne ; CHECK-NEXT: csel r0, r0, r5, ne
; CHECK-NEXT: csel r3, r3, r5, ne ; CHECK-NEXT: csel r3, r3, r5, ne
; CHECK-NEXT: csel r2, r2, r9, ne ; CHECK-NEXT: csel r2, r2, r9, ne
; CHECK-NEXT: csel r1, r1, r5, ne ; CHECK-NEXT: csel r1, r1, r5, ne
; CHECK-NEXT: rsbs r5, r0, #0 ; CHECK-NEXT: rsbs r5, r0, #0
; CHECK-NEXT: sbcs.w r5, r4, r1 ; CHECK-NEXT: sbcs.w r5, r4, r1
; CHECK-NEXT: sbcs.w r2, r4, r2 ; CHECK-NEXT: sbcs.w r2, r4, r2
; CHECK-NEXT: sbcs.w r2, r4, r3 ; CHECK-NEXT: sbcs.w r2, r4, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: movlt r4, #1 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: csel r2, r0, r3, ne
; CHECK-NEXT: csel r2, r0, r4, ne ; CHECK-NEXT: csel r3, r1, r3, ne
; CHECK-NEXT: csel r3, r1, r4, ne
; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r7 ; CHECK-NEXT: mov r1, r7
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc} ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
entry: entry:
%conv = fptosi <2 x double> %x to <2 x i128> %conv = fptosi <2 x double> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616> %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616> %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
Show All 9 Lines

llvm/test/CodeGen/Thumb2/mve-vqmovn.ll

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Linesentry:
%c2 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15> %c2 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
%s2 = select <16 x i1> %c2, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15> %s2 = select <16 x i1> %c2, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
ret <16 x i8> %s2 ret <16 x i8> %s2
} }
define arm_aapcs_vfpcc <2 x i64> @vqmovni64_smaxmin(<2 x i64> %s0) { define arm_aapcs_vfpcc <2 x i64> @vqmovni64_smaxmin(<2 x i64> %s0) {
; CHECK-LABEL: vqmovni64_smaxmin: ; CHECK-LABEL: vqmovni64_smaxmin:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r1, r2, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: mvn r12, #-2147483648 ; CHECK-NEXT: mvn r2, #-2147483648
; CHECK-NEXT: movs r0, #0 ; CHECK-NEXT: subs r0, r0, r2
; CHECK-NEXT: subs.w r1, r1, r12 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: sbcs r1, r2, #0 ; CHECK-NEXT: vmov r1, r3, d0
; CHECK-NEXT: vmov r2, r3, d0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: subs r1, r1, r2
; CHECK-NEXT: mov.w r2, #-1
; CHECK-NEXT: sbcs r1, r3, #0
; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs.w r2, r2, r12 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: mov.w r12, #-1 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: sbcs r2, r3, #0 ; CHECK-NEXT: adr r0, .LCPI12_0
; CHECK-NEXT: mov.w r2, #0 ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov q1[2], q1[0], r2, r1
; CHECK-NEXT: vmov q1[3], q1[1], r2, r1
; CHECK-NEXT: adr r1, .LCPI12_0
; CHECK-NEXT: vldrw.u32 q2, [r1]
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vbic q2, q2, q1 ; CHECK-NEXT: vbic q2, q2, q1
; CHECK-NEXT: vorr q0, q0, q2 ; CHECK-NEXT: vorr q0, q0, q2
; CHECK-NEXT: vmov r1, r2, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: rsbs.w r0, r0, #-2147483648
; CHECK-NEXT: sbcs.w r0, r2, r1
; CHECK-NEXT: vmov r1, r3, d0
; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs.w r1, r1, #-2147483648 ; CHECK-NEXT: rsbs.w r1, r1, #-2147483648
; CHECK-NEXT: sbcs.w r1, r12, r2 ; CHECK-NEXT: sbcs.w r1, r2, r3
; CHECK-NEXT: vmov r2, r3, d0 ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: rsbs.w r2, r2, #-2147483648 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: sbcs.w r2, r12, r3 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q1[2], q1[0], r0, r1
; CHECK-NEXT: vmov q1[3], q1[1], r0, r1
; CHECK-NEXT: adr r0, .LCPI12_1 ; CHECK-NEXT: adr r0, .LCPI12_1
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vbic q2, q2, q1 ; CHECK-NEXT: vbic q2, q2, q1
; CHECK-NEXT: vorr q0, q0, q2 ; CHECK-NEXT: vorr q0, q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
Show All 13 Linesentry:
%c2 = icmp sgt <2 x i64> %s1, <i64 -2147483648, i64 -2147483648> %c2 = icmp sgt <2 x i64> %s1, <i64 -2147483648, i64 -2147483648>
%s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 -2147483648, i64 -2147483648> %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 -2147483648, i64 -2147483648>
ret <2 x i64> %s2 ret <2 x i64> %s2
} }
define arm_aapcs_vfpcc <2 x i64> @vqmovni64_sminmax(<2 x i64> %s0) { define arm_aapcs_vfpcc <2 x i64> @vqmovni64_sminmax(<2 x i64> %s0) {
; CHECK-LABEL: vqmovni64_sminmax: ; CHECK-LABEL: vqmovni64_sminmax:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r1, r2, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: mov.w r12, #-1 ; CHECK-NEXT: mov.w r2, #-1
; CHECK-NEXT: movs r0, #0 ; CHECK-NEXT: rsbs.w r0, r0, #-2147483648
; CHECK-NEXT: sbcs.w r0, r2, r1
; CHECK-NEXT: vmov r1, r3, d0
; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs.w r1, r1, #-2147483648 ; CHECK-NEXT: rsbs.w r1, r1, #-2147483648
; CHECK-NEXT: sbcs.w r1, r12, r2 ; CHECK-NEXT: sbcs.w r1, r2, r3
; CHECK-NEXT: vmov r2, r3, d0 ; CHECK-NEXT: mvn r2, #-2147483648
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: rsbs.w r2, r2, #-2147483648 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: sbcs.w r2, r12, r3 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: mvn r12, #-2147483648 ; CHECK-NEXT: adr r0, .LCPI13_0
; CHECK-NEXT: mov.w r2, #0 ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov q1[2], q1[0], r2, r1
; CHECK-NEXT: vmov q1[3], q1[1], r2, r1
; CHECK-NEXT: adr r1, .LCPI13_0
; CHECK-NEXT: vldrw.u32 q2, [r1]
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vbic q2, q2, q1 ; CHECK-NEXT: vbic q2, q2, q1
; CHECK-NEXT: vorr q0, q0, q2 ; CHECK-NEXT: vorr q0, q0, q2
; CHECK-NEXT: vmov r1, r2, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: subs.w r1, r1, r12 ; CHECK-NEXT: subs r0, r0, r2
; CHECK-NEXT: sbcs r1, r2, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov r2, r3, d0 ; CHECK-NEXT: vmov r1, r3, d0
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs.w r2, r2, r12
; CHECK-NEXT: sbcs r2, r3, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q1[2], q1[0], r0, r1 ; CHECK-NEXT: subs r1, r1, r2
; CHECK-NEXT: vmov q1[3], q1[1], r0, r1 ; CHECK-NEXT: sbcs r1, r3, #0
; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: adr r0, .LCPI13_1 ; CHECK-NEXT: adr r0, .LCPI13_1
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vbic q2, q2, q1 ; CHECK-NEXT: vbic q2, q2, q1
; CHECK-NEXT: vorr q0, q0, q2 ; CHECK-NEXT: vorr q0, q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
Show All 14 Linesentry:
%s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 2147483647, i64 2147483647> %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 2147483647, i64 2147483647>
ret <2 x i64> %s2 ret <2 x i64> %s2
} }
define arm_aapcs_vfpcc <2 x i64> @vqmovni64_umaxmin(<2 x i64> %s0) { define arm_aapcs_vfpcc <2 x i64> @vqmovni64_umaxmin(<2 x i64> %s0) {
; CHECK-LABEL: vqmovni64_umaxmin: ; CHECK-LABEL: vqmovni64_umaxmin:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: vmov.i64 q2, #0xffffffff ; CHECK-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-NEXT: subs.w r0, r0, #-1 ; CHECK-NEXT: subs.w r0, r0, #-1
; CHECK-NEXT: sbcs r0, r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov r1, r3, d0 ; CHECK-NEXT: vmov r1, r2, d0
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs.w r1, r1, #-1 ; CHECK-NEXT: subs.w r1, r1, #-1
; CHECK-NEXT: sbcs r1, r3, #0 ; CHECK-NEXT: sbcs r1, r2, #0
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r1, lo
; CHECK-NEXT: movlo r2, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: vbic q2, q2, q1 ; CHECK-NEXT: vbic q2, q2, q1
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vorr q0, q0, q2 ; CHECK-NEXT: vorr q0, q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c1 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295> %c1 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295> %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
ret <2 x i64> %s1 ret <2 x i64> %s1
} }
define arm_aapcs_vfpcc <2 x i64> @vqmovni64_uminmax(<2 x i64> %s0) { define arm_aapcs_vfpcc <2 x i64> @vqmovni64_uminmax(<2 x i64> %s0) {
; CHECK-LABEL: vqmovni64_uminmax: ; CHECK-LABEL: vqmovni64_uminmax:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: vmov.i64 q2, #0xffffffff ; CHECK-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-NEXT: subs.w r0, r0, #-1 ; CHECK-NEXT: subs.w r0, r0, #-1
; CHECK-NEXT: sbcs r0, r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov r1, r3, d0 ; CHECK-NEXT: vmov r1, r2, d0
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs.w r1, r1, #-1 ; CHECK-NEXT: subs.w r1, r1, #-1
; CHECK-NEXT: sbcs r1, r3, #0 ; CHECK-NEXT: sbcs r1, r2, #0
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r1, lo
; CHECK-NEXT: movlo r2, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: vbic q2, q2, q1 ; CHECK-NEXT: vbic q2, q2, q1
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vorr q0, q0, q2 ; CHECK-NEXT: vorr q0, q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c2 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295> %c2 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>
%s2 = select <2 x i1> %c2, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295> %s2 = select <2 x i1> %c2, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
ret <2 x i64> %s2 ret <2 x i64> %s2
} }

llvm/test/CodeGen/Thumb2/mve-vqshrn.ll

Show First 20 Lines • Show All 174 Lines • ▼ Show 20 Linesentry:
%c2 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15> %c2 = icmp ult <16 x i8> %s0, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
%s2 = select <16 x i1> %c2, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15> %s2 = select <16 x i1> %c2, <16 x i8> %s0, <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>
ret <16 x i8> %s2 ret <16 x i8> %s2
} }
define arm_aapcs_vfpcc <2 x i64> @vqshrni64_smaxmin(<2 x i64> %so) { define arm_aapcs_vfpcc <2 x i64> @vqshrni64_smaxmin(<2 x i64> %so) {
; CHECK-LABEL: vqshrni64_smaxmin: ; CHECK-LABEL: vqshrni64_smaxmin:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr} ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: mvn r12, #-2147483648
; CHECK-NEXT: vmov r2, r3, d1 ; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: mvn lr, #-2147483648
; CHECK-NEXT: vmov r0, r1, d0
; CHECK-NEXT: asrl r2, r3, #3
; CHECK-NEXT: asrl r0, r1, #3 ; CHECK-NEXT: asrl r0, r1, #3
; CHECK-NEXT: mov.w r12, #0 ; CHECK-NEXT: asrl r2, r3, #3
; CHECK-NEXT: vmov q0[2], q0[0], r0, r2 ; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
; CHECK-NEXT: subs.w r2, r2, lr ; CHECK-NEXT: subs.w r0, r0, r12
; CHECK-NEXT: sbcs r2, r3, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r3
; CHECK-NEXT: mov.w r2, #0
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: subs.w r0, r0, lr
; CHECK-NEXT: sbcs r0, r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: vmov q0[3], q0[1], r3, r1
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov q1[2], q1[0], r0, r2 ; CHECK-NEXT: subs.w r1, r2, r12
; CHECK-NEXT: vmov q1[3], q1[1], r0, r2 ; CHECK-NEXT: sbcs r1, r3, #0
; CHECK-NEXT: mov.w r2, #-1
; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: adr r0, .LCPI12_0 ; CHECK-NEXT: adr r0, .LCPI12_0
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: mov.w r2, #-1
; CHECK-NEXT: vbic q1, q2, q1 ; CHECK-NEXT: vbic q1, q2, q1
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: rsbs.w r0, r0, #-2147483648 ; CHECK-NEXT: rsbs.w r0, r0, #-2147483648
; CHECK-NEXT: sbcs.w r0, r2, r1 ; CHECK-NEXT: sbcs.w r0, r2, r1
; CHECK-NEXT: vmov r1, r3, d0 ; CHECK-NEXT: vmov r1, r3, d0
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs.w r1, r1, #-2147483648 ; CHECK-NEXT: rsbs.w r1, r1, #-2147483648
; CHECK-NEXT: sbcs.w r1, r2, r3 ; CHECK-NEXT: sbcs.w r1, r2, r3
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt.w r12, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: adr r0, .LCPI12_1 ; CHECK-NEXT: adr r0, .LCPI12_1
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vbic q2, q2, q1 ; CHECK-NEXT: vbic q2, q2, q1
; CHECK-NEXT: vorr q0, q0, q2 ; CHECK-NEXT: vorr q0, q0, q2
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI12_0: ; CHECK-NEXT: .LCPI12_0:
; CHECK-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
; CHECK-NEXT: .long 0 @ 0x0 ; CHECK-NEXT: .long 0 @ 0x0
; CHECK-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
; CHECK-NEXT: .long 0 @ 0x0 ; CHECK-NEXT: .long 0 @ 0x0
; CHECK-NEXT: .LCPI12_1: ; CHECK-NEXT: .LCPI12_1:
; CHECK-NEXT: .long 2147483648 @ 0x80000000 ; CHECK-NEXT: .long 2147483648 @ 0x80000000
; CHECK-NEXT: .long 4294967295 @ 0xffffffff ; CHECK-NEXT: .long 4294967295 @ 0xffffffff
; CHECK-NEXT: .long 2147483648 @ 0x80000000 ; CHECK-NEXT: .long 2147483648 @ 0x80000000
; CHECK-NEXT: .long 4294967295 @ 0xffffffff ; CHECK-NEXT: .long 4294967295 @ 0xffffffff
entry: entry:
%s0 = ashr <2 x i64> %so, <i64 3, i64 3> %s0 = ashr <2 x i64> %so, <i64 3, i64 3>
%c1 = icmp slt <2 x i64> %s0, <i64 2147483647, i64 2147483647> %c1 = icmp slt <2 x i64> %s0, <i64 2147483647, i64 2147483647>
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 2147483647, i64 2147483647> %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 2147483647, i64 2147483647>
%c2 = icmp sgt <2 x i64> %s1, <i64 -2147483648, i64 -2147483648> %c2 = icmp sgt <2 x i64> %s1, <i64 -2147483648, i64 -2147483648>
%s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 -2147483648, i64 -2147483648> %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 -2147483648, i64 -2147483648>
ret <2 x i64> %s2 ret <2 x i64> %s2
} }
define arm_aapcs_vfpcc <2 x i64> @vqshrni64_sminmax(<2 x i64> %so) { define arm_aapcs_vfpcc <2 x i64> @vqshrni64_sminmax(<2 x i64> %so) {
; CHECK-LABEL: vqshrni64_sminmax: ; CHECK-LABEL: vqshrni64_sminmax:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: vmov r2, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: mov.w r12, #-1 ; CHECK-NEXT: mov.w r12, #-1
; CHECK-NEXT: asrl r2, r1, #3 ; CHECK-NEXT: asrl r0, r1, #3
; CHECK-NEXT: mov.w lr, #0 ; CHECK-NEXT: rsbs.w r3, r0, #-2147483648
; CHECK-NEXT: rsbs.w r3, r2, #-2147483648
; CHECK-NEXT: sbcs.w r3, r12, r1 ; CHECK-NEXT: sbcs.w r3, r12, r1
; CHECK-NEXT: mov.w r3, #0 ; CHECK-NEXT: cset r3, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: vmov r4, r3, d0 ; CHECK-NEXT: vmov r4, r3, d0
; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: asrl r4, r3, #3 ; CHECK-NEXT: asrl r4, r3, #3
; CHECK-NEXT: rsbs.w r5, r4, #-2147483648 ; CHECK-NEXT: csetm lr, ne
; CHECK-NEXT: vmov q2[2], q2[0], r4, r2 ; CHECK-NEXT: rsbs.w r2, r4, #-2147483648
; CHECK-NEXT: sbcs.w r5, r12, r3 ; CHECK-NEXT: vmov q2[2], q2[0], r4, r0
; CHECK-NEXT: sbcs.w r2, r12, r3
; CHECK-NEXT: vmov q2[3], q2[1], r3, r1 ; CHECK-NEXT: vmov q2[3], q2[1], r3, r1
; CHECK-NEXT: mov.w r5, #0 ; CHECK-NEXT: cset r2, lt
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov q0[2], q0[0], r2, lr
; CHECK-NEXT: vmov q0[3], q0[1], r2, lr
; CHECK-NEXT: adr r2, .LCPI13_0
; CHECK-NEXT: vldrw.u32 q1, [r2]
; CHECK-NEXT: mvn r2, #-2147483648 ; CHECK-NEXT: mvn r2, #-2147483648
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r5, #1
; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: csetm r5, ne
; CHECK-NEXT: vmov q0[2], q0[0], r5, r0
; CHECK-NEXT: vmov q0[3], q0[1], r5, r0
; CHECK-NEXT: adr r0, .LCPI13_0
; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vbic q1, q1, q0 ; CHECK-NEXT: vbic q1, q1, q0
; CHECK-NEXT: vand q0, q2, q0 ; CHECK-NEXT: vand q0, q2, q0
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: vmov r0, r1, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: subs r0, r0, r2 ; CHECK-NEXT: subs r0, r0, r2
; CHECK-NEXT: sbcs r0, r1, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov r1, r3, d0 ; CHECK-NEXT: vmov r1, r3, d0
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lt
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs r1, r1, r2 ; CHECK-NEXT: subs r1, r1, r2
; CHECK-NEXT: sbcs r1, r3, #0 ; CHECK-NEXT: sbcs r1, r3, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: cset r1, lt
; CHECK-NEXT: movlt.w lr, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp.w lr, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: adr r0, .LCPI13_1 ; CHECK-NEXT: adr r0, .LCPI13_1
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vbic q2, q2, q1 ; CHECK-NEXT: vbic q2, q2, q1
; CHECK-NEXT: vorr q0, q0, q2 ; CHECK-NEXT: vorr q0, q0, q2
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI13_0: ; CHECK-NEXT: .LCPI13_0:
; CHECK-NEXT: .long 2147483648 @ 0x80000000 ; CHECK-NEXT: .long 2147483648 @ 0x80000000
; CHECK-NEXT: .long 4294967295 @ 0xffffffff ; CHECK-NEXT: .long 4294967295 @ 0xffffffff
; CHECK-NEXT: .long 2147483648 @ 0x80000000 ; CHECK-NEXT: .long 2147483648 @ 0x80000000
; CHECK-NEXT: .long 4294967295 @ 0xffffffff ; CHECK-NEXT: .long 4294967295 @ 0xffffffff
; CHECK-NEXT: .LCPI13_1: ; CHECK-NEXT: .LCPI13_1:
; CHECK-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
; CHECK-NEXT: .long 0 @ 0x0 ; CHECK-NEXT: .long 0 @ 0x0
; CHECK-NEXT: .long 2147483647 @ 0x7fffffff ; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
; CHECK-NEXT: .long 0 @ 0x0 ; CHECK-NEXT: .long 0 @ 0x0
entry: entry:
%s0 = ashr <2 x i64> %so, <i64 3, i64 3> %s0 = ashr <2 x i64> %so, <i64 3, i64 3>
%c1 = icmp sgt <2 x i64> %s0, <i64 -2147483648, i64 -2147483648> %c1 = icmp sgt <2 x i64> %s0, <i64 -2147483648, i64 -2147483648>
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 -2147483648, i64 -2147483648> %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 -2147483648, i64 -2147483648>
%c2 = icmp slt <2 x i64> %s1, <i64 2147483647, i64 2147483647> %c2 = icmp slt <2 x i64> %s1, <i64 2147483647, i64 2147483647>
%s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 2147483647, i64 2147483647> %s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 2147483647, i64 2147483647>
ret <2 x i64> %s2 ret <2 x i64> %s2
} }
define arm_aapcs_vfpcc <2 x i64> @vqshrni64_umaxmin(<2 x i64> %so) { define arm_aapcs_vfpcc <2 x i64> @vqshrni64_umaxmin(<2 x i64> %so) {
; CHECK-LABEL: vqshrni64_umaxmin: ; CHECK-LABEL: vqshrni64_umaxmin:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, r3, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: vmov r2, r1, d0
; CHECK-NEXT: lsrl r0, r3, #3
; CHECK-NEXT: lsrl r2, r1, #3
; CHECK-NEXT: vmov.i64 q2, #0xffffffff ; CHECK-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: lsrl r0, r1, #3
; CHECK-NEXT: lsrl r2, r3, #3
; CHECK-NEXT: vmov q0[2], q0[0], r2, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
; CHECK-NEXT: subs.w r0, r0, #-1 ; CHECK-NEXT: subs.w r0, r0, #-1
; CHECK-NEXT: sbcs r0, r3, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r3 ; CHECK-NEXT: vmov q0[3], q0[1], r3, r1
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs.w r2, r2, #-1 ; CHECK-NEXT: subs.w r1, r2, #-1
; CHECK-NEXT: sbcs r1, r1, #0 ; CHECK-NEXT: sbcs r1, r3, #0
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r1, lo
; CHECK-NEXT: movlo.w r12, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vbic q1, q2, q1 ; CHECK-NEXT: vbic q1, q2, q1
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0 = lshr <2 x i64> %so, <i64 3, i64 3> %s0 = lshr <2 x i64> %so, <i64 3, i64 3>
%c1 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295> %c1 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>
%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295> %s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
ret <2 x i64> %s1 ret <2 x i64> %s1
} }
define arm_aapcs_vfpcc <2 x i64> @vqshrni64_uminmax(<2 x i64> %so) { define arm_aapcs_vfpcc <2 x i64> @vqshrni64_uminmax(<2 x i64> %so) {
; CHECK-LABEL: vqshrni64_uminmax: ; CHECK-LABEL: vqshrni64_uminmax:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, r3, d1 ; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: vmov r2, r1, d0
; CHECK-NEXT: lsrl r0, r3, #3
; CHECK-NEXT: lsrl r2, r1, #3
; CHECK-NEXT: vmov.i64 q2, #0xffffffff ; CHECK-NEXT: vmov.i64 q2, #0xffffffff
; CHECK-NEXT: vmov r2, r3, d0
; CHECK-NEXT: lsrl r0, r1, #3
; CHECK-NEXT: lsrl r2, r3, #3
; CHECK-NEXT: vmov q0[2], q0[0], r2, r0 ; CHECK-NEXT: vmov q0[2], q0[0], r2, r0
; CHECK-NEXT: subs.w r0, r0, #-1 ; CHECK-NEXT: subs.w r0, r0, #-1
; CHECK-NEXT: sbcs r0, r3, #0 ; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov q0[3], q0[1], r1, r3 ; CHECK-NEXT: vmov q0[3], q0[1], r3, r1
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csetm r0, ne ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: subs.w r2, r2, #-1 ; CHECK-NEXT: subs.w r1, r2, #-1
; CHECK-NEXT: sbcs r1, r1, #0 ; CHECK-NEXT: sbcs r1, r3, #0
; CHECK-NEXT: it lo ; CHECK-NEXT: cset r1, lo
; CHECK-NEXT: movlo.w r12, #1 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csetm r1, ne ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0 ; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0 ; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: vbic q1, q2, q1 ; CHECK-NEXT: vbic q1, q2, q1
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0 = lshr <2 x i64> %so, <i64 3, i64 3> %s0 = lshr <2 x i64> %so, <i64 3, i64 3>
%c2 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295> %c2 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>
%s2 = select <2 x i1> %c2, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295> %s2 = select <2 x i1> %c2, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
ret <2 x i64> %s2 ret <2 x i64> %s2
} }