AArch64: don't claim to preserve registers used by the prologue for `cxx_fast_tlscc`

[t.p.northover]

Summary

When realigning the stack or needing a base pointer, the prologue code can use x19 and x9. For cxx_fast_tlscc we also defer saving registers to COPY instructions instead of the normal prologue save sequence, so these registers get clobbered before they're saved in the main body.

Easiest fix seems to be to remove these registers from the CSR list for this convention (there's already some there for both this reason and possible interprocedural uses).

[Gerolf]

LGTM.

[t.p.northover]

Thanks. Committed as 581e85.

llvm/lib/Target/AArch64/AArch64CallingConvention.td

: CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17),
                            (sequence "Q%u", 0, 31))>;
 
 // We can only handle a register pair with adjacent registers, the register pair
 // should belong to the same class as well. Since the access function on the
 // fast path calls a function that follows CSR_Darwin_AArch64_TLS,
 // CSR_Darwin_AArch64_CXX_TLS should be a subset of CSR_Darwin_AArch64_TLS.
 def CSR_Darwin_AArch64_CXX_TLS
     : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS,
-                           (sub (sequence "X%u", 1, 28), X15, X16, X17, X18),
+                           (sub (sequence "X%u", 1, 28), X9, X15, X16, X17, X18, X19),
                            (sequence "D%u", 0, 31))>;
 
 // CSRs that are handled by prologue, epilogue.
 def CSR_Darwin_AArch64_CXX_TLS_PE
     : CalleeSavedRegs<(add LR, FP)>;
 
 // CSRs that are handled explicitly via copies.
 def CSR_Darwin_AArch64_CXX_TLS_ViaCopy

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

static void computeCalleeSaveRegisterPairs(
   bool NeedsWinCFI = needsWinCFI(MF);
   AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   CallingConv::ID CC = MF.getFunction().getCallingConv();
   unsigned Count = CSI.size();
   (void)CC;
   // MachO's compact unwind format relies on all registers being stored in
   // pairs.
   assert((!produceCompactUnwindFrame(MF) ||
-          CC == CallingConv::PreserveMost ||
+          CC == CallingConv::PreserveMost || CC == CallingConv::CXX_FAST_TLS ||
           (Count & 1) == 0) &&
          "Odd number of callee-saved regs to spill!");
   int ByteOffset = AFI->getCalleeSavedStackSize();
   int StackFillDir = -1;
   int RegInc = 1;
   unsigned FirstReg = 0;
   if (NeedsWinCFI) {
     // For WinCFI, fill the stack from the bottom up.
for (unsigned i = FirstReg; i < Count; i += RegInc) {
 
     // Windows AAPCS has FP and LR reversed.
     assert((!RPI.isPaired() || !NeedsFrameRecord || RPI.Reg1 != AArch64::FP ||
             RPI.Reg2 == AArch64::LR) &&
            "FrameRecord must be allocated together with LR");
 
     // MachO's compact unwind format relies on all registers being stored in
     // adjacent register pairs.
     assert((!produceCompactUnwindFrame(MF) ||
-            CC == CallingConv::PreserveMost ||
+            CC == CallingConv::PreserveMost || CC == CallingConv::CXX_FAST_TLS ||
             (RPI.isPaired() &&
              ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) ||
               RPI.Reg1 + 1 == RPI.Reg2))) &&
            "Callee-save registers not saved as adjacent register pair!");
 
     RPI.FrameIdx = CSI[i].getFrameIdx();
     if (NeedsWinCFI &&
         RPI.isPaired()) // RPI.FrameIdx must be the lower index of the pair

llvm/test/CodeGen/AArch64/cxx-tlscc.ll

 ; CHECK-O0: stp d23, d22
 ; CHECK-O0: stp d21, d20
 ; CHECK-O0: stp d19, d18
 ; CHECK-O0: stp d17, d16
 ; CHECK-O0: stp d7, d6
 ; CHECK-O0: stp d5, d4
 ; CHECK-O0: stp d3, d2
 ; CHECK-O0: stp d1, d0
-; CHECK-O0: stp x14, x13
-; CHECK-O0: stp x12, x11
-; CHECK-O0: stp x10, x9
+; CHECK-O0: str x14
+; CHECK-O0: stp x13, x12
+; CHECK-O0: stp x11, x10
 ; CHECK-O0: stp x8, x7
 ; CHECK-O0: stp x6, x5
 ; CHECK-O0: stp x4, x3
 ; CHECK-O0: stp x2, x1
 ; CHECK-O0: blr
 ; CHECK-O0: tbnz w{{.*}}, #0, [[BB_end:.?LBB0_[0-9]+]]
 ; CHECK-O0: blr
 ; CHECK-O0: tlv_atexit
 ; CHECK-O0: [[BB_end]]:
 ; CHECK-O0: blr
 ; CHECK-O0: ldp x2, x1
 ; CHECK-O0: ldp x4, x3
 ; CHECK-O0: ldp x6, x5
 ; CHECK-O0: ldp x8, x7
-; CHECK-O0: ldp x10, x9
-; CHECK-O0: ldp x12, x11
-; CHECK-O0: ldp x14, x13
+; CHECK-O0: ldp x11, x10
+; CHECK-O0: ldp x13, x12
+; CHECK-O0: ldr x14
 ; CHECK-O0: ldp d1, d0
 ; CHECK-O0: ldp d3, d2
 ; CHECK-O0: ldp d5, d4
 ; CHECK-O0: ldp d7, d6
 ; CHECK-O0: ldp d17, d16
 ; CHECK-O0: ldp d19, d18
 ; CHECK-O0: ldp d21, d20
 ; CHECK-O0: ldp d23, d22

 ; CHECK: bl __tlv_atexit
 define cxx_fast_tlscc void @__tls_test() {
 entry:
   store i32 0, i32* getelementptr inbounds (%class.C, %class.C* @tC, i64 0, i32 0), align 4
   %0 = tail call i32 @_tlv_atexit(void (i8*)* bitcast (%class.C* (%class.C*)* @_ZN1CD1Ev to void (i8*)*), i8* bitcast (%class.C* @tC to i8*), i8* nonnull @__dso_handle) #1
   ret void
 }
 
+define cxx_fast_tlscc void @weird_prologue_regs(i32 %n) #1 {
+; CHECK-LABEL: weird_prologue_regs:
+; CHECK-NOT: str x9
+; CHECK-NOT: stp{{.*}}x9{{.*}}[
+; CHECK-NOT: str x19
+; CHECK-NOT: stp{{.*}}x19{{.*}}[
+
+; CHECK: sub x9, sp, #
+; CHECK: and sp, x9, #0x
+; CHECK: mov x19, sp
+
+; CHECK-NOT: str x9
+; CHECK-NOT: stp{{.*}}x9{{.*}}[
+; CHECK-NOT: str x19
+; CHECK-NOT: stp{{.*}}x19{{.*}}[
+
+  %p0 = alloca i32, i32 200
+  %p1 = alloca i32, align 32
+  %p2 = alloca i32, i32 %n
+  call void @callee(i32* %p0)
+  call void @callee(i32* %p1)
+  call void @callee(i32* %p2)
+  ret void
+}
+declare void @callee(i32*)
+
 attributes #0 = { nounwind "frame-pointer"="all" }
 attributes #1 = { nounwind }