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Differential D113679

[AMDGPU] Simplify 64-bit division/remainder expansion
ClosedPublic

Authored by foad on Nov 11 2021, 7:36 AM.

Details

Reviewers
arsenm
rampitec
b-sumner
Commits
rGa70bbb5f7af0: [AMDGPU] Simplify 64-bit division/remainder expansion
Summary

The old expansion open-coded a 64-bit addition in a strange way, by
adding the high parts *without* carry-in from the low part, and then
adding the carry back in later on. Fixing this saves a couple of
instructions and makes the code much easier to understand.

Diff Detail

Unit TestsFailed

TimeTest
990 msx64 debian > LLVM.CodeGen/AMDGPU::wave32.ll

Event Timeline

foad created this revision.Nov 11 2021, 7:36 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 7 others. · View Herald TranscriptNov 11 2021, 7:36 AM
foad requested review of this revision.Nov 11 2021, 7:36 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 11 2021, 7:36 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
foad added reviewers: arsenm, rampitec, b-sumner.Nov 11 2021, 7:59 AM
foad added inline comments.
llvm/test/CodeGen/AMDGPU/udiv64.ll
257–258

This is probably the clearest place to see the effect of the patch. Here, in the old code, we save the carry-out from one add into s[4:5] in order to use it again 20-odd instructions later...

279–280

.. and here we recompute v5+v9 but without carry-in from the corresponding low part addition v4+v8, but in the very next instruction we add back in the missing carry!

arsenm accepted this revision.Nov 11 2021, 8:04 AM
This revision is now accepted and ready to land.Nov 11 2021, 8:04 AM
Harbormaster completed remote builds in B133721: Diff 386513.Nov 11 2021, 8:23 AM
This revision was landed with ongoing or failed builds.Nov 12 2021, 7:51 AM
Closed by commit rGa70bbb5f7af0: [AMDGPU] Simplify 64-bit division/remainder expansion (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rGa70bbb5f7af0: [AMDGPU] Simplify 64-bit division/remainder expansion.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
23 lines
5 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
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Diff 386513

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 1,833 Lines • ▼ Show 20 Lines if (DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), Zero}); SDValue REM = DAG.getBuildVector(MVT::v2i32, DL, {Res.getValue(1), Zero});
Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV)); Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));
Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM)); Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));
return; return;
} }
if (isTypeLegal(MVT::i64)) { if (isTypeLegal(MVT::i64)) {
// The algorithm here is based on ideas from "Software Integer Division",
// Tom Rodeheffer, August 2008.
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
// Compute denominator reciprocal. // Compute denominator reciprocal.
unsigned FMAD = !Subtarget->hasMadMacF32Insts() ? unsigned FMAD = !Subtarget->hasMadMacF32Insts() ?
(unsigned)ISD::FMA : (unsigned)ISD::FMA :
!MFI->getMode().allFP32Denormals() ? !MFI->getMode().allFP32Denormals() ?
(unsigned)ISD::FMAD : (unsigned)ISD::FMAD :
Show All 18 Lines if (isTypeLegal(MVT::i64)) {
SDValue Rcp64 = DAG.getBitcast(VT, SDValue Rcp64 = DAG.getBitcast(VT,
DAG.getBuildVector(MVT::v2i32, DL, {Rcp_Lo, Rcp_Hi})); DAG.getBuildVector(MVT::v2i32, DL, {Rcp_Lo, Rcp_Hi}));
SDValue Zero64 = DAG.getConstant(0, DL, VT); SDValue Zero64 = DAG.getConstant(0, DL, VT);
SDValue One64 = DAG.getConstant(1, DL, VT); SDValue One64 = DAG.getConstant(1, DL, VT);
SDValue Zero1 = DAG.getConstant(0, DL, MVT::i1); SDValue Zero1 = DAG.getConstant(0, DL, MVT::i1);
SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1); SDVTList HalfCarryVT = DAG.getVTList(HalfVT, MVT::i1);
// First round of UNR (Unsigned integer Newton-Raphson).
SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS); SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS);
SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64); SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64);
SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1); SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);
SDValue Mulhi1_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1, SDValue Mulhi1_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,
Zero); Zero);
SDValue Mulhi1_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1, SDValue Mulhi1_Hi =
One); DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1, One);
SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo, SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo,
Mulhi1_Lo, Zero1); Mulhi1_Lo, Zero1);
SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi, SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi,
Mulhi1_Hi, Add1_Lo.getValue(1)); Mulhi1_Hi, Add1_Lo.getValue(1));
SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi);
SDValue Add1 = DAG.getBitcast(VT, SDValue Add1 = DAG.getBitcast(VT,
DAG.getBuildVector(MVT::v2i32, DL, {Add1_Lo, Add1_Hi})); DAG.getBuildVector(MVT::v2i32, DL, {Add1_Lo, Add1_Hi}));
// Second round of UNR.
SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1); SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1);
SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);
SDValue Mulhi2_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2, SDValue Mulhi2_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,
Zero); Zero);
SDValue Mulhi2_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2, SDValue Mulhi2_Hi =
One); DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2, One);
SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo, SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo,
Mulhi2_Lo, Zero1); Mulhi2_Lo, Zero1);
SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc, SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Hi,
Mulhi2_Hi, Add1_Lo.getValue(1)); Mulhi2_Hi, Add2_Lo.getValue(1));
SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC,
Zero, Add2_Lo.getValue(1));
SDValue Add2 = DAG.getBitcast(VT, SDValue Add2 = DAG.getBitcast(VT,
DAG.getBuildVector(MVT::v2i32, DL, {Add2_Lo, Add2_Hi})); DAG.getBuildVector(MVT::v2i32, DL, {Add2_Lo, Add2_Hi}));
SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2); SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);
SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3); SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3);
SDValue Mul3_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, Zero); SDValue Mul3_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, Zero);
SDValue Mul3_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, One); SDValue Mul3_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, One);
SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo, SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,
Mul3_Lo, Zero1); Mul3_Lo, Zero1);
▲ Show 20 Lines • Show All 2,948 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 3,045 Lines • ▼ Show 20 Linesvoid AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B,
auto MulHi1 = B.buildUMulH(S64, Rcp, MulLo1); auto MulHi1 = B.buildUMulH(S64, Rcp, MulLo1);
auto UnmergeMulHi1 = B.buildUnmerge(S32, MulHi1); auto UnmergeMulHi1 = B.buildUnmerge(S32, MulHi1);
Register MulHi1_Lo = UnmergeMulHi1.getReg(0); Register MulHi1_Lo = UnmergeMulHi1.getReg(0);
Register MulHi1_Hi = UnmergeMulHi1.getReg(1); Register MulHi1_Hi = UnmergeMulHi1.getReg(1);
auto Add1_Lo = B.buildUAddo(S32, S1, RcpLo, MulHi1_Lo); auto Add1_Lo = B.buildUAddo(S32, S1, RcpLo, MulHi1_Lo);
auto Add1_Hi = B.buildUAdde(S32, S1, RcpHi, MulHi1_Hi, Add1_Lo.getReg(1)); auto Add1_Hi = B.buildUAdde(S32, S1, RcpHi, MulHi1_Hi, Add1_Lo.getReg(1));
auto Add1_HiNc = B.buildAdd(S32, RcpHi, MulHi1_Hi);
auto Add1 = B.buildMerge(S64, {Add1_Lo, Add1_Hi}); auto Add1 = B.buildMerge(S64, {Add1_Lo, Add1_Hi});
auto MulLo2 = B.buildMul(S64, NegDenom, Add1); auto MulLo2 = B.buildMul(S64, NegDenom, Add1);
auto MulHi2 = B.buildUMulH(S64, Add1, MulLo2); auto MulHi2 = B.buildUMulH(S64, Add1, MulLo2);
auto UnmergeMulHi2 = B.buildUnmerge(S32, MulHi2); auto UnmergeMulHi2 = B.buildUnmerge(S32, MulHi2);
Register MulHi2_Lo = UnmergeMulHi2.getReg(0); Register MulHi2_Lo = UnmergeMulHi2.getReg(0);
Register MulHi2_Hi = UnmergeMulHi2.getReg(1); Register MulHi2_Hi = UnmergeMulHi2.getReg(1);
auto Zero32 = B.buildConstant(S32, 0); auto Zero32 = B.buildConstant(S32, 0);
auto Add2_Lo = B.buildUAddo(S32, S1, Add1_Lo, MulHi2_Lo); auto Add2_Lo = B.buildUAddo(S32, S1, Add1_Lo, MulHi2_Lo);
auto Add2_HiC = auto Add2_Hi = B.buildUAdde(S32, S1, Add1_Hi, MulHi2_Hi, Add2_Lo.getReg(1));
B.buildUAdde(S32, S1, Add1_HiNc, MulHi2_Hi, Add1_Lo.getReg(1));
auto Add2_Hi = B.buildUAdde(S32, S1, Add2_HiC, Zero32, Add2_Lo.getReg(1));
auto Add2 = B.buildMerge(S64, {Add2_Lo, Add2_Hi}); auto Add2 = B.buildMerge(S64, {Add2_Lo, Add2_Hi});
auto UnmergeNumer = B.buildUnmerge(S32, Numer); auto UnmergeNumer = B.buildUnmerge(S32, Numer);
Register NumerLo = UnmergeNumer.getReg(0); Register NumerLo = UnmergeNumer.getReg(0);
Register NumerHi = UnmergeNumer.getReg(1); Register NumerHi = UnmergeNumer.getReg(1);
auto MulHi3 = B.buildUMulH(S64, Numer, Add2); auto MulHi3 = B.buildUMulH(S64, Numer, Add2);
auto Mul3 = B.buildMul(S64, Denom, MulHi3); auto Mul3 = B.buildMul(S64, Denom, MulHi3);
▲ Show 20 Lines • Show All 2,071 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir

Show First 20 Lines • Show All 409 Lines • ▼ Show 20 Lines bb.0:
; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]] ; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]]
; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE8]] ; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE6]]
; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]] ; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]]
; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE8]] ; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE6]]
; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]] ; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]]
; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE8]] ; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE6]]
; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE8]] ; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE6]]
; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD16]](s32) ; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD15]](s32)
; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]] ; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]]
; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]] ; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]]
; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD16]] ; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD15]]
; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]] ; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]]
; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]] ; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD18]], [[USUBO3]] ; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD17]], [[USUBO3]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD18]] ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD17]]
; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]] ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]]
; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]] ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]]
; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX6-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV20]] ; GFX6-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV20]]
; GFX6-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV21]], [[USUBO3]] ; GFX6-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV21]], [[USUBO3]]
; GFX6-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]] ; GFX6-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]]
; GFX6-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX6-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX6-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX6-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV22]] ; GFX6-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV22]]
; GFX6-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV23]], [[UADDO39]] ; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV23]], [[UADDO39]]
; GFX6-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE10]](s32) ; GFX6-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE8]](s32)
; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV21]] ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV21]]
; GFX6-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX6-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV20]] ; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV20]]
; GFX6-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX6-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV21]] ; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV21]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX6-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX6-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX6-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV24]] ; GFX6-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV24]]
; GFX6-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UADDE10]], [[UV25]], [[UADDO41]] ; GFX6-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[UV25]], [[UADDO41]]
; GFX6-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE12]](s32) ; GFX6-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE10]](s32)
; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]] ; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]] ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]]
; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]] ; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]] ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]]
; GFX6-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]] ; GFX6-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]] ; GFX6-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]]
; GFX6-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX6-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX6-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64) ; GFX6-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64)
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; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]] ; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]]
; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE8]] ; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE6]]
; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]] ; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]]
; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE8]] ; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE6]]
; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]] ; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]]
; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE8]] ; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE6]]
; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE8]] ; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE6]]
; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD16]](s32) ; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD15]](s32)
; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]] ; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]]
; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]] ; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]]
; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD16]] ; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD15]]
; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]] ; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]]
; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]] ; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD18]], [[USUBO3]] ; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD17]], [[USUBO3]]
; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD18]] ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD17]]
; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]] ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]] ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]]
; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]] ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX8-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV20]] ; GFX8-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV20]]
; GFX8-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV21]], [[USUBO3]] ; GFX8-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV21]], [[USUBO3]]
; GFX8-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]] ; GFX8-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]]
; GFX8-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX8-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX8-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX8-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX8-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV22]] ; GFX8-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV22]]
; GFX8-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV23]], [[UADDO39]] ; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV23]], [[UADDO39]]
; GFX8-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE10]](s32) ; GFX8-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE8]](s32)
; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV21]] ; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV21]]
; GFX8-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX8-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX8-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV20]] ; GFX8-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV20]]
; GFX8-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX8-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX8-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV21]] ; GFX8-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV21]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX8-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX8-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX8-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV24]] ; GFX8-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV24]]
; GFX8-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UADDE10]], [[UV25]], [[UADDO41]] ; GFX8-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[UV25]], [[UADDO41]]
; GFX8-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE12]](s32) ; GFX8-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE10]](s32)
; GFX8-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]] ; GFX8-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]] ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]]
; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]] ; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]] ; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]]
; GFX8-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]] ; GFX8-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]] ; GFX8-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]]
; GFX8-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX8-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX8-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64) ; GFX8-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64)
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; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]] ; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]]
; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE8]] ; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE6]]
; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]] ; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]]
; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE8]] ; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE6]]
; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]] ; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]]
; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE8]] ; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE6]]
; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE8]] ; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE6]]
; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD16]](s32) ; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD15]](s32)
; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]] ; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]]
; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]] ; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]]
; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD16]] ; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD15]]
; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]] ; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]]
; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]] ; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD18]], [[USUBO3]] ; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD17]], [[USUBO3]]
; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD18]] ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD17]]
; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]] ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]]
; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]] ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]]
; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]] ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX9-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV20]] ; GFX9-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV20]]
; GFX9-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV21]], [[USUBO3]] ; GFX9-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV21]], [[USUBO3]]
; GFX9-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]] ; GFX9-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]]
; GFX9-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX9-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX9-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX9-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV22]] ; GFX9-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV22]]
; GFX9-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV23]], [[UADDO39]] ; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV23]], [[UADDO39]]
; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE10]](s32) ; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE8]](s32)
; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV21]] ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV21]]
; GFX9-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX9-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV20]] ; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV20]]
; GFX9-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX9-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV21]] ; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV21]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX9-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX9-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX9-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV24]] ; GFX9-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV24]]
; GFX9-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UADDE10]], [[UV25]], [[UADDO41]] ; GFX9-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[UV25]], [[UADDO41]]
; GFX9-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE12]](s32) ; GFX9-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE10]](s32)
; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]] ; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]] ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]]
; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]] ; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]] ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]]
; GFX9-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]] ; GFX9-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]] ; GFX9-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]]
; GFX9-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX9-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX9-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64) ; GFX9-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64)
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; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDO26]] ; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDO26]]
; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV20]], [[UADDE8]] ; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV20]], [[UADDE6]]
; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDO26]] ; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDO26]]
; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDE8]] ; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDE6]]
; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDO26]] ; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDO26]]
; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDE8]] ; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDE6]]
; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDE8]] ; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDE6]]
; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD16]](s32) ; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD15]](s32)
; GFX6-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX6-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[UADDO36]] ; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[UADDO36]]
; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV23]], [[UADDO36]] ; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV23]], [[UADDO36]]
; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[ADD16]] ; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[ADD15]]
; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV22]], [[UADDO36]] ; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV22]], [[UADDO36]]
; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV18]], [[MUL15]] ; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV18]], [[MUL15]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV19]], [[ADD18]], [[USUBO3]] ; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV19]], [[ADD17]], [[USUBO3]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV19]], [[ADD18]] ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV19]], [[ADD17]]
; GFX6-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX6-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV25]] ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV25]]
; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV24]] ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV24]]
; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV25]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV25]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX6-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV24]] ; GFX6-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV24]]
; GFX6-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV25]], [[USUBO3]] ; GFX6-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV25]], [[USUBO3]]
; GFX6-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]] ; GFX6-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]]
; GFX6-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX6-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX6-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX6-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV26]] ; GFX6-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV26]]
; GFX6-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV27]], [[UADDO39]] ; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV27]], [[UADDO39]]
; GFX6-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE10]](s32) ; GFX6-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE8]](s32)
; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV25]] ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV25]]
; GFX6-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX6-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV24]] ; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV24]]
; GFX6-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX6-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV25]] ; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV25]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX6-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX6-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX6-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV28]] ; GFX6-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV28]]
; GFX6-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UADDE10]], [[UV29]], [[UADDO41]] ; GFX6-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[UV29]], [[UADDO41]]
; GFX6-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE12]](s32) ; GFX6-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE10]](s32)
; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]] ; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]] ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]]
; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]] ; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]] ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]]
; GFX6-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]] ; GFX6-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]] ; GFX6-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]]
; GFX6-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX6-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX6-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64) ; GFX6-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64)
; GFX6-NEXT: [[USUBO6:%[0-9]+]]:_(s32), [[USUBO7:%[0-9]+]]:_(s1) = G_USUBO [[UV30]], [[UV32]] ; GFX6-NEXT: [[USUBO6:%[0-9]+]]:_(s32), [[USUBO7:%[0-9]+]]:_(s1) = G_USUBO [[UV30]], [[UV32]]
; GFX6-NEXT: [[USUBE8:%[0-9]+]]:_(s32), [[USUBE9:%[0-9]+]]:_(s1) = G_USUBE [[UV31]], [[UV33]], [[USUBO7]] ; GFX6-NEXT: [[USUBE8:%[0-9]+]]:_(s32), [[USUBE9:%[0-9]+]]:_(s1) = G_USUBE [[UV31]], [[UV33]], [[USUBO7]]
; GFX6-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO6]](s32), [[USUBE8]](s32) ; GFX6-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO6]](s32), [[USUBE8]](s32)
; GFX6-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; GFX6-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; GFX6-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C]](s32) ; GFX6-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C]](s32)
; GFX6-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX6-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX6-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR2]](s64) ; GFX6-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR2]](s64)
; GFX6-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[UV34]], [[UV36]] ; GFX6-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[UV34]], [[UV36]]
; GFX6-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UV35]], [[UV37]], [[UADDO43]] ; GFX6-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UV35]], [[UV37]], [[UADDO43]]
; GFX6-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO42]](s32), [[UADDE14]](s32) ; GFX6-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO42]](s32), [[UADDE12]](s32)
; GFX6-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX6-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX6-NEXT: [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR3]](s64) ; GFX6-NEXT: [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR3]](s64)
; GFX6-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UV38]], [[UV40]] ; GFX6-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UV38]], [[UV40]]
; GFX6-NEXT: [[UADDE16:%[0-9]+]]:_(s32), [[UADDE17:%[0-9]+]]:_(s1) = G_UADDE [[UV39]], [[UV41]], [[UADDO45]] ; GFX6-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UV39]], [[UV41]], [[UADDO45]]
; GFX6-NEXT: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO44]](s32), [[UADDE16]](s32) ; GFX6-NEXT: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO44]](s32), [[UADDE14]](s32)
; GFX6-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[MV6]], [[ASHR2]] ; GFX6-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[MV6]], [[ASHR2]]
; GFX6-NEXT: [[XOR5:%[0-9]+]]:_(s64) = G_XOR [[MV7]], [[ASHR3]] ; GFX6-NEXT: [[XOR5:%[0-9]+]]:_(s64) = G_XOR [[MV7]], [[ASHR3]]
; GFX6-NEXT: [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64) ; GFX6-NEXT: [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64)
; GFX6-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV42]](s32) ; GFX6-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV42]](s32)
; GFX6-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV43]](s32) ; GFX6-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV43]](s32)
; GFX6-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 ; GFX6-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
; GFX6-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP3]], [[C8]] ; GFX6-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP3]], [[C8]]
; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL4]], [[UITOFP2]] ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL4]], [[UITOFP2]]
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; GFX6-NEXT: [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C5]](s64) ; GFX6-NEXT: [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C5]](s64)
; GFX6-NEXT: [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64) ; GFX6-NEXT: [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64)
; GFX6-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV44]], [[UV46]] ; GFX6-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV44]], [[UV46]]
; GFX6-NEXT: [[USUBE10:%[0-9]+]]:_(s32), [[USUBE11:%[0-9]+]]:_(s1) = G_USUBE [[UV45]], [[UV47]], [[USUBO9]] ; GFX6-NEXT: [[USUBE10:%[0-9]+]]:_(s32), [[USUBE11:%[0-9]+]]:_(s1) = G_USUBE [[UV45]], [[UV47]], [[USUBO9]]
; GFX6-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI2]] ; GFX6-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI2]]
; GFX6-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE10]], [[FPTOUI2]] ; GFX6-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE10]], [[FPTOUI2]]
; GFX6-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI3]] ; GFX6-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI3]]
; GFX6-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[FPTOUI2]] ; GFX6-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[FPTOUI2]]
; GFX6-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]] ; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]]
; GFX6-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ADD19]], [[UMULH15]] ; GFX6-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[ADD18]], [[UMULH15]]
; GFX6-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]] ; GFX6-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]]
; GFX6-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD20]] ; GFX6-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD19]]
; GFX6-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]] ; GFX6-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]]
; GFX6-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]] ; GFX6-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]]
; GFX6-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1) ; GFX6-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1)
; GFX6-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH16]] ; GFX6-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH16]]
; GFX6-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1) ; GFX6-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1)
; GFX6-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]] ; GFX6-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]]
; GFX6-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD20]] ; GFX6-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD19]]
; GFX6-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]] ; GFX6-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]]
; GFX6-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD20]] ; GFX6-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD19]]
; GFX6-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]] ; GFX6-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]]
; GFX6-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1) ; GFX6-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1)
; GFX6-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH18]] ; GFX6-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH18]]
; GFX6-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1) ; GFX6-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1)
; GFX6-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]] ; GFX6-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]]
; GFX6-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[ADD21]] ; GFX6-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[ADD20]]
; GFX6-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1) ; GFX6-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1)
; GFX6-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[ADD22]], [[ZEXT19]] ; GFX6-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ADD21]], [[ZEXT19]]
; GFX6-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD20]] ; GFX6-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD19]]
; GFX6-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD23]] ; GFX6-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD22]]
; GFX6-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO54]] ; GFX6-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO54]]
; GFX6-NEXT: [[UADDE18:%[0-9]+]]:_(s32), [[UADDE19:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD24]], [[UADDO57]] ; GFX6-NEXT: [[UADDE16:%[0-9]+]]:_(s32), [[UADDE17:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD23]], [[UADDO57]]
; GFX6-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI3]], [[ADD24]]
; GFX6-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDO56]] ; GFX6-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDO56]]
; GFX6-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE10]], [[UADDO56]] ; GFX6-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE10]], [[UADDO56]]
; GFX6-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDE18]] ; GFX6-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDE16]]
; GFX6-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[UADDO56]] ; GFX6-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[UADDO56]]
; GFX6-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]] ; GFX6-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]]
; GFX6-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ADD26]], [[UMULH20]] ; GFX6-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[ADD24]], [[UMULH20]]
; GFX6-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE18]], [[MUL24]] ; GFX6-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE16]], [[MUL24]]
; GFX6-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO56]], [[ADD27]] ; GFX6-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO56]], [[ADD25]]
; GFX6-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO56]], [[MUL24]] ; GFX6-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO56]], [[MUL24]]
; GFX6-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]] ; GFX6-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]]
; GFX6-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1) ; GFX6-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1)
; GFX6-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH21]] ; GFX6-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH21]]
; GFX6-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1) ; GFX6-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1)
; GFX6-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]] ; GFX6-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]]
; GFX6-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE18]], [[ADD27]] ; GFX6-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE16]], [[ADD25]]
; GFX6-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE18]], [[MUL24]] ; GFX6-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE16]], [[MUL24]]
; GFX6-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO56]], [[ADD27]] ; GFX6-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO56]], [[ADD25]]
; GFX6-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]] ; GFX6-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]]
; GFX6-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1) ; GFX6-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1)
; GFX6-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH23]] ; GFX6-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH23]]
; GFX6-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1) ; GFX6-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1)
; GFX6-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]] ; GFX6-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]]
; GFX6-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[UADDO64]], [[ADD28]] ; GFX6-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[UADDO64]], [[ADD26]]
; GFX6-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1) ; GFX6-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1)
; GFX6-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ADD29]], [[ZEXT24]] ; GFX6-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ADD27]], [[ZEXT24]]
; GFX6-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE18]], [[ADD27]] ; GFX6-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE16]], [[ADD25]]
; GFX6-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD30]] ; GFX6-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD28]]
; GFX6-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO56]], [[UADDO66]] ; GFX6-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO56]], [[UADDO66]]
; GFX6-NEXT: [[UADDE20:%[0-9]+]]:_(s32), [[UADDE21:%[0-9]+]]:_(s1) = G_UADDE [[ADD25]], [[ADD31]], [[UADDO57]] ; GFX6-NEXT: [[UADDE18:%[0-9]+]]:_(s32), [[UADDE19:%[0-9]+]]:_(s1) = G_UADDE [[UADDE16]], [[ADD29]], [[UADDO69]]
; GFX6-NEXT: [[UADDE22:%[0-9]+]]:_(s32), [[UADDE23:%[0-9]+]]:_(s1) = G_UADDE [[UADDE20]], [[C6]], [[UADDO69]]
; GFX6-NEXT: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX6-NEXT: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX6-NEXT: [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX6-NEXT: [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX6-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV51]], [[UADDO68]] ; GFX6-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV51]], [[UADDO68]]
; GFX6-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV50]], [[UADDE22]] ; GFX6-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV50]], [[UADDE18]]
; GFX6-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV50]], [[UADDO68]] ; GFX6-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV50]], [[UADDO68]]
; GFX6-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]] ; GFX6-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]]
; GFX6-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1) ; GFX6-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1)
; GFX6-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UMULH25]] ; GFX6-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UMULH25]]
; GFX6-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO73]](s1) ; GFX6-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO73]](s1)
; GFX6-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]] ; GFX6-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]]
; GFX6-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV51]], [[UADDE22]] ; GFX6-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV51]], [[UADDE18]]
; GFX6-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV51]], [[UADDO68]] ; GFX6-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV51]], [[UADDO68]]
; GFX6-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV50]], [[UADDE22]] ; GFX6-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV50]], [[UADDE18]]
; GFX6-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]] ; GFX6-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]]
; GFX6-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO75]](s1) ; GFX6-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO75]](s1)
; GFX6-NEXT: [[UADDO76:%[0-9]+]]:_(s32), [[UADDO77:%[0-9]+]]:_(s1) = G_UADDO [[UADDO74]], [[UMULH27]] ; GFX6-NEXT: [[UADDO76:%[0-9]+]]:_(s32), [[UADDO77:%[0-9]+]]:_(s1) = G_UADDO [[UADDO74]], [[UMULH27]]
; GFX6-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO77]](s1) ; GFX6-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO77]](s1)
; GFX6-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]] ; GFX6-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]]
; GFX6-NEXT: [[UADDO78:%[0-9]+]]:_(s32), [[UADDO79:%[0-9]+]]:_(s1) = G_UADDO [[UADDO76]], [[ADD32]] ; GFX6-NEXT: [[UADDO78:%[0-9]+]]:_(s32), [[UADDO79:%[0-9]+]]:_(s1) = G_UADDO [[UADDO76]], [[ADD30]]
; GFX6-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO79]](s1) ; GFX6-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO79]](s1)
; GFX6-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[ADD33]], [[ZEXT29]] ; GFX6-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ADD31]], [[ZEXT29]]
; GFX6-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV51]], [[UADDE22]] ; GFX6-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV51]], [[UADDE18]]
; GFX6-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD34]] ; GFX6-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD32]]
; GFX6-NEXT: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO78]](s32), [[ADD35]](s32) ; GFX6-NEXT: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO78]](s32), [[ADD33]](s32)
; GFX6-NEXT: [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64) ; GFX6-NEXT: [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64)
; GFX6-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV52]], [[UADDO78]] ; GFX6-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV52]], [[UADDO78]]
; GFX6-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV53]], [[UADDO78]] ; GFX6-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV53]], [[UADDO78]]
; GFX6-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV52]], [[ADD35]] ; GFX6-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV52]], [[ADD33]]
; GFX6-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV52]], [[UADDO78]] ; GFX6-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV52]], [[UADDO78]]
; GFX6-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]] ; GFX6-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]]
; GFX6-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[ADD36]], [[UMULH29]] ; GFX6-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[ADD34]], [[UMULH29]]
; GFX6-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV48]], [[MUL33]] ; GFX6-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV48]], [[MUL33]]
; GFX6-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV49]], [[ADD37]], [[USUBO11]] ; GFX6-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV49]], [[ADD35]], [[USUBO11]]
; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV49]], [[ADD37]] ; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV49]], [[ADD35]]
; GFX6-NEXT: [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64) ; GFX6-NEXT: [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64)
; GFX6-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE12]](s32), [[UV55]] ; GFX6-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE12]](s32), [[UV55]]
; GFX6-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1) ; GFX6-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1)
; GFX6-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV54]] ; GFX6-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV54]]
; GFX6-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1) ; GFX6-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1)
; GFX6-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE12]](s32), [[UV55]] ; GFX6-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE12]](s32), [[UV55]]
; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]] ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]]
; GFX6-NEXT: [[USUBO12:%[0-9]+]]:_(s32), [[USUBO13:%[0-9]+]]:_(s1) = G_USUBO [[USUBO10]], [[UV54]] ; GFX6-NEXT: [[USUBO12:%[0-9]+]]:_(s32), [[USUBO13:%[0-9]+]]:_(s1) = G_USUBO [[USUBO10]], [[UV54]]
; GFX6-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[SUB1]], [[UV55]], [[USUBO11]] ; GFX6-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[SUB1]], [[UV55]], [[USUBO11]]
; GFX6-NEXT: [[USUBE16:%[0-9]+]]:_(s32), [[USUBE17:%[0-9]+]]:_(s1) = G_USUBE [[USUBE14]], [[C6]], [[USUBO13]] ; GFX6-NEXT: [[USUBE16:%[0-9]+]]:_(s32), [[USUBE17:%[0-9]+]]:_(s1) = G_USUBE [[USUBE14]], [[C6]], [[USUBO13]]
; GFX6-NEXT: [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX6-NEXT: [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX6-NEXT: [[UADDO80:%[0-9]+]]:_(s32), [[UADDO81:%[0-9]+]]:_(s1) = G_UADDO [[UADDO78]], [[UV56]] ; GFX6-NEXT: [[UADDO80:%[0-9]+]]:_(s32), [[UADDO81:%[0-9]+]]:_(s1) = G_UADDO [[UADDO78]], [[UV56]]
; GFX6-NEXT: [[UADDE24:%[0-9]+]]:_(s32), [[UADDE25:%[0-9]+]]:_(s1) = G_UADDE [[ADD35]], [[UV57]], [[UADDO81]] ; GFX6-NEXT: [[UADDE20:%[0-9]+]]:_(s32), [[UADDE21:%[0-9]+]]:_(s1) = G_UADDE [[ADD33]], [[UV57]], [[UADDO81]]
; GFX6-NEXT: [[MV9:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO80]](s32), [[UADDE24]](s32) ; GFX6-NEXT: [[MV9:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO80]](s32), [[UADDE20]](s32)
; GFX6-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE16]](s32), [[UV55]] ; GFX6-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE16]](s32), [[UV55]]
; GFX6-NEXT: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[ICMP11]](s1) ; GFX6-NEXT: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[ICMP11]](s1)
; GFX6-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO12]](s32), [[UV54]] ; GFX6-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO12]](s32), [[UV54]]
; GFX6-NEXT: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[ICMP12]](s1) ; GFX6-NEXT: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[ICMP12]](s1)
; GFX6-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE16]](s32), [[UV55]] ; GFX6-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE16]](s32), [[UV55]]
; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP13]](s1), [[SEXT7]], [[SEXT6]] ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP13]](s1), [[SEXT7]], [[SEXT6]]
; GFX6-NEXT: [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX6-NEXT: [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX6-NEXT: [[UADDO82:%[0-9]+]]:_(s32), [[UADDO83:%[0-9]+]]:_(s1) = G_UADDO [[UADDO80]], [[UV58]] ; GFX6-NEXT: [[UADDO82:%[0-9]+]]:_(s32), [[UADDO83:%[0-9]+]]:_(s1) = G_UADDO [[UADDO80]], [[UV58]]
; GFX6-NEXT: [[UADDE26:%[0-9]+]]:_(s32), [[UADDE27:%[0-9]+]]:_(s1) = G_UADDE [[UADDE24]], [[UV59]], [[UADDO83]] ; GFX6-NEXT: [[UADDE22:%[0-9]+]]:_(s32), [[UADDE23:%[0-9]+]]:_(s1) = G_UADDE [[UADDE20]], [[UV59]], [[UADDO83]]
; GFX6-NEXT: [[MV10:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO82]](s32), [[UADDE26]](s32) ; GFX6-NEXT: [[MV10:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO82]](s32), [[UADDE22]](s32)
; GFX6-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT5]](s32), [[C6]] ; GFX6-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT5]](s32), [[C6]]
; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP14]](s1), [[MV10]], [[MV9]] ; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP14]](s1), [[MV10]], [[MV9]]
; GFX6-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT4]](s32), [[C6]] ; GFX6-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT4]](s32), [[C6]]
; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV8]] ; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV8]]
; GFX6-NEXT: [[XOR6:%[0-9]+]]:_(s64) = G_XOR [[ASHR2]], [[ASHR3]] ; GFX6-NEXT: [[XOR6:%[0-9]+]]:_(s64) = G_XOR [[ASHR2]], [[ASHR3]]
; GFX6-NEXT: [[XOR7:%[0-9]+]]:_(s64) = G_XOR [[SELECT7]], [[XOR6]] ; GFX6-NEXT: [[XOR7:%[0-9]+]]:_(s64) = G_XOR [[SELECT7]], [[XOR6]]
; GFX6-NEXT: [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR7]](s64) ; GFX6-NEXT: [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR7]](s64)
; GFX6-NEXT: [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR6]](s64) ; GFX6-NEXT: [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR6]](s64)
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; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDO26]] ; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDO26]]
; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV20]], [[UADDE8]] ; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV20]], [[UADDE6]]
; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDO26]] ; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDO26]]
; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDE8]] ; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDE6]]
; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDO26]] ; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDO26]]
; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDE8]] ; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDE6]]
; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDE8]] ; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDE6]]
; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD16]](s32) ; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD15]](s32)
; GFX8-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX8-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[UADDO36]] ; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[UADDO36]]
; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV23]], [[UADDO36]] ; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV23]], [[UADDO36]]
; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[ADD16]] ; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[ADD15]]
; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV22]], [[UADDO36]] ; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV22]], [[UADDO36]]
; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV18]], [[MUL15]] ; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV18]], [[MUL15]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV19]], [[ADD18]], [[USUBO3]] ; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV19]], [[ADD17]], [[USUBO3]]
; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV19]], [[ADD18]] ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV19]], [[ADD17]]
; GFX8-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX8-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV25]] ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV25]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV24]] ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV24]]
; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV25]] ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV25]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX8-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV24]] ; GFX8-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV24]]
; GFX8-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV25]], [[USUBO3]] ; GFX8-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV25]], [[USUBO3]]
; GFX8-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]] ; GFX8-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]]
; GFX8-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX8-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX8-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX8-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX8-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV26]] ; GFX8-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV26]]
; GFX8-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV27]], [[UADDO39]] ; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV27]], [[UADDO39]]
; GFX8-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE10]](s32) ; GFX8-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE8]](s32)
; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV25]] ; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV25]]
; GFX8-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX8-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX8-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV24]] ; GFX8-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV24]]
; GFX8-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX8-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX8-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV25]] ; GFX8-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV25]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX8-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX8-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX8-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV28]] ; GFX8-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV28]]
; GFX8-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UADDE10]], [[UV29]], [[UADDO41]] ; GFX8-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[UV29]], [[UADDO41]]
; GFX8-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE12]](s32) ; GFX8-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE10]](s32)
; GFX8-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]] ; GFX8-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]] ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]]
; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]] ; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]] ; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]]
; GFX8-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]] ; GFX8-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]] ; GFX8-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]]
; GFX8-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX8-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX8-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64) ; GFX8-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64)
; GFX8-NEXT: [[USUBO6:%[0-9]+]]:_(s32), [[USUBO7:%[0-9]+]]:_(s1) = G_USUBO [[UV30]], [[UV32]] ; GFX8-NEXT: [[USUBO6:%[0-9]+]]:_(s32), [[USUBO7:%[0-9]+]]:_(s1) = G_USUBO [[UV30]], [[UV32]]
; GFX8-NEXT: [[USUBE8:%[0-9]+]]:_(s32), [[USUBE9:%[0-9]+]]:_(s1) = G_USUBE [[UV31]], [[UV33]], [[USUBO7]] ; GFX8-NEXT: [[USUBE8:%[0-9]+]]:_(s32), [[USUBE9:%[0-9]+]]:_(s1) = G_USUBE [[UV31]], [[UV33]], [[USUBO7]]
; GFX8-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO6]](s32), [[USUBE8]](s32) ; GFX8-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO6]](s32), [[USUBE8]](s32)
; GFX8-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; GFX8-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; GFX8-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C]](s32) ; GFX8-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C]](s32)
; GFX8-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX8-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX8-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR2]](s64) ; GFX8-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR2]](s64)
; GFX8-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[UV34]], [[UV36]] ; GFX8-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[UV34]], [[UV36]]
; GFX8-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UV35]], [[UV37]], [[UADDO43]] ; GFX8-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UV35]], [[UV37]], [[UADDO43]]
; GFX8-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO42]](s32), [[UADDE14]](s32) ; GFX8-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO42]](s32), [[UADDE12]](s32)
; GFX8-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX8-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX8-NEXT: [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR3]](s64) ; GFX8-NEXT: [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR3]](s64)
; GFX8-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UV38]], [[UV40]] ; GFX8-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UV38]], [[UV40]]
; GFX8-NEXT: [[UADDE16:%[0-9]+]]:_(s32), [[UADDE17:%[0-9]+]]:_(s1) = G_UADDE [[UV39]], [[UV41]], [[UADDO45]] ; GFX8-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UV39]], [[UV41]], [[UADDO45]]
; GFX8-NEXT: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO44]](s32), [[UADDE16]](s32) ; GFX8-NEXT: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO44]](s32), [[UADDE14]](s32)
; GFX8-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[MV6]], [[ASHR2]] ; GFX8-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[MV6]], [[ASHR2]]
; GFX8-NEXT: [[XOR5:%[0-9]+]]:_(s64) = G_XOR [[MV7]], [[ASHR3]] ; GFX8-NEXT: [[XOR5:%[0-9]+]]:_(s64) = G_XOR [[MV7]], [[ASHR3]]
; GFX8-NEXT: [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64) ; GFX8-NEXT: [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64)
; GFX8-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV42]](s32) ; GFX8-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV42]](s32)
; GFX8-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV43]](s32) ; GFX8-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV43]](s32)
; GFX8-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 ; GFX8-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
; GFX8-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP3]], [[C8]] ; GFX8-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP3]], [[C8]]
; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL4]], [[UITOFP2]] ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL4]], [[UITOFP2]]
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; GFX8-NEXT: [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C5]](s64) ; GFX8-NEXT: [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C5]](s64)
; GFX8-NEXT: [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64) ; GFX8-NEXT: [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64)
; GFX8-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV44]], [[UV46]] ; GFX8-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV44]], [[UV46]]
; GFX8-NEXT: [[USUBE10:%[0-9]+]]:_(s32), [[USUBE11:%[0-9]+]]:_(s1) = G_USUBE [[UV45]], [[UV47]], [[USUBO9]] ; GFX8-NEXT: [[USUBE10:%[0-9]+]]:_(s32), [[USUBE11:%[0-9]+]]:_(s1) = G_USUBE [[UV45]], [[UV47]], [[USUBO9]]
; GFX8-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI2]] ; GFX8-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI2]]
; GFX8-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE10]], [[FPTOUI2]] ; GFX8-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE10]], [[FPTOUI2]]
; GFX8-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI3]] ; GFX8-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI3]]
; GFX8-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[FPTOUI2]] ; GFX8-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[FPTOUI2]]
; GFX8-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]] ; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]]
; GFX8-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ADD19]], [[UMULH15]] ; GFX8-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[ADD18]], [[UMULH15]]
; GFX8-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]] ; GFX8-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]]
; GFX8-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD20]] ; GFX8-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD19]]
; GFX8-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]] ; GFX8-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]]
; GFX8-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]] ; GFX8-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]]
; GFX8-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1) ; GFX8-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1)
; GFX8-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH16]] ; GFX8-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH16]]
; GFX8-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1) ; GFX8-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1)
; GFX8-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]] ; GFX8-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]]
; GFX8-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD20]] ; GFX8-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD19]]
; GFX8-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]] ; GFX8-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]]
; GFX8-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD20]] ; GFX8-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD19]]
; GFX8-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]] ; GFX8-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]]
; GFX8-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1) ; GFX8-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1)
; GFX8-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH18]] ; GFX8-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH18]]
; GFX8-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1) ; GFX8-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1)
; GFX8-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]] ; GFX8-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]]
; GFX8-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[ADD21]] ; GFX8-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[ADD20]]
; GFX8-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1) ; GFX8-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1)
; GFX8-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[ADD22]], [[ZEXT19]] ; GFX8-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ADD21]], [[ZEXT19]]
; GFX8-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD20]] ; GFX8-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD19]]
; GFX8-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD23]] ; GFX8-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD22]]
; GFX8-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO54]] ; GFX8-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO54]]
; GFX8-NEXT: [[UADDE18:%[0-9]+]]:_(s32), [[UADDE19:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD24]], [[UADDO57]] ; GFX8-NEXT: [[UADDE16:%[0-9]+]]:_(s32), [[UADDE17:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD23]], [[UADDO57]]
; GFX8-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI3]], [[ADD24]]
; GFX8-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDO56]] ; GFX8-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDO56]]
; GFX8-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE10]], [[UADDO56]] ; GFX8-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE10]], [[UADDO56]]
; GFX8-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDE18]] ; GFX8-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDE16]]
; GFX8-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[UADDO56]] ; GFX8-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[UADDO56]]
; GFX8-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]] ; GFX8-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]]
; GFX8-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ADD26]], [[UMULH20]] ; GFX8-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[ADD24]], [[UMULH20]]
; GFX8-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE18]], [[MUL24]] ; GFX8-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE16]], [[MUL24]]
; GFX8-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO56]], [[ADD27]] ; GFX8-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO56]], [[ADD25]]
; GFX8-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO56]], [[MUL24]] ; GFX8-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO56]], [[MUL24]]
; GFX8-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]] ; GFX8-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]]
; GFX8-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1) ; GFX8-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1)
; GFX8-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH21]] ; GFX8-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH21]]
; GFX8-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1) ; GFX8-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1)
; GFX8-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]] ; GFX8-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]]
; GFX8-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE18]], [[ADD27]] ; GFX8-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE16]], [[ADD25]]
; GFX8-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE18]], [[MUL24]] ; GFX8-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE16]], [[MUL24]]
; GFX8-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO56]], [[ADD27]] ; GFX8-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO56]], [[ADD25]]
; GFX8-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]] ; GFX8-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]]
; GFX8-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1) ; GFX8-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1)
; GFX8-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH23]] ; GFX8-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH23]]
; GFX8-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1) ; GFX8-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1)
; GFX8-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]] ; GFX8-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]]
; GFX8-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[UADDO64]], [[ADD28]] ; GFX8-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[UADDO64]], [[ADD26]]
; GFX8-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1) ; GFX8-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1)
; GFX8-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ADD29]], [[ZEXT24]] ; GFX8-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ADD27]], [[ZEXT24]]
; GFX8-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE18]], [[ADD27]] ; GFX8-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE16]], [[ADD25]]
; GFX8-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD30]] ; GFX8-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD28]]
; GFX8-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO56]], [[UADDO66]] ; GFX8-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO56]], [[UADDO66]]
; GFX8-NEXT: [[UADDE20:%[0-9]+]]:_(s32), [[UADDE21:%[0-9]+]]:_(s1) = G_UADDE [[ADD25]], [[ADD31]], [[UADDO57]] ; GFX8-NEXT: [[UADDE18:%[0-9]+]]:_(s32), [[UADDE19:%[0-9]+]]:_(s1) = G_UADDE [[UADDE16]], [[ADD29]], [[UADDO69]]
; GFX8-NEXT: [[UADDE22:%[0-9]+]]:_(s32), [[UADDE23:%[0-9]+]]:_(s1) = G_UADDE [[UADDE20]], [[C6]], [[UADDO69]]
; GFX8-NEXT: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX8-NEXT: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX8-NEXT: [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX8-NEXT: [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX8-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV51]], [[UADDO68]] ; GFX8-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV51]], [[UADDO68]]
; GFX8-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV50]], [[UADDE22]] ; GFX8-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV50]], [[UADDE18]]
; GFX8-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV50]], [[UADDO68]] ; GFX8-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV50]], [[UADDO68]]
; GFX8-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]] ; GFX8-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]]
; GFX8-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1) ; GFX8-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1)
; GFX8-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UMULH25]] ; GFX8-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UMULH25]]
; GFX8-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO73]](s1) ; GFX8-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO73]](s1)
; GFX8-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]] ; GFX8-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]]
; GFX8-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV51]], [[UADDE22]] ; GFX8-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV51]], [[UADDE18]]
; GFX8-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV51]], [[UADDO68]] ; GFX8-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV51]], [[UADDO68]]
; GFX8-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV50]], [[UADDE22]] ; GFX8-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV50]], [[UADDE18]]
; GFX8-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]] ; GFX8-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]]
; GFX8-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO75]](s1) ; GFX8-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO75]](s1)
; GFX8-NEXT: [[UADDO76:%[0-9]+]]:_(s32), [[UADDO77:%[0-9]+]]:_(s1) = G_UADDO [[UADDO74]], [[UMULH27]] ; GFX8-NEXT: [[UADDO76:%[0-9]+]]:_(s32), [[UADDO77:%[0-9]+]]:_(s1) = G_UADDO [[UADDO74]], [[UMULH27]]
; GFX8-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO77]](s1) ; GFX8-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO77]](s1)
; GFX8-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]] ; GFX8-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]]
; GFX8-NEXT: [[UADDO78:%[0-9]+]]:_(s32), [[UADDO79:%[0-9]+]]:_(s1) = G_UADDO [[UADDO76]], [[ADD32]] ; GFX8-NEXT: [[UADDO78:%[0-9]+]]:_(s32), [[UADDO79:%[0-9]+]]:_(s1) = G_UADDO [[UADDO76]], [[ADD30]]
; GFX8-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO79]](s1) ; GFX8-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO79]](s1)
; GFX8-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[ADD33]], [[ZEXT29]] ; GFX8-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ADD31]], [[ZEXT29]]
; GFX8-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV51]], [[UADDE22]] ; GFX8-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV51]], [[UADDE18]]
; GFX8-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD34]] ; GFX8-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD32]]
; GFX8-NEXT: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO78]](s32), [[ADD35]](s32) ; GFX8-NEXT: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO78]](s32), [[ADD33]](s32)
; GFX8-NEXT: [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64) ; GFX8-NEXT: [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64)
; GFX8-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV52]], [[UADDO78]] ; GFX8-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV52]], [[UADDO78]]
; GFX8-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV53]], [[UADDO78]] ; GFX8-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV53]], [[UADDO78]]
; GFX8-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV52]], [[ADD35]] ; GFX8-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV52]], [[ADD33]]
; GFX8-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV52]], [[UADDO78]] ; GFX8-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV52]], [[UADDO78]]
; GFX8-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]] ; GFX8-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]]
; GFX8-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[ADD36]], [[UMULH29]] ; GFX8-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[ADD34]], [[UMULH29]]
; GFX8-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV48]], [[MUL33]] ; GFX8-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV48]], [[MUL33]]
; GFX8-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV49]], [[ADD37]], [[USUBO11]] ; GFX8-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV49]], [[ADD35]], [[USUBO11]]
; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV49]], [[ADD37]] ; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV49]], [[ADD35]]
; GFX8-NEXT: [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64) ; GFX8-NEXT: [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64)
; GFX8-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE12]](s32), [[UV55]] ; GFX8-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE12]](s32), [[UV55]]
; GFX8-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1) ; GFX8-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1)
; GFX8-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV54]] ; GFX8-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV54]]
; GFX8-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1) ; GFX8-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1)
; GFX8-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE12]](s32), [[UV55]] ; GFX8-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE12]](s32), [[UV55]]
; GFX8-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]] ; GFX8-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]]
; GFX8-NEXT: [[USUBO12:%[0-9]+]]:_(s32), [[USUBO13:%[0-9]+]]:_(s1) = G_USUBO [[USUBO10]], [[UV54]] ; GFX8-NEXT: [[USUBO12:%[0-9]+]]:_(s32), [[USUBO13:%[0-9]+]]:_(s1) = G_USUBO [[USUBO10]], [[UV54]]
; GFX8-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[SUB1]], [[UV55]], [[USUBO11]] ; GFX8-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[SUB1]], [[UV55]], [[USUBO11]]
; GFX8-NEXT: [[USUBE16:%[0-9]+]]:_(s32), [[USUBE17:%[0-9]+]]:_(s1) = G_USUBE [[USUBE14]], [[C6]], [[USUBO13]] ; GFX8-NEXT: [[USUBE16:%[0-9]+]]:_(s32), [[USUBE17:%[0-9]+]]:_(s1) = G_USUBE [[USUBE14]], [[C6]], [[USUBO13]]
; GFX8-NEXT: [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX8-NEXT: [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX8-NEXT: [[UADDO80:%[0-9]+]]:_(s32), [[UADDO81:%[0-9]+]]:_(s1) = G_UADDO [[UADDO78]], [[UV56]] ; GFX8-NEXT: [[UADDO80:%[0-9]+]]:_(s32), [[UADDO81:%[0-9]+]]:_(s1) = G_UADDO [[UADDO78]], [[UV56]]
; GFX8-NEXT: [[UADDE24:%[0-9]+]]:_(s32), [[UADDE25:%[0-9]+]]:_(s1) = G_UADDE [[ADD35]], [[UV57]], [[UADDO81]] ; GFX8-NEXT: [[UADDE20:%[0-9]+]]:_(s32), [[UADDE21:%[0-9]+]]:_(s1) = G_UADDE [[ADD33]], [[UV57]], [[UADDO81]]
; GFX8-NEXT: [[MV9:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO80]](s32), [[UADDE24]](s32) ; GFX8-NEXT: [[MV9:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO80]](s32), [[UADDE20]](s32)
; GFX8-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE16]](s32), [[UV55]] ; GFX8-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE16]](s32), [[UV55]]
; GFX8-NEXT: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[ICMP11]](s1) ; GFX8-NEXT: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[ICMP11]](s1)
; GFX8-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO12]](s32), [[UV54]] ; GFX8-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO12]](s32), [[UV54]]
; GFX8-NEXT: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[ICMP12]](s1) ; GFX8-NEXT: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[ICMP12]](s1)
; GFX8-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE16]](s32), [[UV55]] ; GFX8-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE16]](s32), [[UV55]]
; GFX8-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP13]](s1), [[SEXT7]], [[SEXT6]] ; GFX8-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP13]](s1), [[SEXT7]], [[SEXT6]]
; GFX8-NEXT: [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX8-NEXT: [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX8-NEXT: [[UADDO82:%[0-9]+]]:_(s32), [[UADDO83:%[0-9]+]]:_(s1) = G_UADDO [[UADDO80]], [[UV58]] ; GFX8-NEXT: [[UADDO82:%[0-9]+]]:_(s32), [[UADDO83:%[0-9]+]]:_(s1) = G_UADDO [[UADDO80]], [[UV58]]
; GFX8-NEXT: [[UADDE26:%[0-9]+]]:_(s32), [[UADDE27:%[0-9]+]]:_(s1) = G_UADDE [[UADDE24]], [[UV59]], [[UADDO83]] ; GFX8-NEXT: [[UADDE22:%[0-9]+]]:_(s32), [[UADDE23:%[0-9]+]]:_(s1) = G_UADDE [[UADDE20]], [[UV59]], [[UADDO83]]
; GFX8-NEXT: [[MV10:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO82]](s32), [[UADDE26]](s32) ; GFX8-NEXT: [[MV10:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO82]](s32), [[UADDE22]](s32)
; GFX8-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT5]](s32), [[C6]] ; GFX8-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT5]](s32), [[C6]]
; GFX8-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP14]](s1), [[MV10]], [[MV9]] ; GFX8-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP14]](s1), [[MV10]], [[MV9]]
; GFX8-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT4]](s32), [[C6]] ; GFX8-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT4]](s32), [[C6]]
; GFX8-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV8]] ; GFX8-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV8]]
; GFX8-NEXT: [[XOR6:%[0-9]+]]:_(s64) = G_XOR [[ASHR2]], [[ASHR3]] ; GFX8-NEXT: [[XOR6:%[0-9]+]]:_(s64) = G_XOR [[ASHR2]], [[ASHR3]]
; GFX8-NEXT: [[XOR7:%[0-9]+]]:_(s64) = G_XOR [[SELECT7]], [[XOR6]] ; GFX8-NEXT: [[XOR7:%[0-9]+]]:_(s64) = G_XOR [[SELECT7]], [[XOR6]]
; GFX8-NEXT: [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR7]](s64) ; GFX8-NEXT: [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR7]](s64)
; GFX8-NEXT: [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR6]](s64) ; GFX8-NEXT: [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR6]](s64)
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; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDO26]] ; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDO26]]
; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV20]], [[UADDE8]] ; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV20]], [[UADDE6]]
; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDO26]] ; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDO26]]
; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDE8]] ; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDE6]]
; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDO26]] ; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDO26]]
; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDE8]] ; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDE6]]
; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDE8]] ; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDE6]]
; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD16]](s32) ; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD15]](s32)
; GFX9-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX9-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[UADDO36]] ; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[UADDO36]]
; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV23]], [[UADDO36]] ; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV23]], [[UADDO36]]
; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[ADD16]] ; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[ADD15]]
; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV22]], [[UADDO36]] ; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV22]], [[UADDO36]]
; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV18]], [[MUL15]] ; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV18]], [[MUL15]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV19]], [[ADD18]], [[USUBO3]] ; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV19]], [[ADD17]], [[USUBO3]]
; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV19]], [[ADD18]] ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV19]], [[ADD17]]
; GFX9-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX9-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV25]] ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV25]]
; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV24]] ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV24]]
; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV25]] ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV25]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX9-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV24]] ; GFX9-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV24]]
; GFX9-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV25]], [[USUBO3]] ; GFX9-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV25]], [[USUBO3]]
; GFX9-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]] ; GFX9-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]]
; GFX9-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX9-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX9-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX9-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV26]] ; GFX9-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV26]]
; GFX9-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV27]], [[UADDO39]] ; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV27]], [[UADDO39]]
; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE10]](s32) ; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE8]](s32)
; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV25]] ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV25]]
; GFX9-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX9-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV24]] ; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV24]]
; GFX9-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX9-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV25]] ; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV25]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX9-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX9-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX9-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV28]] ; GFX9-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV28]]
; GFX9-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UADDE10]], [[UV29]], [[UADDO41]] ; GFX9-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[UV29]], [[UADDO41]]
; GFX9-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE12]](s32) ; GFX9-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE10]](s32)
; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]] ; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]] ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]]
; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]] ; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]] ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]]
; GFX9-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]] ; GFX9-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]] ; GFX9-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]]
; GFX9-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX9-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX9-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64) ; GFX9-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64)
; GFX9-NEXT: [[USUBO6:%[0-9]+]]:_(s32), [[USUBO7:%[0-9]+]]:_(s1) = G_USUBO [[UV30]], [[UV32]] ; GFX9-NEXT: [[USUBO6:%[0-9]+]]:_(s32), [[USUBO7:%[0-9]+]]:_(s1) = G_USUBO [[UV30]], [[UV32]]
; GFX9-NEXT: [[USUBE8:%[0-9]+]]:_(s32), [[USUBE9:%[0-9]+]]:_(s1) = G_USUBE [[UV31]], [[UV33]], [[USUBO7]] ; GFX9-NEXT: [[USUBE8:%[0-9]+]]:_(s32), [[USUBE9:%[0-9]+]]:_(s1) = G_USUBE [[UV31]], [[UV33]], [[USUBO7]]
; GFX9-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO6]](s32), [[USUBE8]](s32) ; GFX9-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO6]](s32), [[USUBE8]](s32)
; GFX9-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; GFX9-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; GFX9-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C]](s32) ; GFX9-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C]](s32)
; GFX9-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX9-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX9-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR2]](s64) ; GFX9-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR2]](s64)
; GFX9-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[UV34]], [[UV36]] ; GFX9-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[UV34]], [[UV36]]
; GFX9-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UV35]], [[UV37]], [[UADDO43]] ; GFX9-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UV35]], [[UV37]], [[UADDO43]]
; GFX9-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO42]](s32), [[UADDE14]](s32) ; GFX9-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO42]](s32), [[UADDE12]](s32)
; GFX9-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX9-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX9-NEXT: [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR3]](s64) ; GFX9-NEXT: [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR3]](s64)
; GFX9-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UV38]], [[UV40]] ; GFX9-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UV38]], [[UV40]]
; GFX9-NEXT: [[UADDE16:%[0-9]+]]:_(s32), [[UADDE17:%[0-9]+]]:_(s1) = G_UADDE [[UV39]], [[UV41]], [[UADDO45]] ; GFX9-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UV39]], [[UV41]], [[UADDO45]]
; GFX9-NEXT: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO44]](s32), [[UADDE16]](s32) ; GFX9-NEXT: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO44]](s32), [[UADDE14]](s32)
; GFX9-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[MV6]], [[ASHR2]] ; GFX9-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[MV6]], [[ASHR2]]
; GFX9-NEXT: [[XOR5:%[0-9]+]]:_(s64) = G_XOR [[MV7]], [[ASHR3]] ; GFX9-NEXT: [[XOR5:%[0-9]+]]:_(s64) = G_XOR [[MV7]], [[ASHR3]]
; GFX9-NEXT: [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64) ; GFX9-NEXT: [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64)
; GFX9-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV42]](s32) ; GFX9-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV42]](s32)
; GFX9-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV43]](s32) ; GFX9-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV43]](s32)
; GFX9-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 ; GFX9-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
; GFX9-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP3]], [[C8]] ; GFX9-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP3]], [[C8]]
; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL4]], [[UITOFP2]] ; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL4]], [[UITOFP2]]
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; GFX9-NEXT: [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C5]](s64) ; GFX9-NEXT: [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C5]](s64)
; GFX9-NEXT: [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64) ; GFX9-NEXT: [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64)
; GFX9-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV44]], [[UV46]] ; GFX9-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV44]], [[UV46]]
; GFX9-NEXT: [[USUBE10:%[0-9]+]]:_(s32), [[USUBE11:%[0-9]+]]:_(s1) = G_USUBE [[UV45]], [[UV47]], [[USUBO9]] ; GFX9-NEXT: [[USUBE10:%[0-9]+]]:_(s32), [[USUBE11:%[0-9]+]]:_(s1) = G_USUBE [[UV45]], [[UV47]], [[USUBO9]]
; GFX9-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI2]] ; GFX9-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI2]]
; GFX9-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE10]], [[FPTOUI2]] ; GFX9-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE10]], [[FPTOUI2]]
; GFX9-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI3]] ; GFX9-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI3]]
; GFX9-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[FPTOUI2]] ; GFX9-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[FPTOUI2]]
; GFX9-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]] ; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]]
; GFX9-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ADD19]], [[UMULH15]] ; GFX9-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[ADD18]], [[UMULH15]]
; GFX9-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]] ; GFX9-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]]
; GFX9-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD20]] ; GFX9-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD19]]
; GFX9-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]] ; GFX9-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]]
; GFX9-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]] ; GFX9-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]]
; GFX9-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1) ; GFX9-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1)
; GFX9-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH16]] ; GFX9-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH16]]
; GFX9-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1) ; GFX9-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1)
; GFX9-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]] ; GFX9-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]]
; GFX9-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD20]] ; GFX9-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD19]]
; GFX9-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]] ; GFX9-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]]
; GFX9-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD20]] ; GFX9-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD19]]
; GFX9-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]] ; GFX9-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]]
; GFX9-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1) ; GFX9-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1)
; GFX9-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH18]] ; GFX9-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH18]]
; GFX9-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1) ; GFX9-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1)
; GFX9-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]] ; GFX9-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]]
; GFX9-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[ADD21]] ; GFX9-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[ADD20]]
; GFX9-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1) ; GFX9-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1)
; GFX9-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[ADD22]], [[ZEXT19]] ; GFX9-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ADD21]], [[ZEXT19]]
; GFX9-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD20]] ; GFX9-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD19]]
; GFX9-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD23]] ; GFX9-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD22]]
; GFX9-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO54]] ; GFX9-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO54]]
; GFX9-NEXT: [[UADDE18:%[0-9]+]]:_(s32), [[UADDE19:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD24]], [[UADDO57]] ; GFX9-NEXT: [[UADDE16:%[0-9]+]]:_(s32), [[UADDE17:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD23]], [[UADDO57]]
; GFX9-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI3]], [[ADD24]]
; GFX9-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDO56]] ; GFX9-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDO56]]
; GFX9-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE10]], [[UADDO56]] ; GFX9-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE10]], [[UADDO56]]
; GFX9-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDE18]] ; GFX9-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDE16]]
; GFX9-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[UADDO56]] ; GFX9-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[UADDO56]]
; GFX9-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]] ; GFX9-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]]
; GFX9-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ADD26]], [[UMULH20]] ; GFX9-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[ADD24]], [[UMULH20]]
; GFX9-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE18]], [[MUL24]] ; GFX9-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE16]], [[MUL24]]
; GFX9-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO56]], [[ADD27]] ; GFX9-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO56]], [[ADD25]]
; GFX9-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO56]], [[MUL24]] ; GFX9-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO56]], [[MUL24]]
; GFX9-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]] ; GFX9-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]]
; GFX9-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1) ; GFX9-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1)
; GFX9-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH21]] ; GFX9-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH21]]
; GFX9-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1) ; GFX9-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1)
; GFX9-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]] ; GFX9-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]]
; GFX9-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE18]], [[ADD27]] ; GFX9-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE16]], [[ADD25]]
; GFX9-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE18]], [[MUL24]] ; GFX9-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE16]], [[MUL24]]
; GFX9-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO56]], [[ADD27]] ; GFX9-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO56]], [[ADD25]]
; GFX9-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]] ; GFX9-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]]
; GFX9-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1) ; GFX9-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1)
; GFX9-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH23]] ; GFX9-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH23]]
; GFX9-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1) ; GFX9-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1)
; GFX9-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]] ; GFX9-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]]
; GFX9-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[UADDO64]], [[ADD28]] ; GFX9-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[UADDO64]], [[ADD26]]
; GFX9-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1) ; GFX9-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1)
; GFX9-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ADD29]], [[ZEXT24]] ; GFX9-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ADD27]], [[ZEXT24]]
; GFX9-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE18]], [[ADD27]] ; GFX9-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE16]], [[ADD25]]
; GFX9-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD30]] ; GFX9-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD28]]
; GFX9-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO56]], [[UADDO66]] ; GFX9-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO56]], [[UADDO66]]
; GFX9-NEXT: [[UADDE20:%[0-9]+]]:_(s32), [[UADDE21:%[0-9]+]]:_(s1) = G_UADDE [[ADD25]], [[ADD31]], [[UADDO57]] ; GFX9-NEXT: [[UADDE18:%[0-9]+]]:_(s32), [[UADDE19:%[0-9]+]]:_(s1) = G_UADDE [[UADDE16]], [[ADD29]], [[UADDO69]]
; GFX9-NEXT: [[UADDE22:%[0-9]+]]:_(s32), [[UADDE23:%[0-9]+]]:_(s1) = G_UADDE [[UADDE20]], [[C6]], [[UADDO69]]
; GFX9-NEXT: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX9-NEXT: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX9-NEXT: [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX9-NEXT: [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX9-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV51]], [[UADDO68]] ; GFX9-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV51]], [[UADDO68]]
; GFX9-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV50]], [[UADDE22]] ; GFX9-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV50]], [[UADDE18]]
; GFX9-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV50]], [[UADDO68]] ; GFX9-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV50]], [[UADDO68]]
; GFX9-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]] ; GFX9-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]]
; GFX9-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1) ; GFX9-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1)
; GFX9-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UMULH25]] ; GFX9-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UMULH25]]
; GFX9-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO73]](s1) ; GFX9-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO73]](s1)
; GFX9-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]] ; GFX9-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]]
; GFX9-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV51]], [[UADDE22]] ; GFX9-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV51]], [[UADDE18]]
; GFX9-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV51]], [[UADDO68]] ; GFX9-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV51]], [[UADDO68]]
; GFX9-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV50]], [[UADDE22]] ; GFX9-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV50]], [[UADDE18]]
; GFX9-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]] ; GFX9-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]]
; GFX9-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO75]](s1) ; GFX9-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO75]](s1)
; GFX9-NEXT: [[UADDO76:%[0-9]+]]:_(s32), [[UADDO77:%[0-9]+]]:_(s1) = G_UADDO [[UADDO74]], [[UMULH27]] ; GFX9-NEXT: [[UADDO76:%[0-9]+]]:_(s32), [[UADDO77:%[0-9]+]]:_(s1) = G_UADDO [[UADDO74]], [[UMULH27]]
; GFX9-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO77]](s1) ; GFX9-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO77]](s1)
; GFX9-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]] ; GFX9-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]]
; GFX9-NEXT: [[UADDO78:%[0-9]+]]:_(s32), [[UADDO79:%[0-9]+]]:_(s1) = G_UADDO [[UADDO76]], [[ADD32]] ; GFX9-NEXT: [[UADDO78:%[0-9]+]]:_(s32), [[UADDO79:%[0-9]+]]:_(s1) = G_UADDO [[UADDO76]], [[ADD30]]
; GFX9-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO79]](s1) ; GFX9-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO79]](s1)
; GFX9-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[ADD33]], [[ZEXT29]] ; GFX9-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ADD31]], [[ZEXT29]]
; GFX9-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV51]], [[UADDE22]] ; GFX9-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV51]], [[UADDE18]]
; GFX9-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD34]] ; GFX9-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD32]]
; GFX9-NEXT: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO78]](s32), [[ADD35]](s32) ; GFX9-NEXT: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO78]](s32), [[ADD33]](s32)
; GFX9-NEXT: [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64) ; GFX9-NEXT: [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64)
; GFX9-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV52]], [[UADDO78]] ; GFX9-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV52]], [[UADDO78]]
; GFX9-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV53]], [[UADDO78]] ; GFX9-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV53]], [[UADDO78]]
; GFX9-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV52]], [[ADD35]] ; GFX9-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV52]], [[ADD33]]
; GFX9-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV52]], [[UADDO78]] ; GFX9-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV52]], [[UADDO78]]
; GFX9-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]] ; GFX9-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]]
; GFX9-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[ADD36]], [[UMULH29]] ; GFX9-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[ADD34]], [[UMULH29]]
; GFX9-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV48]], [[MUL33]] ; GFX9-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV48]], [[MUL33]]
; GFX9-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV49]], [[ADD37]], [[USUBO11]] ; GFX9-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV49]], [[ADD35]], [[USUBO11]]
; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV49]], [[ADD37]] ; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV49]], [[ADD35]]
; GFX9-NEXT: [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64) ; GFX9-NEXT: [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR5]](s64)
; GFX9-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE12]](s32), [[UV55]] ; GFX9-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE12]](s32), [[UV55]]
; GFX9-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1) ; GFX9-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1)
; GFX9-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV54]] ; GFX9-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV54]]
; GFX9-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1) ; GFX9-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1)
; GFX9-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE12]](s32), [[UV55]] ; GFX9-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE12]](s32), [[UV55]]
; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]] ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]]
; GFX9-NEXT: [[USUBO12:%[0-9]+]]:_(s32), [[USUBO13:%[0-9]+]]:_(s1) = G_USUBO [[USUBO10]], [[UV54]] ; GFX9-NEXT: [[USUBO12:%[0-9]+]]:_(s32), [[USUBO13:%[0-9]+]]:_(s1) = G_USUBO [[USUBO10]], [[UV54]]
; GFX9-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[SUB1]], [[UV55]], [[USUBO11]] ; GFX9-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[SUB1]], [[UV55]], [[USUBO11]]
; GFX9-NEXT: [[USUBE16:%[0-9]+]]:_(s32), [[USUBE17:%[0-9]+]]:_(s1) = G_USUBE [[USUBE14]], [[C6]], [[USUBO13]] ; GFX9-NEXT: [[USUBE16:%[0-9]+]]:_(s32), [[USUBE17:%[0-9]+]]:_(s1) = G_USUBE [[USUBE14]], [[C6]], [[USUBO13]]
; GFX9-NEXT: [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX9-NEXT: [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX9-NEXT: [[UADDO80:%[0-9]+]]:_(s32), [[UADDO81:%[0-9]+]]:_(s1) = G_UADDO [[UADDO78]], [[UV56]] ; GFX9-NEXT: [[UADDO80:%[0-9]+]]:_(s32), [[UADDO81:%[0-9]+]]:_(s1) = G_UADDO [[UADDO78]], [[UV56]]
; GFX9-NEXT: [[UADDE24:%[0-9]+]]:_(s32), [[UADDE25:%[0-9]+]]:_(s1) = G_UADDE [[ADD35]], [[UV57]], [[UADDO81]] ; GFX9-NEXT: [[UADDE20:%[0-9]+]]:_(s32), [[UADDE21:%[0-9]+]]:_(s1) = G_UADDE [[ADD33]], [[UV57]], [[UADDO81]]
; GFX9-NEXT: [[MV9:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO80]](s32), [[UADDE24]](s32) ; GFX9-NEXT: [[MV9:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO80]](s32), [[UADDE20]](s32)
; GFX9-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE16]](s32), [[UV55]] ; GFX9-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE16]](s32), [[UV55]]
; GFX9-NEXT: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[ICMP11]](s1) ; GFX9-NEXT: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[ICMP11]](s1)
; GFX9-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO12]](s32), [[UV54]] ; GFX9-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO12]](s32), [[UV54]]
; GFX9-NEXT: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[ICMP12]](s1) ; GFX9-NEXT: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[ICMP12]](s1)
; GFX9-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE16]](s32), [[UV55]] ; GFX9-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE16]](s32), [[UV55]]
; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP13]](s1), [[SEXT7]], [[SEXT6]] ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP13]](s1), [[SEXT7]], [[SEXT6]]
; GFX9-NEXT: [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX9-NEXT: [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX9-NEXT: [[UADDO82:%[0-9]+]]:_(s32), [[UADDO83:%[0-9]+]]:_(s1) = G_UADDO [[UADDO80]], [[UV58]] ; GFX9-NEXT: [[UADDO82:%[0-9]+]]:_(s32), [[UADDO83:%[0-9]+]]:_(s1) = G_UADDO [[UADDO80]], [[UV58]]
; GFX9-NEXT: [[UADDE26:%[0-9]+]]:_(s32), [[UADDE27:%[0-9]+]]:_(s1) = G_UADDE [[UADDE24]], [[UV59]], [[UADDO83]] ; GFX9-NEXT: [[UADDE22:%[0-9]+]]:_(s32), [[UADDE23:%[0-9]+]]:_(s1) = G_UADDE [[UADDE20]], [[UV59]], [[UADDO83]]
; GFX9-NEXT: [[MV10:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO82]](s32), [[UADDE26]](s32) ; GFX9-NEXT: [[MV10:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO82]](s32), [[UADDE22]](s32)
; GFX9-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT5]](s32), [[C6]] ; GFX9-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT5]](s32), [[C6]]
; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP14]](s1), [[MV10]], [[MV9]] ; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP14]](s1), [[MV10]], [[MV9]]
; GFX9-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT4]](s32), [[C6]] ; GFX9-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT4]](s32), [[C6]]
; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV8]] ; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV8]]
; GFX9-NEXT: [[XOR6:%[0-9]+]]:_(s64) = G_XOR [[ASHR2]], [[ASHR3]] ; GFX9-NEXT: [[XOR6:%[0-9]+]]:_(s64) = G_XOR [[ASHR2]], [[ASHR3]]
; GFX9-NEXT: [[XOR7:%[0-9]+]]:_(s64) = G_XOR [[SELECT7]], [[XOR6]] ; GFX9-NEXT: [[XOR7:%[0-9]+]]:_(s64) = G_XOR [[SELECT7]], [[XOR6]]
; GFX9-NEXT: [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR7]](s64) ; GFX9-NEXT: [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR7]](s64)
; GFX9-NEXT: [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR6]](s64) ; GFX9-NEXT: [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR6]](s64)
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; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]] ; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]]
; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE8]] ; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE6]]
; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]] ; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]]
; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE8]] ; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE6]]
; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]] ; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]]
; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE8]] ; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE6]]
; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE8]] ; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE6]]
; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD16]](s32) ; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD15]](s32)
; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]] ; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]]
; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]] ; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]]
; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD16]] ; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD15]]
; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]] ; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]]
; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]] ; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD18]], [[USUBO3]] ; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD17]], [[USUBO3]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD18]] ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD17]]
; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]] ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]]
; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]] ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]]
; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX6-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV20]] ; GFX6-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV20]]
; GFX6-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV21]], [[USUBO3]] ; GFX6-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV21]], [[USUBO3]]
; GFX6-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]] ; GFX6-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]]
; GFX6-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX6-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX6-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX6-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV22]] ; GFX6-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV22]]
; GFX6-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV23]], [[UADDO39]] ; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV23]], [[UADDO39]]
; GFX6-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE10]](s32) ; GFX6-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE8]](s32)
; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV21]] ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV21]]
; GFX6-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX6-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV20]] ; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV20]]
; GFX6-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX6-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV21]] ; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV21]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX6-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX6-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX6-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV24]] ; GFX6-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV24]]
; GFX6-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UADDE10]], [[UV25]], [[UADDO41]] ; GFX6-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[UV25]], [[UADDO41]]
; GFX6-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE12]](s32) ; GFX6-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE10]](s32)
; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]] ; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]] ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]]
; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]] ; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]] ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]]
; GFX6-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]] ; GFX6-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]] ; GFX6-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]]
; GFX6-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX6-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX6-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64) ; GFX6-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64)
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; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]] ; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]]
; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE8]] ; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE6]]
; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]] ; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]]
; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE8]] ; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE6]]
; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]] ; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]]
; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE8]] ; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE6]]
; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE8]] ; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE6]]
; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD16]](s32) ; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD15]](s32)
; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]] ; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]]
; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]] ; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]]
; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD16]] ; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD15]]
; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]] ; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]]
; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]] ; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD18]], [[USUBO3]] ; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD17]], [[USUBO3]]
; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD18]] ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD17]]
; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]] ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]] ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]]
; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]] ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX8-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV20]] ; GFX8-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV20]]
; GFX8-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV21]], [[USUBO3]] ; GFX8-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV21]], [[USUBO3]]
; GFX8-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]] ; GFX8-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]]
; GFX8-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX8-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX8-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX8-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX8-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV22]] ; GFX8-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV22]]
; GFX8-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV23]], [[UADDO39]] ; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV23]], [[UADDO39]]
; GFX8-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE10]](s32) ; GFX8-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE8]](s32)
; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV21]] ; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV21]]
; GFX8-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX8-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX8-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV20]] ; GFX8-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV20]]
; GFX8-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX8-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX8-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV21]] ; GFX8-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV21]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX8-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX8-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX8-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV24]] ; GFX8-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV24]]
; GFX8-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UADDE10]], [[UV25]], [[UADDO41]] ; GFX8-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[UV25]], [[UADDO41]]
; GFX8-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE12]](s32) ; GFX8-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE10]](s32)
; GFX8-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]] ; GFX8-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]] ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]]
; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]] ; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]] ; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]]
; GFX8-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]] ; GFX8-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]] ; GFX8-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]]
; GFX8-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX8-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX8-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64) ; GFX8-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64)
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; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]] ; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]]
; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE8]] ; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE6]]
; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]] ; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]]
; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE8]] ; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE6]]
; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]] ; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]]
; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE8]] ; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE6]]
; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE8]] ; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE6]]
; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD16]](s32) ; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[ADD15]](s32)
; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]] ; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]]
; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]] ; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]]
; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD16]] ; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD15]]
; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]] ; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]]
; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]] ; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD18]], [[USUBO3]] ; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD17]], [[USUBO3]]
; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD18]] ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD17]]
; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]] ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]]
; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]] ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]]
; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]] ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX9-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV20]] ; GFX9-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV20]]
; GFX9-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV21]], [[USUBO3]] ; GFX9-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV21]], [[USUBO3]]
; GFX9-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]] ; GFX9-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]]
; GFX9-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX9-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX9-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX9-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV22]] ; GFX9-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UADDO36]], [[UV22]]
; GFX9-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV23]], [[UADDO39]] ; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV23]], [[UADDO39]]
; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE10]](s32) ; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE8]](s32)
; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV21]] ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV21]]
; GFX9-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX9-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV20]] ; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV20]]
; GFX9-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX9-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV21]] ; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV21]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX9-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX9-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX9-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV24]] ; GFX9-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UV24]]
; GFX9-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UADDE10]], [[UV25]], [[UADDO41]] ; GFX9-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[UV25]], [[UADDO41]]
; GFX9-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE12]](s32) ; GFX9-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE10]](s32)
; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]] ; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]] ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV4]], [[MV3]]
; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]] ; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]] ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV2]]
; GFX9-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]] ; GFX9-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]] ; GFX9-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[XOR2]]
; GFX9-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX9-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX9-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64) ; GFX9-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR2]](s64)
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llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir

Show First 20 Lines • Show All 376 Lines • ▼ Show 20 Lines bb.0:
; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]] ; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]]
; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE8]] ; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE6]]
; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]] ; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]]
; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE8]] ; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE6]]
; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]] ; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]]
; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE8]] ; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE6]]
; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE8]] ; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE6]]
; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]] ; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]]
; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]] ; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]]
; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD16]] ; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD15]]
; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]] ; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]]
; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]] ; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD18]], [[USUBO3]] ; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD17]], [[USUBO3]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD18]] ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD17]]
; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]] ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]]
; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]] ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]]
; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]] ; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]]
; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE8]] ; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE6]]
; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]] ; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]]
; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE8]] ; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE6]]
; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]] ; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]]
; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE8]] ; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE6]]
; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE8]] ; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE6]]
; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]] ; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]]
; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]] ; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]]
; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD16]] ; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD15]]
; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]] ; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]]
; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]] ; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD18]], [[USUBO3]] ; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD17]], [[USUBO3]]
; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD18]] ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD17]]
; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]] ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]] ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]]
; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]] ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]] ; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]]
; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE8]] ; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE6]]
; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]] ; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]]
; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE8]] ; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE6]]
; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]] ; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]]
; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE8]] ; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE6]]
; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE8]] ; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE6]]
; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]] ; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]]
; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]] ; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]]
; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD16]] ; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD15]]
; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]] ; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]]
; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]] ; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD18]], [[USUBO3]] ; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD17]], [[USUBO3]]
; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD18]] ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD17]]
; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]] ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]]
; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]] ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]]
; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]] ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDO26]] ; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDO26]]
; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV20]], [[UADDE8]] ; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV20]], [[UADDE6]]
; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDO26]] ; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDO26]]
; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDE8]] ; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDE6]]
; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDO26]] ; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDO26]]
; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDE8]] ; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDE6]]
; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDE8]] ; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDE6]]
; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX6-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX6-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[UADDO36]] ; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[UADDO36]]
; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV23]], [[UADDO36]] ; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV23]], [[UADDO36]]
; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[ADD16]] ; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[ADD15]]
; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV22]], [[UADDO36]] ; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV22]], [[UADDO36]]
; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV18]], [[MUL15]] ; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV18]], [[MUL15]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV19]], [[ADD18]], [[USUBO3]] ; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV19]], [[ADD17]], [[USUBO3]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV19]], [[ADD18]] ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV19]], [[ADD17]]
; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX6-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX6-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV25]] ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV25]]
; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV24]] ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV24]]
; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV25]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV25]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX6-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV26]], [[UV28]] ; GFX6-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV26]], [[UV28]]
; GFX6-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV27]], [[UV29]], [[USUBO9]] ; GFX6-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV27]], [[UV29]], [[USUBO9]]
; GFX6-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO8]](s32), [[USUBE12]](s32) ; GFX6-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO8]](s32), [[USUBE12]](s32)
; GFX6-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; GFX6-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; GFX6-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C]](s32) ; GFX6-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C]](s32)
; GFX6-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX6-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX6-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR2]](s64) ; GFX6-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR2]](s64)
; GFX6-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UV30]], [[UV32]] ; GFX6-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UV30]], [[UV32]]
; GFX6-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UV31]], [[UV33]], [[UADDO39]] ; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UV31]], [[UV33]], [[UADDO39]]
; GFX6-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE10]](s32) ; GFX6-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE8]](s32)
; GFX6-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX6-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX6-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR3]](s64) ; GFX6-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR3]](s64)
; GFX6-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UV34]], [[UV36]] ; GFX6-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UV34]], [[UV36]]
; GFX6-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UV35]], [[UV37]], [[UADDO41]] ; GFX6-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UV35]], [[UV37]], [[UADDO41]]
; GFX6-NEXT: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE12]](s32) ; GFX6-NEXT: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE10]](s32)
; GFX6-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[MV6]], [[ASHR2]] ; GFX6-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[MV6]], [[ASHR2]]
; GFX6-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[MV7]], [[ASHR3]] ; GFX6-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[MV7]], [[ASHR3]]
; GFX6-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX6-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX6-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV38]](s32) ; GFX6-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV38]](s32)
; GFX6-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV39]](s32) ; GFX6-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV39]](s32)
; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
; GFX6-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP3]], [[C7]] ; GFX6-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP3]], [[C7]]
; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL4]], [[UITOFP2]] ; GFX6-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL4]], [[UITOFP2]]
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; GFX6-NEXT: [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C5]](s64) ; GFX6-NEXT: [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C5]](s64)
; GFX6-NEXT: [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX6-NEXT: [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX6-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV40]], [[UV42]] ; GFX6-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV40]], [[UV42]]
; GFX6-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[UV41]], [[UV43]], [[USUBO11]] ; GFX6-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[UV41]], [[UV43]], [[USUBO11]]
; GFX6-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[FPTOUI2]] ; GFX6-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[FPTOUI2]]
; GFX6-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE14]], [[FPTOUI2]] ; GFX6-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE14]], [[FPTOUI2]]
; GFX6-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[FPTOUI3]] ; GFX6-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[FPTOUI3]]
; GFX6-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO10]], [[FPTOUI2]] ; GFX6-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO10]], [[FPTOUI2]]
; GFX6-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]] ; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]]
; GFX6-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ADD19]], [[UMULH15]] ; GFX6-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[ADD18]], [[UMULH15]]
; GFX6-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]] ; GFX6-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]]
; GFX6-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD20]] ; GFX6-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD19]]
; GFX6-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]] ; GFX6-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]]
; GFX6-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]] ; GFX6-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]]
; GFX6-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1) ; GFX6-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1)
; GFX6-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UADDO42]], [[UMULH16]] ; GFX6-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UADDO42]], [[UMULH16]]
; GFX6-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO45]](s1) ; GFX6-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO45]](s1)
; GFX6-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]] ; GFX6-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]]
; GFX6-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD20]] ; GFX6-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD19]]
; GFX6-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]] ; GFX6-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]]
; GFX6-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD20]] ; GFX6-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD19]]
; GFX6-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]] ; GFX6-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]]
; GFX6-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1) ; GFX6-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1)
; GFX6-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH18]] ; GFX6-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH18]]
; GFX6-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1) ; GFX6-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1)
; GFX6-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]] ; GFX6-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]]
; GFX6-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[UADDO48]], [[ADD21]] ; GFX6-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[UADDO48]], [[ADD20]]
; GFX6-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1) ; GFX6-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1)
; GFX6-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[ADD22]], [[ZEXT19]] ; GFX6-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ADD21]], [[ZEXT19]]
; GFX6-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD20]] ; GFX6-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD19]]
; GFX6-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD23]] ; GFX6-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD22]]
; GFX6-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO50]] ; GFX6-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO50]]
; GFX6-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD24]], [[UADDO53]] ; GFX6-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD23]], [[UADDO53]]
; GFX6-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI3]], [[ADD24]]
; GFX6-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[UADDO52]] ; GFX6-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[UADDO52]]
; GFX6-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE14]], [[UADDO52]] ; GFX6-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE14]], [[UADDO52]]
; GFX6-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[UADDE14]] ; GFX6-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[UADDE12]]
; GFX6-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO10]], [[UADDO52]] ; GFX6-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO10]], [[UADDO52]]
; GFX6-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]] ; GFX6-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]]
; GFX6-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ADD26]], [[UMULH20]] ; GFX6-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[ADD24]], [[UMULH20]]
; GFX6-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE14]], [[MUL24]] ; GFX6-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE12]], [[MUL24]]
; GFX6-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO52]], [[ADD27]] ; GFX6-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO52]], [[ADD25]]
; GFX6-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO52]], [[MUL24]] ; GFX6-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO52]], [[MUL24]]
; GFX6-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]] ; GFX6-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]]
; GFX6-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1) ; GFX6-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1)
; GFX6-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO54]], [[UMULH21]] ; GFX6-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO54]], [[UMULH21]]
; GFX6-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO57]](s1) ; GFX6-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO57]](s1)
; GFX6-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]] ; GFX6-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]]
; GFX6-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE14]], [[ADD27]] ; GFX6-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE12]], [[ADD25]]
; GFX6-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE14]], [[MUL24]] ; GFX6-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE12]], [[MUL24]]
; GFX6-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO52]], [[ADD27]] ; GFX6-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO52]], [[ADD25]]
; GFX6-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]] ; GFX6-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]]
; GFX6-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1) ; GFX6-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1)
; GFX6-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH23]] ; GFX6-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH23]]
; GFX6-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1) ; GFX6-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1)
; GFX6-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]] ; GFX6-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]]
; GFX6-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[UADDO60]], [[ADD28]] ; GFX6-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[UADDO60]], [[ADD26]]
; GFX6-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1) ; GFX6-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1)
; GFX6-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ADD29]], [[ZEXT24]] ; GFX6-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ADD27]], [[ZEXT24]]
; GFX6-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE14]], [[ADD27]] ; GFX6-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE12]], [[ADD25]]
; GFX6-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD30]] ; GFX6-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD28]]
; GFX6-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[UADDO62]] ; GFX6-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[UADDO62]]
; GFX6-NEXT: [[UADDE16:%[0-9]+]]:_(s32), [[UADDE17:%[0-9]+]]:_(s1) = G_UADDE [[ADD25]], [[ADD31]], [[UADDO53]] ; GFX6-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UADDE12]], [[ADD29]], [[UADDO65]]
; GFX6-NEXT: [[UADDE18:%[0-9]+]]:_(s32), [[UADDE19:%[0-9]+]]:_(s1) = G_UADDE [[UADDE16]], [[C6]], [[UADDO65]]
; GFX6-NEXT: [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX6-NEXT: [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX6-NEXT: [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX6-NEXT: [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX6-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV47]], [[UADDO64]] ; GFX6-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV47]], [[UADDO64]]
; GFX6-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV46]], [[UADDE18]] ; GFX6-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV46]], [[UADDE14]]
; GFX6-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV46]], [[UADDO64]] ; GFX6-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV46]], [[UADDO64]]
; GFX6-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]] ; GFX6-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]]
; GFX6-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1) ; GFX6-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1)
; GFX6-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO66]], [[UMULH25]] ; GFX6-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO66]], [[UMULH25]]
; GFX6-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO69]](s1) ; GFX6-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO69]](s1)
; GFX6-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]] ; GFX6-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]]
; GFX6-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV47]], [[UADDE18]] ; GFX6-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV47]], [[UADDE14]]
; GFX6-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV47]], [[UADDO64]] ; GFX6-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV47]], [[UADDO64]]
; GFX6-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV46]], [[UADDE18]] ; GFX6-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV46]], [[UADDE14]]
; GFX6-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]] ; GFX6-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]]
; GFX6-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1) ; GFX6-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1)
; GFX6-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UMULH27]] ; GFX6-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UMULH27]]
; GFX6-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO73]](s1) ; GFX6-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO73]](s1)
; GFX6-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]] ; GFX6-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]]
; GFX6-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[UADDO72]], [[ADD32]] ; GFX6-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[UADDO72]], [[ADD30]]
; GFX6-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO75]](s1) ; GFX6-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO75]](s1)
; GFX6-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[ADD33]], [[ZEXT29]] ; GFX6-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ADD31]], [[ZEXT29]]
; GFX6-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV47]], [[UADDE18]] ; GFX6-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV47]], [[UADDE14]]
; GFX6-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD34]] ; GFX6-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD32]]
; GFX6-NEXT: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX6-NEXT: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX6-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV48]], [[UADDO74]] ; GFX6-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV48]], [[UADDO74]]
; GFX6-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV49]], [[UADDO74]] ; GFX6-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV49]], [[UADDO74]]
; GFX6-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV48]], [[ADD35]] ; GFX6-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV48]], [[ADD33]]
; GFX6-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV48]], [[UADDO74]] ; GFX6-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV48]], [[UADDO74]]
; GFX6-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]] ; GFX6-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]]
; GFX6-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[ADD36]], [[UMULH29]] ; GFX6-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[ADD34]], [[UMULH29]]
; GFX6-NEXT: [[USUBO12:%[0-9]+]]:_(s32), [[USUBO13:%[0-9]+]]:_(s1) = G_USUBO [[UV44]], [[MUL33]] ; GFX6-NEXT: [[USUBO12:%[0-9]+]]:_(s32), [[USUBO13:%[0-9]+]]:_(s1) = G_USUBO [[UV44]], [[MUL33]]
; GFX6-NEXT: [[USUBE16:%[0-9]+]]:_(s32), [[USUBE17:%[0-9]+]]:_(s1) = G_USUBE [[UV45]], [[ADD37]], [[USUBO13]] ; GFX6-NEXT: [[USUBE16:%[0-9]+]]:_(s32), [[USUBE17:%[0-9]+]]:_(s1) = G_USUBE [[UV45]], [[ADD35]], [[USUBO13]]
; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV45]], [[ADD37]] ; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV45]], [[ADD35]]
; GFX6-NEXT: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO12]](s32), [[USUBE16]](s32) ; GFX6-NEXT: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO12]](s32), [[USUBE16]](s32)
; GFX6-NEXT: [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX6-NEXT: [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX6-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE16]](s32), [[UV51]] ; GFX6-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE16]](s32), [[UV51]]
; GFX6-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1) ; GFX6-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1)
; GFX6-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO12]](s32), [[UV50]] ; GFX6-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO12]](s32), [[UV50]]
; GFX6-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1) ; GFX6-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1)
; GFX6-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE16]](s32), [[UV51]] ; GFX6-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE16]](s32), [[UV51]]
; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]] ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]]
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; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDO26]] ; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDO26]]
; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV20]], [[UADDE8]] ; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV20]], [[UADDE6]]
; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDO26]] ; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDO26]]
; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDE8]] ; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDE6]]
; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDO26]] ; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDO26]]
; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDE8]] ; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDE6]]
; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDE8]] ; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDE6]]
; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX8-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX8-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[UADDO36]] ; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[UADDO36]]
; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV23]], [[UADDO36]] ; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV23]], [[UADDO36]]
; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[ADD16]] ; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[ADD15]]
; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV22]], [[UADDO36]] ; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV22]], [[UADDO36]]
; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV18]], [[MUL15]] ; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV18]], [[MUL15]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV19]], [[ADD18]], [[USUBO3]] ; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV19]], [[ADD17]], [[USUBO3]]
; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV19]], [[ADD18]] ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV19]], [[ADD17]]
; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX8-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX8-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV25]] ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV25]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV24]] ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV24]]
; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV25]] ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV25]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX8-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV26]], [[UV28]] ; GFX8-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV26]], [[UV28]]
; GFX8-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV27]], [[UV29]], [[USUBO9]] ; GFX8-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV27]], [[UV29]], [[USUBO9]]
; GFX8-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO8]](s32), [[USUBE12]](s32) ; GFX8-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO8]](s32), [[USUBE12]](s32)
; GFX8-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; GFX8-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; GFX8-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C]](s32) ; GFX8-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C]](s32)
; GFX8-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX8-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX8-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR2]](s64) ; GFX8-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR2]](s64)
; GFX8-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UV30]], [[UV32]] ; GFX8-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UV30]], [[UV32]]
; GFX8-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UV31]], [[UV33]], [[UADDO39]] ; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UV31]], [[UV33]], [[UADDO39]]
; GFX8-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE10]](s32) ; GFX8-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE8]](s32)
; GFX8-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX8-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX8-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR3]](s64) ; GFX8-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR3]](s64)
; GFX8-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UV34]], [[UV36]] ; GFX8-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UV34]], [[UV36]]
; GFX8-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UV35]], [[UV37]], [[UADDO41]] ; GFX8-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UV35]], [[UV37]], [[UADDO41]]
; GFX8-NEXT: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE12]](s32) ; GFX8-NEXT: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE10]](s32)
; GFX8-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[MV6]], [[ASHR2]] ; GFX8-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[MV6]], [[ASHR2]]
; GFX8-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[MV7]], [[ASHR3]] ; GFX8-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[MV7]], [[ASHR3]]
; GFX8-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX8-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX8-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV38]](s32) ; GFX8-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV38]](s32)
; GFX8-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV39]](s32) ; GFX8-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV39]](s32)
; GFX8-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 ; GFX8-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
; GFX8-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP3]], [[C7]] ; GFX8-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP3]], [[C7]]
; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL4]], [[UITOFP2]] ; GFX8-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL4]], [[UITOFP2]]
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; GFX8-NEXT: [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C5]](s64) ; GFX8-NEXT: [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C5]](s64)
; GFX8-NEXT: [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX8-NEXT: [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX8-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV40]], [[UV42]] ; GFX8-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV40]], [[UV42]]
; GFX8-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[UV41]], [[UV43]], [[USUBO11]] ; GFX8-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[UV41]], [[UV43]], [[USUBO11]]
; GFX8-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[FPTOUI2]] ; GFX8-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[FPTOUI2]]
; GFX8-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE14]], [[FPTOUI2]] ; GFX8-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE14]], [[FPTOUI2]]
; GFX8-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[FPTOUI3]] ; GFX8-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[FPTOUI3]]
; GFX8-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO10]], [[FPTOUI2]] ; GFX8-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO10]], [[FPTOUI2]]
; GFX8-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]] ; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]]
; GFX8-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ADD19]], [[UMULH15]] ; GFX8-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[ADD18]], [[UMULH15]]
; GFX8-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]] ; GFX8-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]]
; GFX8-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD20]] ; GFX8-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD19]]
; GFX8-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]] ; GFX8-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]]
; GFX8-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]] ; GFX8-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]]
; GFX8-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1) ; GFX8-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1)
; GFX8-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UADDO42]], [[UMULH16]] ; GFX8-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UADDO42]], [[UMULH16]]
; GFX8-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO45]](s1) ; GFX8-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO45]](s1)
; GFX8-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]] ; GFX8-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]]
; GFX8-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD20]] ; GFX8-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD19]]
; GFX8-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]] ; GFX8-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]]
; GFX8-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD20]] ; GFX8-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD19]]
; GFX8-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]] ; GFX8-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]]
; GFX8-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1) ; GFX8-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1)
; GFX8-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH18]] ; GFX8-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH18]]
; GFX8-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1) ; GFX8-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1)
; GFX8-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]] ; GFX8-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]]
; GFX8-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[UADDO48]], [[ADD21]] ; GFX8-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[UADDO48]], [[ADD20]]
; GFX8-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1) ; GFX8-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1)
; GFX8-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[ADD22]], [[ZEXT19]] ; GFX8-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ADD21]], [[ZEXT19]]
; GFX8-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD20]] ; GFX8-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD19]]
; GFX8-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD23]] ; GFX8-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD22]]
; GFX8-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO50]] ; GFX8-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO50]]
; GFX8-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD24]], [[UADDO53]] ; GFX8-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD23]], [[UADDO53]]
; GFX8-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI3]], [[ADD24]]
; GFX8-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[UADDO52]] ; GFX8-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[UADDO52]]
; GFX8-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE14]], [[UADDO52]] ; GFX8-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE14]], [[UADDO52]]
; GFX8-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[UADDE14]] ; GFX8-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[UADDE12]]
; GFX8-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO10]], [[UADDO52]] ; GFX8-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO10]], [[UADDO52]]
; GFX8-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]] ; GFX8-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]]
; GFX8-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ADD26]], [[UMULH20]] ; GFX8-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[ADD24]], [[UMULH20]]
; GFX8-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE14]], [[MUL24]] ; GFX8-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE12]], [[MUL24]]
; GFX8-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO52]], [[ADD27]] ; GFX8-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO52]], [[ADD25]]
; GFX8-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO52]], [[MUL24]] ; GFX8-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO52]], [[MUL24]]
; GFX8-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]] ; GFX8-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]]
; GFX8-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1) ; GFX8-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1)
; GFX8-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO54]], [[UMULH21]] ; GFX8-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO54]], [[UMULH21]]
; GFX8-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO57]](s1) ; GFX8-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO57]](s1)
; GFX8-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]] ; GFX8-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]]
; GFX8-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE14]], [[ADD27]] ; GFX8-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE12]], [[ADD25]]
; GFX8-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE14]], [[MUL24]] ; GFX8-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE12]], [[MUL24]]
; GFX8-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO52]], [[ADD27]] ; GFX8-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO52]], [[ADD25]]
; GFX8-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]] ; GFX8-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]]
; GFX8-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1) ; GFX8-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1)
; GFX8-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH23]] ; GFX8-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH23]]
; GFX8-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1) ; GFX8-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1)
; GFX8-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]] ; GFX8-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]]
; GFX8-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[UADDO60]], [[ADD28]] ; GFX8-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[UADDO60]], [[ADD26]]
; GFX8-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1) ; GFX8-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1)
; GFX8-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ADD29]], [[ZEXT24]] ; GFX8-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ADD27]], [[ZEXT24]]
; GFX8-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE14]], [[ADD27]] ; GFX8-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE12]], [[ADD25]]
; GFX8-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD30]] ; GFX8-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD28]]
; GFX8-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[UADDO62]] ; GFX8-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[UADDO62]]
; GFX8-NEXT: [[UADDE16:%[0-9]+]]:_(s32), [[UADDE17:%[0-9]+]]:_(s1) = G_UADDE [[ADD25]], [[ADD31]], [[UADDO53]] ; GFX8-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UADDE12]], [[ADD29]], [[UADDO65]]
; GFX8-NEXT: [[UADDE18:%[0-9]+]]:_(s32), [[UADDE19:%[0-9]+]]:_(s1) = G_UADDE [[UADDE16]], [[C6]], [[UADDO65]]
; GFX8-NEXT: [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX8-NEXT: [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX8-NEXT: [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX8-NEXT: [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX8-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV47]], [[UADDO64]] ; GFX8-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV47]], [[UADDO64]]
; GFX8-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV46]], [[UADDE18]] ; GFX8-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV46]], [[UADDE14]]
; GFX8-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV46]], [[UADDO64]] ; GFX8-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV46]], [[UADDO64]]
; GFX8-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]] ; GFX8-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]]
; GFX8-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1) ; GFX8-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1)
; GFX8-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO66]], [[UMULH25]] ; GFX8-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO66]], [[UMULH25]]
; GFX8-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO69]](s1) ; GFX8-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO69]](s1)
; GFX8-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]] ; GFX8-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]]
; GFX8-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV47]], [[UADDE18]] ; GFX8-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV47]], [[UADDE14]]
; GFX8-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV47]], [[UADDO64]] ; GFX8-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV47]], [[UADDO64]]
; GFX8-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV46]], [[UADDE18]] ; GFX8-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV46]], [[UADDE14]]
; GFX8-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]] ; GFX8-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]]
; GFX8-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1) ; GFX8-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1)
; GFX8-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UMULH27]] ; GFX8-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UMULH27]]
; GFX8-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO73]](s1) ; GFX8-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO73]](s1)
; GFX8-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]] ; GFX8-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]]
; GFX8-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[UADDO72]], [[ADD32]] ; GFX8-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[UADDO72]], [[ADD30]]
; GFX8-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO75]](s1) ; GFX8-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO75]](s1)
; GFX8-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[ADD33]], [[ZEXT29]] ; GFX8-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ADD31]], [[ZEXT29]]
; GFX8-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV47]], [[UADDE18]] ; GFX8-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV47]], [[UADDE14]]
; GFX8-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD34]] ; GFX8-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD32]]
; GFX8-NEXT: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX8-NEXT: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX8-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV48]], [[UADDO74]] ; GFX8-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV48]], [[UADDO74]]
; GFX8-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV49]], [[UADDO74]] ; GFX8-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV49]], [[UADDO74]]
; GFX8-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV48]], [[ADD35]] ; GFX8-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV48]], [[ADD33]]
; GFX8-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV48]], [[UADDO74]] ; GFX8-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV48]], [[UADDO74]]
; GFX8-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]] ; GFX8-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]]
; GFX8-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[ADD36]], [[UMULH29]] ; GFX8-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[ADD34]], [[UMULH29]]
; GFX8-NEXT: [[USUBO12:%[0-9]+]]:_(s32), [[USUBO13:%[0-9]+]]:_(s1) = G_USUBO [[UV44]], [[MUL33]] ; GFX8-NEXT: [[USUBO12:%[0-9]+]]:_(s32), [[USUBO13:%[0-9]+]]:_(s1) = G_USUBO [[UV44]], [[MUL33]]
; GFX8-NEXT: [[USUBE16:%[0-9]+]]:_(s32), [[USUBE17:%[0-9]+]]:_(s1) = G_USUBE [[UV45]], [[ADD37]], [[USUBO13]] ; GFX8-NEXT: [[USUBE16:%[0-9]+]]:_(s32), [[USUBE17:%[0-9]+]]:_(s1) = G_USUBE [[UV45]], [[ADD35]], [[USUBO13]]
; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV45]], [[ADD37]] ; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV45]], [[ADD35]]
; GFX8-NEXT: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO12]](s32), [[USUBE16]](s32) ; GFX8-NEXT: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO12]](s32), [[USUBE16]](s32)
; GFX8-NEXT: [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX8-NEXT: [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX8-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE16]](s32), [[UV51]] ; GFX8-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE16]](s32), [[UV51]]
; GFX8-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1) ; GFX8-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1)
; GFX8-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO12]](s32), [[UV50]] ; GFX8-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO12]](s32), [[UV50]]
; GFX8-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1) ; GFX8-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1)
; GFX8-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE16]](s32), [[UV51]] ; GFX8-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE16]](s32), [[UV51]]
; GFX8-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]] ; GFX8-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]]
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; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDO26]] ; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDO26]]
; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV20]], [[UADDE8]] ; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV20]], [[UADDE6]]
; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDO26]] ; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDO26]]
; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDE8]] ; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV21]], [[UADDE6]]
; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDO26]] ; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDO26]]
; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDE8]] ; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV20]], [[UADDE6]]
; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDE8]] ; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV21]], [[UADDE6]]
; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX9-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX9-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[UADDO36]] ; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[UADDO36]]
; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV23]], [[UADDO36]] ; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV23]], [[UADDO36]]
; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[ADD16]] ; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV22]], [[ADD15]]
; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV22]], [[UADDO36]] ; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV22]], [[UADDO36]]
; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV18]], [[MUL15]] ; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV18]], [[MUL15]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV19]], [[ADD18]], [[USUBO3]] ; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV19]], [[ADD17]], [[USUBO3]]
; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV19]], [[ADD18]] ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV19]], [[ADD17]]
; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX9-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX9-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV25]] ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV25]]
; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV24]] ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV24]]
; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV25]] ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV25]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX9-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV26]], [[UV28]] ; GFX9-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV26]], [[UV28]]
; GFX9-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV27]], [[UV29]], [[USUBO9]] ; GFX9-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV27]], [[UV29]], [[USUBO9]]
; GFX9-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO8]](s32), [[USUBE12]](s32) ; GFX9-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO8]](s32), [[USUBE12]](s32)
; GFX9-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32) ; GFX9-NEXT: [[ASHR2:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
; GFX9-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C]](s32) ; GFX9-NEXT: [[ASHR3:%[0-9]+]]:_(s64) = G_ASHR [[UV3]], [[C]](s32)
; GFX9-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX9-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX9-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR2]](s64) ; GFX9-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR2]](s64)
; GFX9-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UV30]], [[UV32]] ; GFX9-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[UV30]], [[UV32]]
; GFX9-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UV31]], [[UV33]], [[UADDO39]] ; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UV31]], [[UV33]], [[UADDO39]]
; GFX9-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE10]](s32) ; GFX9-NEXT: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO38]](s32), [[UADDE8]](s32)
; GFX9-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX9-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX9-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR3]](s64) ; GFX9-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR3]](s64)
; GFX9-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UV34]], [[UV36]] ; GFX9-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UV34]], [[UV36]]
; GFX9-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[UV35]], [[UV37]], [[UADDO41]] ; GFX9-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UV35]], [[UV37]], [[UADDO41]]
; GFX9-NEXT: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE12]](s32) ; GFX9-NEXT: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO40]](s32), [[UADDE10]](s32)
; GFX9-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[MV6]], [[ASHR2]] ; GFX9-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[MV6]], [[ASHR2]]
; GFX9-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[MV7]], [[ASHR3]] ; GFX9-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[MV7]], [[ASHR3]]
; GFX9-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX9-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX9-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV38]](s32) ; GFX9-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV38]](s32)
; GFX9-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV39]](s32) ; GFX9-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV39]](s32)
; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
; GFX9-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP3]], [[C7]] ; GFX9-NEXT: [[FMUL4:%[0-9]+]]:_(s32) = G_FMUL [[UITOFP3]], [[C7]]
; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL4]], [[UITOFP2]] ; GFX9-NEXT: [[FADD2:%[0-9]+]]:_(s32) = G_FADD [[FMUL4]], [[UITOFP2]]
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; GFX9-NEXT: [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C5]](s64) ; GFX9-NEXT: [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C5]](s64)
; GFX9-NEXT: [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX9-NEXT: [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX9-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV40]], [[UV42]] ; GFX9-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV40]], [[UV42]]
; GFX9-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[UV41]], [[UV43]], [[USUBO11]] ; GFX9-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[UV41]], [[UV43]], [[USUBO11]]
; GFX9-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[FPTOUI2]] ; GFX9-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[FPTOUI2]]
; GFX9-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE14]], [[FPTOUI2]] ; GFX9-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE14]], [[FPTOUI2]]
; GFX9-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[FPTOUI3]] ; GFX9-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[FPTOUI3]]
; GFX9-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO10]], [[FPTOUI2]] ; GFX9-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO10]], [[FPTOUI2]]
; GFX9-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]] ; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]]
; GFX9-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ADD19]], [[UMULH15]] ; GFX9-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[ADD18]], [[UMULH15]]
; GFX9-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]] ; GFX9-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]]
; GFX9-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD20]] ; GFX9-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD19]]
; GFX9-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]] ; GFX9-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]]
; GFX9-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]] ; GFX9-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]]
; GFX9-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1) ; GFX9-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1)
; GFX9-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UADDO42]], [[UMULH16]] ; GFX9-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UADDO42]], [[UMULH16]]
; GFX9-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO45]](s1) ; GFX9-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO45]](s1)
; GFX9-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]] ; GFX9-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]]
; GFX9-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD20]] ; GFX9-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD19]]
; GFX9-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]] ; GFX9-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]]
; GFX9-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD20]] ; GFX9-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD19]]
; GFX9-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]] ; GFX9-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]]
; GFX9-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1) ; GFX9-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1)
; GFX9-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH18]] ; GFX9-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH18]]
; GFX9-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1) ; GFX9-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1)
; GFX9-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]] ; GFX9-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]]
; GFX9-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[UADDO48]], [[ADD21]] ; GFX9-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[UADDO48]], [[ADD20]]
; GFX9-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1) ; GFX9-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1)
; GFX9-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[ADD22]], [[ZEXT19]] ; GFX9-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ADD21]], [[ZEXT19]]
; GFX9-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD20]] ; GFX9-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD19]]
; GFX9-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD23]] ; GFX9-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD22]]
; GFX9-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO50]] ; GFX9-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO50]]
; GFX9-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD24]], [[UADDO53]] ; GFX9-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD23]], [[UADDO53]]
; GFX9-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI3]], [[ADD24]]
; GFX9-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[UADDO52]] ; GFX9-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[UADDO52]]
; GFX9-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE14]], [[UADDO52]] ; GFX9-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE14]], [[UADDO52]]
; GFX9-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[UADDE14]] ; GFX9-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO10]], [[UADDE12]]
; GFX9-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO10]], [[UADDO52]] ; GFX9-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO10]], [[UADDO52]]
; GFX9-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]] ; GFX9-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]]
; GFX9-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ADD26]], [[UMULH20]] ; GFX9-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[ADD24]], [[UMULH20]]
; GFX9-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE14]], [[MUL24]] ; GFX9-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE12]], [[MUL24]]
; GFX9-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO52]], [[ADD27]] ; GFX9-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO52]], [[ADD25]]
; GFX9-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO52]], [[MUL24]] ; GFX9-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO52]], [[MUL24]]
; GFX9-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]] ; GFX9-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]]
; GFX9-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1) ; GFX9-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1)
; GFX9-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO54]], [[UMULH21]] ; GFX9-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO54]], [[UMULH21]]
; GFX9-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO57]](s1) ; GFX9-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO57]](s1)
; GFX9-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]] ; GFX9-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]]
; GFX9-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE14]], [[ADD27]] ; GFX9-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE12]], [[ADD25]]
; GFX9-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE14]], [[MUL24]] ; GFX9-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE12]], [[MUL24]]
; GFX9-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO52]], [[ADD27]] ; GFX9-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO52]], [[ADD25]]
; GFX9-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]] ; GFX9-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]]
; GFX9-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1) ; GFX9-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1)
; GFX9-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH23]] ; GFX9-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH23]]
; GFX9-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1) ; GFX9-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1)
; GFX9-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]] ; GFX9-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]]
; GFX9-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[UADDO60]], [[ADD28]] ; GFX9-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[UADDO60]], [[ADD26]]
; GFX9-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1) ; GFX9-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1)
; GFX9-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ADD29]], [[ZEXT24]] ; GFX9-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ADD27]], [[ZEXT24]]
; GFX9-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE14]], [[ADD27]] ; GFX9-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE12]], [[ADD25]]
; GFX9-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD30]] ; GFX9-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD28]]
; GFX9-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[UADDO62]] ; GFX9-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[UADDO62]]
; GFX9-NEXT: [[UADDE16:%[0-9]+]]:_(s32), [[UADDE17:%[0-9]+]]:_(s1) = G_UADDE [[ADD25]], [[ADD31]], [[UADDO53]] ; GFX9-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UADDE12]], [[ADD29]], [[UADDO65]]
; GFX9-NEXT: [[UADDE18:%[0-9]+]]:_(s32), [[UADDE19:%[0-9]+]]:_(s1) = G_UADDE [[UADDE16]], [[C6]], [[UADDO65]]
; GFX9-NEXT: [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX9-NEXT: [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX9-NEXT: [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64) ; GFX9-NEXT: [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR3]](s64)
; GFX9-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV47]], [[UADDO64]] ; GFX9-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV47]], [[UADDO64]]
; GFX9-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV46]], [[UADDE18]] ; GFX9-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV46]], [[UADDE14]]
; GFX9-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV46]], [[UADDO64]] ; GFX9-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV46]], [[UADDO64]]
; GFX9-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]] ; GFX9-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]]
; GFX9-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1) ; GFX9-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1)
; GFX9-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO66]], [[UMULH25]] ; GFX9-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO66]], [[UMULH25]]
; GFX9-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO69]](s1) ; GFX9-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO69]](s1)
; GFX9-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]] ; GFX9-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]]
; GFX9-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV47]], [[UADDE18]] ; GFX9-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV47]], [[UADDE14]]
; GFX9-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV47]], [[UADDO64]] ; GFX9-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV47]], [[UADDO64]]
; GFX9-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV46]], [[UADDE18]] ; GFX9-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV46]], [[UADDE14]]
; GFX9-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]] ; GFX9-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]]
; GFX9-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1) ; GFX9-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1)
; GFX9-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UMULH27]] ; GFX9-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UMULH27]]
; GFX9-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO73]](s1) ; GFX9-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO73]](s1)
; GFX9-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]] ; GFX9-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]]
; GFX9-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[UADDO72]], [[ADD32]] ; GFX9-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[UADDO72]], [[ADD30]]
; GFX9-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO75]](s1) ; GFX9-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO75]](s1)
; GFX9-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[ADD33]], [[ZEXT29]] ; GFX9-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ADD31]], [[ZEXT29]]
; GFX9-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV47]], [[UADDE18]] ; GFX9-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV47]], [[UADDE14]]
; GFX9-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD34]] ; GFX9-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD32]]
; GFX9-NEXT: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX9-NEXT: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX9-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV48]], [[UADDO74]] ; GFX9-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV48]], [[UADDO74]]
; GFX9-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV49]], [[UADDO74]] ; GFX9-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV49]], [[UADDO74]]
; GFX9-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV48]], [[ADD35]] ; GFX9-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV48]], [[ADD33]]
; GFX9-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV48]], [[UADDO74]] ; GFX9-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV48]], [[UADDO74]]
; GFX9-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]] ; GFX9-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]]
; GFX9-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[ADD36]], [[UMULH29]] ; GFX9-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[ADD34]], [[UMULH29]]
; GFX9-NEXT: [[USUBO12:%[0-9]+]]:_(s32), [[USUBO13:%[0-9]+]]:_(s1) = G_USUBO [[UV44]], [[MUL33]] ; GFX9-NEXT: [[USUBO12:%[0-9]+]]:_(s32), [[USUBO13:%[0-9]+]]:_(s1) = G_USUBO [[UV44]], [[MUL33]]
; GFX9-NEXT: [[USUBE16:%[0-9]+]]:_(s32), [[USUBE17:%[0-9]+]]:_(s1) = G_USUBE [[UV45]], [[ADD37]], [[USUBO13]] ; GFX9-NEXT: [[USUBE16:%[0-9]+]]:_(s32), [[USUBE17:%[0-9]+]]:_(s1) = G_USUBE [[UV45]], [[ADD35]], [[USUBO13]]
; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV45]], [[ADD37]] ; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV45]], [[ADD35]]
; GFX9-NEXT: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO12]](s32), [[USUBE16]](s32) ; GFX9-NEXT: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO12]](s32), [[USUBE16]](s32)
; GFX9-NEXT: [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64) ; GFX9-NEXT: [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR4]](s64)
; GFX9-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE16]](s32), [[UV51]] ; GFX9-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE16]](s32), [[UV51]]
; GFX9-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1) ; GFX9-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1)
; GFX9-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO12]](s32), [[UV50]] ; GFX9-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO12]](s32), [[UV50]]
; GFX9-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1) ; GFX9-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1)
; GFX9-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE16]](s32), [[UV51]] ; GFX9-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE16]](s32), [[UV51]]
; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]] ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]]
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; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]] ; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]]
; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE8]] ; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE6]]
; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]] ; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]]
; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE8]] ; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE6]]
; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]] ; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]]
; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE8]] ; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE6]]
; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE8]] ; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE6]]
; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]] ; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]]
; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]] ; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]]
; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD16]] ; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD15]]
; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]] ; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]]
; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]] ; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD18]], [[USUBO3]] ; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD17]], [[USUBO3]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD18]] ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD17]]
; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]] ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]]
; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]] ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]]
; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]] ; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]]
; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE8]] ; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE6]]
; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]] ; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]]
; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE8]] ; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE6]]
; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]] ; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]]
; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE8]] ; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE6]]
; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE8]] ; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE6]]
; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]] ; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]]
; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]] ; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]]
; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD16]] ; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD15]]
; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]] ; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]]
; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]] ; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD18]], [[USUBO3]] ; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD17]], [[USUBO3]]
; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD18]] ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD17]]
; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]] ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]] ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]]
; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]] ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]] ; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[ADD2]]
; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]] ; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO12]]
; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]] ; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO15]]
; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]] ; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO14]]
; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]] ; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO14]]
; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]] ; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE4]]
; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]] ; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO14]]
; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]] ; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL6]]
; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD8]] ; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO14]], [[ADD7]]
; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]] ; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[MUL6]]
; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]] ; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH6]]
; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD8]] ; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD7]]
; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]] ; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL6]]
; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD8]] ; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO14]], [[ADD7]]
; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]] ; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO20]], [[UMULH8]]
; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1) ; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO23]](s1)
; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD9]] ; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[UADDO22]], [[ADD8]]
; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD8]] ; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD7]]
; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]] ; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO14]], [[UADDO24]]
; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO15]] ; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD11]], [[UADDO27]]
; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[C6]], [[UADDO27]]
; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64) ; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR]](s64)
; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]] ; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDO26]]
; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE8]] ; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV16]], [[UADDE6]]
; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]] ; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDO26]]
; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]] ; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH10]]
; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE8]] ; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV17]], [[UADDE6]]
; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]] ; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDO26]]
; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE8]] ; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV16]], [[UADDE6]]
; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]] ; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UMULH12]]
; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD13]] ; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[ADD12]]
; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE8]] ; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV17]], [[UADDE6]]
; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]] ; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[UADDO36]]
; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]] ; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV19]], [[UADDO36]]
; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD16]] ; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV18]], [[ADD15]]
; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]] ; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV18]], [[UADDO36]]
; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]] ; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV14]], [[MUL15]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD18]], [[USUBO3]] ; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV15]], [[ADD17]], [[USUBO3]]
; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD18]] ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV15]], [[ADD17]]
; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64) ; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[XOR1]](s64)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]] ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV21]]
; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]] ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV20]]
; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]] ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV21]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
Show All 33 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir

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; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX6-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX6-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX6-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX6-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C5]], [[UADDO23]]
; GFX6-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; GFX6-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]] ; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]]
; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE4]] ; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE2]]
; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]] ; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]]
; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE4]] ; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE2]]
; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]] ; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]]
; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE4]] ; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE2]]
; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE4]] ; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE2]]
; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD16]](s32) ; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD15]](s32)
; GFX6-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) ; GFX6-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]] ; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]]
; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]] ; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]]
; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD16]] ; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD15]]
; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]] ; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]]
; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]] ; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD18]], [[USUBO3]] ; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD17]], [[USUBO3]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD18]] ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD17]]
; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) ; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]] ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]]
; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]] ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]]
; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX6-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV12]] ; GFX6-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV12]]
; GFX6-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV13]], [[USUBO3]] ; GFX6-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV13]], [[USUBO3]]
; GFX6-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C5]], [[USUBO5]] ; GFX6-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C5]], [[USUBO5]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX6-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV14]] ; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV14]]
; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV15]], [[UADDO35]] ; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV15]], [[UADDO35]]
; GFX6-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE6]](s32) ; GFX6-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE4]](s32)
; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV13]] ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV13]]
; GFX6-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX6-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV12]] ; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV12]]
; GFX6-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX6-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV13]] ; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV13]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV16]] ; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV16]]
; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[UV17]], [[UADDO37]] ; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[UV17]], [[UADDO37]]
; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE8]](s32) ; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE6]](s32)
; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C5]] ; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C5]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]] ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]] ; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]] ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64) ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
; GFX8-LABEL: name: test_udiv_s64 ; GFX8-LABEL: name: test_udiv_s64
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
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; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX8-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX8-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX8-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX8-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C5]], [[UADDO23]]
; GFX8-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; GFX8-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]] ; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]]
; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE4]] ; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE2]]
; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]] ; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]]
; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE4]] ; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE2]]
; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]] ; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]]
; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE4]] ; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE2]]
; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE4]] ; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE2]]
; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD16]](s32) ; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD15]](s32)
; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) ; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]] ; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]]
; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]] ; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]]
; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD16]] ; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD15]]
; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]] ; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]]
; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]] ; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD18]], [[USUBO3]] ; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD17]], [[USUBO3]]
; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD18]] ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD17]]
; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) ; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]] ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]] ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]]
; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]] ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX8-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV12]] ; GFX8-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV12]]
; GFX8-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV13]], [[USUBO3]] ; GFX8-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV13]], [[USUBO3]]
; GFX8-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C5]], [[USUBO5]] ; GFX8-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C5]], [[USUBO5]]
; GFX8-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV14]] ; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV14]]
; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV15]], [[UADDO35]] ; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV15]], [[UADDO35]]
; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE6]](s32) ; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE4]](s32)
; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV13]] ; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV13]]
; GFX8-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX8-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX8-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV12]] ; GFX8-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV12]]
; GFX8-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX8-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX8-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV13]] ; GFX8-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV13]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV16]] ; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV16]]
; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[UV17]], [[UADDO37]] ; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[UV17]], [[UADDO37]]
; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE8]](s32) ; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE6]](s32)
; GFX8-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C5]] ; GFX8-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C5]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]] ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]] ; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]]
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]] ; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64) ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
; GFX9-LABEL: name: test_udiv_s64 ; GFX9-LABEL: name: test_udiv_s64
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
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; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX9-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX9-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX9-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX9-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX9-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX9-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX9-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX9-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C5]], [[UADDO23]]
; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]] ; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]]
; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE4]] ; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE2]]
; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]] ; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]]
; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE4]] ; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE2]]
; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]] ; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]]
; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE4]] ; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE2]]
; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE4]] ; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE2]]
; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD16]](s32) ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD15]](s32)
; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) ; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]] ; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]]
; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]] ; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]]
; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD16]] ; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD15]]
; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]] ; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]]
; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]] ; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD18]], [[USUBO3]] ; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD17]], [[USUBO3]]
; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD18]] ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD17]]
; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) ; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]] ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]]
; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]] ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]]
; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]] ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX9-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV12]] ; GFX9-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV12]]
; GFX9-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV13]], [[USUBO3]] ; GFX9-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV13]], [[USUBO3]]
; GFX9-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C5]], [[USUBO5]] ; GFX9-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C5]], [[USUBO5]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX9-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV14]] ; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV14]]
; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV15]], [[UADDO35]] ; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV15]], [[UADDO35]]
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE6]](s32) ; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE4]](s32)
; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV13]] ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV13]]
; GFX9-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX9-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV12]] ; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV12]]
; GFX9-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX9-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV13]] ; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV13]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV16]] ; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV16]]
; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[UV17]], [[UADDO37]] ; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[UV17]], [[UADDO37]]
; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE8]](s32) ; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE6]](s32)
; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C5]] ; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C5]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]] ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]] ; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]]
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]] ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64) ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3 %1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_UDIV %0, %1 %2:_(s64) = G_UDIV %0, %1
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; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX6-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX6-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX6-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX6-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C5]], [[UADDO23]]
; GFX6-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) ; GFX6-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) ; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDO22]] ; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDO22]]
; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV12]], [[UADDE4]] ; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV12]], [[UADDE2]]
; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDO22]] ; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDO22]]
; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDE4]] ; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDE2]]
; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDO22]] ; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDO22]]
; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDE4]] ; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDE2]]
; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDE4]] ; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDE2]]
; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD16]](s32) ; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD15]](s32)
; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) ; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[UADDO32]] ; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[UADDO32]]
; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV15]], [[UADDO32]] ; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV15]], [[UADDO32]]
; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[ADD16]] ; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[ADD15]]
; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV14]], [[UADDO32]] ; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV14]], [[UADDO32]]
; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV10]], [[MUL15]] ; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV10]], [[MUL15]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV11]], [[ADD18]], [[USUBO3]] ; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV11]], [[ADD17]], [[USUBO3]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV11]], [[ADD18]] ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV11]], [[ADD17]]
; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) ; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV17]] ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV17]]
; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV16]] ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV16]]
; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV17]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV17]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX6-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV16]] ; GFX6-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV16]]
; GFX6-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV17]], [[USUBO3]] ; GFX6-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV17]], [[USUBO3]]
; GFX6-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C5]], [[USUBO5]] ; GFX6-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C5]], [[USUBO5]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX6-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX6-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV18]] ; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV18]]
; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV19]], [[UADDO35]] ; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV19]], [[UADDO35]]
; GFX6-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE6]](s32) ; GFX6-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE4]](s32)
; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV17]] ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV17]]
; GFX6-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX6-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV16]] ; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV16]]
; GFX6-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX6-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV17]] ; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV17]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV20]] ; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV20]]
; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[UV21]], [[UADDO37]] ; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[UV21]], [[UADDO37]]
; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE8]](s32) ; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE6]](s32)
; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C5]] ; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C5]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]] ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]] ; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]] ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX6-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX6-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX6-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV22]](s32) ; GFX6-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV22]](s32)
; GFX6-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV23]](s32) ; GFX6-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV23]](s32)
; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
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; GFX6-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64) ; GFX6-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)
; GFX6-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX6-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX6-NEXT: [[USUBO6:%[0-9]+]]:_(s32), [[USUBO7:%[0-9]+]]:_(s1) = G_USUBO [[UV24]], [[UV26]] ; GFX6-NEXT: [[USUBO6:%[0-9]+]]:_(s32), [[USUBO7:%[0-9]+]]:_(s1) = G_USUBO [[UV24]], [[UV26]]
; GFX6-NEXT: [[USUBE8:%[0-9]+]]:_(s32), [[USUBE9:%[0-9]+]]:_(s1) = G_USUBE [[UV25]], [[UV27]], [[USUBO7]] ; GFX6-NEXT: [[USUBE8:%[0-9]+]]:_(s32), [[USUBE9:%[0-9]+]]:_(s1) = G_USUBE [[UV25]], [[UV27]], [[USUBO7]]
; GFX6-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[FPTOUI2]] ; GFX6-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[FPTOUI2]]
; GFX6-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE8]], [[FPTOUI2]] ; GFX6-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE8]], [[FPTOUI2]]
; GFX6-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[FPTOUI3]] ; GFX6-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[FPTOUI3]]
; GFX6-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO6]], [[FPTOUI2]] ; GFX6-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO6]], [[FPTOUI2]]
; GFX6-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]] ; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]]
; GFX6-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ADD19]], [[UMULH15]] ; GFX6-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[ADD18]], [[UMULH15]]
; GFX6-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]] ; GFX6-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]]
; GFX6-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD20]] ; GFX6-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD19]]
; GFX6-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]] ; GFX6-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]]
; GFX6-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]] ; GFX6-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]]
; GFX6-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO39]](s1) ; GFX6-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO39]](s1)
; GFX6-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UMULH16]] ; GFX6-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UMULH16]]
; GFX6-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO41]](s1) ; GFX6-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO41]](s1)
; GFX6-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]] ; GFX6-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]]
; GFX6-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD20]] ; GFX6-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD19]]
; GFX6-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]] ; GFX6-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]]
; GFX6-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD20]] ; GFX6-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD19]]
; GFX6-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]] ; GFX6-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]]
; GFX6-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1) ; GFX6-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1)
; GFX6-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UADDO42]], [[UMULH18]] ; GFX6-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UADDO42]], [[UMULH18]]
; GFX6-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO45]](s1) ; GFX6-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO45]](s1)
; GFX6-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]] ; GFX6-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]]
; GFX6-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[UADDO44]], [[ADD21]] ; GFX6-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[UADDO44]], [[ADD20]]
; GFX6-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1) ; GFX6-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1)
; GFX6-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[ADD22]], [[ZEXT19]] ; GFX6-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ADD21]], [[ZEXT19]]
; GFX6-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD20]] ; GFX6-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD19]]
; GFX6-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD23]] ; GFX6-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD22]]
; GFX6-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO46]] ; GFX6-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO46]]
; GFX6-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD24]], [[UADDO49]] ; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD23]], [[UADDO49]]
; GFX6-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI3]], [[ADD24]]
; GFX6-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[UADDO48]] ; GFX6-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[UADDO48]]
; GFX6-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE8]], [[UADDO48]] ; GFX6-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE8]], [[UADDO48]]
; GFX6-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[UADDE10]] ; GFX6-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[UADDE8]]
; GFX6-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO6]], [[UADDO48]] ; GFX6-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO6]], [[UADDO48]]
; GFX6-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]] ; GFX6-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]]
; GFX6-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ADD26]], [[UMULH20]] ; GFX6-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[ADD24]], [[UMULH20]]
; GFX6-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE10]], [[MUL24]] ; GFX6-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE8]], [[MUL24]]
; GFX6-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO48]], [[ADD27]] ; GFX6-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO48]], [[ADD25]]
; GFX6-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO48]], [[MUL24]] ; GFX6-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO48]], [[MUL24]]
; GFX6-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]] ; GFX6-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]]
; GFX6-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1) ; GFX6-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1)
; GFX6-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH21]] ; GFX6-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH21]]
; GFX6-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1) ; GFX6-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1)
; GFX6-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]] ; GFX6-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]]
; GFX6-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE10]], [[ADD27]] ; GFX6-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE8]], [[ADD25]]
; GFX6-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE10]], [[MUL24]] ; GFX6-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE8]], [[MUL24]]
; GFX6-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO48]], [[ADD27]] ; GFX6-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO48]], [[ADD25]]
; GFX6-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]] ; GFX6-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]]
; GFX6-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1) ; GFX6-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1)
; GFX6-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO54]], [[UMULH23]] ; GFX6-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO54]], [[UMULH23]]
; GFX6-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO57]](s1) ; GFX6-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO57]](s1)
; GFX6-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]] ; GFX6-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]]
; GFX6-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[UADDO56]], [[ADD28]] ; GFX6-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[UADDO56]], [[ADD26]]
; GFX6-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1) ; GFX6-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1)
; GFX6-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ADD29]], [[ZEXT24]] ; GFX6-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ADD27]], [[ZEXT24]]
; GFX6-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE10]], [[ADD27]] ; GFX6-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE8]], [[ADD25]]
; GFX6-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD30]] ; GFX6-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD28]]
; GFX6-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO48]], [[UADDO58]] ; GFX6-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO48]], [[UADDO58]]
; GFX6-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[ADD25]], [[ADD31]], [[UADDO49]] ; GFX6-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[ADD29]], [[UADDO61]]
; GFX6-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UADDE12]], [[C5]], [[UADDO61]]
; GFX6-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX6-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX6-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX6-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX6-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV31]], [[UADDO60]] ; GFX6-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV31]], [[UADDO60]]
; GFX6-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV30]], [[UADDE14]] ; GFX6-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV30]], [[UADDE10]]
; GFX6-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV30]], [[UADDO60]] ; GFX6-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV30]], [[UADDO60]]
; GFX6-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]] ; GFX6-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]]
; GFX6-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1) ; GFX6-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1)
; GFX6-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH25]] ; GFX6-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH25]]
; GFX6-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1) ; GFX6-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1)
; GFX6-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]] ; GFX6-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]]
; GFX6-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV31]], [[UADDE14]] ; GFX6-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV31]], [[UADDE10]]
; GFX6-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV31]], [[UADDO60]] ; GFX6-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV31]], [[UADDO60]]
; GFX6-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV30]], [[UADDE14]] ; GFX6-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV30]], [[UADDE10]]
; GFX6-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]] ; GFX6-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]]
; GFX6-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1) ; GFX6-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1)
; GFX6-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO66]], [[UMULH27]] ; GFX6-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO66]], [[UMULH27]]
; GFX6-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO69]](s1) ; GFX6-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO69]](s1)
; GFX6-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]] ; GFX6-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]]
; GFX6-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[UADDO68]], [[ADD32]] ; GFX6-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[UADDO68]], [[ADD30]]
; GFX6-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1) ; GFX6-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1)
; GFX6-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[ADD33]], [[ZEXT29]] ; GFX6-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ADD31]], [[ZEXT29]]
; GFX6-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV31]], [[UADDE14]] ; GFX6-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV31]], [[UADDE10]]
; GFX6-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD34]] ; GFX6-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD32]]
; GFX6-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO70]](s32), [[ADD35]](s32) ; GFX6-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO70]](s32), [[ADD33]](s32)
; GFX6-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX6-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX6-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV32]], [[UADDO70]] ; GFX6-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV32]], [[UADDO70]]
; GFX6-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV33]], [[UADDO70]] ; GFX6-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV33]], [[UADDO70]]
; GFX6-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV32]], [[ADD35]] ; GFX6-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV32]], [[ADD33]]
; GFX6-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV32]], [[UADDO70]] ; GFX6-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV32]], [[UADDO70]]
; GFX6-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]] ; GFX6-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]]
; GFX6-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[ADD36]], [[UMULH29]] ; GFX6-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[ADD34]], [[UMULH29]]
; GFX6-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV28]], [[MUL33]] ; GFX6-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV28]], [[MUL33]]
; GFX6-NEXT: [[USUBE10:%[0-9]+]]:_(s32), [[USUBE11:%[0-9]+]]:_(s1) = G_USUBE [[UV29]], [[ADD37]], [[USUBO9]] ; GFX6-NEXT: [[USUBE10:%[0-9]+]]:_(s32), [[USUBE11:%[0-9]+]]:_(s1) = G_USUBE [[UV29]], [[ADD35]], [[USUBO9]]
; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV29]], [[ADD37]] ; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV29]], [[ADD35]]
; GFX6-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX6-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX6-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE10]](s32), [[UV35]] ; GFX6-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE10]](s32), [[UV35]]
; GFX6-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1) ; GFX6-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1)
; GFX6-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO8]](s32), [[UV34]] ; GFX6-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO8]](s32), [[UV34]]
; GFX6-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1) ; GFX6-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1)
; GFX6-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE10]](s32), [[UV35]] ; GFX6-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE10]](s32), [[UV35]]
; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]] ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]]
; GFX6-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[USUBO8]], [[UV34]] ; GFX6-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[USUBO8]], [[UV34]]
; GFX6-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[SUB1]], [[UV35]], [[USUBO9]] ; GFX6-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[SUB1]], [[UV35]], [[USUBO9]]
; GFX6-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[USUBE12]], [[C5]], [[USUBO11]] ; GFX6-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[USUBE12]], [[C5]], [[USUBO11]]
; GFX6-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX6-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX6-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UV36]] ; GFX6-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UV36]]
; GFX6-NEXT: [[UADDE16:%[0-9]+]]:_(s32), [[UADDE17:%[0-9]+]]:_(s1) = G_UADDE [[ADD35]], [[UV37]], [[UADDO73]] ; GFX6-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[ADD33]], [[UV37]], [[UADDO73]]
; GFX6-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO72]](s32), [[UADDE16]](s32) ; GFX6-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO72]](s32), [[UADDE12]](s32)
; GFX6-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE14]](s32), [[UV35]] ; GFX6-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE14]](s32), [[UV35]]
; GFX6-NEXT: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[ICMP11]](s1) ; GFX6-NEXT: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[ICMP11]](s1)
; GFX6-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV34]] ; GFX6-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV34]]
; GFX6-NEXT: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[ICMP12]](s1) ; GFX6-NEXT: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[ICMP12]](s1)
; GFX6-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE14]](s32), [[UV35]] ; GFX6-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE14]](s32), [[UV35]]
; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP13]](s1), [[SEXT7]], [[SEXT6]] ; GFX6-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP13]](s1), [[SEXT7]], [[SEXT6]]
; GFX6-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX6-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX6-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[UADDO72]], [[UV38]] ; GFX6-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[UADDO72]], [[UV38]]
; GFX6-NEXT: [[UADDE18:%[0-9]+]]:_(s32), [[UADDE19:%[0-9]+]]:_(s1) = G_UADDE [[UADDE16]], [[UV39]], [[UADDO75]] ; GFX6-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UADDE12]], [[UV39]], [[UADDO75]]
; GFX6-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO74]](s32), [[UADDE18]](s32) ; GFX6-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO74]](s32), [[UADDE14]](s32)
; GFX6-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT5]](s32), [[C5]] ; GFX6-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT5]](s32), [[C5]]
; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP14]](s1), [[MV5]], [[MV4]] ; GFX6-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP14]](s1), [[MV5]], [[MV4]]
; GFX6-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT4]](s32), [[C5]] ; GFX6-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT4]](s32), [[C5]]
; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV3]] ; GFX6-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV3]]
; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT3]](s64), [[SELECT7]](s64) ; GFX6-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT3]](s64), [[SELECT7]](s64)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) ; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
; GFX8-LABEL: name: test_udiv_v2s64 ; GFX8-LABEL: name: test_udiv_v2s64
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX8: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX8-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX8-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX8-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX8-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C5]], [[UADDO23]]
; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) ; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) ; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDO22]] ; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDO22]]
; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV12]], [[UADDE4]] ; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV12]], [[UADDE2]]
; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDO22]] ; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDO22]]
; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDE4]] ; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDE2]]
; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDO22]] ; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDO22]]
; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDE4]] ; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDE2]]
; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDE4]] ; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDE2]]
; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD16]](s32) ; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD15]](s32)
; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) ; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[UADDO32]] ; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[UADDO32]]
; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV15]], [[UADDO32]] ; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV15]], [[UADDO32]]
; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[ADD16]] ; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[ADD15]]
; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV14]], [[UADDO32]] ; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV14]], [[UADDO32]]
; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV10]], [[MUL15]] ; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV10]], [[MUL15]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV11]], [[ADD18]], [[USUBO3]] ; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV11]], [[ADD17]], [[USUBO3]]
; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV11]], [[ADD18]] ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV11]], [[ADD17]]
; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) ; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV17]] ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV17]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV16]] ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV16]]
; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV17]] ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV17]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX8-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV16]] ; GFX8-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV16]]
; GFX8-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV17]], [[USUBO3]] ; GFX8-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV17]], [[USUBO3]]
; GFX8-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C5]], [[USUBO5]] ; GFX8-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C5]], [[USUBO5]]
; GFX8-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX8-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV18]] ; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV18]]
; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV19]], [[UADDO35]] ; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV19]], [[UADDO35]]
; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE6]](s32) ; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE4]](s32)
; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV17]] ; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV17]]
; GFX8-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX8-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX8-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV16]] ; GFX8-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV16]]
; GFX8-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX8-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX8-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV17]] ; GFX8-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV17]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV20]] ; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV20]]
; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[UV21]], [[UADDO37]] ; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[UV21]], [[UADDO37]]
; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE8]](s32) ; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE6]](s32)
; GFX8-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C5]] ; GFX8-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C5]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]] ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]] ; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]]
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]] ; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX8-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX8-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX8-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV22]](s32) ; GFX8-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV22]](s32)
; GFX8-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV23]](s32) ; GFX8-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV23]](s32)
; GFX8-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 ; GFX8-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
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; GFX8-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64) ; GFX8-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)
; GFX8-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX8-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX8-NEXT: [[USUBO6:%[0-9]+]]:_(s32), [[USUBO7:%[0-9]+]]:_(s1) = G_USUBO [[UV24]], [[UV26]] ; GFX8-NEXT: [[USUBO6:%[0-9]+]]:_(s32), [[USUBO7:%[0-9]+]]:_(s1) = G_USUBO [[UV24]], [[UV26]]
; GFX8-NEXT: [[USUBE8:%[0-9]+]]:_(s32), [[USUBE9:%[0-9]+]]:_(s1) = G_USUBE [[UV25]], [[UV27]], [[USUBO7]] ; GFX8-NEXT: [[USUBE8:%[0-9]+]]:_(s32), [[USUBE9:%[0-9]+]]:_(s1) = G_USUBE [[UV25]], [[UV27]], [[USUBO7]]
; GFX8-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[FPTOUI2]] ; GFX8-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[FPTOUI2]]
; GFX8-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE8]], [[FPTOUI2]] ; GFX8-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE8]], [[FPTOUI2]]
; GFX8-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[FPTOUI3]] ; GFX8-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[FPTOUI3]]
; GFX8-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO6]], [[FPTOUI2]] ; GFX8-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO6]], [[FPTOUI2]]
; GFX8-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]] ; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]]
; GFX8-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ADD19]], [[UMULH15]] ; GFX8-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[ADD18]], [[UMULH15]]
; GFX8-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]] ; GFX8-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]]
; GFX8-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD20]] ; GFX8-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD19]]
; GFX8-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]] ; GFX8-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]]
; GFX8-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]] ; GFX8-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]]
; GFX8-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO39]](s1) ; GFX8-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO39]](s1)
; GFX8-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UMULH16]] ; GFX8-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UMULH16]]
; GFX8-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO41]](s1) ; GFX8-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO41]](s1)
; GFX8-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]] ; GFX8-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]]
; GFX8-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD20]] ; GFX8-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD19]]
; GFX8-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]] ; GFX8-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]]
; GFX8-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD20]] ; GFX8-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD19]]
; GFX8-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]] ; GFX8-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]]
; GFX8-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1) ; GFX8-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1)
; GFX8-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UADDO42]], [[UMULH18]] ; GFX8-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UADDO42]], [[UMULH18]]
; GFX8-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO45]](s1) ; GFX8-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO45]](s1)
; GFX8-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]] ; GFX8-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]]
; GFX8-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[UADDO44]], [[ADD21]] ; GFX8-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[UADDO44]], [[ADD20]]
; GFX8-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1) ; GFX8-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1)
; GFX8-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[ADD22]], [[ZEXT19]] ; GFX8-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ADD21]], [[ZEXT19]]
; GFX8-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD20]] ; GFX8-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD19]]
; GFX8-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD23]] ; GFX8-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD22]]
; GFX8-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO46]] ; GFX8-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO46]]
; GFX8-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD24]], [[UADDO49]] ; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD23]], [[UADDO49]]
; GFX8-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI3]], [[ADD24]]
; GFX8-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[UADDO48]] ; GFX8-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[UADDO48]]
; GFX8-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE8]], [[UADDO48]] ; GFX8-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE8]], [[UADDO48]]
; GFX8-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[UADDE10]] ; GFX8-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[UADDE8]]
; GFX8-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO6]], [[UADDO48]] ; GFX8-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO6]], [[UADDO48]]
; GFX8-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]] ; GFX8-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]]
; GFX8-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ADD26]], [[UMULH20]] ; GFX8-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[ADD24]], [[UMULH20]]
; GFX8-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE10]], [[MUL24]] ; GFX8-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE8]], [[MUL24]]
; GFX8-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO48]], [[ADD27]] ; GFX8-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO48]], [[ADD25]]
; GFX8-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO48]], [[MUL24]] ; GFX8-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO48]], [[MUL24]]
; GFX8-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]] ; GFX8-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]]
; GFX8-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1) ; GFX8-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1)
; GFX8-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH21]] ; GFX8-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH21]]
; GFX8-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1) ; GFX8-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1)
; GFX8-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]] ; GFX8-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]]
; GFX8-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE10]], [[ADD27]] ; GFX8-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE8]], [[ADD25]]
; GFX8-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE10]], [[MUL24]] ; GFX8-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE8]], [[MUL24]]
; GFX8-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO48]], [[ADD27]] ; GFX8-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO48]], [[ADD25]]
; GFX8-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]] ; GFX8-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]]
; GFX8-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1) ; GFX8-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1)
; GFX8-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO54]], [[UMULH23]] ; GFX8-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO54]], [[UMULH23]]
; GFX8-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO57]](s1) ; GFX8-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO57]](s1)
; GFX8-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]] ; GFX8-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]]
; GFX8-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[UADDO56]], [[ADD28]] ; GFX8-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[UADDO56]], [[ADD26]]
; GFX8-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1) ; GFX8-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1)
; GFX8-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ADD29]], [[ZEXT24]] ; GFX8-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ADD27]], [[ZEXT24]]
; GFX8-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE10]], [[ADD27]] ; GFX8-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE8]], [[ADD25]]
; GFX8-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD30]] ; GFX8-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD28]]
; GFX8-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO48]], [[UADDO58]] ; GFX8-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO48]], [[UADDO58]]
; GFX8-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[ADD25]], [[ADD31]], [[UADDO49]] ; GFX8-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[ADD29]], [[UADDO61]]
; GFX8-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UADDE12]], [[C5]], [[UADDO61]]
; GFX8-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX8-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX8-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX8-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX8-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV31]], [[UADDO60]] ; GFX8-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV31]], [[UADDO60]]
; GFX8-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV30]], [[UADDE14]] ; GFX8-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV30]], [[UADDE10]]
; GFX8-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV30]], [[UADDO60]] ; GFX8-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV30]], [[UADDO60]]
; GFX8-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]] ; GFX8-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]]
; GFX8-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1) ; GFX8-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1)
; GFX8-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH25]] ; GFX8-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH25]]
; GFX8-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1) ; GFX8-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1)
; GFX8-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]] ; GFX8-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]]
; GFX8-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV31]], [[UADDE14]] ; GFX8-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV31]], [[UADDE10]]
; GFX8-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV31]], [[UADDO60]] ; GFX8-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV31]], [[UADDO60]]
; GFX8-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV30]], [[UADDE14]] ; GFX8-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV30]], [[UADDE10]]
; GFX8-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]] ; GFX8-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]]
; GFX8-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1) ; GFX8-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1)
; GFX8-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO66]], [[UMULH27]] ; GFX8-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO66]], [[UMULH27]]
; GFX8-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO69]](s1) ; GFX8-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO69]](s1)
; GFX8-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]] ; GFX8-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]]
; GFX8-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[UADDO68]], [[ADD32]] ; GFX8-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[UADDO68]], [[ADD30]]
; GFX8-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1) ; GFX8-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1)
; GFX8-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[ADD33]], [[ZEXT29]] ; GFX8-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ADD31]], [[ZEXT29]]
; GFX8-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV31]], [[UADDE14]] ; GFX8-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV31]], [[UADDE10]]
; GFX8-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD34]] ; GFX8-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD32]]
; GFX8-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO70]](s32), [[ADD35]](s32) ; GFX8-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO70]](s32), [[ADD33]](s32)
; GFX8-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX8-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX8-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV32]], [[UADDO70]] ; GFX8-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV32]], [[UADDO70]]
; GFX8-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV33]], [[UADDO70]] ; GFX8-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV33]], [[UADDO70]]
; GFX8-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV32]], [[ADD35]] ; GFX8-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV32]], [[ADD33]]
; GFX8-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV32]], [[UADDO70]] ; GFX8-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV32]], [[UADDO70]]
; GFX8-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]] ; GFX8-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]]
; GFX8-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[ADD36]], [[UMULH29]] ; GFX8-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[ADD34]], [[UMULH29]]
; GFX8-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV28]], [[MUL33]] ; GFX8-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV28]], [[MUL33]]
; GFX8-NEXT: [[USUBE10:%[0-9]+]]:_(s32), [[USUBE11:%[0-9]+]]:_(s1) = G_USUBE [[UV29]], [[ADD37]], [[USUBO9]] ; GFX8-NEXT: [[USUBE10:%[0-9]+]]:_(s32), [[USUBE11:%[0-9]+]]:_(s1) = G_USUBE [[UV29]], [[ADD35]], [[USUBO9]]
; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV29]], [[ADD37]] ; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV29]], [[ADD35]]
; GFX8-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX8-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX8-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE10]](s32), [[UV35]] ; GFX8-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE10]](s32), [[UV35]]
; GFX8-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1) ; GFX8-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1)
; GFX8-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO8]](s32), [[UV34]] ; GFX8-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO8]](s32), [[UV34]]
; GFX8-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1) ; GFX8-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1)
; GFX8-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE10]](s32), [[UV35]] ; GFX8-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE10]](s32), [[UV35]]
; GFX8-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]] ; GFX8-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]]
; GFX8-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[USUBO8]], [[UV34]] ; GFX8-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[USUBO8]], [[UV34]]
; GFX8-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[SUB1]], [[UV35]], [[USUBO9]] ; GFX8-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[SUB1]], [[UV35]], [[USUBO9]]
; GFX8-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[USUBE12]], [[C5]], [[USUBO11]] ; GFX8-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[USUBE12]], [[C5]], [[USUBO11]]
; GFX8-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX8-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX8-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UV36]] ; GFX8-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UV36]]
; GFX8-NEXT: [[UADDE16:%[0-9]+]]:_(s32), [[UADDE17:%[0-9]+]]:_(s1) = G_UADDE [[ADD35]], [[UV37]], [[UADDO73]] ; GFX8-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[ADD33]], [[UV37]], [[UADDO73]]
; GFX8-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO72]](s32), [[UADDE16]](s32) ; GFX8-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO72]](s32), [[UADDE12]](s32)
; GFX8-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE14]](s32), [[UV35]] ; GFX8-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE14]](s32), [[UV35]]
; GFX8-NEXT: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[ICMP11]](s1) ; GFX8-NEXT: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[ICMP11]](s1)
; GFX8-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV34]] ; GFX8-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV34]]
; GFX8-NEXT: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[ICMP12]](s1) ; GFX8-NEXT: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[ICMP12]](s1)
; GFX8-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE14]](s32), [[UV35]] ; GFX8-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE14]](s32), [[UV35]]
; GFX8-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP13]](s1), [[SEXT7]], [[SEXT6]] ; GFX8-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP13]](s1), [[SEXT7]], [[SEXT6]]
; GFX8-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX8-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX8-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[UADDO72]], [[UV38]] ; GFX8-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[UADDO72]], [[UV38]]
; GFX8-NEXT: [[UADDE18:%[0-9]+]]:_(s32), [[UADDE19:%[0-9]+]]:_(s1) = G_UADDE [[UADDE16]], [[UV39]], [[UADDO75]] ; GFX8-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UADDE12]], [[UV39]], [[UADDO75]]
; GFX8-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO74]](s32), [[UADDE18]](s32) ; GFX8-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO74]](s32), [[UADDE14]](s32)
; GFX8-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT5]](s32), [[C5]] ; GFX8-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT5]](s32), [[C5]]
; GFX8-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP14]](s1), [[MV5]], [[MV4]] ; GFX8-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP14]](s1), [[MV5]], [[MV4]]
; GFX8-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT4]](s32), [[C5]] ; GFX8-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT4]](s32), [[C5]]
; GFX8-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV3]] ; GFX8-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV3]]
; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT3]](s64), [[SELECT7]](s64) ; GFX8-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT3]](s64), [[SELECT7]](s64)
; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) ; GFX8-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
; GFX9-LABEL: name: test_udiv_v2s64 ; GFX9-LABEL: name: test_udiv_v2s64
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX9-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX9-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX9-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX9-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX9-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX9-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX9-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX9-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C5]], [[UADDO23]]
; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) ; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) ; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDO22]] ; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDO22]]
; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV12]], [[UADDE4]] ; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV12]], [[UADDE2]]
; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDO22]] ; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDO22]]
; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDE4]] ; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDE2]]
; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDO22]] ; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDO22]]
; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDE4]] ; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDE2]]
; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDE4]] ; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDE2]]
; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD16]](s32) ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD15]](s32)
; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) ; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[UADDO32]] ; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[UADDO32]]
; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV15]], [[UADDO32]] ; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV15]], [[UADDO32]]
; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[ADD16]] ; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[ADD15]]
; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV14]], [[UADDO32]] ; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV14]], [[UADDO32]]
; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV10]], [[MUL15]] ; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV10]], [[MUL15]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV11]], [[ADD18]], [[USUBO3]] ; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV11]], [[ADD17]], [[USUBO3]]
; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV11]], [[ADD18]] ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV11]], [[ADD17]]
; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) ; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV17]] ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV17]]
; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV16]] ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV16]]
; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV17]] ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV17]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX9-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV16]] ; GFX9-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV16]]
; GFX9-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV17]], [[USUBO3]] ; GFX9-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV17]], [[USUBO3]]
; GFX9-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C5]], [[USUBO5]] ; GFX9-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C5]], [[USUBO5]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX9-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX9-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV18]] ; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV18]]
; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV19]], [[UADDO35]] ; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV19]], [[UADDO35]]
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE6]](s32) ; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE4]](s32)
; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV17]] ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV17]]
; GFX9-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX9-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV16]] ; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV16]]
; GFX9-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX9-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV17]] ; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV17]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV20]] ; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV20]]
; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[UV21]], [[UADDO37]] ; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[UV21]], [[UADDO37]]
; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE8]](s32) ; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE6]](s32)
; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C5]] ; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C5]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]] ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]] ; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C5]]
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]] ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX9-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX9-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX9-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV22]](s32) ; GFX9-NEXT: [[UITOFP2:%[0-9]+]]:_(s32) = G_UITOFP [[UV22]](s32)
; GFX9-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV23]](s32) ; GFX9-NEXT: [[UITOFP3:%[0-9]+]]:_(s32) = G_UITOFP [[UV23]](s32)
; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000 ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41F0000000000000
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; GFX9-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64) ; GFX9-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)
; GFX9-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX9-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX9-NEXT: [[USUBO6:%[0-9]+]]:_(s32), [[USUBO7:%[0-9]+]]:_(s1) = G_USUBO [[UV24]], [[UV26]] ; GFX9-NEXT: [[USUBO6:%[0-9]+]]:_(s32), [[USUBO7:%[0-9]+]]:_(s1) = G_USUBO [[UV24]], [[UV26]]
; GFX9-NEXT: [[USUBE8:%[0-9]+]]:_(s32), [[USUBE9:%[0-9]+]]:_(s1) = G_USUBE [[UV25]], [[UV27]], [[USUBO7]] ; GFX9-NEXT: [[USUBE8:%[0-9]+]]:_(s32), [[USUBE9:%[0-9]+]]:_(s1) = G_USUBE [[UV25]], [[UV27]], [[USUBO7]]
; GFX9-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[FPTOUI2]] ; GFX9-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[FPTOUI2]]
; GFX9-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE8]], [[FPTOUI2]] ; GFX9-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE8]], [[FPTOUI2]]
; GFX9-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[FPTOUI3]] ; GFX9-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[FPTOUI3]]
; GFX9-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO6]], [[FPTOUI2]] ; GFX9-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO6]], [[FPTOUI2]]
; GFX9-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]] ; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]]
; GFX9-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ADD19]], [[UMULH15]] ; GFX9-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[ADD18]], [[UMULH15]]
; GFX9-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]] ; GFX9-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]]
; GFX9-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD20]] ; GFX9-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD19]]
; GFX9-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]] ; GFX9-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]]
; GFX9-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]] ; GFX9-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]]
; GFX9-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO39]](s1) ; GFX9-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO39]](s1)
; GFX9-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UMULH16]] ; GFX9-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UMULH16]]
; GFX9-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO41]](s1) ; GFX9-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO41]](s1)
; GFX9-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]] ; GFX9-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]]
; GFX9-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD20]] ; GFX9-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD19]]
; GFX9-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]] ; GFX9-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]]
; GFX9-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD20]] ; GFX9-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD19]]
; GFX9-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]] ; GFX9-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]]
; GFX9-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1) ; GFX9-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1)
; GFX9-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UADDO42]], [[UMULH18]] ; GFX9-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[UADDO42]], [[UMULH18]]
; GFX9-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO45]](s1) ; GFX9-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO45]](s1)
; GFX9-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]] ; GFX9-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]]
; GFX9-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[UADDO44]], [[ADD21]] ; GFX9-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[UADDO44]], [[ADD20]]
; GFX9-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1) ; GFX9-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1)
; GFX9-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[ADD22]], [[ZEXT19]] ; GFX9-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ADD21]], [[ZEXT19]]
; GFX9-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD20]] ; GFX9-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD19]]
; GFX9-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD23]] ; GFX9-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD22]]
; GFX9-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO46]] ; GFX9-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO46]]
; GFX9-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD24]], [[UADDO49]] ; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD23]], [[UADDO49]]
; GFX9-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI3]], [[ADD24]]
; GFX9-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[UADDO48]] ; GFX9-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[UADDO48]]
; GFX9-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE8]], [[UADDO48]] ; GFX9-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE8]], [[UADDO48]]
; GFX9-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[UADDE10]] ; GFX9-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO6]], [[UADDE8]]
; GFX9-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO6]], [[UADDO48]] ; GFX9-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO6]], [[UADDO48]]
; GFX9-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]] ; GFX9-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]]
; GFX9-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ADD26]], [[UMULH20]] ; GFX9-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[ADD24]], [[UMULH20]]
; GFX9-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE10]], [[MUL24]] ; GFX9-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE8]], [[MUL24]]
; GFX9-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO48]], [[ADD27]] ; GFX9-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO48]], [[ADD25]]
; GFX9-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO48]], [[MUL24]] ; GFX9-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO48]], [[MUL24]]
; GFX9-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]] ; GFX9-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]]
; GFX9-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1) ; GFX9-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1)
; GFX9-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH21]] ; GFX9-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH21]]
; GFX9-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1) ; GFX9-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1)
; GFX9-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]] ; GFX9-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]]
; GFX9-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE10]], [[ADD27]] ; GFX9-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE8]], [[ADD25]]
; GFX9-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE10]], [[MUL24]] ; GFX9-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE8]], [[MUL24]]
; GFX9-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO48]], [[ADD27]] ; GFX9-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO48]], [[ADD25]]
; GFX9-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]] ; GFX9-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]]
; GFX9-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1) ; GFX9-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1)
; GFX9-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO54]], [[UMULH23]] ; GFX9-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO54]], [[UMULH23]]
; GFX9-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO57]](s1) ; GFX9-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO57]](s1)
; GFX9-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]] ; GFX9-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]]
; GFX9-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[UADDO56]], [[ADD28]] ; GFX9-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[UADDO56]], [[ADD26]]
; GFX9-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1) ; GFX9-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1)
; GFX9-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ADD29]], [[ZEXT24]] ; GFX9-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ADD27]], [[ZEXT24]]
; GFX9-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE10]], [[ADD27]] ; GFX9-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE8]], [[ADD25]]
; GFX9-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD30]] ; GFX9-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD28]]
; GFX9-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO48]], [[UADDO58]] ; GFX9-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO48]], [[UADDO58]]
; GFX9-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[ADD25]], [[ADD31]], [[UADDO49]] ; GFX9-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[ADD29]], [[UADDO61]]
; GFX9-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UADDE12]], [[C5]], [[UADDO61]]
; GFX9-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX9-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX9-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX9-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX9-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV31]], [[UADDO60]] ; GFX9-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV31]], [[UADDO60]]
; GFX9-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV30]], [[UADDE14]] ; GFX9-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV30]], [[UADDE10]]
; GFX9-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV30]], [[UADDO60]] ; GFX9-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV30]], [[UADDO60]]
; GFX9-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]] ; GFX9-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]]
; GFX9-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1) ; GFX9-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1)
; GFX9-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH25]] ; GFX9-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH25]]
; GFX9-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1) ; GFX9-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1)
; GFX9-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]] ; GFX9-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]]
; GFX9-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV31]], [[UADDE14]] ; GFX9-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV31]], [[UADDE10]]
; GFX9-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV31]], [[UADDO60]] ; GFX9-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV31]], [[UADDO60]]
; GFX9-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV30]], [[UADDE14]] ; GFX9-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV30]], [[UADDE10]]
; GFX9-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]] ; GFX9-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]]
; GFX9-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1) ; GFX9-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1)
; GFX9-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO66]], [[UMULH27]] ; GFX9-NEXT: [[UADDO68:%[0-9]+]]:_(s32), [[UADDO69:%[0-9]+]]:_(s1) = G_UADDO [[UADDO66]], [[UMULH27]]
; GFX9-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO69]](s1) ; GFX9-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO69]](s1)
; GFX9-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]] ; GFX9-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]]
; GFX9-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[UADDO68]], [[ADD32]] ; GFX9-NEXT: [[UADDO70:%[0-9]+]]:_(s32), [[UADDO71:%[0-9]+]]:_(s1) = G_UADDO [[UADDO68]], [[ADD30]]
; GFX9-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1) ; GFX9-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO71]](s1)
; GFX9-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[ADD33]], [[ZEXT29]] ; GFX9-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ADD31]], [[ZEXT29]]
; GFX9-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV31]], [[UADDE14]] ; GFX9-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV31]], [[UADDE10]]
; GFX9-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD34]] ; GFX9-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD32]]
; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO70]](s32), [[ADD35]](s32) ; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO70]](s32), [[ADD33]](s32)
; GFX9-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX9-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX9-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV32]], [[UADDO70]] ; GFX9-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV32]], [[UADDO70]]
; GFX9-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV33]], [[UADDO70]] ; GFX9-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV33]], [[UADDO70]]
; GFX9-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV32]], [[ADD35]] ; GFX9-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV32]], [[ADD33]]
; GFX9-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV32]], [[UADDO70]] ; GFX9-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV32]], [[UADDO70]]
; GFX9-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]] ; GFX9-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]]
; GFX9-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[ADD36]], [[UMULH29]] ; GFX9-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[ADD34]], [[UMULH29]]
; GFX9-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV28]], [[MUL33]] ; GFX9-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV28]], [[MUL33]]
; GFX9-NEXT: [[USUBE10:%[0-9]+]]:_(s32), [[USUBE11:%[0-9]+]]:_(s1) = G_USUBE [[UV29]], [[ADD37]], [[USUBO9]] ; GFX9-NEXT: [[USUBE10:%[0-9]+]]:_(s32), [[USUBE11:%[0-9]+]]:_(s1) = G_USUBE [[UV29]], [[ADD35]], [[USUBO9]]
; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV29]], [[ADD37]] ; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV29]], [[ADD35]]
; GFX9-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX9-NEXT: [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX9-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE10]](s32), [[UV35]] ; GFX9-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE10]](s32), [[UV35]]
; GFX9-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1) ; GFX9-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1)
; GFX9-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO8]](s32), [[UV34]] ; GFX9-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO8]](s32), [[UV34]]
; GFX9-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1) ; GFX9-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1)
; GFX9-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE10]](s32), [[UV35]] ; GFX9-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE10]](s32), [[UV35]]
; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]] ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]]
; GFX9-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[USUBO8]], [[UV34]] ; GFX9-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[USUBO8]], [[UV34]]
; GFX9-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[SUB1]], [[UV35]], [[USUBO9]] ; GFX9-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[SUB1]], [[UV35]], [[USUBO9]]
; GFX9-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[USUBE12]], [[C5]], [[USUBO11]] ; GFX9-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[USUBE12]], [[C5]], [[USUBO11]]
; GFX9-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX9-NEXT: [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX9-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UV36]] ; GFX9-NEXT: [[UADDO72:%[0-9]+]]:_(s32), [[UADDO73:%[0-9]+]]:_(s1) = G_UADDO [[UADDO70]], [[UV36]]
; GFX9-NEXT: [[UADDE16:%[0-9]+]]:_(s32), [[UADDE17:%[0-9]+]]:_(s1) = G_UADDE [[ADD35]], [[UV37]], [[UADDO73]] ; GFX9-NEXT: [[UADDE12:%[0-9]+]]:_(s32), [[UADDE13:%[0-9]+]]:_(s1) = G_UADDE [[ADD33]], [[UV37]], [[UADDO73]]
; GFX9-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO72]](s32), [[UADDE16]](s32) ; GFX9-NEXT: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO72]](s32), [[UADDE12]](s32)
; GFX9-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE14]](s32), [[UV35]] ; GFX9-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE14]](s32), [[UV35]]
; GFX9-NEXT: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[ICMP11]](s1) ; GFX9-NEXT: [[SEXT6:%[0-9]+]]:_(s32) = G_SEXT [[ICMP11]](s1)
; GFX9-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV34]] ; GFX9-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV34]]
; GFX9-NEXT: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[ICMP12]](s1) ; GFX9-NEXT: [[SEXT7:%[0-9]+]]:_(s32) = G_SEXT [[ICMP12]](s1)
; GFX9-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE14]](s32), [[UV35]] ; GFX9-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE14]](s32), [[UV35]]
; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP13]](s1), [[SEXT7]], [[SEXT6]] ; GFX9-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP13]](s1), [[SEXT7]], [[SEXT6]]
; GFX9-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64) ; GFX9-NEXT: [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
; GFX9-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[UADDO72]], [[UV38]] ; GFX9-NEXT: [[UADDO74:%[0-9]+]]:_(s32), [[UADDO75:%[0-9]+]]:_(s1) = G_UADDO [[UADDO72]], [[UV38]]
; GFX9-NEXT: [[UADDE18:%[0-9]+]]:_(s32), [[UADDE19:%[0-9]+]]:_(s1) = G_UADDE [[UADDE16]], [[UV39]], [[UADDO75]] ; GFX9-NEXT: [[UADDE14:%[0-9]+]]:_(s32), [[UADDE15:%[0-9]+]]:_(s1) = G_UADDE [[UADDE12]], [[UV39]], [[UADDO75]]
; GFX9-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO74]](s32), [[UADDE18]](s32) ; GFX9-NEXT: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO74]](s32), [[UADDE14]](s32)
; GFX9-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT5]](s32), [[C5]] ; GFX9-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT5]](s32), [[C5]]
; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP14]](s1), [[MV5]], [[MV4]] ; GFX9-NEXT: [[SELECT6:%[0-9]+]]:_(s64) = G_SELECT [[ICMP14]](s1), [[MV5]], [[MV4]]
; GFX9-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT4]](s32), [[C5]] ; GFX9-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT4]](s32), [[C5]]
; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV3]] ; GFX9-NEXT: [[SELECT7:%[0-9]+]]:_(s64) = G_SELECT [[ICMP15]](s1), [[SELECT6]], [[MV3]]
; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT3]](s64), [[SELECT7]](s64) ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SELECT3]](s64), [[SELECT7]](s64)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>) ; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7 %1:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
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; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX6-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX6-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX6-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX6-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C6]], [[UADDO23]]
; GFX6-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64) ; GFX6-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64) ; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]] ; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]]
; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE4]] ; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE2]]
; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]] ; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]]
; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE4]] ; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE2]]
; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]] ; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]]
; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE4]] ; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE2]]
; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE4]] ; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE2]]
; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD16]](s32) ; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD15]](s32)
; GFX6-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64) ; GFX6-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]] ; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]]
; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]] ; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]]
; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD16]] ; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD15]]
; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]] ; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]]
; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]] ; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD18]], [[USUBO3]] ; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD17]], [[USUBO3]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD18]] ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD17]]
; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64) ; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]] ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]]
; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]] ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]]
; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX6-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV12]] ; GFX6-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV12]]
; GFX6-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV13]], [[USUBO3]] ; GFX6-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV13]], [[USUBO3]]
; GFX6-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]] ; GFX6-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]]
; GFX6-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX6-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV14]] ; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV14]]
; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV15]], [[UADDO35]] ; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV15]], [[UADDO35]]
; GFX6-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE6]](s32) ; GFX6-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE4]](s32)
; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV13]] ; GFX6-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV13]]
; GFX6-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX6-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV12]] ; GFX6-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV12]]
; GFX6-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX6-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV13]] ; GFX6-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV13]]
; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX6-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV16]] ; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV16]]
; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[UV17]], [[UADDO37]] ; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[UV17]], [[UADDO37]]
; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE8]](s32) ; GFX6-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE6]](s32)
; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]] ; GFX6-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]]
; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]] ; GFX6-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]] ; GFX6-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]] ; GFX6-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64) ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
; GFX8-LABEL: name: test_udiv_s33 ; GFX8-LABEL: name: test_udiv_s33
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX8-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
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; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX8-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX8-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX8-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX8-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C6]], [[UADDO23]]
; GFX8-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64) ; GFX8-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64) ; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]] ; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]]
; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE4]] ; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE2]]
; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]] ; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]]
; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE4]] ; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE2]]
; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]] ; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]]
; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE4]] ; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE2]]
; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE4]] ; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE2]]
; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD16]](s32) ; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD15]](s32)
; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64) ; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]] ; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]]
; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]] ; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]]
; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD16]] ; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD15]]
; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]] ; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]]
; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]] ; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD18]], [[USUBO3]] ; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD17]], [[USUBO3]]
; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD18]] ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD17]]
; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64) ; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]] ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]] ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]]
; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]] ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX8-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV12]] ; GFX8-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV12]]
; GFX8-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV13]], [[USUBO3]] ; GFX8-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV13]], [[USUBO3]]
; GFX8-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]] ; GFX8-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]]
; GFX8-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX8-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV14]] ; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV14]]
; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV15]], [[UADDO35]] ; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV15]], [[UADDO35]]
; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE6]](s32) ; GFX8-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE4]](s32)
; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV13]] ; GFX8-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV13]]
; GFX8-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX8-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX8-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV12]] ; GFX8-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV12]]
; GFX8-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX8-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX8-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV13]] ; GFX8-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV13]]
; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX8-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV16]] ; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV16]]
; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[UV17]], [[UADDO37]] ; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[UV17]], [[UADDO37]]
; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE8]](s32) ; GFX8-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE6]](s32)
; GFX8-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]] ; GFX8-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]]
; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]] ; GFX8-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]] ; GFX8-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]] ; GFX8-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64) ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
; GFX9-LABEL: name: test_udiv_s33 ; GFX9-LABEL: name: test_udiv_s33
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
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; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX9-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX9-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX9-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX9-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX9-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX9-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX9-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX9-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C6]], [[UADDO23]]
; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64) ; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64) ; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]] ; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]]
; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE4]] ; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE2]]
; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]] ; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]]
; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE4]] ; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE2]]
; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]] ; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]]
; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE4]] ; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE2]]
; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE4]] ; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE2]]
; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD16]](s32) ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO32]](s32), [[ADD15]](s32)
; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64) ; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]] ; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]]
; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]] ; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]]
; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD16]] ; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD15]]
; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]] ; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]]
; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]] ; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD18]], [[USUBO3]] ; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD17]], [[USUBO3]]
; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD18]] ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD17]]
; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64) ; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]] ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]]
; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]] ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]]
; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]] ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
; GFX9-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV12]] ; GFX9-NEXT: [[USUBO4:%[0-9]+]]:_(s32), [[USUBO5:%[0-9]+]]:_(s1) = G_USUBO [[USUBO2]], [[UV12]]
; GFX9-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV13]], [[USUBO3]] ; GFX9-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[SUB]], [[UV13]], [[USUBO3]]
; GFX9-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]] ; GFX9-NEXT: [[USUBE6:%[0-9]+]]:_(s32), [[USUBE7:%[0-9]+]]:_(s1) = G_USUBE [[USUBE4]], [[C6]], [[USUBO5]]
; GFX9-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; GFX9-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV14]] ; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[UADDO32]], [[UV14]]
; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[ADD16]], [[UV15]], [[UADDO35]] ; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[ADD15]], [[UV15]], [[UADDO35]]
; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE6]](s32) ; GFX9-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO34]](s32), [[UADDE4]](s32)
; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV13]] ; GFX9-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE6]](s32), [[UV13]]
; GFX9-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1) ; GFX9-NEXT: [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[ICMP3]](s1)
; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV12]] ; GFX9-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO4]](s32), [[UV12]]
; GFX9-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1) ; GFX9-NEXT: [[SEXT3:%[0-9]+]]:_(s32) = G_SEXT [[ICMP4]](s1)
; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV13]] ; GFX9-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE6]](s32), [[UV13]]
; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]] ; GFX9-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SEXT3]], [[SEXT2]]
; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64) ; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C7]](s64)
; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV16]] ; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UV16]]
; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[UADDE6]], [[UV17]], [[UADDO37]] ; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[UV17]], [[UADDO37]]
; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE8]](s32) ; GFX9-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO36]](s32), [[UADDE6]](s32)
; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]] ; GFX9-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT1]](s32), [[C6]]
; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]] ; GFX9-NEXT: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]] ; GFX9-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]] ; GFX9-NEXT: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64) ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3 %1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s33) = G_TRUNC %0 %2:_(s33) = G_TRUNC %0
%3:_(s33) = G_TRUNC %1 %3:_(s33) = G_TRUNC %1
%4:_(s33) = G_UDIV %2, %3 %4:_(s33) = G_UDIV %2, %3
%5:_(s64) = G_ANYEXT %4 %5:_(s64) = G_ANYEXT %4
$vgpr0_vgpr1 = COPY %5 $vgpr0_vgpr1 = COPY %5
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir

Show First 20 Lines • Show All 283 Lines • ▼ Show 20 Lines bb.0:
; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX6-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX6-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX6-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX6-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C5]], [[UADDO23]]
; GFX6-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; GFX6-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]] ; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]]
; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE4]] ; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE2]]
; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]] ; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]]
; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE4]] ; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE2]]
; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]] ; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]]
; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE4]] ; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE2]]
; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE4]] ; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE2]]
; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX6-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) ; GFX6-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]] ; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]]
; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]] ; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]]
; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD16]] ; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD15]]
; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]] ; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]]
; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]] ; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD18]], [[USUBO3]] ; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD17]], [[USUBO3]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD18]] ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD17]]
; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) ; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]] ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]]
; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]] ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]]
; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX8-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX8-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX8-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX8-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C5]], [[UADDO23]]
; GFX8-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; GFX8-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]] ; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]]
; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE4]] ; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE2]]
; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]] ; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]]
; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE4]] ; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE2]]
; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]] ; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]]
; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE4]] ; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE2]]
; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE4]] ; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE2]]
; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) ; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]] ; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]]
; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]] ; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]]
; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD16]] ; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD15]]
; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]] ; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]]
; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]] ; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD18]], [[USUBO3]] ; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD17]], [[USUBO3]]
; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD18]] ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD17]]
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) ; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]] ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]] ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]]
; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]] ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX9-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX9-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX9-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX9-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX9-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX9-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX9-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX9-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C5]], [[UADDO23]]
; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]] ; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]]
; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE4]] ; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE2]]
; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]] ; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]]
; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE4]] ; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE2]]
; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]] ; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]]
; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE4]] ; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE2]]
; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE4]] ; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE2]]
; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) ; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]] ; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]]
; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]] ; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]]
; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD16]] ; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD15]]
; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]] ; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]]
; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]] ; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD18]], [[USUBO3]] ; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD17]], [[USUBO3]]
; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD18]] ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD17]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64) ; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]] ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]]
; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]] ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]]
; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]] ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX6-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX6-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX6-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX6-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX6-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C5]], [[UADDO23]]
; GFX6-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) ; GFX6-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) ; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDO22]] ; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDO22]]
; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV12]], [[UADDE4]] ; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV12]], [[UADDE2]]
; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDO22]] ; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDO22]]
; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDE4]] ; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDE2]]
; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDO22]] ; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDO22]]
; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDE4]] ; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDE2]]
; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDE4]] ; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDE2]]
; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) ; GFX6-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[UADDO32]] ; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[UADDO32]]
; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV15]], [[UADDO32]] ; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV15]], [[UADDO32]]
; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[ADD16]] ; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[ADD15]]
; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV14]], [[UADDO32]] ; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV14]], [[UADDO32]]
; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV10]], [[MUL15]] ; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV10]], [[MUL15]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV11]], [[ADD18]], [[USUBO3]] ; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV11]], [[ADD17]], [[USUBO3]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV11]], [[ADD18]] ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV11]], [[ADD17]]
; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) ; GFX6-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV17]] ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV17]]
; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV16]] ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV16]]
; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV17]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV17]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64) ; GFX6-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)
; GFX6-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX6-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX6-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV20]], [[UV22]] ; GFX6-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV20]], [[UV22]]
; GFX6-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV21]], [[UV23]], [[USUBO9]] ; GFX6-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV21]], [[UV23]], [[USUBO9]]
; GFX6-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI2]] ; GFX6-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI2]]
; GFX6-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE12]], [[FPTOUI2]] ; GFX6-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE12]], [[FPTOUI2]]
; GFX6-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI3]] ; GFX6-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI3]]
; GFX6-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[FPTOUI2]] ; GFX6-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[FPTOUI2]]
; GFX6-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]] ; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]]
; GFX6-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ADD19]], [[UMULH15]] ; GFX6-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[ADD18]], [[UMULH15]]
; GFX6-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]] ; GFX6-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]]
; GFX6-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD20]] ; GFX6-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD19]]
; GFX6-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]] ; GFX6-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]]
; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]] ; GFX6-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]]
; GFX6-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX6-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UMULH16]] ; GFX6-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UMULH16]]
; GFX6-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX6-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX6-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]] ; GFX6-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]]
; GFX6-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD20]] ; GFX6-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD19]]
; GFX6-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]] ; GFX6-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]]
; GFX6-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD20]] ; GFX6-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD19]]
; GFX6-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]] ; GFX6-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]]
; GFX6-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO39]](s1) ; GFX6-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO39]](s1)
; GFX6-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UMULH18]] ; GFX6-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UMULH18]]
; GFX6-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO41]](s1) ; GFX6-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO41]](s1)
; GFX6-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]] ; GFX6-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]]
; GFX6-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[UADDO40]], [[ADD21]] ; GFX6-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[UADDO40]], [[ADD20]]
; GFX6-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1) ; GFX6-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1)
; GFX6-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[ADD22]], [[ZEXT19]] ; GFX6-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ADD21]], [[ZEXT19]]
; GFX6-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD20]] ; GFX6-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD19]]
; GFX6-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD23]] ; GFX6-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD22]]
; GFX6-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO42]] ; GFX6-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO42]]
; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD24]], [[UADDO45]] ; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD23]], [[UADDO45]]
; GFX6-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI3]], [[ADD24]]
; GFX6-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDO44]] ; GFX6-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDO44]]
; GFX6-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE12]], [[UADDO44]] ; GFX6-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE12]], [[UADDO44]]
; GFX6-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDE6]] ; GFX6-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDE4]]
; GFX6-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[UADDO44]] ; GFX6-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[UADDO44]]
; GFX6-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]] ; GFX6-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]]
; GFX6-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ADD26]], [[UMULH20]] ; GFX6-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[ADD24]], [[UMULH20]]
; GFX6-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE6]], [[MUL24]] ; GFX6-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL24]]
; GFX6-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO44]], [[ADD27]] ; GFX6-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO44]], [[ADD25]]
; GFX6-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO44]], [[MUL24]] ; GFX6-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO44]], [[MUL24]]
; GFX6-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]] ; GFX6-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]]
; GFX6-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1) ; GFX6-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1)
; GFX6-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH21]] ; GFX6-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH21]]
; GFX6-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1) ; GFX6-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1)
; GFX6-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]] ; GFX6-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]]
; GFX6-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE6]], [[ADD27]] ; GFX6-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD25]]
; GFX6-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE6]], [[MUL24]] ; GFX6-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL24]]
; GFX6-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO44]], [[ADD27]] ; GFX6-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO44]], [[ADD25]]
; GFX6-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]] ; GFX6-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]]
; GFX6-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1) ; GFX6-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1)
; GFX6-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH23]] ; GFX6-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH23]]
; GFX6-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1) ; GFX6-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1)
; GFX6-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]] ; GFX6-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]]
; GFX6-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[ADD28]] ; GFX6-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[ADD26]]
; GFX6-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1) ; GFX6-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1)
; GFX6-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ADD29]], [[ZEXT24]] ; GFX6-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ADD27]], [[ZEXT24]]
; GFX6-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE6]], [[ADD27]] ; GFX6-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD25]]
; GFX6-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD30]] ; GFX6-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD28]]
; GFX6-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO44]], [[UADDO54]] ; GFX6-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO44]], [[UADDO54]]
; GFX6-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[ADD25]], [[ADD31]], [[UADDO45]] ; GFX6-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD29]], [[UADDO57]]
; GFX6-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[C5]], [[UADDO57]]
; GFX6-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX6-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX6-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX6-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX6-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV27]], [[UADDO56]] ; GFX6-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV27]], [[UADDO56]]
; GFX6-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV26]], [[UADDE10]] ; GFX6-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV26]], [[UADDE6]]
; GFX6-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV26]], [[UADDO56]] ; GFX6-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV26]], [[UADDO56]]
; GFX6-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]] ; GFX6-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]]
; GFX6-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1) ; GFX6-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1)
; GFX6-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH25]] ; GFX6-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH25]]
; GFX6-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1) ; GFX6-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1)
; GFX6-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]] ; GFX6-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]]
; GFX6-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV27]], [[UADDE10]] ; GFX6-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV27]], [[UADDE6]]
; GFX6-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV27]], [[UADDO56]] ; GFX6-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV27]], [[UADDO56]]
; GFX6-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV26]], [[UADDE10]] ; GFX6-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV26]], [[UADDE6]]
; GFX6-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]] ; GFX6-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]]
; GFX6-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1) ; GFX6-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1)
; GFX6-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH27]] ; GFX6-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH27]]
; GFX6-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1) ; GFX6-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1)
; GFX6-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]] ; GFX6-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]]
; GFX6-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[UADDO64]], [[ADD32]] ; GFX6-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[UADDO64]], [[ADD30]]
; GFX6-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1) ; GFX6-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1)
; GFX6-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[ADD33]], [[ZEXT29]] ; GFX6-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ADD31]], [[ZEXT29]]
; GFX6-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV27]], [[UADDE10]] ; GFX6-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV27]], [[UADDE6]]
; GFX6-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD34]] ; GFX6-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD32]]
; GFX6-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX6-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX6-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV28]], [[UADDO66]] ; GFX6-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV28]], [[UADDO66]]
; GFX6-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV29]], [[UADDO66]] ; GFX6-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV29]], [[UADDO66]]
; GFX6-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV28]], [[ADD35]] ; GFX6-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV28]], [[ADD33]]
; GFX6-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV28]], [[UADDO66]] ; GFX6-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV28]], [[UADDO66]]
; GFX6-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]] ; GFX6-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]]
; GFX6-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[ADD36]], [[UMULH29]] ; GFX6-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[ADD34]], [[UMULH29]]
; GFX6-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV24]], [[MUL33]] ; GFX6-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV24]], [[MUL33]]
; GFX6-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[UV25]], [[ADD37]], [[USUBO11]] ; GFX6-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[UV25]], [[ADD35]], [[USUBO11]]
; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV25]], [[ADD37]] ; GFX6-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV25]], [[ADD35]]
; GFX6-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO10]](s32), [[USUBE14]](s32) ; GFX6-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO10]](s32), [[USUBE14]](s32)
; GFX6-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX6-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX6-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE14]](s32), [[UV31]] ; GFX6-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE14]](s32), [[UV31]]
; GFX6-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1) ; GFX6-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1)
; GFX6-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV30]] ; GFX6-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV30]]
; GFX6-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1) ; GFX6-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1)
; GFX6-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE14]](s32), [[UV31]] ; GFX6-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE14]](s32), [[UV31]]
; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]] ; GFX6-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]]
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; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX8-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX8-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX8-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX8-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C5]], [[UADDO23]]
; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) ; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) ; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDO22]] ; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDO22]]
; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV12]], [[UADDE4]] ; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV12]], [[UADDE2]]
; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDO22]] ; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDO22]]
; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDE4]] ; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDE2]]
; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDO22]] ; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDO22]]
; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDE4]] ; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDE2]]
; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDE4]] ; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDE2]]
; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) ; GFX8-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[UADDO32]] ; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[UADDO32]]
; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV15]], [[UADDO32]] ; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV15]], [[UADDO32]]
; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[ADD16]] ; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[ADD15]]
; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV14]], [[UADDO32]] ; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV14]], [[UADDO32]]
; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV10]], [[MUL15]] ; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV10]], [[MUL15]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV11]], [[ADD18]], [[USUBO3]] ; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV11]], [[ADD17]], [[USUBO3]]
; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV11]], [[ADD18]] ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV11]], [[ADD17]]
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) ; GFX8-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV17]] ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV17]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV16]] ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV16]]
; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV17]] ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV17]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64) ; GFX8-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)
; GFX8-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX8-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX8-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV20]], [[UV22]] ; GFX8-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV20]], [[UV22]]
; GFX8-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV21]], [[UV23]], [[USUBO9]] ; GFX8-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV21]], [[UV23]], [[USUBO9]]
; GFX8-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI2]] ; GFX8-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI2]]
; GFX8-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE12]], [[FPTOUI2]] ; GFX8-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE12]], [[FPTOUI2]]
; GFX8-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI3]] ; GFX8-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI3]]
; GFX8-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[FPTOUI2]] ; GFX8-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[FPTOUI2]]
; GFX8-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]] ; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]]
; GFX8-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ADD19]], [[UMULH15]] ; GFX8-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[ADD18]], [[UMULH15]]
; GFX8-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]] ; GFX8-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]]
; GFX8-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD20]] ; GFX8-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD19]]
; GFX8-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]] ; GFX8-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]]
; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]] ; GFX8-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]]
; GFX8-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX8-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UMULH16]] ; GFX8-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UMULH16]]
; GFX8-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX8-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX8-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]] ; GFX8-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]]
; GFX8-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD20]] ; GFX8-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD19]]
; GFX8-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]] ; GFX8-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]]
; GFX8-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD20]] ; GFX8-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD19]]
; GFX8-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]] ; GFX8-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]]
; GFX8-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO39]](s1) ; GFX8-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO39]](s1)
; GFX8-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UMULH18]] ; GFX8-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UMULH18]]
; GFX8-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO41]](s1) ; GFX8-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO41]](s1)
; GFX8-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]] ; GFX8-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]]
; GFX8-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[UADDO40]], [[ADD21]] ; GFX8-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[UADDO40]], [[ADD20]]
; GFX8-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1) ; GFX8-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1)
; GFX8-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[ADD22]], [[ZEXT19]] ; GFX8-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ADD21]], [[ZEXT19]]
; GFX8-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD20]] ; GFX8-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD19]]
; GFX8-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD23]] ; GFX8-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD22]]
; GFX8-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO42]] ; GFX8-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO42]]
; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD24]], [[UADDO45]] ; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD23]], [[UADDO45]]
; GFX8-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI3]], [[ADD24]]
; GFX8-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDO44]] ; GFX8-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDO44]]
; GFX8-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE12]], [[UADDO44]] ; GFX8-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE12]], [[UADDO44]]
; GFX8-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDE6]] ; GFX8-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDE4]]
; GFX8-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[UADDO44]] ; GFX8-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[UADDO44]]
; GFX8-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]] ; GFX8-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]]
; GFX8-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ADD26]], [[UMULH20]] ; GFX8-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[ADD24]], [[UMULH20]]
; GFX8-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE6]], [[MUL24]] ; GFX8-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL24]]
; GFX8-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO44]], [[ADD27]] ; GFX8-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO44]], [[ADD25]]
; GFX8-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO44]], [[MUL24]] ; GFX8-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO44]], [[MUL24]]
; GFX8-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]] ; GFX8-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]]
; GFX8-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1) ; GFX8-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1)
; GFX8-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH21]] ; GFX8-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH21]]
; GFX8-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1) ; GFX8-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1)
; GFX8-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]] ; GFX8-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]]
; GFX8-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE6]], [[ADD27]] ; GFX8-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD25]]
; GFX8-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE6]], [[MUL24]] ; GFX8-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL24]]
; GFX8-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO44]], [[ADD27]] ; GFX8-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO44]], [[ADD25]]
; GFX8-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]] ; GFX8-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]]
; GFX8-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1) ; GFX8-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1)
; GFX8-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH23]] ; GFX8-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH23]]
; GFX8-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1) ; GFX8-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1)
; GFX8-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]] ; GFX8-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]]
; GFX8-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[ADD28]] ; GFX8-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[ADD26]]
; GFX8-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1) ; GFX8-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1)
; GFX8-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ADD29]], [[ZEXT24]] ; GFX8-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ADD27]], [[ZEXT24]]
; GFX8-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE6]], [[ADD27]] ; GFX8-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD25]]
; GFX8-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD30]] ; GFX8-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD28]]
; GFX8-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO44]], [[UADDO54]] ; GFX8-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO44]], [[UADDO54]]
; GFX8-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[ADD25]], [[ADD31]], [[UADDO45]] ; GFX8-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD29]], [[UADDO57]]
; GFX8-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[C5]], [[UADDO57]]
; GFX8-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX8-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX8-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX8-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX8-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV27]], [[UADDO56]] ; GFX8-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV27]], [[UADDO56]]
; GFX8-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV26]], [[UADDE10]] ; GFX8-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV26]], [[UADDE6]]
; GFX8-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV26]], [[UADDO56]] ; GFX8-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV26]], [[UADDO56]]
; GFX8-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]] ; GFX8-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]]
; GFX8-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1) ; GFX8-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1)
; GFX8-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH25]] ; GFX8-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH25]]
; GFX8-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1) ; GFX8-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1)
; GFX8-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]] ; GFX8-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]]
; GFX8-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV27]], [[UADDE10]] ; GFX8-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV27]], [[UADDE6]]
; GFX8-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV27]], [[UADDO56]] ; GFX8-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV27]], [[UADDO56]]
; GFX8-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV26]], [[UADDE10]] ; GFX8-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV26]], [[UADDE6]]
; GFX8-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]] ; GFX8-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]]
; GFX8-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1) ; GFX8-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1)
; GFX8-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH27]] ; GFX8-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH27]]
; GFX8-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1) ; GFX8-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1)
; GFX8-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]] ; GFX8-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]]
; GFX8-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[UADDO64]], [[ADD32]] ; GFX8-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[UADDO64]], [[ADD30]]
; GFX8-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1) ; GFX8-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1)
; GFX8-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[ADD33]], [[ZEXT29]] ; GFX8-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ADD31]], [[ZEXT29]]
; GFX8-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV27]], [[UADDE10]] ; GFX8-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV27]], [[UADDE6]]
; GFX8-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD34]] ; GFX8-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD32]]
; GFX8-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX8-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX8-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV28]], [[UADDO66]] ; GFX8-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV28]], [[UADDO66]]
; GFX8-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV29]], [[UADDO66]] ; GFX8-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV29]], [[UADDO66]]
; GFX8-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV28]], [[ADD35]] ; GFX8-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV28]], [[ADD33]]
; GFX8-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV28]], [[UADDO66]] ; GFX8-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV28]], [[UADDO66]]
; GFX8-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]] ; GFX8-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]]
; GFX8-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[ADD36]], [[UMULH29]] ; GFX8-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[ADD34]], [[UMULH29]]
; GFX8-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV24]], [[MUL33]] ; GFX8-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV24]], [[MUL33]]
; GFX8-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[UV25]], [[ADD37]], [[USUBO11]] ; GFX8-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[UV25]], [[ADD35]], [[USUBO11]]
; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV25]], [[ADD37]] ; GFX8-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV25]], [[ADD35]]
; GFX8-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO10]](s32), [[USUBE14]](s32) ; GFX8-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO10]](s32), [[USUBE14]](s32)
; GFX8-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX8-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX8-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE14]](s32), [[UV31]] ; GFX8-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE14]](s32), [[UV31]]
; GFX8-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1) ; GFX8-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1)
; GFX8-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV30]] ; GFX8-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV30]]
; GFX8-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1) ; GFX8-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1)
; GFX8-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE14]](s32), [[UV31]] ; GFX8-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE14]](s32), [[UV31]]
; GFX8-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]] ; GFX8-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]]
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; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX9-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX9-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX9-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX9-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX9-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX9-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX9-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX9-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C5]], [[UADDO23]]
; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) ; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64) ; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDO22]] ; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDO22]]
; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV12]], [[UADDE4]] ; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV12]], [[UADDE2]]
; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDO22]] ; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDO22]]
; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDE4]] ; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV13]], [[UADDE2]]
; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDO22]] ; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDO22]]
; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDE4]] ; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV12]], [[UADDE2]]
; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDE4]] ; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV13]], [[UADDE2]]
; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) ; GFX9-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[UADDO32]] ; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[UADDO32]]
; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV15]], [[UADDO32]] ; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV15]], [[UADDO32]]
; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[ADD16]] ; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV14]], [[ADD15]]
; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV14]], [[UADDO32]] ; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV14]], [[UADDO32]]
; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV10]], [[MUL15]] ; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV10]], [[MUL15]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV11]], [[ADD18]], [[USUBO3]] ; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV11]], [[ADD17]], [[USUBO3]]
; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV11]], [[ADD18]] ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV11]], [[ADD17]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64) ; GFX9-NEXT: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV17]] ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV17]]
; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV16]] ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV16]]
; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV17]] ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV17]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64) ; GFX9-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)
; GFX9-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX9-NEXT: [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX9-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV20]], [[UV22]] ; GFX9-NEXT: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV20]], [[UV22]]
; GFX9-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV21]], [[UV23]], [[USUBO9]] ; GFX9-NEXT: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV21]], [[UV23]], [[USUBO9]]
; GFX9-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI2]] ; GFX9-NEXT: [[MUL18:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI2]]
; GFX9-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE12]], [[FPTOUI2]] ; GFX9-NEXT: [[MUL19:%[0-9]+]]:_(s32) = G_MUL [[USUBE12]], [[FPTOUI2]]
; GFX9-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI3]] ; GFX9-NEXT: [[MUL20:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[FPTOUI3]]
; GFX9-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[FPTOUI2]] ; GFX9-NEXT: [[UMULH15:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[FPTOUI2]]
; GFX9-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]] ; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[MUL19]], [[MUL20]]
; GFX9-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ADD19]], [[UMULH15]] ; GFX9-NEXT: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[ADD18]], [[UMULH15]]
; GFX9-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]] ; GFX9-NEXT: [[MUL21:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[MUL18]]
; GFX9-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD20]] ; GFX9-NEXT: [[MUL22:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI2]], [[ADD19]]
; GFX9-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]] ; GFX9-NEXT: [[UMULH16:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[MUL18]]
; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]] ; GFX9-NEXT: [[UADDO34:%[0-9]+]]:_(s32), [[UADDO35:%[0-9]+]]:_(s1) = G_UADDO [[MUL21]], [[MUL22]]
; GFX9-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1) ; GFX9-NEXT: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO35]](s1)
; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UMULH16]] ; GFX9-NEXT: [[UADDO36:%[0-9]+]]:_(s32), [[UADDO37:%[0-9]+]]:_(s1) = G_UADDO [[UADDO34]], [[UMULH16]]
; GFX9-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1) ; GFX9-NEXT: [[ZEXT16:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO37]](s1)
; GFX9-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]] ; GFX9-NEXT: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[ZEXT15]], [[ZEXT16]]
; GFX9-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD20]] ; GFX9-NEXT: [[MUL23:%[0-9]+]]:_(s32) = G_MUL [[FPTOUI3]], [[ADD19]]
; GFX9-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]] ; GFX9-NEXT: [[UMULH17:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[MUL18]]
; GFX9-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD20]] ; GFX9-NEXT: [[UMULH18:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI2]], [[ADD19]]
; GFX9-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]] ; GFX9-NEXT: [[UADDO38:%[0-9]+]]:_(s32), [[UADDO39:%[0-9]+]]:_(s1) = G_UADDO [[MUL23]], [[UMULH17]]
; GFX9-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO39]](s1) ; GFX9-NEXT: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO39]](s1)
; GFX9-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UMULH18]] ; GFX9-NEXT: [[UADDO40:%[0-9]+]]:_(s32), [[UADDO41:%[0-9]+]]:_(s1) = G_UADDO [[UADDO38]], [[UMULH18]]
; GFX9-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO41]](s1) ; GFX9-NEXT: [[ZEXT18:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO41]](s1)
; GFX9-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]] ; GFX9-NEXT: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[ZEXT17]], [[ZEXT18]]
; GFX9-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[UADDO40]], [[ADD21]] ; GFX9-NEXT: [[UADDO42:%[0-9]+]]:_(s32), [[UADDO43:%[0-9]+]]:_(s1) = G_UADDO [[UADDO40]], [[ADD20]]
; GFX9-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1) ; GFX9-NEXT: [[ZEXT19:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO43]](s1)
; GFX9-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[ADD22]], [[ZEXT19]] ; GFX9-NEXT: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[ADD21]], [[ZEXT19]]
; GFX9-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD20]] ; GFX9-NEXT: [[UMULH19:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI3]], [[ADD19]]
; GFX9-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD23]] ; GFX9-NEXT: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UMULH19]], [[ADD22]]
; GFX9-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO42]] ; GFX9-NEXT: [[UADDO44:%[0-9]+]]:_(s32), [[UADDO45:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI2]], [[UADDO42]]
; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD24]], [[UADDO45]] ; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI3]], [[ADD23]], [[UADDO45]]
; GFX9-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI3]], [[ADD24]]
; GFX9-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDO44]] ; GFX9-NEXT: [[MUL24:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDO44]]
; GFX9-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE12]], [[UADDO44]] ; GFX9-NEXT: [[MUL25:%[0-9]+]]:_(s32) = G_MUL [[USUBE12]], [[UADDO44]]
; GFX9-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDE6]] ; GFX9-NEXT: [[MUL26:%[0-9]+]]:_(s32) = G_MUL [[USUBO8]], [[UADDE4]]
; GFX9-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[UADDO44]] ; GFX9-NEXT: [[UMULH20:%[0-9]+]]:_(s32) = G_UMULH [[USUBO8]], [[UADDO44]]
; GFX9-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]] ; GFX9-NEXT: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[MUL25]], [[MUL26]]
; GFX9-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ADD26]], [[UMULH20]] ; GFX9-NEXT: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[ADD24]], [[UMULH20]]
; GFX9-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE6]], [[MUL24]] ; GFX9-NEXT: [[MUL27:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[MUL24]]
; GFX9-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO44]], [[ADD27]] ; GFX9-NEXT: [[MUL28:%[0-9]+]]:_(s32) = G_MUL [[UADDO44]], [[ADD25]]
; GFX9-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO44]], [[MUL24]] ; GFX9-NEXT: [[UMULH21:%[0-9]+]]:_(s32) = G_UMULH [[UADDO44]], [[MUL24]]
; GFX9-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]] ; GFX9-NEXT: [[UADDO46:%[0-9]+]]:_(s32), [[UADDO47:%[0-9]+]]:_(s1) = G_UADDO [[MUL27]], [[MUL28]]
; GFX9-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1) ; GFX9-NEXT: [[ZEXT20:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO47]](s1)
; GFX9-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH21]] ; GFX9-NEXT: [[UADDO48:%[0-9]+]]:_(s32), [[UADDO49:%[0-9]+]]:_(s1) = G_UADDO [[UADDO46]], [[UMULH21]]
; GFX9-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1) ; GFX9-NEXT: [[ZEXT21:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO49]](s1)
; GFX9-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]] ; GFX9-NEXT: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[ZEXT20]], [[ZEXT21]]
; GFX9-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE6]], [[ADD27]] ; GFX9-NEXT: [[MUL29:%[0-9]+]]:_(s32) = G_MUL [[UADDE4]], [[ADD25]]
; GFX9-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE6]], [[MUL24]] ; GFX9-NEXT: [[UMULH22:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[MUL24]]
; GFX9-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO44]], [[ADD27]] ; GFX9-NEXT: [[UMULH23:%[0-9]+]]:_(s32) = G_UMULH [[UADDO44]], [[ADD25]]
; GFX9-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]] ; GFX9-NEXT: [[UADDO50:%[0-9]+]]:_(s32), [[UADDO51:%[0-9]+]]:_(s1) = G_UADDO [[MUL29]], [[UMULH22]]
; GFX9-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1) ; GFX9-NEXT: [[ZEXT22:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO51]](s1)
; GFX9-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH23]] ; GFX9-NEXT: [[UADDO52:%[0-9]+]]:_(s32), [[UADDO53:%[0-9]+]]:_(s1) = G_UADDO [[UADDO50]], [[UMULH23]]
; GFX9-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1) ; GFX9-NEXT: [[ZEXT23:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO53]](s1)
; GFX9-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]] ; GFX9-NEXT: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[ZEXT22]], [[ZEXT23]]
; GFX9-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[ADD28]] ; GFX9-NEXT: [[UADDO54:%[0-9]+]]:_(s32), [[UADDO55:%[0-9]+]]:_(s1) = G_UADDO [[UADDO52]], [[ADD26]]
; GFX9-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1) ; GFX9-NEXT: [[ZEXT24:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO55]](s1)
; GFX9-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ADD29]], [[ZEXT24]] ; GFX9-NEXT: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[ADD27]], [[ZEXT24]]
; GFX9-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE6]], [[ADD27]] ; GFX9-NEXT: [[UMULH24:%[0-9]+]]:_(s32) = G_UMULH [[UADDE4]], [[ADD25]]
; GFX9-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD30]] ; GFX9-NEXT: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UMULH24]], [[ADD28]]
; GFX9-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO44]], [[UADDO54]] ; GFX9-NEXT: [[UADDO56:%[0-9]+]]:_(s32), [[UADDO57:%[0-9]+]]:_(s1) = G_UADDO [[UADDO44]], [[UADDO54]]
; GFX9-NEXT: [[UADDE8:%[0-9]+]]:_(s32), [[UADDE9:%[0-9]+]]:_(s1) = G_UADDE [[ADD25]], [[ADD31]], [[UADDO45]] ; GFX9-NEXT: [[UADDE6:%[0-9]+]]:_(s32), [[UADDE7:%[0-9]+]]:_(s1) = G_UADDE [[UADDE4]], [[ADD29]], [[UADDO57]]
; GFX9-NEXT: [[UADDE10:%[0-9]+]]:_(s32), [[UADDE11:%[0-9]+]]:_(s1) = G_UADDE [[UADDE8]], [[C5]], [[UADDO57]]
; GFX9-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX9-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX9-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64) ; GFX9-NEXT: [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; GFX9-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV27]], [[UADDO56]] ; GFX9-NEXT: [[MUL30:%[0-9]+]]:_(s32) = G_MUL [[UV27]], [[UADDO56]]
; GFX9-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV26]], [[UADDE10]] ; GFX9-NEXT: [[MUL31:%[0-9]+]]:_(s32) = G_MUL [[UV26]], [[UADDE6]]
; GFX9-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV26]], [[UADDO56]] ; GFX9-NEXT: [[UMULH25:%[0-9]+]]:_(s32) = G_UMULH [[UV26]], [[UADDO56]]
; GFX9-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]] ; GFX9-NEXT: [[UADDO58:%[0-9]+]]:_(s32), [[UADDO59:%[0-9]+]]:_(s1) = G_UADDO [[MUL30]], [[MUL31]]
; GFX9-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1) ; GFX9-NEXT: [[ZEXT25:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO59]](s1)
; GFX9-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH25]] ; GFX9-NEXT: [[UADDO60:%[0-9]+]]:_(s32), [[UADDO61:%[0-9]+]]:_(s1) = G_UADDO [[UADDO58]], [[UMULH25]]
; GFX9-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1) ; GFX9-NEXT: [[ZEXT26:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO61]](s1)
; GFX9-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]] ; GFX9-NEXT: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[ZEXT25]], [[ZEXT26]]
; GFX9-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV27]], [[UADDE10]] ; GFX9-NEXT: [[MUL32:%[0-9]+]]:_(s32) = G_MUL [[UV27]], [[UADDE6]]
; GFX9-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV27]], [[UADDO56]] ; GFX9-NEXT: [[UMULH26:%[0-9]+]]:_(s32) = G_UMULH [[UV27]], [[UADDO56]]
; GFX9-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV26]], [[UADDE10]] ; GFX9-NEXT: [[UMULH27:%[0-9]+]]:_(s32) = G_UMULH [[UV26]], [[UADDE6]]
; GFX9-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]] ; GFX9-NEXT: [[UADDO62:%[0-9]+]]:_(s32), [[UADDO63:%[0-9]+]]:_(s1) = G_UADDO [[MUL32]], [[UMULH26]]
; GFX9-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1) ; GFX9-NEXT: [[ZEXT27:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO63]](s1)
; GFX9-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH27]] ; GFX9-NEXT: [[UADDO64:%[0-9]+]]:_(s32), [[UADDO65:%[0-9]+]]:_(s1) = G_UADDO [[UADDO62]], [[UMULH27]]
; GFX9-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1) ; GFX9-NEXT: [[ZEXT28:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO65]](s1)
; GFX9-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]] ; GFX9-NEXT: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[ZEXT27]], [[ZEXT28]]
; GFX9-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[UADDO64]], [[ADD32]] ; GFX9-NEXT: [[UADDO66:%[0-9]+]]:_(s32), [[UADDO67:%[0-9]+]]:_(s1) = G_UADDO [[UADDO64]], [[ADD30]]
; GFX9-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1) ; GFX9-NEXT: [[ZEXT29:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO67]](s1)
; GFX9-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[ADD33]], [[ZEXT29]] ; GFX9-NEXT: [[ADD32:%[0-9]+]]:_(s32) = G_ADD [[ADD31]], [[ZEXT29]]
; GFX9-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV27]], [[UADDE10]] ; GFX9-NEXT: [[UMULH28:%[0-9]+]]:_(s32) = G_UMULH [[UV27]], [[UADDE6]]
; GFX9-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD34]] ; GFX9-NEXT: [[ADD33:%[0-9]+]]:_(s32) = G_ADD [[UMULH28]], [[ADD32]]
; GFX9-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX9-NEXT: [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX9-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV28]], [[UADDO66]] ; GFX9-NEXT: [[MUL33:%[0-9]+]]:_(s32) = G_MUL [[UV28]], [[UADDO66]]
; GFX9-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV29]], [[UADDO66]] ; GFX9-NEXT: [[MUL34:%[0-9]+]]:_(s32) = G_MUL [[UV29]], [[UADDO66]]
; GFX9-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV28]], [[ADD35]] ; GFX9-NEXT: [[MUL35:%[0-9]+]]:_(s32) = G_MUL [[UV28]], [[ADD33]]
; GFX9-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV28]], [[UADDO66]] ; GFX9-NEXT: [[UMULH29:%[0-9]+]]:_(s32) = G_UMULH [[UV28]], [[UADDO66]]
; GFX9-NEXT: [[ADD36:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]] ; GFX9-NEXT: [[ADD34:%[0-9]+]]:_(s32) = G_ADD [[MUL34]], [[MUL35]]
; GFX9-NEXT: [[ADD37:%[0-9]+]]:_(s32) = G_ADD [[ADD36]], [[UMULH29]] ; GFX9-NEXT: [[ADD35:%[0-9]+]]:_(s32) = G_ADD [[ADD34]], [[UMULH29]]
; GFX9-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV24]], [[MUL33]] ; GFX9-NEXT: [[USUBO10:%[0-9]+]]:_(s32), [[USUBO11:%[0-9]+]]:_(s1) = G_USUBO [[UV24]], [[MUL33]]
; GFX9-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[UV25]], [[ADD37]], [[USUBO11]] ; GFX9-NEXT: [[USUBE14:%[0-9]+]]:_(s32), [[USUBE15:%[0-9]+]]:_(s1) = G_USUBE [[UV25]], [[ADD35]], [[USUBO11]]
; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV25]], [[ADD37]] ; GFX9-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV25]], [[ADD35]]
; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO10]](s32), [[USUBE14]](s32) ; GFX9-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO10]](s32), [[USUBE14]](s32)
; GFX9-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64) ; GFX9-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](s64)
; GFX9-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE14]](s32), [[UV31]] ; GFX9-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE14]](s32), [[UV31]]
; GFX9-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1) ; GFX9-NEXT: [[SEXT4:%[0-9]+]]:_(s32) = G_SEXT [[ICMP8]](s1)
; GFX9-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV30]] ; GFX9-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO10]](s32), [[UV30]]
; GFX9-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1) ; GFX9-NEXT: [[SEXT5:%[0-9]+]]:_(s32) = G_SEXT [[ICMP9]](s1)
; GFX9-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE14]](s32), [[UV31]] ; GFX9-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE14]](s32), [[UV31]]
; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]] ; GFX9-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP10]](s1), [[SEXT5]], [[SEXT4]]
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; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX6-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX6-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX6-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX6-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX6-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX6-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX6-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX6-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX6-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX6-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX6-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX6-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX6-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX6-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX6-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX6-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX6-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX6-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX6-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX6-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX6-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX6-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX6-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX6-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX6-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX6-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX6-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX6-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX6-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX6-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX6-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX6-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX6-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX6-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX6-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX6-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX6-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX6-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX6-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX6-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX6-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C6]], [[UADDO23]]
; GFX6-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64) ; GFX6-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64) ; GFX6-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]] ; GFX6-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]]
; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE4]] ; GFX6-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE2]]
; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]] ; GFX6-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]]
; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX6-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX6-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX6-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX6-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX6-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE4]] ; GFX6-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE2]]
; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]] ; GFX6-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]]
; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE4]] ; GFX6-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE2]]
; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX6-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX6-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX6-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX6-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX6-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX6-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX6-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX6-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE4]] ; GFX6-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE2]]
; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX6-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX6-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64) ; GFX6-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]] ; GFX6-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]]
; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]] ; GFX6-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]]
; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD16]] ; GFX6-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD15]]
; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]] ; GFX6-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]]
; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX6-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX6-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX6-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]] ; GFX6-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]]
; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD18]], [[USUBO3]] ; GFX6-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD17]], [[USUBO3]]
; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD18]] ; GFX6-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD17]]
; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX6-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64) ; GFX6-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]] ; GFX6-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]]
; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]] ; GFX6-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]]
; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX6-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]] ; GFX6-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]]
; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX8-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX8-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX8-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX8-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX8-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX8-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX8-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX8-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX8-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX8-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX8-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX8-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX8-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX8-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX8-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX8-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX8-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX8-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX8-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX8-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX8-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX8-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX8-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX8-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX8-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX8-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX8-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX8-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX8-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX8-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX8-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX8-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX8-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX8-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX8-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX8-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX8-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX8-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX8-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX8-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C6]], [[UADDO23]]
; GFX8-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64) ; GFX8-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64) ; GFX8-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]] ; GFX8-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]]
; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE4]] ; GFX8-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE2]]
; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]] ; GFX8-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]]
; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX8-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX8-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX8-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX8-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX8-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE4]] ; GFX8-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE2]]
; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]] ; GFX8-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]]
; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE4]] ; GFX8-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE2]]
; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX8-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX8-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX8-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX8-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX8-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX8-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX8-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX8-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE4]] ; GFX8-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE2]]
; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX8-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64) ; GFX8-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]] ; GFX8-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]]
; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]] ; GFX8-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]]
; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD16]] ; GFX8-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD15]]
; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]] ; GFX8-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]]
; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX8-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX8-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX8-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]] ; GFX8-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]]
; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD18]], [[USUBO3]] ; GFX8-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD17]], [[USUBO3]]
; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD18]] ; GFX8-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD17]]
; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX8-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64) ; GFX8-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]] ; GFX8-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]]
; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]] ; GFX8-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]]
; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX8-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]] ; GFX8-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]]
; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
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; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]] ; GFX9-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[ZEXT2]], [[ZEXT3]]
; GFX9-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]] ; GFX9-NEXT: [[UADDO8:%[0-9]+]]:_(s32), [[UADDO9:%[0-9]+]]:_(s1) = G_UADDO [[UADDO6]], [[ADD2]]
; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1) ; GFX9-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO9]](s1)
; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]] ; GFX9-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[ZEXT4]]
; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]] ; GFX9-NEXT: [[UMULH4:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI1]], [[ADD1]]
; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]] ; GFX9-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UMULH4]], [[ADD4]]
; GFX9-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]] ; GFX9-NEXT: [[UADDO10:%[0-9]+]]:_(s32), [[UADDO11:%[0-9]+]]:_(s1) = G_UADDO [[FPTOUI]], [[UADDO8]]
; GFX9-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]] ; GFX9-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[FPTOUI1]], [[ADD5]], [[UADDO11]]
; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI1]], [[ADD5]]
; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]] ; GFX9-NEXT: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDO10]]
; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]] ; GFX9-NEXT: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[USUBE]], [[UADDO10]]
; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]] ; GFX9-NEXT: [[MUL8:%[0-9]+]]:_(s32) = G_MUL [[USUBO]], [[UADDE]]
; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]] ; GFX9-NEXT: [[UMULH5:%[0-9]+]]:_(s32) = G_UMULH [[USUBO]], [[UADDO10]]
; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]] ; GFX9-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[MUL7]], [[MUL8]]
; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[UMULH5]] ; GFX9-NEXT: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH5]]
; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]] ; GFX9-NEXT: [[MUL9:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[MUL6]]
; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD8]] ; GFX9-NEXT: [[MUL10:%[0-9]+]]:_(s32) = G_MUL [[UADDO10]], [[ADD7]]
; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]] ; GFX9-NEXT: [[UMULH6:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[MUL6]]
; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]] ; GFX9-NEXT: [[UADDO12:%[0-9]+]]:_(s32), [[UADDO13:%[0-9]+]]:_(s1) = G_UADDO [[MUL9]], [[MUL10]]
; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1) ; GFX9-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO13]](s1)
; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]] ; GFX9-NEXT: [[UADDO14:%[0-9]+]]:_(s32), [[UADDO15:%[0-9]+]]:_(s1) = G_UADDO [[UADDO12]], [[UMULH6]]
; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1) ; GFX9-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO15]](s1)
; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]] ; GFX9-NEXT: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ZEXT5]], [[ZEXT6]]
; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD8]] ; GFX9-NEXT: [[MUL11:%[0-9]+]]:_(s32) = G_MUL [[UADDE]], [[ADD7]]
; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]] ; GFX9-NEXT: [[UMULH7:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[MUL6]]
; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD8]] ; GFX9-NEXT: [[UMULH8:%[0-9]+]]:_(s32) = G_UMULH [[UADDO10]], [[ADD7]]
; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]] ; GFX9-NEXT: [[UADDO16:%[0-9]+]]:_(s32), [[UADDO17:%[0-9]+]]:_(s1) = G_UADDO [[MUL11]], [[UMULH7]]
; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1) ; GFX9-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO17]](s1)
; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]] ; GFX9-NEXT: [[UADDO18:%[0-9]+]]:_(s32), [[UADDO19:%[0-9]+]]:_(s1) = G_UADDO [[UADDO16]], [[UMULH8]]
; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1) ; GFX9-NEXT: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO19]](s1)
; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]] ; GFX9-NEXT: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ZEXT7]], [[ZEXT8]]
; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD9]] ; GFX9-NEXT: [[UADDO20:%[0-9]+]]:_(s32), [[UADDO21:%[0-9]+]]:_(s1) = G_UADDO [[UADDO18]], [[ADD8]]
; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1) ; GFX9-NEXT: [[ZEXT9:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO21]](s1)
; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD10]], [[ZEXT9]] ; GFX9-NEXT: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[ZEXT9]]
; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD8]] ; GFX9-NEXT: [[UMULH9:%[0-9]+]]:_(s32) = G_UMULH [[UADDE]], [[ADD7]]
; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD11]] ; GFX9-NEXT: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UMULH9]], [[ADD10]]
; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]] ; GFX9-NEXT: [[UADDO22:%[0-9]+]]:_(s32), [[UADDO23:%[0-9]+]]:_(s1) = G_UADDO [[UADDO10]], [[UADDO20]]
; GFX9-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[ADD6]], [[ADD12]], [[UADDO11]] ; GFX9-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UADDE]], [[ADD11]], [[UADDO23]]
; GFX9-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UADDE2]], [[C6]], [[UADDO23]]
; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64) ; GFX9-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64) ; GFX9-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]] ; GFX9-NEXT: [[MUL12:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDO22]]
; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE4]] ; GFX9-NEXT: [[MUL13:%[0-9]+]]:_(s32) = G_MUL [[UV8]], [[UADDE2]]
; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]] ; GFX9-NEXT: [[UMULH10:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDO22]]
; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]] ; GFX9-NEXT: [[UADDO24:%[0-9]+]]:_(s32), [[UADDO25:%[0-9]+]]:_(s1) = G_UADDO [[MUL12]], [[MUL13]]
; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1) ; GFX9-NEXT: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO25]](s1)
; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]] ; GFX9-NEXT: [[UADDO26:%[0-9]+]]:_(s32), [[UADDO27:%[0-9]+]]:_(s1) = G_UADDO [[UADDO24]], [[UMULH10]]
; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1) ; GFX9-NEXT: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO27]](s1)
; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]] ; GFX9-NEXT: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[ZEXT10]], [[ZEXT11]]
; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE4]] ; GFX9-NEXT: [[MUL14:%[0-9]+]]:_(s32) = G_MUL [[UV9]], [[UADDE2]]
; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]] ; GFX9-NEXT: [[UMULH11:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDO22]]
; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE4]] ; GFX9-NEXT: [[UMULH12:%[0-9]+]]:_(s32) = G_UMULH [[UV8]], [[UADDE2]]
; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]] ; GFX9-NEXT: [[UADDO28:%[0-9]+]]:_(s32), [[UADDO29:%[0-9]+]]:_(s1) = G_UADDO [[MUL14]], [[UMULH11]]
; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1) ; GFX9-NEXT: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO29]](s1)
; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]] ; GFX9-NEXT: [[UADDO30:%[0-9]+]]:_(s32), [[UADDO31:%[0-9]+]]:_(s1) = G_UADDO [[UADDO28]], [[UMULH12]]
; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1) ; GFX9-NEXT: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO31]](s1)
; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]] ; GFX9-NEXT: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[ZEXT12]], [[ZEXT13]]
; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD13]] ; GFX9-NEXT: [[UADDO32:%[0-9]+]]:_(s32), [[UADDO33:%[0-9]+]]:_(s1) = G_UADDO [[UADDO30]], [[ADD12]]
; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1) ; GFX9-NEXT: [[ZEXT14:%[0-9]+]]:_(s32) = G_ZEXT [[UADDO33]](s1)
; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[ADD14]], [[ZEXT14]] ; GFX9-NEXT: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[ADD13]], [[ZEXT14]]
; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE4]] ; GFX9-NEXT: [[UMULH13:%[0-9]+]]:_(s32) = G_UMULH [[UV9]], [[UADDE2]]
; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD15]] ; GFX9-NEXT: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UMULH13]], [[ADD14]]
; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64) ; GFX9-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]] ; GFX9-NEXT: [[MUL15:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[UADDO32]]
; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]] ; GFX9-NEXT: [[MUL16:%[0-9]+]]:_(s32) = G_MUL [[UV11]], [[UADDO32]]
; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD16]] ; GFX9-NEXT: [[MUL17:%[0-9]+]]:_(s32) = G_MUL [[UV10]], [[ADD15]]
; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]] ; GFX9-NEXT: [[UMULH14:%[0-9]+]]:_(s32) = G_UMULH [[UV10]], [[UADDO32]]
; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]] ; GFX9-NEXT: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[MUL16]], [[MUL17]]
; GFX9-NEXT: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[ADD17]], [[UMULH14]] ; GFX9-NEXT: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[ADD16]], [[UMULH14]]
; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]] ; GFX9-NEXT: [[USUBO2:%[0-9]+]]:_(s32), [[USUBO3:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[MUL15]]
; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD18]], [[USUBO3]] ; GFX9-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[ADD17]], [[USUBO3]]
; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD18]] ; GFX9-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV7]], [[ADD17]]
; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32) ; GFX9-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO2]](s32), [[USUBE2]](s32)
; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64) ; GFX9-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]] ; GFX9-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBE2]](s32), [[UV13]]
; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1) ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]] ; GFX9-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[USUBO2]](s32), [[UV12]]
; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1) ; GFX9-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[ICMP1]](s1)
; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]] ; GFX9-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[USUBE2]](s32), [[UV13]]
; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]] ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SEXT1]], [[SEXT]]
Show All 27 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v13, vcc, v14, v13 ; CHECK-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CHECK-NEXT: v_mul_hi_u32 v10, v6, v10 ; CHECK-NEXT: v_mul_hi_u32 v10, v6, v10
; CHECK-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v11 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v11
; CHECK-NEXT: v_addc_u32_e64 v11, s[4:5], v6, v10, vcc ; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v9, v3 ; CHECK-NEXT: v_mul_lo_u32 v9, v9, v3
; CHECK-NEXT: v_mul_lo_u32 v12, v8, v11 ; CHECK-NEXT: v_mul_lo_u32 v10, v8, v6
; CHECK-NEXT: v_mul_lo_u32 v13, v8, v3 ; CHECK-NEXT: v_mul_lo_u32 v11, v8, v3
; CHECK-NEXT: v_mul_hi_u32 v8, v8, v3 ; CHECK-NEXT: v_mul_hi_u32 v8, v8, v3
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v10 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; CHECK-NEXT: v_mul_lo_u32 v9, v6, v11
; CHECK-NEXT: v_mul_lo_u32 v9, v11, v13 ; CHECK-NEXT: v_mul_lo_u32 v10, v3, v8
; CHECK-NEXT: v_mul_lo_u32 v12, v3, v8 ; CHECK-NEXT: v_mul_hi_u32 v12, v3, v11
; CHECK-NEXT: v_mul_hi_u32 v10, v3, v13 ; CHECK-NEXT: v_mul_hi_u32 v11, v6, v11
; CHECK-NEXT: v_mul_hi_u32 v13, v11, v13 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CHECK-NEXT: v_mul_lo_u32 v12, v6, v8
; CHECK-NEXT: v_mul_lo_u32 v10, v11, v8 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; CHECK-NEXT: v_mul_hi_u32 v10, v3, v8
; CHECK-NEXT: v_mul_hi_u32 v12, v3, v8 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CHECK-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CHECK-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; CHECK-NEXT: v_mul_hi_u32 v8, v6, v8
; CHECK-NEXT: v_mul_hi_u32 v8, v11, v8 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v10, v9 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e64 v10, s[4:5], v12, v10 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v9 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v9
; CHECK-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc
; CHECK-NEXT: v_mul_lo_u32 v8, v5, v3 ; CHECK-NEXT: v_mul_lo_u32 v8, v5, v3
; CHECK-NEXT: v_mul_lo_u32 v9, v4, v6 ; CHECK-NEXT: v_mul_lo_u32 v9, v4, v6
; CHECK-NEXT: v_mul_hi_u32 v10, v4, v3 ; CHECK-NEXT: v_mul_hi_u32 v10, v4, v3
; CHECK-NEXT: v_mul_hi_u32 v3, v5, v3 ; CHECK-NEXT: v_mul_hi_u32 v3, v5, v3
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; CHECK-NEXT: s_cmp_lg_u32 s3, 0 ; CHECK-NEXT: s_cmp_lg_u32 s3, 0
; CHECK-NEXT: s_mov_b32 s9, s8 ; CHECK-NEXT: s_mov_b32 s9, s8
; CHECK-NEXT: s_addc_u32 s11, s5, s8 ; CHECK-NEXT: s_addc_u32 s11, s5, s8
; CHECK-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9] ; CHECK-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9]
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s10 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s10
; CHECK-NEXT: v_cvt_f32_u32_e32 v1, s11 ; CHECK-NEXT: v_cvt_f32_u32_e32 v1, s11
; CHECK-NEXT: s_mov_b32 s7, s6 ; CHECK-NEXT: s_mov_b32 s7, s6
; CHECK-NEXT: s_xor_b64 s[12:13], s[0:1], s[6:7] ; CHECK-NEXT: s_xor_b64 s[12:13], s[0:1], s[6:7]
; CHECK-NEXT: s_sub_u32 s3, 0, s10 ; CHECK-NEXT: s_sub_u32 s0, 0, s10
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: s_cselect_b32 s0, 1, 0 ; CHECK-NEXT: s_cselect_b32 s1, 1, 0
; CHECK-NEXT: s_and_b32 s0, s0, 1 ; CHECK-NEXT: s_and_b32 s1, s1, 1
; CHECK-NEXT: s_cmp_lg_u32 s0, 0 ; CHECK-NEXT: s_cmp_lg_u32 s1, 0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; CHECK-NEXT: v_trunc_f32_e32 v1, v1 ; CHECK-NEXT: v_trunc_f32_e32 v1, v1
; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1 ; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: s_subb_u32 s5, 0, s11 ; CHECK-NEXT: s_subb_u32 s1, 0, s11
; CHECK-NEXT: v_mul_lo_u32 v3, s0, v1
; CHECK-NEXT: v_mul_lo_u32 v2, s1, v0
; CHECK-NEXT: v_mul_hi_u32 v5, s0, v0
; CHECK-NEXT: v_mul_lo_u32 v4, s0, v0
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_mul_lo_u32 v3, v1, v4
; CHECK-NEXT: v_mul_lo_u32 v5, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v6, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v6, v1, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; CHECK-NEXT: v_mul_hi_u32 v5, v0, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CHECK-NEXT: v_mul_lo_u32 v2, s1, v0
; CHECK-NEXT: v_mul_lo_u32 v3, s0, v1
; CHECK-NEXT: v_mul_hi_u32 v5, s0, v0
; CHECK-NEXT: v_mul_lo_u32 v4, s0, v0
; CHECK-NEXT: v_mov_b32_e32 v6, s11 ; CHECK-NEXT: v_mov_b32_e32 v6, s11
; CHECK-NEXT: v_mul_lo_u32 v3, s3, v1
; CHECK-NEXT: v_mul_lo_u32 v2, s5, v0
; CHECK-NEXT: v_mul_hi_u32 v5, s3, v0
; CHECK-NEXT: v_mul_lo_u32 v4, s3, v0
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_mul_lo_u32 v3, v1, v4 ; CHECK-NEXT: v_mul_lo_u32 v3, v1, v4
; CHECK-NEXT: v_mul_lo_u32 v5, v0, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v7, v0, v4 ; CHECK-NEXT: v_mul_hi_u32 v7, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v7 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, v1, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, v1, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; CHECK-NEXT: v_mul_hi_u32 v5, v0, v2 ; CHECK-NEXT: v_mul_hi_u32 v5, v0, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_addc_u32_e64 v3, s[0:1], v1, v2, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CHECK-NEXT: v_mul_lo_u32 v4, s5, v0
; CHECK-NEXT: v_mul_lo_u32 v5, s3, v3
; CHECK-NEXT: v_mul_hi_u32 v8, s3, v0
; CHECK-NEXT: v_mul_lo_u32 v7, s3, v0
; CHECK-NEXT: v_add_i32_e64 v1, s[0:1], v1, v2
; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v4, v5
; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v4, v8
; CHECK-NEXT: v_mul_lo_u32 v5, v3, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v2, v0, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v3, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v5, v2
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; CHECK-NEXT: v_mul_lo_u32 v5, v3, v4
; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v8, v2
; CHECK-NEXT: v_mul_hi_u32 v8, v0, v4
; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v7
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; CHECK-NEXT: v_add_i32_e64 v7, s[0:1], v7, v8
; CHECK-NEXT: v_mul_hi_u32 v3, v3, v4
; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v5, v2
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v7, v5
; CHECK-NEXT: v_add_i32_e64 v3, s[0:1], v3, v4
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_mul_lo_u32 v2, s13, v0 ; CHECK-NEXT: v_mul_lo_u32 v2, s13, v0
; CHECK-NEXT: v_mul_lo_u32 v3, s12, v1 ; CHECK-NEXT: v_mul_lo_u32 v3, s12, v1
; CHECK-NEXT: v_mul_hi_u32 v5, s12, v0 ; CHECK-NEXT: v_mul_hi_u32 v5, s12, v0
; CHECK-NEXT: v_mul_hi_u32 v0, s13, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, s13, v0
; CHECK-NEXT: v_mov_b32_e32 v4, s13 ; CHECK-NEXT: v_mov_b32_e32 v4, s13
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v18, v17 ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v18, v17
; GISEL-NEXT: v_mul_hi_u32 v14, v10, v14 ; GISEL-NEXT: v_mul_hi_u32 v14, v10, v14
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v16, v15 ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16 ; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v15 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v15
; GISEL-NEXT: v_addc_u32_e64 v15, s[4:5], v10, v14, vcc ; GISEL-NEXT: v_addc_u32_e32 v10, vcc, v10, v14, vcc
; GISEL-NEXT: v_mul_lo_u32 v13, v13, v9 ; GISEL-NEXT: v_mul_lo_u32 v13, v13, v9
; GISEL-NEXT: v_mul_lo_u32 v16, v12, v15 ; GISEL-NEXT: v_mul_lo_u32 v14, v12, v10
; GISEL-NEXT: v_mul_lo_u32 v17, v12, v9 ; GISEL-NEXT: v_mul_lo_u32 v15, v12, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v12, v9 ; GISEL-NEXT: v_mul_hi_u32 v12, v12, v9
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v16 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; GISEL-NEXT: v_mul_lo_u32 v13, v10, v15
; GISEL-NEXT: v_mul_lo_u32 v13, v15, v17 ; GISEL-NEXT: v_mul_lo_u32 v14, v9, v12
; GISEL-NEXT: v_mul_lo_u32 v16, v9, v12 ; GISEL-NEXT: v_mul_hi_u32 v16, v9, v15
; GISEL-NEXT: v_mul_hi_u32 v14, v9, v17 ; GISEL-NEXT: v_mul_hi_u32 v15, v10, v15
; GISEL-NEXT: v_mul_hi_u32 v17, v15, v17 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v16 ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v16
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14 ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v16, v10, v12
; GISEL-NEXT: v_mul_lo_u32 v14, v15, v12 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v16, v13 ; GISEL-NEXT: v_mul_hi_u32 v14, v9, v12
; GISEL-NEXT: v_mul_hi_u32 v16, v9, v12 ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v17 ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v16 ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; GISEL-NEXT: v_add_i32_e64 v16, s[4:5], v17, v16 ; GISEL-NEXT: v_mul_hi_u32 v12, v10, v12
; GISEL-NEXT: v_mul_hi_u32 v12, v15, v12 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v16, v14 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, v10, v12, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v13 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v13
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc ; GISEL-NEXT: v_addc_u32_e32 v10, vcc, v10, v12, vcc
; GISEL-NEXT: v_mul_lo_u32 v12, v1, v9 ; GISEL-NEXT: v_mul_lo_u32 v12, v1, v9
; GISEL-NEXT: v_mul_lo_u32 v13, v0, v10 ; GISEL-NEXT: v_mul_lo_u32 v13, v0, v10
; GISEL-NEXT: v_mul_hi_u32 v14, v0, v9 ; GISEL-NEXT: v_mul_hi_u32 v14, v0, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v1, v9 ; GISEL-NEXT: v_mul_hi_u32 v9, v1, v9
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16 ; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13 ; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v16, v15 ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v14 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v14
; GISEL-NEXT: v_addc_u32_e64 v14, s[4:5], v9, v13, vcc ; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v13, vcc
; GISEL-NEXT: v_mul_lo_u32 v12, v12, v8 ; GISEL-NEXT: v_mul_lo_u32 v12, v12, v8
; GISEL-NEXT: v_mul_lo_u32 v15, v11, v14 ; GISEL-NEXT: v_mul_lo_u32 v13, v11, v9
; GISEL-NEXT: v_mul_lo_u32 v16, v11, v8 ; GISEL-NEXT: v_mul_lo_u32 v14, v11, v8
; GISEL-NEXT: v_mul_hi_u32 v11, v11, v8 ; GISEL-NEXT: v_mul_hi_u32 v11, v11, v8
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v14, v16
; GISEL-NEXT: v_mul_lo_u32 v15, v8, v11
; GISEL-NEXT: v_mul_hi_u32 v13, v8, v16
; GISEL-NEXT: v_mul_hi_u32 v16, v14, v16
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v10 ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v10
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; GISEL-NEXT: v_mul_lo_u32 v12, v9, v14
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v13, v8, v11
; GISEL-NEXT: v_mul_lo_u32 v13, v14, v11 ; GISEL-NEXT: v_mul_hi_u32 v15, v8, v14
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v15, v12 ; GISEL-NEXT: v_mul_hi_u32 v14, v9, v14
; GISEL-NEXT: v_mul_hi_u32 v15, v8, v11
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v16
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v16, v15
; GISEL-NEXT: v_mul_hi_u32 v11, v14, v11
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v15, v13
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v11, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v5 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v5
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v15, v9, v11
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_mul_hi_u32 v13, v8, v11
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_mul_hi_u32 v11, v9, v11
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v11, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, v3, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v3, v8
; GISEL-NEXT: v_mul_lo_u32 v12, v2, v9 ; GISEL-NEXT: v_mul_lo_u32 v12, v2, v9
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc ; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
; GISEL-NEXT: v_mul_hi_u32 v5, v2, v8 ; GISEL-NEXT: v_mul_hi_u32 v5, v2, v8
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v11, v5 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v11, v5
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v17, vcc, v18, v17 ; CGP-NEXT: v_add_i32_e32 v17, vcc, v18, v17
; CGP-NEXT: v_mul_hi_u32 v14, v11, v14 ; CGP-NEXT: v_mul_hi_u32 v14, v11, v14
; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16 ; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v16 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v16
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v15 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v15
; CGP-NEXT: v_addc_u32_e64 v15, s[4:5], v11, v14, vcc ; CGP-NEXT: v_addc_u32_e32 v11, vcc, v11, v14, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v13, v3 ; CGP-NEXT: v_mul_lo_u32 v13, v13, v3
; CGP-NEXT: v_mul_lo_u32 v16, v12, v15 ; CGP-NEXT: v_mul_lo_u32 v14, v12, v11
; CGP-NEXT: v_mul_lo_u32 v17, v12, v3 ; CGP-NEXT: v_mul_lo_u32 v15, v12, v3
; CGP-NEXT: v_mul_hi_u32 v12, v12, v3 ; CGP-NEXT: v_mul_hi_u32 v12, v12, v3
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v16 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; CGP-NEXT: v_mul_lo_u32 v13, v11, v15
; CGP-NEXT: v_mul_lo_u32 v13, v15, v17 ; CGP-NEXT: v_mul_lo_u32 v14, v3, v12
; CGP-NEXT: v_mul_lo_u32 v16, v3, v12 ; CGP-NEXT: v_mul_hi_u32 v16, v3, v15
; CGP-NEXT: v_mul_hi_u32 v14, v3, v17 ; CGP-NEXT: v_mul_hi_u32 v15, v11, v15
; CGP-NEXT: v_mul_hi_u32 v17, v15, v17 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v16 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v16
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14 ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_mul_lo_u32 v16, v11, v12
; CGP-NEXT: v_mul_lo_u32 v14, v15, v12 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v16, v13 ; CGP-NEXT: v_mul_hi_u32 v14, v3, v12
; CGP-NEXT: v_mul_hi_u32 v16, v3, v12 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v17 ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v16 ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; CGP-NEXT: v_add_i32_e64 v16, s[4:5], v17, v16 ; CGP-NEXT: v_mul_hi_u32 v12, v11, v12
; CGP-NEXT: v_mul_hi_u32 v12, v15, v12 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v16, v14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_addc_u32_e32 v11, vcc, v11, v12, vcc
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v13 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v13
; CGP-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc ; CGP-NEXT: v_addc_u32_e32 v11, vcc, v11, v12, vcc
; CGP-NEXT: v_mul_lo_u32 v12, v10, v3 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v3
; CGP-NEXT: v_mul_lo_u32 v13, v4, v11 ; CGP-NEXT: v_mul_lo_u32 v13, v4, v11
; CGP-NEXT: v_mul_hi_u32 v14, v4, v3 ; CGP-NEXT: v_mul_hi_u32 v14, v4, v3
; CGP-NEXT: v_mul_hi_u32 v3, v10, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v10, v3
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; CGP-NEXT: v_mul_hi_u32 v12, v9, v12 ; CGP-NEXT: v_mul_hi_u32 v12, v9, v12
; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v13 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v13
; CGP-NEXT: v_addc_u32_e64 v13, s[4:5], v9, v12, vcc ; CGP-NEXT: v_addc_u32_e32 v9, vcc, v9, v12, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v11, v5 ; CGP-NEXT: v_mul_lo_u32 v11, v11, v5
; CGP-NEXT: v_mul_lo_u32 v14, v10, v13 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v9
; CGP-NEXT: v_mul_lo_u32 v15, v10, v5 ; CGP-NEXT: v_mul_lo_u32 v13, v10, v5
; CGP-NEXT: v_mul_hi_u32 v10, v10, v5 ; CGP-NEXT: v_mul_hi_u32 v10, v10, v5
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; CGP-NEXT: v_mul_lo_u32 v11, v9, v13
; CGP-NEXT: v_mul_lo_u32 v11, v13, v15 ; CGP-NEXT: v_mul_lo_u32 v12, v5, v10
; CGP-NEXT: v_mul_lo_u32 v14, v5, v10 ; CGP-NEXT: v_mul_hi_u32 v14, v5, v13
; CGP-NEXT: v_mul_hi_u32 v12, v5, v15 ; CGP-NEXT: v_mul_hi_u32 v13, v9, v13
; CGP-NEXT: v_mul_hi_u32 v15, v13, v15 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CGP-NEXT: v_mul_lo_u32 v14, v9, v10
; CGP-NEXT: v_mul_lo_u32 v12, v13, v10 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v14, v11 ; CGP-NEXT: v_mul_hi_u32 v12, v5, v10
; CGP-NEXT: v_mul_hi_u32 v14, v5, v10 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v15, v14 ; CGP-NEXT: v_mul_hi_u32 v10, v9, v10
; CGP-NEXT: v_mul_hi_u32 v10, v13, v10 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12
; CGP-NEXT: v_addc_u32_e32 v9, vcc, v9, v10, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v11 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v11
; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc ; CGP-NEXT: v_addc_u32_e32 v9, vcc, v9, v10, vcc
; CGP-NEXT: v_mul_lo_u32 v10, v8, v5 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v5
; CGP-NEXT: v_mul_lo_u32 v11, v6, v9 ; CGP-NEXT: v_mul_lo_u32 v11, v6, v9
; CGP-NEXT: v_mul_hi_u32 v12, v6, v5 ; CGP-NEXT: v_mul_hi_u32 v12, v6, v5
; CGP-NEXT: v_mul_hi_u32 v5, v8, v5 ; CGP-NEXT: v_mul_hi_u32 v5, v8, v5
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines; CGP-NEXT: s_setpc_b64 s[30:31]
%result = sdiv <2 x i64> %num, %den %result = sdiv <2 x i64> %num, %den
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_sdiv_i64_pow2k_denom(i64 %num) { define i64 @v_sdiv_i64_pow2k_denom(i64 %num) {
; CHECK-LABEL: v_sdiv_i64_pow2k_denom: ; CHECK-LABEL: v_sdiv_i64_pow2k_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, 0x1000 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x1000
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
; CHECK-NEXT: s_movk_i32 s6, 0xf000 ; CHECK-NEXT: s_movk_i32 s4, 0xf000
; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; CHECK-NEXT: s_movk_i32 s6, 0x1000
; CHECK-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 ; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v4, v4 ; CHECK-NEXT: v_trunc_f32_e32 v4, v4
; CHECK-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v2 ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v3 ; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4 ; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v8, s6, v3 ; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s6, v3 ; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000 ; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7 ; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v3, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v3, v7 ; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7 ; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5 ; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_mul_hi_u32 v8, v3, v5 ; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5 ; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e64 v6, s[4:5], v4, v5, vcc ; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, -1, v3 ; CHECK-NEXT: v_mul_lo_u32 v5, v1, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s6, v6
; CHECK-NEXT: v_mul_hi_u32 v10, s6, v3
; CHECK-NEXT: v_mul_lo_u32 v9, s6, v3
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v5
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v10
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v9
; CHECK-NEXT: v_mul_lo_u32 v10, v3, v7
; CHECK-NEXT: v_mul_hi_u32 v5, v3, v9
; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9
; CHECK-NEXT: s_movk_i32 s6, 0x1000
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
; CHECK-NEXT: v_mul_hi_u32 v10, v3, v7
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; CHECK-NEXT: v_mul_hi_u32 v6, v6, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v9, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, v1, v3
; CHECK-NEXT: v_mul_lo_u32 v6, v0, v4 ; CHECK-NEXT: v_mul_lo_u32 v6, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v7, v0, v3 ; CHECK-NEXT: v_mul_hi_u32 v7, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v3, v1, v3 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, v1, v4 ; CHECK-NEXT: v_mul_lo_u32 v7, v1, v4
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; CHECK-NEXT: v_mul_hi_u32 v6, v0, v4 ; CHECK-NEXT: v_mul_hi_u32 v6, v0, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v7, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CHECK-NEXT: v_mul_lo_u32 v5, 0, v3 ; CHECK-NEXT: v_mul_lo_u32 v5, 0, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4 ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s6, v3 ; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s6, v3 ; CHECK-NEXT: v_mul_lo_u32 v7, s6, v2
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
; CHECK-NEXT: v_subb_u32_e64 v6, s[4:5], v1, v5, vcc ; CHECK-NEXT: v_subb_u32_e64 v6, s[4:5], v1, v5, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v5 ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v5
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0 ; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CHECK-NEXT: v_mov_b32_e32 v7, s7 ; CHECK-NEXT: v_mov_b32_e32 v7, s7
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v3 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; CHECK-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5]
; CHECK-NEXT: v_addc_u32_e32 v7, vcc, 0, v4, vcc ; CHECK-NEXT: v_addc_u32_e32 v7, vcc, 0, v4, vcc
; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 ; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; CHECK-NEXT: v_mov_b32_e32 v8, s4 ; CHECK-NEXT: v_mov_b32_e32 v8, s4
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v6 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v6
; CHECK-NEXT: v_addc_u32_e32 v8, vcc, 0, v7, vcc ; CHECK-NEXT: v_addc_u32_e32 v8, vcc, 0, v7, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v2 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %num, 4096 %result = sdiv i64 %num, 4096
ret i64 %result ret i64 %result
} }
define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) { define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) {
; GISEL-LABEL: v_sdiv_v2i64_pow2k_denom: ; GISEL-LABEL: v_sdiv_v2i64_pow2k_denom:
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_movk_i32 s10, 0x1000 ; GISEL-NEXT: s_movk_i32 s10, 0x1000
; GISEL-NEXT: s_add_u32 s4, s10, 0 ; GISEL-NEXT: s_add_u32 s4, s10, 0
; GISEL-NEXT: s_cselect_b32 s5, 1, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-NEXT: s_and_b32 s5, s5, 1 ; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: s_mov_b32 s6, 0 ; GISEL-NEXT: s_mov_b32 s6, 0
; GISEL-NEXT: s_cmp_lg_u32 s5, 0 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: s_mov_b32 s7, s6 ; GISEL-NEXT: s_mov_b32 s7, s6
; GISEL-NEXT: s_addc_u32 s5, 0, 0 ; GISEL-NEXT: s_addc_u32 s5, 0, 0
; GISEL-NEXT: s_xor_b64 s[8:9], s[4:5], s[6:7] ; GISEL-NEXT: s_xor_b64 s[8:9], s[4:5], s[6:7]
; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s8 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s8
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s9 ; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s9
; GISEL-NEXT: s_sub_u32 s11, 0, s8 ; GISEL-NEXT: s_sub_u32 s4, 0, s8
; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: s_subb_u32 s12, 0, s9 ; GISEL-NEXT: s_subb_u32 s5, 0, s9
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v1 ; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; GISEL-NEXT: v_trunc_f32_e32 v6, v6 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6
; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_mul_lo_u32 v7, s12, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v8, s11, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v10, s11, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_mul_lo_u32 v9, s11, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7 ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
Show All 10 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v6, v7, vcc ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, s12, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v10, s11, v8 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v12, s11, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_mul_lo_u32 v11, s11, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v7, v5, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v12, v7 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v5, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v11, v6, v7
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v10, v5, v7
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v1, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, v1, v5
; GISEL-NEXT: v_mul_lo_u32 v8, v0, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, v0, v6
; GISEL-NEXT: v_mul_hi_u32 v10, v0, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5
; GISEL-NEXT: v_mov_b32_e32 v9, s9 ; GISEL-NEXT: v_mov_b32_e32 v9, s9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7] ; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s6 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s6
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s7 ; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s7
; GISEL-NEXT: s_sub_u32 s8, 0, s6 ; GISEL-NEXT: s_sub_u32 s4, 0, s6
; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: s_subb_u32 s9, 0, s7 ; GISEL-NEXT: s_subb_u32 s5, 0, s7
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; GISEL-NEXT: v_trunc_f32_e32 v6, v6 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6
; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_mul_lo_u32 v7, s9, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v8, s8, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v10, s8, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GISEL-NEXT: v_mul_lo_u32 v9, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7 ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
Show All 11 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v6, v7, vcc ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, s9, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v10, s8, v8 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v12, s8, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_mul_lo_u32 v11, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v7, v5, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v4 ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v4
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v12, v7 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v5, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v11, v6, v7
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v10, v5, v7
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v3, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, v3, v5
; GISEL-NEXT: v_mul_lo_u32 v8, v2, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, v2, v6
; GISEL-NEXT: v_mul_hi_u32 v10, v2, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, v2, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5
; GISEL-NEXT: v_mov_b32_e32 v9, s7 ; GISEL-NEXT: v_mov_b32_e32 v9, s7
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_sdiv_v2i64_pow2k_denom: ; CGP-LABEL: v_sdiv_v2i64_pow2k_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x1000 ; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x1000
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0 ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
; CGP-NEXT: s_movk_i32 s6, 0xf000 ; CGP-NEXT: s_movk_i32 s6, 0xf000
; CGP-NEXT: s_movk_i32 s7, 0x1000
; CGP-NEXT: v_mov_b32_e32 v4, v5
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v4
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1 ; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; CGP-NEXT: v_mov_b32_e32 v7, v5
; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7 ; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7 ; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7
; CGP-NEXT: v_trunc_f32_e32 v8, v8 ; CGP-NEXT: v_trunc_f32_e32 v8, v8
; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8 ; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 ; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v7
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: v_xor_b32_e32 v0, v0, v4 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_xor_b32_e32 v1, v1, v4 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_mul_hi_u32 v12, v7, v9
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, -1, v7
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7 ; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: s_movk_i32 s7, 0x1000 ; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000 ; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v8, v9 ; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_mul_hi_u32 v12, v7, v9 ; CGP-NEXT: v_mul_hi_u32 v12, v7, v9
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_mul_hi_u32 v9, v8, v9 ; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v8, v9, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v11, -1, v7
; CGP-NEXT: v_mul_lo_u32 v12, s6, v10
; CGP-NEXT: v_mul_hi_u32 v14, s6, v7
; CGP-NEXT: v_mul_lo_u32 v13, s6, v7
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
; CGP-NEXT: v_mul_lo_u32 v12, v10, v13
; CGP-NEXT: v_mul_lo_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v9, v7, v13
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; CGP-NEXT: v_mul_lo_u32 v12, v10, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v14, v9
; CGP-NEXT: v_mul_hi_u32 v14, v7, v11
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; CGP-NEXT: v_mul_hi_u32 v10, v10, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v12
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v9, v1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, v1, v7
; CGP-NEXT: v_mul_lo_u32 v10, v0, v8 ; CGP-NEXT: v_mul_lo_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v11, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v11, v0, v7
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_mul_hi_u32 v8, v7, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v7, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v10, -1, v5 ; CGP-NEXT: v_mul_lo_u32 v8, -1, v5
; CGP-NEXT: v_mul_lo_u32 v11, s6, v9 ; CGP-NEXT: v_mul_lo_u32 v9, s6, v7
; CGP-NEXT: v_mul_hi_u32 v13, s6, v5 ; CGP-NEXT: v_mul_hi_u32 v11, s6, v5
; CGP-NEXT: v_mul_lo_u32 v12, s6, v5 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v5
; CGP-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
; CGP-NEXT: v_mul_lo_u32 v11, v9, v12
; CGP-NEXT: v_mul_lo_u32 v13, v5, v10
; CGP-NEXT: v_mul_hi_u32 v8, v5, v12
; CGP-NEXT: v_mul_hi_u32 v12, v9, v12
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8 ; CGP-NEXT: v_mul_lo_u32 v9, v7, v10
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CGP-NEXT: v_mul_lo_u32 v11, v5, v8
; CGP-NEXT: v_mul_lo_u32 v11, v9, v10 ; CGP-NEXT: v_mul_hi_u32 v12, v5, v10
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v13, v8 ; CGP-NEXT: v_mul_hi_u32 v10, v7, v10
; CGP-NEXT: v_mul_hi_u32 v13, v5, v10
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; CGP-NEXT: v_mul_hi_u32 v9, v9, v10
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v12, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CGP-NEXT: v_xor_b32_e32 v3, v3, v6 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v6
; CGP-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v12, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; CGP-NEXT: v_mul_hi_u32 v11, v5, v8
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_mul_hi_u32 v8, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
; CGP-NEXT: v_xor_b32_e32 v1, v1, v4 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
; CGP-NEXT: v_mul_lo_u32 v8, v3, v5 ; CGP-NEXT: v_mul_lo_u32 v8, v3, v5
; CGP-NEXT: v_mul_lo_u32 v9, v2, v7 ; CGP-NEXT: v_mul_lo_u32 v9, v2, v7
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_hi_u32 v4, v2, v5 ; CGP-NEXT: v_mul_hi_u32 v4, v2, v5
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines; CGP-NEXT: s_setpc_b64 s[30:31]
%result = sdiv <2 x i64> %num, <i64 4096, i64 4096> %result = sdiv <2 x i64> %num, <i64 4096, i64 4096>
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_sdiv_i64_oddk_denom(i64 %num) { define i64 @v_sdiv_i64_oddk_denom(i64 %num) {
; CHECK-LABEL: v_sdiv_i64_oddk_denom: ; CHECK-LABEL: v_sdiv_i64_oddk_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, 0x12d8fb ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x12d8fb
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
; CHECK-NEXT: s_mov_b32 s6, 0xffed2705 ; CHECK-NEXT: s_mov_b32 s4, 0xffed2705
; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb
; CHECK-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 ; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v4, v4 ; CHECK-NEXT: v_trunc_f32_e32 v4, v4
; CHECK-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v2 ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v3 ; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4 ; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v8, s6, v3 ; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s6, v3 ; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000 ; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7 ; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v3, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v3, v7 ; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7 ; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5 ; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_mul_hi_u32 v8, v3, v5 ; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5 ; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e64 v6, s[4:5], v4, v5, vcc ; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, -1, v3 ; CHECK-NEXT: v_mul_lo_u32 v5, v1, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s6, v6
; CHECK-NEXT: v_mul_hi_u32 v10, s6, v3
; CHECK-NEXT: v_mul_lo_u32 v9, s6, v3
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v5
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v10
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v9
; CHECK-NEXT: v_mul_lo_u32 v10, v3, v7
; CHECK-NEXT: v_mul_hi_u32 v5, v3, v9
; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9
; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
; CHECK-NEXT: v_mul_hi_u32 v10, v3, v7
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; CHECK-NEXT: v_mul_hi_u32 v6, v6, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v9, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, v1, v3
; CHECK-NEXT: v_mul_lo_u32 v6, v0, v4 ; CHECK-NEXT: v_mul_lo_u32 v6, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v7, v0, v3 ; CHECK-NEXT: v_mul_hi_u32 v7, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v3, v1, v3 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, v1, v4 ; CHECK-NEXT: v_mul_lo_u32 v7, v1, v4
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; CHECK-NEXT: v_mul_hi_u32 v6, v0, v4 ; CHECK-NEXT: v_mul_hi_u32 v6, v0, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v7, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CHECK-NEXT: v_mul_lo_u32 v5, 0, v3 ; CHECK-NEXT: v_mul_lo_u32 v5, 0, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4 ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s6, v3 ; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s6, v3 ; CHECK-NEXT: v_mul_lo_u32 v7, s6, v2
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
; CHECK-NEXT: v_subb_u32_e64 v6, s[4:5], v1, v5, vcc ; CHECK-NEXT: v_subb_u32_e64 v6, s[4:5], v1, v5, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v5 ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v5
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0 ; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CHECK-NEXT: v_mov_b32_e32 v7, s7 ; CHECK-NEXT: v_mov_b32_e32 v7, s7
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v3 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; CHECK-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[4:5]
; CHECK-NEXT: v_addc_u32_e32 v7, vcc, 0, v4, vcc ; CHECK-NEXT: v_addc_u32_e32 v7, vcc, 0, v4, vcc
; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 ; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; CHECK-NEXT: v_mov_b32_e32 v8, s4 ; CHECK-NEXT: v_mov_b32_e32 v8, s4
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v6 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, 1, v6
; CHECK-NEXT: v_addc_u32_e32 v8, vcc, 0, v7, vcc ; CHECK-NEXT: v_addc_u32_e32 v8, vcc, 0, v7, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v2 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %num, 1235195 %result = sdiv i64 %num, 1235195
ret i64 %result ret i64 %result
} }
define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) { define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-LABEL: v_sdiv_v2i64_oddk_denom: ; GISEL-LABEL: v_sdiv_v2i64_oddk_denom:
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_mov_b32 s10, 0x12d8fb ; GISEL-NEXT: s_mov_b32 s10, 0x12d8fb
; GISEL-NEXT: s_add_u32 s4, s10, 0 ; GISEL-NEXT: s_add_u32 s4, s10, 0
; GISEL-NEXT: s_cselect_b32 s5, 1, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-NEXT: s_and_b32 s5, s5, 1 ; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: s_mov_b32 s6, 0 ; GISEL-NEXT: s_mov_b32 s6, 0
; GISEL-NEXT: s_cmp_lg_u32 s5, 0 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: s_mov_b32 s7, s6 ; GISEL-NEXT: s_mov_b32 s7, s6
; GISEL-NEXT: s_addc_u32 s5, 0, 0 ; GISEL-NEXT: s_addc_u32 s5, 0, 0
; GISEL-NEXT: s_xor_b64 s[8:9], s[4:5], s[6:7] ; GISEL-NEXT: s_xor_b64 s[8:9], s[4:5], s[6:7]
; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s8 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s8
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s9 ; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s9
; GISEL-NEXT: s_sub_u32 s11, 0, s8 ; GISEL-NEXT: s_sub_u32 s4, 0, s8
; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: s_subb_u32 s12, 0, s9 ; GISEL-NEXT: s_subb_u32 s5, 0, s9
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v1 ; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; GISEL-NEXT: v_trunc_f32_e32 v6, v6 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6
; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_mul_lo_u32 v7, s12, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v8, s11, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v10, s11, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_mul_lo_u32 v9, s11, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7 ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
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; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v6, v7, vcc ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, s12, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v10, s11, v8 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v12, s11, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_mul_lo_u32 v11, s11, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v7, v5, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v12, v7 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v5, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v11, v6, v7
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v10, v5, v7
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v1, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, v1, v5
; GISEL-NEXT: v_mul_lo_u32 v8, v0, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, v0, v6
; GISEL-NEXT: v_mul_hi_u32 v10, v0, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5
; GISEL-NEXT: v_mov_b32_e32 v9, s9 ; GISEL-NEXT: v_mov_b32_e32 v9, s9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7] ; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7]
; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s6 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s6
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s7 ; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s7
; GISEL-NEXT: s_sub_u32 s8, 0, s6 ; GISEL-NEXT: s_sub_u32 s4, 0, s6
; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: s_subb_u32 s9, 0, s7 ; GISEL-NEXT: s_subb_u32 s5, 0, s7
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; GISEL-NEXT: v_trunc_f32_e32 v6, v6 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6
; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_mul_lo_u32 v7, s9, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v8, s8, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v10, s8, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GISEL-NEXT: v_mul_lo_u32 v9, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7 ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
Show All 11 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v6, v7, vcc ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, s9, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v10, s8, v8 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v12, s8, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_mul_lo_u32 v11, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v7, v5, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v4 ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v4
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v12, v7 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v5, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v11, v6, v7
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v10, v5, v7
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v3, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, v3, v5
; GISEL-NEXT: v_mul_lo_u32 v8, v2, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, v2, v6
; GISEL-NEXT: v_mul_hi_u32 v10, v2, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, v2, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5
; GISEL-NEXT: v_mov_b32_e32 v9, s7 ; GISEL-NEXT: v_mov_b32_e32 v9, s7
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_sdiv_v2i64_oddk_denom: ; CGP-LABEL: v_sdiv_v2i64_oddk_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x12d8fb ; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x12d8fb
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0 ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
; CGP-NEXT: s_mov_b32 s6, 0xffed2705 ; CGP-NEXT: s_mov_b32 s6, 0xffed2705
; CGP-NEXT: s_mov_b32 s7, 0x12d8fb
; CGP-NEXT: v_mov_b32_e32 v4, v5
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v4
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1 ; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; CGP-NEXT: v_mov_b32_e32 v7, v5
; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7 ; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7 ; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7
; CGP-NEXT: v_trunc_f32_e32 v8, v8 ; CGP-NEXT: v_trunc_f32_e32 v8, v8
; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8 ; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 ; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v7
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: v_xor_b32_e32 v0, v0, v4 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_xor_b32_e32 v1, v1, v4 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_mul_hi_u32 v12, v7, v9
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, -1, v7
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7 ; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: s_mov_b32 s7, 0x12d8fb ; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000 ; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v8, v9 ; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_mul_hi_u32 v12, v7, v9 ; CGP-NEXT: v_mul_hi_u32 v12, v7, v9
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_mul_hi_u32 v9, v8, v9 ; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v8, v9, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v11, -1, v7
; CGP-NEXT: v_mul_lo_u32 v12, s6, v10
; CGP-NEXT: v_mul_hi_u32 v14, s6, v7
; CGP-NEXT: v_mul_lo_u32 v13, s6, v7
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
; CGP-NEXT: v_mul_lo_u32 v12, v10, v13
; CGP-NEXT: v_mul_lo_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v9, v7, v13
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; CGP-NEXT: v_mul_lo_u32 v12, v10, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v14, v9
; CGP-NEXT: v_mul_hi_u32 v14, v7, v11
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; CGP-NEXT: v_mul_hi_u32 v10, v10, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v12
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v9, v1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, v1, v7
; CGP-NEXT: v_mul_lo_u32 v10, v0, v8 ; CGP-NEXT: v_mul_lo_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v11, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v11, v0, v7
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_mul_hi_u32 v8, v7, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v7, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v10, -1, v5 ; CGP-NEXT: v_mul_lo_u32 v8, -1, v5
; CGP-NEXT: v_mul_lo_u32 v11, s6, v9 ; CGP-NEXT: v_mul_lo_u32 v9, s6, v7
; CGP-NEXT: v_mul_hi_u32 v13, s6, v5 ; CGP-NEXT: v_mul_hi_u32 v11, s6, v5
; CGP-NEXT: v_mul_lo_u32 v12, s6, v5 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v5
; CGP-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
; CGP-NEXT: v_mul_lo_u32 v11, v9, v12
; CGP-NEXT: v_mul_lo_u32 v13, v5, v10
; CGP-NEXT: v_mul_hi_u32 v8, v5, v12
; CGP-NEXT: v_mul_hi_u32 v12, v9, v12
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8 ; CGP-NEXT: v_mul_lo_u32 v9, v7, v10
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CGP-NEXT: v_mul_lo_u32 v11, v5, v8
; CGP-NEXT: v_mul_lo_u32 v11, v9, v10 ; CGP-NEXT: v_mul_hi_u32 v12, v5, v10
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v13, v8 ; CGP-NEXT: v_mul_hi_u32 v10, v7, v10
; CGP-NEXT: v_mul_hi_u32 v13, v5, v10
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; CGP-NEXT: v_mul_hi_u32 v9, v9, v10
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v12, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CGP-NEXT: v_xor_b32_e32 v3, v3, v6 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v6
; CGP-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v12, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; CGP-NEXT: v_mul_hi_u32 v11, v5, v8
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_mul_hi_u32 v8, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
; CGP-NEXT: v_xor_b32_e32 v1, v1, v4 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
; CGP-NEXT: v_mul_lo_u32 v8, v3, v5 ; CGP-NEXT: v_mul_lo_u32 v8, v3, v5
; CGP-NEXT: v_mul_lo_u32 v9, v2, v7 ; CGP-NEXT: v_mul_lo_u32 v9, v2, v7
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_hi_u32 v4, v2, v5 ; CGP-NEXT: v_mul_hi_u32 v4, v2, v5
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v13, vcc, v14, v13 ; CHECK-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CHECK-NEXT: v_mul_hi_u32 v10, v6, v10 ; CHECK-NEXT: v_mul_hi_u32 v10, v6, v10
; CHECK-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v11 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v11
; CHECK-NEXT: v_addc_u32_e64 v11, s[4:5], v6, v10, vcc ; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v9, v5 ; CHECK-NEXT: v_mul_lo_u32 v9, v9, v5
; CHECK-NEXT: v_mul_lo_u32 v12, v8, v11 ; CHECK-NEXT: v_mul_lo_u32 v10, v8, v6
; CHECK-NEXT: v_mul_lo_u32 v13, v8, v5 ; CHECK-NEXT: v_mul_lo_u32 v11, v8, v5
; CHECK-NEXT: v_mul_hi_u32 v8, v8, v5 ; CHECK-NEXT: v_mul_hi_u32 v8, v8, v5
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v10 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; CHECK-NEXT: v_mul_lo_u32 v9, v6, v11
; CHECK-NEXT: v_mul_lo_u32 v9, v11, v13 ; CHECK-NEXT: v_mul_lo_u32 v10, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v12, v5, v8 ; CHECK-NEXT: v_mul_hi_u32 v12, v5, v11
; CHECK-NEXT: v_mul_hi_u32 v10, v5, v13 ; CHECK-NEXT: v_mul_hi_u32 v11, v6, v11
; CHECK-NEXT: v_mul_hi_u32 v13, v11, v13 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CHECK-NEXT: v_mul_lo_u32 v12, v6, v8
; CHECK-NEXT: v_mul_lo_u32 v10, v11, v8 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; CHECK-NEXT: v_mul_hi_u32 v10, v5, v8
; CHECK-NEXT: v_mul_hi_u32 v12, v5, v8 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CHECK-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CHECK-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; CHECK-NEXT: v_mul_hi_u32 v8, v6, v8
; CHECK-NEXT: v_mul_hi_u32 v8, v11, v8 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v10, v9 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e64 v10, s[4:5], v12, v10 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; CHECK-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc
; CHECK-NEXT: v_mul_lo_u32 v8, v4, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, v4, v5
; CHECK-NEXT: v_mul_lo_u32 v9, v3, v6 ; CHECK-NEXT: v_mul_lo_u32 v9, v3, v6
; CHECK-NEXT: v_mul_hi_u32 v10, v3, v5 ; CHECK-NEXT: v_mul_hi_u32 v10, v3, v5
; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5 ; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines; CHECK-NEXT: s_setpc_b64 s[30:31]
%r = sdiv i64 %x, %shl.y %r = sdiv i64 %x, %shl.y
ret i64 %r ret i64 %r
} }
define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; GISEL-LABEL: v_sdiv_v2i64_pow2_shl_denom: ; GISEL-LABEL: v_sdiv_v2i64_pow2_shl_denom:
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_mov_b64 s[6:7], 0x1000 ; GISEL-NEXT: s_mov_b64 s[4:5], 0x1000
; GISEL-NEXT: v_lshl_b64 v[7:8], s[6:7], v4 ; GISEL-NEXT: v_lshl_b64 v[7:8], s[4:5], v4
; GISEL-NEXT: v_ashrrev_i32_e32 v10, 31, v1 ; GISEL-NEXT: v_ashrrev_i32_e32 v10, 31, v1
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v8 ; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v8
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v4 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v4
; GISEL-NEXT: v_addc_u32_e32 v7, vcc, v8, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v7, vcc, v8, v4, vcc
; GISEL-NEXT: v_xor_b32_e32 v5, v5, v4 ; GISEL-NEXT: v_xor_b32_e32 v5, v5, v4
; GISEL-NEXT: v_xor_b32_e32 v7, v7, v4 ; GISEL-NEXT: v_xor_b32_e32 v7, v7, v4
; GISEL-NEXT: v_cvt_f32_u32_e32 v8, v5 ; GISEL-NEXT: v_cvt_f32_u32_e32 v8, v5
; GISEL-NEXT: v_cvt_f32_u32_e32 v9, v7 ; GISEL-NEXT: v_cvt_f32_u32_e32 v9, v7
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v10 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v10
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v10, vcc ; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v10, vcc
; GISEL-NEXT: v_mac_f32_e32 v8, 0x4f800000, v9 ; GISEL-NEXT: v_mac_f32_e32 v8, 0x4f800000, v9
; GISEL-NEXT: v_rcp_iflag_f32_e32 v8, v8 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v8, v8
; GISEL-NEXT: v_xor_b32_e32 v9, v0, v10
; GISEL-NEXT: v_sub_i32_e32 v11, vcc, 0, v5 ; GISEL-NEXT: v_sub_i32_e32 v11, vcc, 0, v5
; GISEL-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v8
; GISEL-NEXT: v_mul_f32_e32 v8, 0x2f800000, v0
; GISEL-NEXT: v_trunc_f32_e32 v8, v8
; GISEL-NEXT: v_mac_f32_e32 v0, 0xcf800000, v8
; GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v8
; GISEL-NEXT: v_subb_u32_e32 v12, vcc, 0, v7, vcc ; GISEL-NEXT: v_subb_u32_e32 v12, vcc, 0, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v13, v12, v0 ; GISEL-NEXT: v_mul_f32_e32 v8, 0x5f7ffffc, v8
; GISEL-NEXT: v_mul_lo_u32 v14, v11, v8 ; GISEL-NEXT: v_mul_f32_e32 v9, 0x2f800000, v8
; GISEL-NEXT: v_mul_hi_u32 v16, v11, v0 ; GISEL-NEXT: v_trunc_f32_e32 v9, v9
; GISEL-NEXT: v_mul_lo_u32 v15, v11, v0 ; GISEL-NEXT: v_mac_f32_e32 v8, 0xcf800000, v9
; GISEL-NEXT: v_xor_b32_e32 v17, v1, v10 ; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v8
; GISEL-NEXT: v_cvt_u32_f32_e32 v9, v9
; GISEL-NEXT: v_xor_b32_e32 v17, v0, v10
; GISEL-NEXT: v_mul_lo_u32 v13, v12, v8
; GISEL-NEXT: v_mul_lo_u32 v14, v11, v9
; GISEL-NEXT: v_mul_hi_u32 v16, v11, v8
; GISEL-NEXT: v_mul_lo_u32 v15, v11, v8
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v16 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v16
; GISEL-NEXT: v_mul_lo_u32 v14, v8, v15 ; GISEL-NEXT: v_mul_lo_u32 v14, v9, v15
; GISEL-NEXT: v_mul_lo_u32 v16, v0, v13 ; GISEL-NEXT: v_mul_lo_u32 v16, v8, v13
; GISEL-NEXT: v_mul_hi_u32 v1, v0, v15 ; GISEL-NEXT: v_mul_hi_u32 v0, v8, v15
; GISEL-NEXT: v_mul_hi_u32 v15, v8, v15 ; GISEL-NEXT: v_mul_hi_u32 v15, v9, v15
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v14, v1 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v14, v0
; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v14, v8, v13 ; GISEL-NEXT: v_mul_lo_u32 v14, v9, v13
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v16, v1 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v16, v0
; GISEL-NEXT: v_mul_hi_u32 v16, v0, v13 ; GISEL-NEXT: v_mul_hi_u32 v16, v8, v13
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v15 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16 ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; GISEL-NEXT: v_mul_hi_u32 v13, v8, v13 ; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v14, v1 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v14, v0
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v8, v0
; GISEL-NEXT: v_addc_u32_e64 v1, s[4:5], v8, v13, vcc ; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v9, v13, vcc
; GISEL-NEXT: v_mul_lo_u32 v12, v12, v0 ; GISEL-NEXT: v_mul_lo_u32 v9, v12, v0
; GISEL-NEXT: v_mul_lo_u32 v14, v11, v1 ; GISEL-NEXT: v_mul_lo_u32 v12, v11, v8
; GISEL-NEXT: v_mul_lo_u32 v15, v11, v0 ; GISEL-NEXT: v_mul_lo_u32 v13, v11, v0
; GISEL-NEXT: v_mul_hi_u32 v11, v11, v0 ; GISEL-NEXT: v_mul_hi_u32 v11, v11, v0
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v13 ; GISEL-NEXT: v_xor_b32_e32 v14, v1, v10
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v1, v15 ; GISEL-NEXT: v_mul_lo_u32 v11, v8, v13
; GISEL-NEXT: v_mul_lo_u32 v14, v0, v11 ; GISEL-NEXT: v_mul_lo_u32 v12, v0, v9
; GISEL-NEXT: v_mul_hi_u32 v13, v0, v15 ; GISEL-NEXT: v_mul_hi_u32 v1, v0, v13
; GISEL-NEXT: v_mul_hi_u32 v15, v1, v15 ; GISEL-NEXT: v_mul_hi_u32 v13, v8, v13
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v11, v1
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v13, v1, v11 ; GISEL-NEXT: v_mul_lo_u32 v11, v8, v9
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v12, v1
; GISEL-NEXT: v_mul_hi_u32 v14, v0, v11 ; GISEL-NEXT: v_mul_hi_u32 v12, v0, v9
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v15 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v15, v14
; GISEL-NEXT: v_mul_hi_u32 v1, v1, v11
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v14, v13
; GISEL-NEXT: v_add_i32_e64 v1, s[4:5], v1, v11
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v8, v1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v0, v12
; GISEL-NEXT: v_addc_u32_e32 v11, vcc, 0, v1, vcc
; GISEL-NEXT: v_mul_lo_u32 v12, v17, v8
; GISEL-NEXT: v_mul_lo_u32 v13, v9, v11
; GISEL-NEXT: v_lshl_b64 v[0:1], s[6:7], v6
; GISEL-NEXT: v_mul_hi_u32 v6, v9, v8
; GISEL-NEXT: v_mul_hi_u32 v8, v17, v8
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v12, v6 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_mul_hi_u32 v9, v8, v9
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v11, v1
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v0, v1
; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, v14, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v17, v8
; GISEL-NEXT: v_lshl_b64 v[0:1], s[4:5], v6
; GISEL-NEXT: v_mul_hi_u32 v6, v17, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v14, v11
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v12, v17, v11 ; GISEL-NEXT: v_mul_lo_u32 v9, v14, v8
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v13, v6 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; GISEL-NEXT: v_mul_hi_u32 v13, v9, v11 ; GISEL-NEXT: v_mul_hi_u32 v12, v17, v8
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v12, v8 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v13
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_mul_hi_u32 v11, v17, v11
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v12, v8
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v11, v8
; GISEL-NEXT: v_mul_lo_u32 v11, v7, v6
; GISEL-NEXT: v_mul_lo_u32 v12, v5, v8
; GISEL-NEXT: v_mul_hi_u32 v14, v5, v6
; GISEL-NEXT: v_mul_lo_u32 v13, v5, v6
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 ; GISEL-NEXT: v_mul_hi_u32 v8, v14, v8
; GISEL-NEXT: v_sub_i32_e32 v9, vcc, v9, v13 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GISEL-NEXT: v_subb_u32_e64 v12, s[4:5], v17, v11, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_sub_i32_e64 v11, s[4:5], v17, v11 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_mul_lo_u32 v9, v7, v6
; GISEL-NEXT: v_mul_lo_u32 v11, v5, v8
; GISEL-NEXT: v_mul_hi_u32 v13, v5, v6
; GISEL-NEXT: v_mul_lo_u32 v12, v5, v6
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v13
; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v17, v12
; GISEL-NEXT: v_subb_u32_e64 v12, s[4:5], v14, v9, vcc
; GISEL-NEXT: v_sub_i32_e64 v9, s[4:5], v14, v9
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v12, v7 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v12, v7
; GISEL-NEXT: v_subb_u32_e32 v11, vcc, v11, v7, vcc ; GISEL-NEXT: v_subb_u32_e32 v9, vcc, v9, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v5 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v11, v5
; GISEL-NEXT: v_sub_i32_e32 v9, vcc, v9, v5 ; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v11, v5
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v12, v7 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v12, v7
; GISEL-NEXT: v_subbrev_u32_e32 v11, vcc, 0, v11, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, v13, v14, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, v13, v14, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v13, vcc, 1, v6 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, 1, v6
; GISEL-NEXT: v_addc_u32_e32 v14, vcc, 0, v8, vcc ; GISEL-NEXT: v_addc_u32_e32 v14, vcc, 0, v8, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v11, v7 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v9, v7
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, -1, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v9, v5 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v11, v5
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v11, v7 ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v9, v7
; GISEL-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v13 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v13
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v14, vcc ; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v14, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v7, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v5, v13, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v7, v14, v9, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v7, v14, v9, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GISEL-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
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; GISEL-NEXT: v_ashrrev_i32_e32 v10, 31, v3 ; GISEL-NEXT: v_ashrrev_i32_e32 v10, 31, v3
; GISEL-NEXT: v_xor_b32_e32 v5, v5, v7 ; GISEL-NEXT: v_xor_b32_e32 v5, v5, v7
; GISEL-NEXT: v_xor_b32_e32 v6, v6, v7 ; GISEL-NEXT: v_xor_b32_e32 v6, v6, v7
; GISEL-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GISEL-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GISEL-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v2, v10 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v2, v10
; GISEL-NEXT: v_addc_u32_e32 v2, vcc, v3, v10, vcc ; GISEL-NEXT: v_addc_u32_e32 v2, vcc, v3, v10, vcc
; GISEL-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GISEL-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GISEL-NEXT: v_xor_b32_e32 v3, v1, v10 ; GISEL-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
; GISEL-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GISEL-NEXT: v_trunc_f32_e32 v3, v3
; GISEL-NEXT: v_trunc_f32_e32 v1, v1 ; GISEL-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
; GISEL-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
; GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3
; GISEL-NEXT: v_sub_i32_e32 v11, vcc, 0, v8 ; GISEL-NEXT: v_sub_i32_e32 v11, vcc, 0, v8
; GISEL-NEXT: v_subb_u32_e32 v12, vcc, 0, v9, vcc ; GISEL-NEXT: v_subb_u32_e32 v12, vcc, 0, v9, vcc
; GISEL-NEXT: v_mul_lo_u32 v13, v12, v0 ; GISEL-NEXT: v_mul_lo_u32 v13, v12, v0
; GISEL-NEXT: v_mul_lo_u32 v14, v11, v1 ; GISEL-NEXT: v_mul_lo_u32 v14, v11, v3
; GISEL-NEXT: v_mul_hi_u32 v16, v11, v0 ; GISEL-NEXT: v_mul_hi_u32 v16, v11, v0
; GISEL-NEXT: v_mul_lo_u32 v15, v11, v0 ; GISEL-NEXT: v_mul_lo_u32 v15, v11, v0
; GISEL-NEXT: v_xor_b32_e32 v2, v2, v10 ; GISEL-NEXT: v_xor_b32_e32 v17, v1, v10
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v16 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v16
; GISEL-NEXT: v_mul_lo_u32 v14, v1, v15 ; GISEL-NEXT: v_mul_lo_u32 v14, v3, v15
; GISEL-NEXT: v_mul_lo_u32 v16, v0, v13 ; GISEL-NEXT: v_mul_lo_u32 v16, v0, v13
; GISEL-NEXT: v_mul_hi_u32 v17, v0, v15 ; GISEL-NEXT: v_mul_hi_u32 v1, v0, v15
; GISEL-NEXT: v_mul_hi_u32 v15, v1, v15 ; GISEL-NEXT: v_mul_hi_u32 v15, v3, v15
; GISEL-NEXT: v_xor_b32_e32 v4, v10, v4 ; GISEL-NEXT: v_xor_b32_e32 v2, v2, v10
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v17 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v14, v1
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v17, v1, v13 ; GISEL-NEXT: v_mul_lo_u32 v14, v3, v13
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v16, v14 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v16, v1
; GISEL-NEXT: v_mul_hi_u32 v16, v0, v13 ; GISEL-NEXT: v_mul_hi_u32 v16, v0, v13
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v17, v15 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v15
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16 ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; GISEL-NEXT: v_mul_hi_u32 v13, v1, v13 ; GISEL-NEXT: v_mul_hi_u32 v13, v3, v13
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v14, v1
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v16, v15 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15 ; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v3, v13, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v14 ; GISEL-NEXT: v_mul_lo_u32 v3, v12, v0
; GISEL-NEXT: v_addc_u32_e64 v14, s[4:5], v1, v13, vcc ; GISEL-NEXT: v_mul_lo_u32 v12, v11, v1
; GISEL-NEXT: v_mul_lo_u32 v12, v12, v0 ; GISEL-NEXT: v_mul_lo_u32 v13, v11, v0
; GISEL-NEXT: v_mul_lo_u32 v15, v11, v14
; GISEL-NEXT: v_mul_lo_u32 v16, v11, v0
; GISEL-NEXT: v_mul_hi_u32 v11, v11, v0 ; GISEL-NEXT: v_mul_hi_u32 v11, v11, v0
; GISEL-NEXT: v_add_i32_e64 v1, s[4:5], v1, v13 ; GISEL-NEXT: v_xor_b32_e32 v4, v10, v4
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v12
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v14, v16 ; GISEL-NEXT: v_mul_lo_u32 v11, v1, v13
; GISEL-NEXT: v_mul_lo_u32 v15, v0, v11 ; GISEL-NEXT: v_mul_lo_u32 v12, v0, v3
; GISEL-NEXT: v_mul_hi_u32 v13, v0, v16 ; GISEL-NEXT: v_mul_hi_u32 v14, v0, v13
; GISEL-NEXT: v_mul_hi_u32 v16, v14, v16 ; GISEL-NEXT: v_mul_hi_u32 v13, v1, v13
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v13, v14, v11 ; GISEL-NEXT: v_mul_lo_u32 v14, v1, v3
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v15, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_mul_hi_u32 v15, v0, v11 ; GISEL-NEXT: v_mul_hi_u32 v12, v0, v3
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v16 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v15 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v16, v15 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_mul_hi_u32 v11, v14, v11 ; GISEL-NEXT: v_mul_hi_u32 v3, v1, v3
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v15, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v12
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v11, vcc ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v0, v11
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v0, v12 ; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc
; GISEL-NEXT: v_addc_u32_e32 v12, vcc, 0, v1, vcc ; GISEL-NEXT: v_mul_lo_u32 v12, v2, v11
; GISEL-NEXT: v_mul_lo_u32 v13, v2, v11 ; GISEL-NEXT: v_mul_lo_u32 v13, v17, v3
; GISEL-NEXT: v_mul_lo_u32 v14, v3, v12
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v5, v7 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v5, v7
; GISEL-NEXT: v_mul_hi_u32 v5, v3, v11 ; GISEL-NEXT: v_mul_hi_u32 v5, v17, v11
; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v6, v7, vcc ; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v6, v7, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v12, v13
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v6, v2, v12 ; GISEL-NEXT: v_mul_lo_u32 v6, v2, v3
; GISEL-NEXT: v_mul_hi_u32 v11, v2, v11 ; GISEL-NEXT: v_mul_hi_u32 v11, v2, v11
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GISEL-NEXT: v_mul_hi_u32 v7, v3, v12 ; GISEL-NEXT: v_mul_hi_u32 v7, v17, v3
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v11 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v11, v7 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; GISEL-NEXT: v_mul_hi_u32 v11, v2, v12 ; GISEL-NEXT: v_mul_hi_u32 v3, v2, v3
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v11, v6 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GISEL-NEXT: v_mul_lo_u32 v7, v9, v5 ; GISEL-NEXT: v_mul_lo_u32 v6, v9, v5
; GISEL-NEXT: v_mul_lo_u32 v11, v8, v6 ; GISEL-NEXT: v_mul_lo_u32 v7, v8, v3
; GISEL-NEXT: v_mul_hi_u32 v13, v8, v5 ; GISEL-NEXT: v_mul_hi_u32 v12, v8, v5
; GISEL-NEXT: v_mul_lo_u32 v12, v8, v5 ; GISEL-NEXT: v_mul_lo_u32 v11, v8, v5
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v13 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v12
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v3, v12 ; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v17, v11
; GISEL-NEXT: v_subb_u32_e64 v11, s[4:5], v2, v7, vcc ; GISEL-NEXT: v_subb_u32_e64 v11, s[4:5], v2, v6, vcc
; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v7 ; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v6
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v11, v9 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v11, v9
; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v9, vcc ; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v9, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v8 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v8
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v3, v8 ; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v11, v9 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v11, v9
; GISEL-NEXT: v_add_i32_e32 v11, vcc, 1, v5 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, 1, v5
; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v12, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v6, v6, v12, s[4:5]
; GISEL-NEXT: v_addc_u32_e32 v12, vcc, 0, v6, vcc ; GISEL-NEXT: v_addc_u32_e32 v12, vcc, 0, v3, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v2, v9 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v2, v9
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v3, v8 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v9 ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v9
; GISEL-NEXT: v_cndmask_b32_e32 v2, v13, v3, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v2, v13, v7, vcc
; GISEL-NEXT: v_add_i32_e32 v3, vcc, 1, v11 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v11
; GISEL-NEXT: v_addc_u32_e32 v8, vcc, 0, v12, vcc ; GISEL-NEXT: v_addc_u32_e32 v8, vcc, 0, v12, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GISEL-NEXT: v_cndmask_b32_e32 v2, v11, v3, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v2, v11, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v12, v8, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v7, v12, v8, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GISEL-NEXT: v_xor_b32_e32 v2, v2, v4 ; GISEL-NEXT: v_xor_b32_e32 v2, v2, v4
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v4 ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v4
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v4 ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc ; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_sdiv_v2i64_pow2_shl_denom: ; CGP-LABEL: v_sdiv_v2i64_pow2_shl_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v17, vcc, v18, v17 ; CGP-NEXT: v_add_i32_e32 v17, vcc, v18, v17
; CGP-NEXT: v_mul_hi_u32 v14, v9, v14 ; CGP-NEXT: v_mul_hi_u32 v14, v9, v14
; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16 ; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v16 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v16
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v15 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v15
; CGP-NEXT: v_addc_u32_e64 v15, s[4:5], v9, v14, vcc ; CGP-NEXT: v_addc_u32_e32 v9, vcc, v9, v14, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v13, v3 ; CGP-NEXT: v_mul_lo_u32 v13, v13, v3
; CGP-NEXT: v_mul_lo_u32 v16, v12, v15 ; CGP-NEXT: v_mul_lo_u32 v14, v12, v9
; CGP-NEXT: v_mul_lo_u32 v17, v12, v3 ; CGP-NEXT: v_mul_lo_u32 v15, v12, v3
; CGP-NEXT: v_mul_hi_u32 v12, v12, v3 ; CGP-NEXT: v_mul_hi_u32 v12, v12, v3
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v16 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; CGP-NEXT: v_mul_lo_u32 v13, v9, v15
; CGP-NEXT: v_mul_lo_u32 v13, v15, v17 ; CGP-NEXT: v_mul_lo_u32 v14, v3, v12
; CGP-NEXT: v_mul_lo_u32 v16, v3, v12 ; CGP-NEXT: v_mul_hi_u32 v16, v3, v15
; CGP-NEXT: v_mul_hi_u32 v14, v3, v17 ; CGP-NEXT: v_mul_hi_u32 v15, v9, v15
; CGP-NEXT: v_mul_hi_u32 v17, v15, v17 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v16 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v16
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14 ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_mul_lo_u32 v16, v9, v12
; CGP-NEXT: v_mul_lo_u32 v14, v15, v12 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v16, v13 ; CGP-NEXT: v_mul_hi_u32 v14, v3, v12
; CGP-NEXT: v_mul_hi_u32 v16, v3, v12 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v17 ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v16 ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; CGP-NEXT: v_add_i32_e64 v16, s[4:5], v17, v16 ; CGP-NEXT: v_mul_hi_u32 v12, v9, v12
; CGP-NEXT: v_mul_hi_u32 v12, v15, v12 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v16, v14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_addc_u32_e32 v9, vcc, v9, v12, vcc
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v13 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v13
; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc ; CGP-NEXT: v_addc_u32_e32 v9, vcc, v9, v12, vcc
; CGP-NEXT: v_mul_lo_u32 v12, v8, v3 ; CGP-NEXT: v_mul_lo_u32 v12, v8, v3
; CGP-NEXT: v_mul_lo_u32 v13, v4, v9 ; CGP-NEXT: v_mul_lo_u32 v13, v4, v9
; CGP-NEXT: v_mul_hi_u32 v14, v4, v3 ; CGP-NEXT: v_mul_hi_u32 v14, v4, v3
; CGP-NEXT: v_mul_hi_u32 v3, v8, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v8, v3
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; CGP-NEXT: v_mul_hi_u32 v12, v8, v12 ; CGP-NEXT: v_mul_hi_u32 v12, v8, v12
; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v13 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v13
; CGP-NEXT: v_addc_u32_e64 v13, s[4:5], v8, v12, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v12, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v11, v6 ; CGP-NEXT: v_mul_lo_u32 v11, v11, v6
; CGP-NEXT: v_mul_lo_u32 v14, v10, v13 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v8
; CGP-NEXT: v_mul_lo_u32 v15, v10, v6 ; CGP-NEXT: v_mul_lo_u32 v13, v10, v6
; CGP-NEXT: v_mul_hi_u32 v10, v10, v6 ; CGP-NEXT: v_mul_hi_u32 v10, v10, v6
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; CGP-NEXT: v_mul_lo_u32 v11, v8, v13
; CGP-NEXT: v_mul_lo_u32 v11, v13, v15 ; CGP-NEXT: v_mul_lo_u32 v12, v6, v10
; CGP-NEXT: v_mul_lo_u32 v14, v6, v10 ; CGP-NEXT: v_mul_hi_u32 v14, v6, v13
; CGP-NEXT: v_mul_hi_u32 v12, v6, v15 ; CGP-NEXT: v_mul_hi_u32 v13, v8, v13
; CGP-NEXT: v_mul_hi_u32 v15, v13, v15 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CGP-NEXT: v_mul_lo_u32 v14, v8, v10
; CGP-NEXT: v_mul_lo_u32 v12, v13, v10 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v14, v11 ; CGP-NEXT: v_mul_hi_u32 v12, v6, v10
; CGP-NEXT: v_mul_hi_u32 v14, v6, v10 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v15, v14 ; CGP-NEXT: v_mul_hi_u32 v10, v8, v10
; CGP-NEXT: v_mul_hi_u32 v10, v13, v10 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v11 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v11
; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; CGP-NEXT: v_mul_lo_u32 v10, v7, v6 ; CGP-NEXT: v_mul_lo_u32 v10, v7, v6
; CGP-NEXT: v_mul_lo_u32 v11, v5, v8 ; CGP-NEXT: v_mul_lo_u32 v11, v5, v8
; CGP-NEXT: v_mul_hi_u32 v12, v5, v6 ; CGP-NEXT: v_mul_hi_u32 v12, v5, v6
; CGP-NEXT: v_mul_hi_u32 v6, v7, v6 ; CGP-NEXT: v_mul_hi_u32 v6, v7, v6
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_mov_b32 s6, 0xffffff ; GISEL-NEXT: s_mov_b32 s6, 0xffffff
; GISEL-NEXT: v_and_b32_e32 v1, s6, v4 ; GISEL-NEXT: v_and_b32_e32 v1, s6, v4
; GISEL-NEXT: v_add_i32_e32 v1, vcc, 0, v1 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, 0, v1
; GISEL-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc ; GISEL-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v1 ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v1
; GISEL-NEXT: v_cvt_f32_u32_e32 v5, v3 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, v3
; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v1 ; GISEL-NEXT: v_sub_i32_e32 v8, vcc, 0, v1
; GISEL-NEXT: v_subb_u32_e32 v8, vcc, 0, v3, vcc ; GISEL-NEXT: v_subb_u32_e32 v9, vcc, 0, v3, vcc
; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GISEL-NEXT: v_and_b32_e32 v5, s6, v0 ; GISEL-NEXT: v_and_b32_e32 v5, s6, v0
; GISEL-NEXT: v_and_b32_e32 v0, s6, v2
; GISEL-NEXT: v_and_b32_e32 v6, s6, v6 ; GISEL-NEXT: v_and_b32_e32 v6, s6, v6
; GISEL-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v4 ; GISEL-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v4
; GISEL-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x2f800000, v0
; GISEL-NEXT: v_trunc_f32_e32 v4, v4 ; GISEL-NEXT: v_trunc_f32_e32 v4, v4
; GISEL-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4 ; GISEL-NEXT: v_mac_f32_e32 v0, 0xcf800000, v4
; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v0
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
; GISEL-NEXT: v_mul_lo_u32 v9, v8, v2 ; GISEL-NEXT: v_mul_lo_u32 v0, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v7, v4 ; GISEL-NEXT: v_mul_lo_u32 v10, v8, v4
; GISEL-NEXT: v_mul_hi_u32 v12, v7, v2 ; GISEL-NEXT: v_mul_hi_u32 v12, v8, v7
; GISEL-NEXT: v_mul_lo_u32 v11, v7, v2 ; GISEL-NEXT: v_mul_lo_u32 v11, v8, v7
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v10
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v0, v12
; GISEL-NEXT: v_mul_lo_u32 v10, v4, v11 ; GISEL-NEXT: v_mul_lo_u32 v12, v4, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v2, v9 ; GISEL-NEXT: v_mul_lo_u32 v13, v7, v10
; GISEL-NEXT: v_mul_hi_u32 v14, v2, v11 ; GISEL-NEXT: v_and_b32_e32 v0, s6, v2
; GISEL-NEXT: v_add_i32_e32 v5, vcc, 0, v5 ; GISEL-NEXT: v_mul_hi_u32 v2, v7, v11
; GISEL-NEXT: v_addc_u32_e64 v13, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v14
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v14, v4, v9
; GISEL-NEXT: v_mul_hi_u32 v11, v4, v11 ; GISEL-NEXT: v_mul_hi_u32 v11, v4, v11
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_mul_hi_u32 v12, v2, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v14, v11 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v12, v2
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_mul_lo_u32 v12, v4, v10
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v13, v2
; GISEL-NEXT: v_mul_hi_u32 v13, v7, v10
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v14, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_mul_hi_u32 v9, v4, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_mul_hi_u32 v10, v4, v10
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v11, v2
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v10 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; GISEL-NEXT: v_addc_u32_e64 v10, s[4:5], v4, v9, vcc ; GISEL-NEXT: v_addc_u32_e32 v4, vcc, v4, v10, vcc
; GISEL-NEXT: v_mul_lo_u32 v8, v8, v2 ; GISEL-NEXT: v_mul_lo_u32 v7, v9, v2
; GISEL-NEXT: v_mul_lo_u32 v11, v7, v10 ; GISEL-NEXT: v_mul_lo_u32 v9, v8, v4
; GISEL-NEXT: v_mul_lo_u32 v12, v7, v2 ; GISEL-NEXT: v_mul_lo_u32 v10, v8, v2
; GISEL-NEXT: v_mul_hi_u32 v7, v7, v2 ; GISEL-NEXT: v_mul_hi_u32 v8, v8, v2
; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v4, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v8, v7 ; GISEL-NEXT: v_mul_lo_u32 v8, v4, v10
; GISEL-NEXT: v_mul_lo_u32 v8, v10, v12 ; GISEL-NEXT: v_mul_lo_u32 v9, v2, v7
; GISEL-NEXT: v_mul_lo_u32 v11, v2, v7 ; GISEL-NEXT: v_mul_hi_u32 v12, v2, v10
; GISEL-NEXT: v_mul_hi_u32 v9, v2, v12 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, 0, v5
; GISEL-NEXT: v_mul_hi_u32 v12, v10, v12 ; GISEL-NEXT: v_addc_u32_e64 v11, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v12, v4, v7
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8 ; GISEL-NEXT: v_mul_hi_u32 v10, v4, v10
; GISEL-NEXT: v_mul_hi_u32 v11, v2, v7 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; GISEL-NEXT: v_mul_hi_u32 v9, v2, v7
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_mul_hi_u32 v7, v10, v7 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; GISEL-NEXT: v_mul_hi_u32 v7, v4, v7
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v7, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; GISEL-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v13, v2 ; GISEL-NEXT: v_mul_lo_u32 v7, v11, v2
; GISEL-NEXT: v_mul_lo_u32 v8, v5, v4 ; GISEL-NEXT: v_mul_lo_u32 v8, v5, v4
; GISEL-NEXT: v_mul_hi_u32 v9, v5, v2 ; GISEL-NEXT: v_mul_hi_u32 v9, v5, v2
; GISEL-NEXT: v_mul_hi_u32 v2, v13, v2 ; GISEL-NEXT: v_mul_hi_u32 v2, v11, v2
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, v13, v4 ; GISEL-NEXT: v_mul_lo_u32 v9, v11, v4
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GISEL-NEXT: v_mul_hi_u32 v8, v5, v4 ; GISEL-NEXT: v_mul_hi_u32 v8, v5, v4
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v9, v2 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v9, v2
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_mul_hi_u32 v4, v13, v4 ; GISEL-NEXT: v_mul_hi_u32 v4, v11, v4
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v7 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v7
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GISEL-NEXT: v_mul_lo_u32 v7, v3, v2 ; GISEL-NEXT: v_mul_lo_u32 v7, v3, v2
; GISEL-NEXT: v_mul_lo_u32 v8, v1, v4 ; GISEL-NEXT: v_mul_lo_u32 v8, v1, v4
; GISEL-NEXT: v_mul_hi_u32 v10, v1, v2 ; GISEL-NEXT: v_mul_hi_u32 v10, v1, v2
; GISEL-NEXT: v_mul_lo_u32 v9, v1, v2 ; GISEL-NEXT: v_mul_lo_u32 v9, v1, v2
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v5, v9 ; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v5, v9
; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v13, v7, vcc ; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v11, v7, vcc
; GISEL-NEXT: v_sub_i32_e64 v7, s[4:5], v13, v7 ; GISEL-NEXT: v_sub_i32_e64 v7, s[4:5], v11, v7
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v3 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v3
; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v7, v3, vcc ; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v7, v3, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v1 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v1
; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v5, v1 ; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v5, v1
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v3 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v3
; GISEL-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v8, v9, v10, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v8, v9, v10, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v2 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v2
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1
; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v7, v3 ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v7, v3
; GISEL-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc
; GISEL-NEXT: v_add_i32_e32 v3, vcc, 1, v9 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, 0, v6
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, 0, v10, vcc ; GISEL-NEXT: v_addc_u32_e64 v5, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, 0, v6 ; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3
; GISEL-NEXT: v_addc_u32_e64 v7, s[4:5], 0, 0, vcc ; GISEL-NEXT: v_cvt_f32_u32_e32 v7, v5
; GISEL-NEXT: v_cvt_f32_u32_e32 v11, v6 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, 1, v9
; GISEL-NEXT: v_cvt_f32_u32_e32 v12, v7 ; GISEL-NEXT: v_addc_u32_e32 v12, vcc, 0, v10, vcc
; GISEL-NEXT: v_mac_f32_e32 v6, 0x4f800000, v7
; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v3, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v11, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v5, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v7, v10, v12, vcc
; GISEL-NEXT: v_mac_f32_e32 v11, 0x4f800000, v12
; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v11
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc ; GISEL-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v6
; GISEL-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v2
; GISEL-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6
; GISEL-NEXT: v_trunc_f32_e32 v4, v4 ; GISEL-NEXT: v_mac_f32_e32 v2, 0xcf800000, v6
; GISEL-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4 ; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
; GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GISEL-NEXT: v_sub_i32_e64 v8, s[4:5], 0, v3
; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v6 ; GISEL-NEXT: v_subb_u32_e64 v9, s[4:5], 0, v5, s[4:5]
; GISEL-NEXT: v_subb_u32_e32 v8, vcc, 0, v7, vcc ; GISEL-NEXT: v_mul_lo_u32 v10, v9, v2
; GISEL-NEXT: v_mul_lo_u32 v9, v8, v3 ; GISEL-NEXT: v_mul_lo_u32 v11, v8, v6
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v4 ; GISEL-NEXT: v_mul_hi_u32 v13, v8, v2
; GISEL-NEXT: v_mul_hi_u32 v12, v5, v3 ; GISEL-NEXT: v_mul_lo_u32 v12, v8, v2
; GISEL-NEXT: v_mul_lo_u32 v11, v5, v3 ; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
; GISEL-NEXT: v_mul_lo_u32 v10, v4, v11 ; GISEL-NEXT: v_mul_lo_u32 v11, v6, v12
; GISEL-NEXT: v_mul_lo_u32 v12, v3, v9 ; GISEL-NEXT: v_mul_lo_u32 v13, v2, v10
; GISEL-NEXT: v_add_i32_e32 v13, vcc, 0, v0 ; GISEL-NEXT: v_mul_hi_u32 v7, v2, v12
; GISEL-NEXT: v_mul_hi_u32 v0, v3, v11 ; GISEL-NEXT: v_mul_hi_u32 v12, v6, v12
; GISEL-NEXT: v_addc_u32_e64 v14, s[4:5], 0, 0, vcc ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, v6, v10
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v13, v7
; GISEL-NEXT: v_mul_hi_u32 v13, v2, v10
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v10, v0 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v10, v4, v9 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_mul_hi_u32 v11, v4, v11 ; GISEL-NEXT: v_mul_hi_u32 v10, v6, v10
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v12, v0 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; GISEL-NEXT: v_mul_hi_u32 v12, v3, v9
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v7
; GISEL-NEXT: v_mul_hi_u32 v9, v4, v9 ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v10, v0 ; GISEL-NEXT: v_mul_lo_u32 v7, v9, v2
; GISEL-NEXT: v_mul_lo_u32 v9, v8, v6
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v2
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v2
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_mul_lo_u32 v8, v6, v10
; GISEL-NEXT: v_mul_lo_u32 v9, v2, v7
; GISEL-NEXT: v_add_i32_e32 v11, vcc, 0, v0
; GISEL-NEXT: v_mul_hi_u32 v0, v2, v10
; GISEL-NEXT: v_addc_u32_e64 v12, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v8, v0
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v8, v6, v7
; GISEL-NEXT: v_mul_hi_u32 v10, v6, v10
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v9, v0
; GISEL-NEXT: v_mul_hi_u32 v9, v2, v7
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v3, v0 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_addc_u32_e64 v3, s[4:5], v4, v9, vcc ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_mul_lo_u32 v8, v8, v0 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v8, v0
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v3 ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, v5, v0 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_mul_hi_u32 v5, v5, v0 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v4, v9 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10 ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, v12, v2
; GISEL-NEXT: v_mul_lo_u32 v8, v3, v11 ; GISEL-NEXT: v_mul_lo_u32 v8, v11, v6
; GISEL-NEXT: v_mul_lo_u32 v10, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v9, v0, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v3, v11
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v9, v3, v5
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v10, v8
; GISEL-NEXT: v_mul_hi_u32 v10, v0, v5
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10
; GISEL-NEXT: v_mul_hi_u32 v3, v3, v5
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v10, v9
; GISEL-NEXT: v_add_i32_e64 v3, s[4:5], v3, v5
; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v0, v8
; GISEL-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GISEL-NEXT: v_mul_lo_u32 v5, v14, v4
; GISEL-NEXT: v_mul_lo_u32 v8, v13, v3
; GISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0, v1 ; GISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0, v1
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v2, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v4, vcc
; GISEL-NEXT: v_mul_hi_u32 v2, v13, v4 ; GISEL-NEXT: v_mul_hi_u32 v4, v11, v2
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v5, v2 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v5, v14, v3 ; GISEL-NEXT: v_mul_lo_u32 v7, v12, v6
; GISEL-NEXT: v_mul_hi_u32 v4, v14, v4 ; GISEL-NEXT: v_mul_hi_u32 v2, v12, v2
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v8, v2 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v8, v4
; GISEL-NEXT: v_mul_hi_u32 v8, v13, v3 ; GISEL-NEXT: v_mul_hi_u32 v8, v11, v6
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_mul_hi_u32 v3, v14, v3 ; GISEL-NEXT: v_mul_hi_u32 v6, v12, v6
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GISEL-NEXT: v_mul_lo_u32 v4, v7, v2 ; GISEL-NEXT: v_mul_lo_u32 v6, v5, v2
; GISEL-NEXT: v_mul_lo_u32 v5, v6, v3 ; GISEL-NEXT: v_mul_lo_u32 v7, v3, v4
; GISEL-NEXT: v_mul_hi_u32 v9, v6, v2 ; GISEL-NEXT: v_mul_hi_u32 v9, v3, v2
; GISEL-NEXT: v_mul_lo_u32 v8, v6, v2 ; GISEL-NEXT: v_mul_lo_u32 v8, v3, v2
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v13, v8 ; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v11, v8
; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v14, v4, vcc ; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v12, v6, vcc
; GISEL-NEXT: v_sub_i32_e64 v4, s[4:5], v14, v4 ; GISEL-NEXT: v_sub_i32_e64 v6, s[4:5], v12, v6
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v7 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v5
; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v4, v7, vcc ; GISEL-NEXT: v_subb_u32_e32 v6, vcc, v6, v5, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v6 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v3
; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v5, v6 ; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v7, v3
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v7 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v5
; GISEL-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v6, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v8, v9, v10, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v8, v9, v10, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v2 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v2
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc ; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v4, v7 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v6, v5
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v5, v6 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v4, v7 ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v6, v5
; GISEL-NEXT: v_cndmask_b32_e32 v4, v11, v5, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v9 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v9
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v10, vcc ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v10, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GISEL-NEXT: v_cndmask_b32_e32 v4, v9, v5, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v5, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v6, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v5, v10, v6, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GISEL-NEXT: v_subrev_i32_e32 v2, vcc, 0, v2 ; GISEL-NEXT: v_subrev_i32_e32 v2, vcc, 0, v2
; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_sdiv_v2i64_24bit: ; CGP-LABEL: v_sdiv_v2i64_24bit:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s4, 0xffffff ; CGP-NEXT: s_mov_b32 s4, 0xffffff
Show All 34 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll

Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
; GFX8-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13] ; GFX8-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX8-NEXT: s_mov_b32 s3, s2 ; GFX8-NEXT: s_mov_b32 s3, s2
; GFX8-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3] ; GFX8-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3]
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_sub_u32 s14, 0, s8 ; GFX8-NEXT: s_sub_u32 s0, 0, s8
; GFX8-NEXT: s_cselect_b32 s0, 1, 0 ; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s0, s0, 1 ; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX8-NEXT: v_trunc_f32_e32 v1, v1 ; GFX8-NEXT: v_trunc_f32_e32 v1, v1
; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX8-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX8-NEXT: v_add_f32_e32 v0, v2, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_cmp_lg_u32 s0, 0 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_subb_u32 s15, 0, s9 ; GFX8-NEXT: s_subb_u32 s1, 0, s9
; GFX8-NEXT: v_mul_lo_u32 v2, s14, v1 ; GFX8-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX8-NEXT: v_mul_lo_u32 v3, s15, v0 ; GFX8-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX8-NEXT: v_mul_hi_u32 v5, s14, v0 ; GFX8-NEXT: v_mul_hi_u32 v5, s0, v0
; GFX8-NEXT: v_mul_lo_u32 v4, s14, v0 ; GFX8-NEXT: v_mul_lo_u32 v4, s0, v0
; GFX8-NEXT: v_mov_b32_e32 v6, s9
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4 ; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4
; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v6, v0, v4
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v6
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3
; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v6, v4
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v6, v5
; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX8-NEXT: v_mul_hi_u32 v5, s0, v0
; GFX8-NEXT: v_mul_lo_u32 v4, s0, v0
; GFX8-NEXT: v_mov_b32_e32 v6, s9
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4
; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v7, v0, v4 ; GFX8-NEXT: v_mul_hi_u32 v7, v0, v4
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v7 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v7
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v7, v1, v2 ; GFX8-NEXT: v_mul_lo_u32 v7, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3
; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2 ; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v5 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v5
; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_addc_u32_e64 v3, s[0:1], v1, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX8-NEXT: v_mul_lo_u32 v4, s15, v0
; GFX8-NEXT: v_mul_lo_u32 v5, s14, v3
; GFX8-NEXT: v_mul_hi_u32 v8, s14, v0
; GFX8-NEXT: v_mul_lo_u32 v7, s14, v0
; GFX8-NEXT: v_add_u32_e64 v1, s[0:1], v1, v2
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], v4, v5
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], v4, v8
; GFX8-NEXT: v_mul_lo_u32 v5, v3, v7
; GFX8-NEXT: v_mul_lo_u32 v8, v0, v4
; GFX8-NEXT: v_mul_hi_u32 v2, v0, v7
; GFX8-NEXT: v_mul_hi_u32 v7, v3, v7
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v8
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], v5, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX8-NEXT: v_mul_lo_u32 v5, v3, v4
; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], v8, v2
; GFX8-NEXT: v_mul_hi_u32 v8, v0, v4
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v7
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v8
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v7, s[0:1], v7, v8
; GFX8-NEXT: v_mul_hi_u32 v3, v3, v4
; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], v5, v2
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], v7, v5
; GFX8-NEXT: v_add_u32_e64 v3, s[0:1], v3, v4
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, s11, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s11, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s10, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s10, v1
; GFX8-NEXT: v_mul_hi_u32 v5, s10, v0 ; GFX8-NEXT: v_mul_hi_u32 v5, s10, v0
; GFX8-NEXT: v_mul_hi_u32 v0, s11, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s11, v0
; GFX8-NEXT: v_mov_b32_e32 v4, s11 ; GFX8-NEXT: v_mov_b32_e32 v4, s11
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
Show All 40 Lines
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s8, v7 ; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s8, v7
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v12, s[0:1], 1, v9 ; GFX8-NEXT: v_add_u32_e64 v12, s[0:1], 1, v9
; GFX8-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
; GFX8-NEXT: v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1] ; GFX8-NEXT: v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1]
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc ; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11
; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v10, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[0:1]
; GFX8-NEXT: s_xor_b64 s[0:1], s[2:3], s[12:13] ; GFX8-NEXT: s_xor_b64 s[0:1], s[2:3], s[12:13]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX8-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX8-NEXT: v_mov_b32_e32 v4, s1 ; GFX8-NEXT: v_mov_b32_e32 v4, s1
; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; GFX8-NEXT: v_xor_b32_e32 v3, s2, v3 ; GFX8-NEXT: v_xor_b32_e32 v3, s2, v3
; GFX8-NEXT: v_xor_b32_e32 v4, s2, v2 ; GFX8-NEXT: v_xor_b32_e32 v4, s2, v2
; GFX8-NEXT: v_mov_b32_e32 v5, s2 ; GFX8-NEXT: v_mov_b32_e32 v5, s2
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s2, v3 ; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s2, v3
Show All 26 Lines
; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13] ; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX9-NEXT: s_mov_b32 s3, s2 ; GFX9-NEXT: s_mov_b32 s3, s2
; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3] ; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3]
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_sub_u32 s14, 0, s8 ; GFX9-NEXT: s_sub_u32 s0, 0, s8
; GFX9-NEXT: s_cselect_b32 s0, 1, 0 ; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX9-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v2, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_subb_u32 s15, 0, s9 ; GFX9-NEXT: s_subb_u32 s1, 0, s9
; GFX9-NEXT: v_mul_lo_u32 v2, s14, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX9-NEXT: v_mul_lo_u32 v3, s15, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s14, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s14, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: v_mov_b32_e32 v8, s11 ; GFX9-NEXT: v_mov_b32_e32 v8, s11
; GFX9-NEXT: v_add3_u32 v2, v3, v2, v4 ; GFX9-NEXT: v_add3_u32 v2, v3, v2, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, v1, v2
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_mul_hi_u32 v4, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2 ; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[0:1], v1, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s15, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s14, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s14, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX9-NEXT: v_mul_lo_u32 v7, s14, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: v_add_u32_e32 v1, v1, v2 ; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4
; GFX9-NEXT: v_add3_u32 v4, v4, v5, v6 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v5, v3, v7 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v7 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v3, v7 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v6 ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1] ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v5, v2 ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX9-NEXT: v_mul_lo_u32 v6, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v5, v3, v4 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_add_u32_e32 v2, v6, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v6, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX9-NEXT: v_mul_hi_u32 v3, v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v7 ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1] ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v6 ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1] ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v5, v2 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
; GFX9-NEXT: v_add_u32_e32 v6, v7, v6 ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1] ; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX9-NEXT: v_add3_u32 v3, v6, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, s11, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s11, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1
; GFX9-NEXT: v_mul_hi_u32 v5, s10, v0 ; GFX9-NEXT: v_mul_hi_u32 v5, s10, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s11, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s11, v0
; GFX9-NEXT: v_mov_b32_e32 v4, s9 ; GFX9-NEXT: v_mov_b32_e32 v4, s9
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5
Show All 39 Lines
; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s8, v8 ; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s8, v8
; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v13, s[0:1], 1, v10 ; GFX9-NEXT: v_add_co_u32_e64 v13, s[0:1], 1, v10
; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v14, s[0:1], 0, v11, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v14, s[0:1], 0, v11, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v12
; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v10, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v11, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v9, v2, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
; GFX9-NEXT: s_xor_b64 s[0:1], s[2:3], s[12:13] ; GFX9-NEXT: s_xor_b64 s[0:1], s[2:3], s[12:13]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX9-NEXT: v_mov_b32_e32 v4, s1 ; GFX9-NEXT: v_mov_b32_e32 v4, s1
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX9-NEXT: v_xor_b32_e32 v3, s2, v3 ; GFX9-NEXT: v_xor_b32_e32 v3, s2, v3
; GFX9-NEXT: v_xor_b32_e32 v4, s2, v2 ; GFX9-NEXT: v_xor_b32_e32 v4, s2, v2
; GFX9-NEXT: v_mov_b32_e32 v5, s2 ; GFX9-NEXT: v_mov_b32_e32 v5, s2
; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s2, v3 ; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s2, v3
Show All 15 Lines
; GFX10-NEXT: s_cmp_lg_u32 s1, 0 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: s_addc_u32 s1, s9, s2 ; GFX10-NEXT: s_addc_u32 s1, s9, s2
; GFX10-NEXT: s_add_u32 s8, s10, s12 ; GFX10-NEXT: s_add_u32 s8, s10, s12
; GFX10-NEXT: s_cselect_b32 s3, 1, 0 ; GFX10-NEXT: s_cselect_b32 s3, 1, 0
; GFX10-NEXT: s_and_b32 s3, s3, 1 ; GFX10-NEXT: s_and_b32 s3, s3, 1
; GFX10-NEXT: s_cmp_lg_u32 s3, 0 ; GFX10-NEXT: s_cmp_lg_u32 s3, 0
; GFX10-NEXT: s_mov_b32 s3, s2 ; GFX10-NEXT: s_mov_b32 s3, s2
; GFX10-NEXT: s_addc_u32 s9, s11, s12 ; GFX10-NEXT: s_addc_u32 s9, s11, s12
; GFX10-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3] ; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13] ; GFX10-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX10-NEXT: s_sub_u32 s1, 0, s8 ; GFX10-NEXT: s_sub_u32 s10, 0, s8
; GFX10-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10-NEXT: s_cselect_b32 s11, 1, 0
; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_and_b32 s11, s11, 1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0
; GFX10-NEXT: s_subb_u32 s14, 0, s9 ; GFX10-NEXT: s_subb_u32 s11, 0, s9
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX10-NEXT: v_trunc_f32_e32 v1, v1 ; GFX10-NEXT: v_trunc_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX10-NEXT: v_add_f32_e32 v0, v2, v0
; GFX10-NEXT: v_mul_lo_u32 v2, s1, v1 ; GFX10-NEXT: v_mul_lo_u32 v2, s10, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s14, v0 ; GFX10-NEXT: v_mul_lo_u32 v3, s11, v0
; GFX10-NEXT: v_mul_hi_u32 v4, s1, v0 ; GFX10-NEXT: v_mul_hi_u32 v4, s10, v0
; GFX10-NEXT: v_mul_lo_u32 v5, s1, v0 ; GFX10-NEXT: v_mul_lo_u32 v5, s10, v0
; GFX10-NEXT: v_add3_u32 v2, v3, v2, v4 ; GFX10-NEXT: v_add3_u32 v2, v3, v2, v4
; GFX10-NEXT: v_mul_lo_u32 v3, v1, v5 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX10-NEXT: v_mul_hi_u32 v6, v1, v5 ; GFX10-NEXT: v_mul_hi_u32 v6, v1, v5
; GFX10-NEXT: v_mul_hi_u32 v5, v0, v5 ; GFX10-NEXT: v_mul_hi_u32 v5, v0, v5
; GFX10-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX10-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX10-NEXT: v_mul_lo_u32 v7, v1, v2 ; GFX10-NEXT: v_mul_lo_u32 v7, v1, v2
; GFX10-NEXT: v_mul_hi_u32 v8, v0, v2 ; GFX10-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX10-NEXT: v_add_co_u32 v3, s0, v3, v4 ; GFX10-NEXT: v_add_co_u32 v3, s14, v3, v4
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s14
; GFX10-NEXT: v_add_co_u32 v6, s0, v7, v6 ; GFX10-NEXT: v_add_co_u32 v6, s14, v7, v6
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s14
; GFX10-NEXT: v_add_co_u32 v3, s0, v3, v5 ; GFX10-NEXT: v_add_co_u32 v3, s14, v3, v5
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s14
; GFX10-NEXT: v_add_co_u32 v5, s0, v6, v8 ; GFX10-NEXT: v_add_co_u32 v5, s14, v6, v8
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s14
; GFX10-NEXT: v_add_nc_u32_e32 v3, v4, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v3, v4, v3
; GFX10-NEXT: v_add_nc_u32_e32 v4, v7, v6 ; GFX10-NEXT: v_add_nc_u32_e32 v4, v7, v6
; GFX10-NEXT: v_add_co_u32 v3, s0, v5, v3 ; GFX10-NEXT: v_add_co_u32 v3, s14, v5, v3
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s14
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
; GFX10-NEXT: v_add3_u32 v2, v4, v5, v2 ; GFX10-NEXT: v_add3_u32 v2, v4, v5, v2
; GFX10-NEXT: v_mul_lo_u32 v4, s14, v0 ; GFX10-NEXT: v_mul_hi_u32 v3, s10, v0
; GFX10-NEXT: v_mul_hi_u32 v5, s1, v0 ; GFX10-NEXT: v_mul_lo_u32 v5, s10, v0
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, v1, v2, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v7, s1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_lo_u32 v6, s1, v3
; GFX10-NEXT: v_mul_hi_u32 v8, v3, v7
; GFX10-NEXT: v_add3_u32 v4, v4, v6, v5
; GFX10-NEXT: v_mul_lo_u32 v5, v3, v7
; GFX10-NEXT: v_mul_hi_u32 v7, v0, v7
; GFX10-NEXT: v_mul_lo_u32 v6, v0, v4
; GFX10-NEXT: v_mul_lo_u32 v9, v3, v4
; GFX10-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX10-NEXT: v_mul_hi_u32 v3, v3, v4
; GFX10-NEXT: v_add_co_u32 v5, s0, v5, v6
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v8, s0, v9, v8
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v5, s0, v5, v7
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v7, s0, v8, v10
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v5, v6, v5
; GFX10-NEXT: v_add_nc_u32_e32 v4, v9, v8
; GFX10-NEXT: v_add_co_u32 v5, s0, v7, v5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_add3_u32 v2, v4, v6, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v2, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v2, vcc_lo
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v5
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v2, s11, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s11, v0
; GFX10-NEXT: v_mul_hi_u32 v4, s11, v0 ; GFX10-NEXT: v_mul_lo_u32 v4, s10, v1
; GFX10-NEXT: v_mul_hi_u32 v0, s10, v0 ; GFX10-NEXT: v_mul_hi_u32 v6, v1, v5
; GFX10-NEXT: v_mul_lo_u32 v3, s10, v1 ; GFX10-NEXT: v_add3_u32 v2, v2, v4, v3
; GFX10-NEXT: v_mul_lo_u32 v5, s11, v1 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX10-NEXT: v_mul_hi_u32 v6, s10, v1 ; GFX10-NEXT: v_mul_hi_u32 v5, v0, v5
; GFX10-NEXT: v_mul_hi_u32 v1, s11, v1 ; GFX10-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v3 ; GFX10-NEXT: v_mul_lo_u32 v7, v1, v2
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 ; GFX10-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX10-NEXT: v_add_co_u32 v4, s0, v5, v4 ; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 ; GFX10-NEXT: v_add_co_u32 v3, s10, v3, v4
; GFX10-NEXT: v_add_co_u32 v0, s0, v2, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s10
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: v_add_co_u32 v6, s10, v7, v6
; GFX10-NEXT: v_add_co_u32 v2, s0, v4, v6 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s10
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0 ; GFX10-NEXT: v_add_co_u32 v3, s10, v3, v5
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s10
; GFX10-NEXT: v_add_co_u32 v5, s10, v6, v8
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s10
; GFX10-NEXT: v_add_nc_u32_e32 v3, v4, v3
; GFX10-NEXT: v_add_nc_u32_e32 v4, v7, v6
; GFX10-NEXT: v_add_co_u32 v3, s10, v5, v3
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s10
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
; GFX10-NEXT: v_add3_u32 v2, v4, v5, v2
; GFX10-NEXT: v_mul_hi_u32 v4, s1, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v2, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX10-NEXT: v_mul_lo_u32 v5, s1, v1
; GFX10-NEXT: v_mul_hi_u32 v6, s0, v1
; GFX10-NEXT: v_mul_hi_u32 v1, s1, v1
; GFX10-NEXT: v_add_co_u32 v2, s10, v2, v3
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s10
; GFX10-NEXT: v_add_co_u32 v4, s10, v5, v4
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s10
; GFX10-NEXT: v_add_co_u32 v0, s10, v2, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s10
; GFX10-NEXT: v_add_co_u32 v2, s10, v4, v6
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s10
; GFX10-NEXT: v_add_nc_u32_e32 v0, v3, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v3, v0
; GFX10-NEXT: v_add_nc_u32_e32 v3, v5, v4 ; GFX10-NEXT: v_add_nc_u32_e32 v3, v5, v4
; GFX10-NEXT: v_add_co_u32 v0, s0, v2, v0 ; GFX10-NEXT: v_add_co_u32 v0, s10, v2, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s10
; GFX10-NEXT: v_mul_lo_u32 v5, s8, v0 ; GFX10-NEXT: v_mul_lo_u32 v5, s8, v0
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v0, 1
; GFX10-NEXT: v_add3_u32 v1, v3, v2, v1 ; GFX10-NEXT: v_add3_u32 v1, v3, v2, v1
; GFX10-NEXT: v_mul_lo_u32 v2, s9, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s9, v0
; GFX10-NEXT: v_mul_hi_u32 v3, s8, v0 ; GFX10-NEXT: v_mul_hi_u32 v3, s8, v0
; GFX10-NEXT: v_mul_lo_u32 v4, s8, v1 ; GFX10-NEXT: v_mul_lo_u32 v4, s8, v1
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add3_u32 v2, v2, v4, v3 ; GFX10-NEXT: v_add3_u32 v2, v2, v4, v3
; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v0, 1 ; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v6, 1
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v7, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v6, s11, v2 ; GFX10-NEXT: v_sub_nc_u32_e32 v8, s1, v2
; GFX10-NEXT: v_sub_co_u32 v5, vcc_lo, s10, v5 ; GFX10-NEXT: v_sub_co_u32 v5, vcc_lo, s0, v5
; GFX10-NEXT: v_sub_co_ci_u32_e64 v2, s0, s11, v2, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e64 v2, s0, s1, v2, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s8, v5 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s8, v5
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v5, s8 ; GFX10-NEXT: v_sub_co_u32 v10, vcc_lo, v5, s8
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v9, s0, 0, v6, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v11, s0, 0, v8, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v2 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v2
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, -1, s0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s9, v11
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v8
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v9
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, s0
; GFX10-NEXT: v_add_co_u32 v13, s0, v3, 1 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v10
; GFX10-NEXT: v_add_co_ci_u32_e64 v14, s0, 0, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v9 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v11
; GFX10-NEXT: v_cndmask_b32_e64 v11, v12, v11, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, -1, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v2
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v12, v9, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v10, v7, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v12, v14, v13, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v10, s0, v8, s8 ; GFX10-NEXT: v_sub_co_u32 v13, vcc_lo, v10, s8
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v6, s0, 0, v6, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v7 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v12
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v9
; GFX10-NEXT: v_cndmask_b32_e32 v7, v8, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc_lo
; GFX10-NEXT: s_xor_b64 s[8:9], s[2:3], s[12:13] ; GFX10-NEXT: s_xor_b64 s[8:9], s[2:3], s[12:13]
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v7, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v13, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v8, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v3, s1
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s1
; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v6, s1
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v7, s1
; GFX10-NEXT: v_mov_b32_e32 v4, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: v_xor_b32_e32 v0, s8, v0 ; GFX10-NEXT: v_xor_b32_e32 v0, s8, v0
; GFX10-NEXT: v_xor_b32_e32 v1, s9, v1 ; GFX10-NEXT: v_xor_b32_e32 v1, s9, v1
; GFX10-NEXT: v_xor_b32_e32 v3, s2, v3 ; GFX10-NEXT: v_xor_b32_e32 v3, s2, v3
; GFX10-NEXT: v_xor_b32_e32 v5, s2, v2 ; GFX10-NEXT: v_xor_b32_e32 v5, s2, v2
; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, v0, s8 ; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, v0, s8
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v3, s2 ; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v3, s2
▲ Show 20 Lines • Show All 701 Lines • ▼ Show 20 Lines
; GFX8-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13] ; GFX8-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13]
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX8-NEXT: s_mov_b32 s7, s6 ; GFX8-NEXT: s_mov_b32 s7, s6
; GFX8-NEXT: s_xor_b64 s[14:15], s[14:15], s[6:7] ; GFX8-NEXT: s_xor_b64 s[14:15], s[14:15], s[6:7]
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_sub_u32 s16, 0, s8 ; GFX8-NEXT: s_sub_u32 s0, 0, s8
; GFX8-NEXT: s_cselect_b32 s0, 1, 0 ; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s0, s0, 1 ; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX8-NEXT: v_trunc_f32_e32 v1, v1 ; GFX8-NEXT: v_trunc_f32_e32 v1, v1
; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX8-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX8-NEXT: v_add_f32_e32 v0, v2, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_cmp_lg_u32 s0, 0 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_subb_u32 s17, 0, s9 ; GFX8-NEXT: s_subb_u32 s1, 0, s9
; GFX8-NEXT: v_mul_lo_u32 v2, s16, v1 ; GFX8-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX8-NEXT: v_mul_lo_u32 v3, s17, v0 ; GFX8-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX8-NEXT: v_mul_hi_u32 v5, s16, v0 ; GFX8-NEXT: v_mul_hi_u32 v5, s0, v0
; GFX8-NEXT: v_mul_lo_u32 v4, s16, v0 ; GFX8-NEXT: v_mul_lo_u32 v4, s0, v0
; GFX8-NEXT: v_mov_b32_e32 v6, s9
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4 ; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4
; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v6, v0, v4
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v6
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3
; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v6, v4
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v6, v5
; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX8-NEXT: v_mul_hi_u32 v5, s0, v0
; GFX8-NEXT: v_mul_lo_u32 v4, s0, v0
; GFX8-NEXT: v_mov_b32_e32 v6, s9
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4
; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v7, v0, v4 ; GFX8-NEXT: v_mul_hi_u32 v7, v0, v4
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v7 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v7
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v7, v1, v2 ; GFX8-NEXT: v_mul_lo_u32 v7, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3
; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2 ; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v5 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v5
; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_addc_u32_e64 v3, s[0:1], v1, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX8-NEXT: v_mul_lo_u32 v4, s17, v0
; GFX8-NEXT: v_mul_lo_u32 v5, s16, v3
; GFX8-NEXT: v_mul_hi_u32 v8, s16, v0
; GFX8-NEXT: v_mul_lo_u32 v7, s16, v0
; GFX8-NEXT: v_add_u32_e64 v1, s[0:1], v1, v2
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], v4, v5
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], v4, v8
; GFX8-NEXT: v_mul_lo_u32 v5, v3, v7
; GFX8-NEXT: v_mul_lo_u32 v8, v0, v4
; GFX8-NEXT: v_mul_hi_u32 v2, v0, v7
; GFX8-NEXT: v_mul_hi_u32 v7, v3, v7
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v8
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], v5, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX8-NEXT: v_mul_lo_u32 v5, v3, v4
; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], v8, v2
; GFX8-NEXT: v_mul_hi_u32 v8, v0, v4
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v7
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v8
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v7, s[0:1], v7, v8
; GFX8-NEXT: v_mul_hi_u32 v3, v3, v4
; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], v5, v2
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], v7, v5
; GFX8-NEXT: v_add_u32_e64 v3, s[0:1], v3, v4
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, s15, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s15, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s14, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s14, v1
; GFX8-NEXT: v_mul_hi_u32 v5, s14, v0 ; GFX8-NEXT: v_mul_hi_u32 v5, s14, v0
; GFX8-NEXT: v_mul_hi_u32 v0, s15, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s15, v0
; GFX8-NEXT: v_mov_b32_e32 v4, s15 ; GFX8-NEXT: v_mov_b32_e32 v4, s15
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
Show All 40 Lines
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s8, v7 ; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s8, v7
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v12, s[0:1], 1, v9 ; GFX8-NEXT: v_add_u32_e64 v12, s[0:1], 1, v9
; GFX8-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
; GFX8-NEXT: v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1] ; GFX8-NEXT: v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1]
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc ; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11
; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v10, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[0:1]
; GFX8-NEXT: s_xor_b64 s[0:1], s[6:7], s[12:13] ; GFX8-NEXT: s_xor_b64 s[0:1], s[6:7], s[12:13]
; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX8-NEXT: s_ashr_i32 s8, s11, 31 ; GFX8-NEXT: s_ashr_i32 s8, s11, 31
; GFX8-NEXT: s_ashr_i32 s12, s3, 31 ; GFX8-NEXT: s_ashr_i32 s12, s3, 31
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: s_add_u32 s0, s10, s8 ; GFX8-NEXT: s_add_u32 s0, s10, s8
; GFX8-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX8-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX8-NEXT: v_mov_b32_e32 v4, s1 ; GFX8-NEXT: v_mov_b32_e32 v4, s1
; GFX8-NEXT: s_cselect_b32 s1, 1, 0 ; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_addc_u32 s1, s11, s8 ; GFX8-NEXT: s_addc_u32 s1, s11, s8
; GFX8-NEXT: s_add_u32 s2, s2, s12 ; GFX8-NEXT: s_add_u32 s2, s2, s12
; GFX8-NEXT: s_cselect_b32 s7, 1, 0 ; GFX8-NEXT: s_cselect_b32 s7, 1, 0
; GFX8-NEXT: s_and_b32 s7, s7, 1 ; GFX8-NEXT: s_and_b32 s7, s7, 1
; GFX8-NEXT: s_cmp_lg_u32 s7, 0 ; GFX8-NEXT: s_cmp_lg_u32 s7, 0
; GFX8-NEXT: s_mov_b32 s13, s12 ; GFX8-NEXT: s_mov_b32 s13, s12
; GFX8-NEXT: s_addc_u32 s3, s3, s12 ; GFX8-NEXT: s_addc_u32 s3, s3, s12
; GFX8-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13] ; GFX8-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13]
; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; GFX8-NEXT: v_cvt_f32_u32_e32 v4, s3 ; GFX8-NEXT: v_cvt_f32_u32_e32 v4, s3
; GFX8-NEXT: v_cvt_f32_u32_e32 v5, s2 ; GFX8-NEXT: v_cvt_f32_u32_e32 v5, s2
; GFX8-NEXT: v_xor_b32_e32 v3, s6, v3 ; GFX8-NEXT: s_mov_b32 s9, s8
; GFX8-NEXT: v_xor_b32_e32 v2, s6, v2 ; GFX8-NEXT: s_xor_b64 s[10:11], s[0:1], s[8:9]
; GFX8-NEXT: v_mul_f32_e32 v4, 0x4f800000, v4 ; GFX8-NEXT: v_mul_f32_e32 v4, 0x4f800000, v4
; GFX8-NEXT: v_add_f32_e32 v4, v4, v5 ; GFX8-NEXT: v_add_f32_e32 v4, v4, v5
; GFX8-NEXT: v_rcp_iflag_f32_e32 v7, v4 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GFX8-NEXT: v_mov_b32_e32 v6, s6 ; GFX8-NEXT: s_sub_u32 s0, 0, s2
; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; GFX8-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4
; GFX8-NEXT: v_trunc_f32_e32 v6, v6
; GFX8-NEXT: v_mul_f32_e32 v7, 0xcf800000, v6
; GFX8-NEXT: v_add_f32_e32 v4, v7, v4
; GFX8-NEXT: v_cvt_u32_f32_e32 v7, v4
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_subb_u32 s1, 0, s3
; GFX8-NEXT: v_mul_lo_u32 v4, s1, v7
; GFX8-NEXT: v_mul_lo_u32 v8, s0, v6
; GFX8-NEXT: v_mul_hi_u32 v10, s0, v7
; GFX8-NEXT: v_mul_lo_u32 v9, s0, v7
; GFX8-NEXT: v_xor_b32_e32 v3, s6, v3
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v8
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v4, v10
; GFX8-NEXT: v_xor_b32_e32 v2, s6, v2
; GFX8-NEXT: v_mov_b32_e32 v5, s6
; GFX8-NEXT: v_mul_lo_u32 v10, v6, v9
; GFX8-NEXT: v_mul_lo_u32 v11, v7, v8
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s6, v3 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s6, v3
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v2, v6, vcc ; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v2, v5, vcc
; GFX8-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v7 ; GFX8-NEXT: v_mul_hi_u32 v2, v7, v9
; GFX8-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v10, v11
; GFX8-NEXT: s_mov_b32 s9, s8 ; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX8-NEXT: v_trunc_f32_e32 v3, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: s_xor_b64 s[6:7], s[0:1], s[8:9] ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_mul_f32_e32 v6, 0xcf800000, v3 ; GFX8-NEXT: v_mul_lo_u32 v3, v6, v8
; GFX8-NEXT: v_add_f32_e32 v2, v6, v2 ; GFX8-NEXT: v_mul_hi_u32 v9, v6, v9
; GFX8-NEXT: s_sub_u32 s10, 0, s2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v10, v2
; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX8-NEXT: v_mul_hi_u32 v10, v7, v8
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v9
; GFX8-NEXT: s_cselect_b32 s0, 1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX8-NEXT: s_and_b32 s0, s0, 1 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v10
; GFX8-NEXT: s_cmp_lg_u32 s0, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX8-NEXT: s_subb_u32 s11, 0, s3 ; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v10
; GFX8-NEXT: v_mul_lo_u32 v6, s11, v2 ; GFX8-NEXT: v_mul_hi_u32 v8, v6, v8
; GFX8-NEXT: v_mul_lo_u32 v7, s10, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_mul_hi_u32 v9, s10, v2 ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v8, s10, v2 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v9, v3
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v8, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v7, v2
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, s1, v2
; GFX8-NEXT: v_mul_lo_u32 v7, s0, v3
; GFX8-NEXT: v_mul_hi_u32 v9, s0, v2
; GFX8-NEXT: v_mul_lo_u32 v8, s0, v2
; GFX8-NEXT: v_mov_b32_e32 v10, s3 ; GFX8-NEXT: v_mov_b32_e32 v10, s3
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9
; GFX8-NEXT: v_mul_lo_u32 v7, v3, v8 ; GFX8-NEXT: v_mul_lo_u32 v7, v3, v8
; GFX8-NEXT: v_mul_lo_u32 v9, v2, v6 ; GFX8-NEXT: v_mul_lo_u32 v9, v2, v6
; GFX8-NEXT: v_mul_hi_u32 v11, v2, v8 ; GFX8-NEXT: v_mul_hi_u32 v11, v2, v8
; GFX8-NEXT: v_mul_hi_u32 v8, v3, v8 ; GFX8-NEXT: v_mul_hi_u32 v8, v3, v8
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v11 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v11
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v11, v3, v6 ; GFX8-NEXT: v_mul_lo_u32 v11, v3, v6
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v9, v7 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v9, v7
; GFX8-NEXT: v_mul_hi_u32 v9, v2, v6 ; GFX8-NEXT: v_mul_hi_u32 v9, v2, v6
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v11, v8 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v11, v8
; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v9 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v9
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v11, v9 ; GFX8-NEXT: v_add_u32_e32 v9, vcc, v11, v9
; GFX8-NEXT: v_mul_hi_u32 v6, v3, v6 ; GFX8-NEXT: v_mul_hi_u32 v6, v3, v6
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v9, v8 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v9, v8
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7
; GFX8-NEXT: v_addc_u32_e64 v7, s[0:1], v3, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc
; GFX8-NEXT: v_mul_lo_u32 v8, s11, v2 ; GFX8-NEXT: v_mul_lo_u32 v6, s11, v2
; GFX8-NEXT: v_mul_lo_u32 v9, s10, v7 ; GFX8-NEXT: v_mul_lo_u32 v7, s10, v3
; GFX8-NEXT: v_mul_hi_u32 v12, s10, v2 ; GFX8-NEXT: v_mul_hi_u32 v9, s10, v2
; GFX8-NEXT: v_mul_lo_u32 v11, s10, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, s11, v2
; GFX8-NEXT: v_add_u32_e64 v3, s[0:1], v3, v6 ; GFX8-NEXT: v_mov_b32_e32 v8, s11
; GFX8-NEXT: v_add_u32_e64 v8, s[0:1], v8, v9
; GFX8-NEXT: v_add_u32_e64 v8, s[0:1], v8, v12
; GFX8-NEXT: v_mul_lo_u32 v9, v7, v11
; GFX8-NEXT: v_mul_lo_u32 v12, v2, v8
; GFX8-NEXT: v_mul_hi_u32 v6, v2, v11
; GFX8-NEXT: v_mul_hi_u32 v11, v7, v11
; GFX8-NEXT: v_add_u32_e64 v9, s[0:1], v9, v12
; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v6, s[0:1], v9, v6
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1]
; GFX8-NEXT: v_mul_lo_u32 v9, v7, v8
; GFX8-NEXT: v_add_u32_e64 v6, s[0:1], v12, v6
; GFX8-NEXT: v_mul_hi_u32 v12, v2, v8
; GFX8-NEXT: v_add_u32_e64 v9, s[0:1], v9, v11
; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v9, s[0:1], v9, v12
; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v11, s[0:1], v11, v12
; GFX8-NEXT: v_mul_hi_u32 v7, v7, v8
; GFX8-NEXT: v_add_u32_e64 v6, s[0:1], v9, v6
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v8, s[0:1], v11, v9
; GFX8-NEXT: v_add_u32_e64 v7, s[0:1], v7, v8
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, s7, v2
; GFX8-NEXT: v_mul_lo_u32 v7, s6, v3
; GFX8-NEXT: v_mul_hi_u32 v9, s6, v2
; GFX8-NEXT: v_mul_hi_u32 v2, s7, v2
; GFX8-NEXT: v_mov_b32_e32 v8, s7
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v9, s7, v3 ; GFX8-NEXT: v_mul_lo_u32 v9, s11, v3
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6
; GFX8-NEXT: v_mul_hi_u32 v7, s6, v3 ; GFX8-NEXT: v_mul_hi_u32 v7, s10, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v9, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v9, v2
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v9, v7 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v9, v7
; GFX8-NEXT: v_mul_hi_u32 v3, s7, v3 ; GFX8-NEXT: v_mul_hi_u32 v3, s11, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v7, v6
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v6 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v6
; GFX8-NEXT: v_mul_lo_u32 v6, s3, v2 ; GFX8-NEXT: v_mul_lo_u32 v6, s3, v2
; GFX8-NEXT: v_mul_lo_u32 v7, s2, v3 ; GFX8-NEXT: v_mul_lo_u32 v7, s2, v3
; GFX8-NEXT: v_mul_hi_u32 v11, s2, v2 ; GFX8-NEXT: v_mul_hi_u32 v11, s2, v2
; GFX8-NEXT: v_mul_lo_u32 v9, s2, v2 ; GFX8-NEXT: v_mul_lo_u32 v9, s2, v2
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v11 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v11
; GFX8-NEXT: v_sub_u32_e32 v7, vcc, s6, v9 ; GFX8-NEXT: v_sub_u32_e32 v7, vcc, s10, v9
; GFX8-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v6, vcc ; GFX8-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v6, vcc
; GFX8-NEXT: v_sub_u32_e64 v6, s[0:1], s7, v6 ; GFX8-NEXT: v_sub_u32_e64 v6, s[0:1], s11, v6
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v8 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v8
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v7 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v7
; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v8 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v8
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v10, vcc ; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[0:1]
; GFX8-NEXT: v_subrev_u32_e32 v11, vcc, s2, v7 ; GFX8-NEXT: v_subrev_u32_e32 v11, vcc, s2, v7
Show All 12 Lines
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; GFX8-NEXT: v_subrev_u32_e64 v13, s[0:1], s2, v11 ; GFX8-NEXT: v_subrev_u32_e64 v13, s[0:1], s2, v11
; GFX8-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1] ; GFX8-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9
; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v6, v12, v6, vcc
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v6, v8, v6, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v6, v8, v6, s[0:1]
; GFX8-NEXT: s_xor_b64 s[0:1], s[8:9], s[12:13] ; GFX8-NEXT: s_xor_b64 s[0:1], s[8:9], s[12:13]
; GFX8-NEXT: v_xor_b32_e32 v2, s0, v2 ; GFX8-NEXT: v_xor_b32_e32 v2, s0, v2
; GFX8-NEXT: v_xor_b32_e32 v3, s1, v3 ; GFX8-NEXT: v_xor_b32_e32 v3, s1, v3
; GFX8-NEXT: v_mov_b32_e32 v8, s1 ; GFX8-NEXT: v_mov_b32_e32 v8, s1
Show All 35 Lines
; GFX9-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13] ; GFX9-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX9-NEXT: s_mov_b32 s7, s6 ; GFX9-NEXT: s_mov_b32 s7, s6
; GFX9-NEXT: s_xor_b64 s[14:15], s[14:15], s[6:7] ; GFX9-NEXT: s_xor_b64 s[14:15], s[14:15], s[6:7]
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_sub_u32 s16, 0, s8 ; GFX9-NEXT: s_sub_u32 s0, 0, s8
; GFX9-NEXT: s_cselect_b32 s0, 1, 0 ; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX9-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v2, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_subb_u32 s17, 0, s9 ; GFX9-NEXT: s_subb_u32 s1, 0, s9
; GFX9-NEXT: v_mul_lo_u32 v2, s16, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX9-NEXT: v_mul_lo_u32 v3, s17, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s16, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s16, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: v_mov_b32_e32 v7, s15
; GFX9-NEXT: v_add3_u32 v2, v3, v2, v4 ; GFX9-NEXT: v_add3_u32 v2, v3, v2, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, v1, v2
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_mul_hi_u32 v4, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2 ; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[0:1], v1, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s17, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s16, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s16, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX9-NEXT: v_mul_lo_u32 v7, s16, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: v_add_u32_e32 v1, v1, v2 ; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4
; GFX9-NEXT: v_add3_u32 v4, v4, v5, v6 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v5, v3, v7 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v7 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v3, v7 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v6 ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1] ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v5, v2 ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX9-NEXT: v_mul_lo_u32 v6, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v5, v3, v4 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_add_u32_e32 v2, v6, v2 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v6, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX9-NEXT: v_mul_hi_u32 v3, v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v7 ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1] ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v6 ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1] ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v5, v2 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
; GFX9-NEXT: v_add_u32_e32 v6, v7, v6 ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1] ; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX9-NEXT: v_add3_u32 v3, v6, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, s15, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s15, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s14, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s14, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s14, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s14, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s15, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s15, v0
; GFX9-NEXT: v_mov_b32_e32 v7, s15 ; GFX9-NEXT: v_mov_b32_e32 v5, s9
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s15, v1 ; GFX9-NEXT: v_mul_lo_u32 v4, s15, v1
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_mul_hi_u32 v3, s14, v1 ; GFX9-NEXT: v_mul_hi_u32 v3, s14, v1
; GFX9-NEXT: v_mul_hi_u32 v1, s15, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s15, v1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v1, v3, v2, v1 ; GFX9-NEXT: v_add3_u32 v1, v3, v2, v1
; GFX9-NEXT: v_mul_lo_u32 v2, s9, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s9, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s8, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s8, v0
; GFX9-NEXT: v_mul_lo_u32 v6, s8, v0 ; GFX9-NEXT: v_mul_lo_u32 v6, s8, v0
; GFX9-NEXT: v_mov_b32_e32 v5, s9
; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4 ; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4
; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s14, v6 ; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s14, v6
; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v7, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v7, v2, vcc
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4
; GFX9-NEXT: v_sub_u32_e32 v2, s15, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, s15, v2
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[0:1]
; GFX9-NEXT: v_subrev_co_u32_e32 v7, vcc, s8, v3 ; GFX9-NEXT: v_subrev_co_u32_e32 v7, vcc, s8, v3
; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[0:1], 0, v2, vcc ; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[0:1], 0, v2, vcc
; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], 1, v0 ; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], 1, v0
; GFX9-NEXT: v_addc_co_u32_e64 v10, s[0:1], 0, v1, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v10, s[0:1], 0, v1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v8 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v8
; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v7 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v7
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v8 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v8
; GFX9-NEXT: v_subrev_co_u32_e32 v5, vcc, s8, v7
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v12, s[0:1], 1, v9 ; GFX9-NEXT: v_add_co_u32_e64 v12, s[0:1], 1, v9
; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v13, s[0:1], 0, v10, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[0:1], 0, v10, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; GFX9-NEXT: v_subrev_co_u32_e32 v5, vcc, s8, v7
; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 ; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v5, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v10, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[0:1]
; GFX9-NEXT: s_xor_b64 s[0:1], s[6:7], s[12:13] ; GFX9-NEXT: s_xor_b64 s[0:1], s[6:7], s[12:13]
; GFX9-NEXT: s_ashr_i32 s8, s11, 31 ; GFX9-NEXT: s_ashr_i32 s8, s11, 31
; GFX9-NEXT: s_ashr_i32 s12, s3, 31 ; GFX9-NEXT: s_ashr_i32 s12, s3, 31
; GFX9-NEXT: s_add_u32 s10, s10, s8 ; GFX9-NEXT: s_add_u32 s10, s10, s8
; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0
; GFX9-NEXT: s_and_b32 s7, s7, 1 ; GFX9-NEXT: s_and_b32 s7, s7, 1
; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0
; GFX9-NEXT: s_addc_u32 s11, s11, s8 ; GFX9-NEXT: s_addc_u32 s11, s11, s8
; GFX9-NEXT: s_add_u32 s2, s2, s12 ; GFX9-NEXT: s_add_u32 s2, s2, s12
; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0
; GFX9-NEXT: s_and_b32 s7, s7, 1 ; GFX9-NEXT: s_and_b32 s7, s7, 1
; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0
; GFX9-NEXT: s_mov_b32 s13, s12 ; GFX9-NEXT: s_mov_b32 s13, s12
; GFX9-NEXT: s_addc_u32 s3, s3, s12 ; GFX9-NEXT: s_addc_u32 s3, s3, s12
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13] ; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13]
; GFX9-NEXT: v_cvt_f32_u32_e32 v4, s3 ; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s2 ; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s3
; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: v_mul_f32_e32 v4, 0x4f800000, v6
; GFX9-NEXT: v_add_f32_e32 v4, v4, v7
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GFX9-NEXT: s_mov_b32 s9, s8 ; GFX9-NEXT: s_mov_b32 s9, s8
; GFX9-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9] ; GFX9-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9]
; GFX9-NEXT: v_mul_f32_e32 v4, 0x4f800000, v4
; GFX9-NEXT: v_add_f32_e32 v4, v4, v5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GFX9-NEXT: s_sub_u32 s7, 0, s2 ; GFX9-NEXT: s_sub_u32 s7, 0, s2
; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; GFX9-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 ; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
; GFX9-NEXT: v_trunc_f32_e32 v6, v6 ; GFX9-NEXT: v_trunc_f32_e32 v5, v5
; GFX9-NEXT: v_mul_f32_e32 v7, 0xcf800000, v6 ; GFX9-NEXT: v_mul_f32_e32 v6, 0xcf800000, v5
; GFX9-NEXT: v_add_f32_e32 v4, v7, v4 ; GFX9-NEXT: v_add_f32_e32 v4, v6, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX9-NEXT: s_cselect_b32 s1, 1, 0 ; GFX9-NEXT: s_cselect_b32 s14, 1, 0
; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_and_b32 s14, s14, 1
; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_cmp_lg_u32 s14, 0
; GFX9-NEXT: s_subb_u32 s14, 0, s3 ; GFX9-NEXT: s_subb_u32 s14, 0, s3
; GFX9-NEXT: v_mul_lo_u32 v8, s14, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, s14, v4
; GFX9-NEXT: v_mul_lo_u32 v9, s7, v6 ; GFX9-NEXT: v_mul_lo_u32 v7, s7, v5
; GFX9-NEXT: v_mul_hi_u32 v10, s7, v4 ; GFX9-NEXT: v_mul_hi_u32 v8, s7, v4
; GFX9-NEXT: v_mul_lo_u32 v7, s7, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX9-NEXT: v_mul_lo_u32 v9, s7, v4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8
; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX9-NEXT: v_mov_b32_e32 v10, s1
; GFX9-NEXT: v_mul_lo_u32 v7, v5, v9
; GFX9-NEXT: v_mul_lo_u32 v8, v4, v6
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v10, vcc
; GFX9-NEXT: v_add3_u32 v5, v8, v9, v10 ; GFX9-NEXT: v_mul_hi_u32 v10, v4, v9
; GFX9-NEXT: v_mul_lo_u32 v8, v6, v7 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8
; GFX9-NEXT: v_mul_lo_u32 v9, v4, v5
; GFX9-NEXT: v_mul_hi_u32 v10, v4, v7
; GFX9-NEXT: v_mul_hi_u32 v7, v6, v7
; GFX9-NEXT: v_xor_b32_e32 v3, s6, v3
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v9
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v6, v5 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v10
; GFX9-NEXT: v_add_u32_e32 v8, v9, v8 ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-NEXT: v_mul_hi_u32 v9, v4, v5 ; GFX9-NEXT: v_mul_lo_u32 v10, v5, v6
; GFX9-NEXT: v_mul_hi_u32 v5, v6, v5 ; GFX9-NEXT: v_mul_hi_u32 v9, v5, v9
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v10, v7 ; GFX9-NEXT: v_add_u32_e32 v7, v8, v7
; GFX9-NEXT: v_mul_hi_u32 v8, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
; GFX9-NEXT: v_add_u32_e32 v9, v10, v9 ; GFX9-NEXT: v_add_u32_e32 v9, v10, v9
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v5, v9, v8, v5 ; GFX9-NEXT: v_add3_u32 v6, v9, v8, v6
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v7 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v7
; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v6, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, s14, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, s14, v4
; GFX9-NEXT: v_mul_lo_u32 v9, s7, v7 ; GFX9-NEXT: v_mul_lo_u32 v7, s7, v5
; GFX9-NEXT: v_mul_hi_u32 v10, s7, v4 ; GFX9-NEXT: v_mul_hi_u32 v8, s7, v4
; GFX9-NEXT: v_mul_lo_u32 v11, s7, v4 ; GFX9-NEXT: v_mul_lo_u32 v9, s7, v4
; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX9-NEXT: v_xor_b32_e32 v3, s6, v3
; GFX9-NEXT: v_xor_b32_e32 v2, s6, v2 ; GFX9-NEXT: v_xor_b32_e32 v2, s6, v2
; GFX9-NEXT: v_add3_u32 v8, v8, v9, v10 ; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8
; GFX9-NEXT: v_mul_lo_u32 v9, v7, v11 ; GFX9-NEXT: v_mul_lo_u32 v7, v5, v9
; GFX9-NEXT: v_mul_lo_u32 v10, v4, v8 ; GFX9-NEXT: v_mul_lo_u32 v8, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v6, v4, v11 ; GFX9-NEXT: v_mul_hi_u32 v11, v4, v9
; GFX9-NEXT: v_mul_hi_u32 v11, v7, v11 ; GFX9-NEXT: v_mul_hi_u32 v9, v5, v9
; GFX9-NEXT: v_mov_b32_e32 v12, s6 ; GFX9-NEXT: v_mov_b32_e32 v10, s6
; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], v9, v10 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8
; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], v9, v6 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v11
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v9, v7, v8 ; GFX9-NEXT: v_mul_lo_u32 v11, v5, v6
; GFX9-NEXT: v_add_u32_e32 v6, v10, v6 ; GFX9-NEXT: v_add_u32_e32 v7, v8, v7
; GFX9-NEXT: v_mul_hi_u32 v10, v4, v8 ; GFX9-NEXT: v_mul_hi_u32 v8, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v7, v7, v8 ; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], v9, v11 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v11, v9
; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], v9, v10 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], v9, v6 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
; GFX9-NEXT: v_add_u32_e32 v10, v11, v10 ; GFX9-NEXT: v_add_u32_e32 v9, v11, v9
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v7, v10, v8, v7 ; GFX9-NEXT: v_add3_u32 v6, v9, v8, v6
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v4, v7
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v4, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v5, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v5, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, s11, v7
; GFX9-NEXT: v_mul_lo_u32 v8, s11, v6 ; GFX9-NEXT: v_mul_lo_u32 v9, s10, v6
; GFX9-NEXT: v_mul_lo_u32 v9, s10, v7
; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s6, v3 ; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s6, v3
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v2, v12, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v2, v10, vcc
; GFX9-NEXT: v_mul_hi_u32 v2, s10, v6 ; GFX9-NEXT: v_mul_hi_u32 v2, s10, v7
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v9 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v9
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, s11, v7 ; GFX9-NEXT: v_mul_lo_u32 v3, s11, v6
; GFX9-NEXT: v_mul_hi_u32 v6, s11, v6
; GFX9-NEXT: v_add_u32_e32 v2, v8, v2
; GFX9-NEXT: v_mul_hi_u32 v8, s10, v7
; GFX9-NEXT: v_mul_hi_u32 v7, s11, v7 ; GFX9-NEXT: v_mul_hi_u32 v7, s11, v7
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 ; GFX9-NEXT: v_add_u32_e32 v2, v8, v2
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_mul_hi_u32 v8, s10, v6
; GFX9-NEXT: v_mul_hi_u32 v6, s11, v6
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8 ; GFX9-NEXT: v_add_u32_e32 v7, v7, v8
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v3, v6, v3, v7 ; GFX9-NEXT: v_add3_u32 v3, v7, v3, v6
; GFX9-NEXT: v_mul_lo_u32 v6, s3, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, s3, v2
; GFX9-NEXT: v_mul_lo_u32 v7, s2, v3 ; GFX9-NEXT: v_mul_lo_u32 v7, s2, v3
; GFX9-NEXT: v_mul_hi_u32 v8, s2, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, s2, v2
; GFX9-NEXT: v_mul_lo_u32 v10, s2, v2 ; GFX9-NEXT: v_mul_lo_u32 v10, s2, v2
; GFX9-NEXT: v_mov_b32_e32 v11, s11 ; GFX9-NEXT: v_mov_b32_e32 v11, s11
; GFX9-NEXT: v_mov_b32_e32 v9, s3 ; GFX9-NEXT: v_mov_b32_e32 v9, s3
; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8 ; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8
; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, s10, v10 ; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, s10, v10
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0
; GFX10-NEXT: s_addc_u32 s15, s9, s12 ; GFX10-NEXT: s_addc_u32 s15, s9, s12
; GFX10-NEXT: s_add_u32 s0, s0, s6 ; GFX10-NEXT: s_add_u32 s0, s0, s6
; GFX10-NEXT: s_cselect_b32 s7, 1, 0 ; GFX10-NEXT: s_cselect_b32 s7, 1, 0
; GFX10-NEXT: s_and_b32 s8, s7, 1 ; GFX10-NEXT: s_and_b32 s8, s7, 1
; GFX10-NEXT: s_mov_b32 s7, s6 ; GFX10-NEXT: s_mov_b32 s7, s6
; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0
; GFX10-NEXT: s_addc_u32 s1, s1, s6 ; GFX10-NEXT: s_addc_u32 s1, s1, s6
; GFX10-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13]
; GFX10-NEXT: s_xor_b64 s[8:9], s[0:1], s[6:7] ; GFX10-NEXT: s_xor_b64 s[8:9], s[0:1], s[6:7]
; GFX10-NEXT: s_xor_b64 s[0:1], s[14:15], s[12:13]
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX10-NEXT: s_sub_u32 s22, 0, s8 ; GFX10-NEXT: s_sub_u32 s20, 0, s8
; GFX10-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10-NEXT: s_cselect_b32 s14, 1, 0
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_and_b32 s14, s14, 1
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
; GFX10-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-NEXT: s_cmp_lg_u32 s14, 0
; GFX10-NEXT: s_subb_u32 s23, 0, s9 ; GFX10-NEXT: s_subb_u32 s21, 0, s9
; GFX10-NEXT: s_ashr_i32 s16, s11, 31 ; GFX10-NEXT: s_ashr_i32 s14, s11, 31
; GFX10-NEXT: s_xor_b64 s[20:21], s[12:13], s[6:7] ; GFX10-NEXT: s_xor_b64 s[18:19], s[12:13], s[6:7]
; GFX10-NEXT: s_ashr_i32 s18, s3, 31 ; GFX10-NEXT: s_ashr_i32 s16, s3, 31
; GFX10-NEXT: v_add_f32_e32 v0, v1, v0 ; GFX10-NEXT: v_add_f32_e32 v0, v1, v0
; GFX10-NEXT: s_add_u32 s0, s10, s16 ; GFX10-NEXT: s_add_u32 s6, s10, s14
; GFX10-NEXT: s_cselect_b32 s1, 1, 0 ; GFX10-NEXT: s_cselect_b32 s7, 1, 0
; GFX10-NEXT: s_mov_b32 s19, s18
; GFX10-NEXT: s_and_b32 s1, s1, 1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: s_mov_b32 s17, s16 ; GFX10-NEXT: s_mov_b32 s17, s16
; GFX10-NEXT: s_addc_u32 s1, s11, s16 ; GFX10-NEXT: s_and_b32 s7, s7, 1
; GFX10-NEXT: s_add_u32 s2, s2, s18 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0
; GFX10-NEXT: s_and_b32 s6, s6, 1 ; GFX10-NEXT: s_mov_b32 s15, s14
; GFX10-NEXT: s_cmp_lg_u32 s6, 0 ; GFX10-NEXT: s_addc_u32 s7, s11, s14
; GFX10-NEXT: s_add_u32 s2, s2, s16
; GFX10-NEXT: s_cselect_b32 s10, 1, 0
; GFX10-NEXT: s_and_b32 s10, s10, 1
; GFX10-NEXT: s_cmp_lg_u32 s10, 0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: s_addc_u32 s3, s3, s18 ; GFX10-NEXT: s_addc_u32 s3, s3, s16
; GFX10-NEXT: s_xor_b64 s[10:11], s[0:1], s[16:17] ; GFX10-NEXT: s_xor_b64 s[10:11], s[6:7], s[14:15]
; GFX10-NEXT: s_xor_b64 s[2:3], s[2:3], s[18:19] ; GFX10-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17]
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s3 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s3
; GFX10-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s2 ; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s2
; GFX10-NEXT: s_sub_u32 s6, 0, s2 ; GFX10-NEXT: s_sub_u32 s6, 0, s2
; GFX10-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10-NEXT: s_cselect_b32 s7, 1, 0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1
; GFX10-NEXT: v_trunc_f32_e32 v2, v2 ; GFX10-NEXT: v_trunc_f32_e32 v2, v2
; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_and_b32 s7, s7, 1
; GFX10-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0
; GFX10-NEXT: v_add_f32_e32 v1, v1, v3 ; GFX10-NEXT: v_add_f32_e32 v1, v1, v3
; GFX10-NEXT: v_mul_f32_e32 v3, 0xcf800000, v2 ; GFX10-NEXT: v_mul_f32_e32 v3, 0xcf800000, v2
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX10-NEXT: s_subb_u32 s7, 0, s3 ; GFX10-NEXT: s_subb_u32 s7, 0, s3
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: v_add_f32_e32 v0, v3, v0 ; GFX10-NEXT: v_add_f32_e32 v0, v3, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s22, v2 ; GFX10-NEXT: v_mul_lo_u32 v3, s20, v2
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
; GFX10-NEXT: v_mul_lo_u32 v4, s23, v0 ; GFX10-NEXT: v_mul_lo_u32 v4, s21, v0
; GFX10-NEXT: v_mul_hi_u32 v5, s22, v0 ; GFX10-NEXT: v_mul_hi_u32 v5, s20, v0
; GFX10-NEXT: v_mul_lo_u32 v6, s22, v0 ; GFX10-NEXT: v_mul_lo_u32 v6, s20, v0
; GFX10-NEXT: v_mul_f32_e32 v7, 0x2f800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v7, 0x2f800000, v1
; GFX10-NEXT: v_add3_u32 v3, v4, v3, v5 ; GFX10-NEXT: v_add3_u32 v3, v4, v3, v5
; GFX10-NEXT: v_trunc_f32_e32 v4, v7 ; GFX10-NEXT: v_trunc_f32_e32 v4, v7
; GFX10-NEXT: v_mul_lo_u32 v5, v2, v6 ; GFX10-NEXT: v_mul_lo_u32 v5, v2, v6
; GFX10-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX10-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX10-NEXT: v_mul_hi_u32 v6, v2, v6 ; GFX10-NEXT: v_mul_hi_u32 v6, v2, v6
; GFX10-NEXT: v_mul_lo_u32 v8, v0, v3 ; GFX10-NEXT: v_mul_lo_u32 v8, v0, v3
; GFX10-NEXT: v_mul_lo_u32 v10, v2, v3 ; GFX10-NEXT: v_mul_lo_u32 v10, v2, v3
; GFX10-NEXT: v_mul_f32_e32 v9, 0xcf800000, v4 ; GFX10-NEXT: v_mul_f32_e32 v9, 0xcf800000, v4
; GFX10-NEXT: v_mul_hi_u32 v11, v0, v3 ; GFX10-NEXT: v_mul_hi_u32 v11, v0, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX10-NEXT: v_cvt_u32_f32_e32 v4, v4
; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3 ; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3
; GFX10-NEXT: v_add_f32_e32 v1, v9, v1 ; GFX10-NEXT: v_add_f32_e32 v1, v9, v1
; GFX10-NEXT: v_add_co_u32 v5, s0, v5, v8 ; GFX10-NEXT: v_add_co_u32 v5, s13, v5, v8
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s13
; GFX10-NEXT: v_add_co_u32 v6, s0, v10, v6 ; GFX10-NEXT: v_add_co_u32 v6, s13, v10, v6
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s13
; GFX10-NEXT: v_add_co_u32 v5, s0, v5, v7 ; GFX10-NEXT: v_add_co_u32 v5, s13, v5, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s13
; GFX10-NEXT: v_mul_lo_u32 v9, s6, v4 ; GFX10-NEXT: v_mul_lo_u32 v9, s6, v4
; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v11 ; GFX10-NEXT: v_add_co_u32 v6, s13, v6, v11
; GFX10-NEXT: v_mul_lo_u32 v12, s7, v1 ; GFX10-NEXT: v_mul_lo_u32 v12, s7, v1
; GFX10-NEXT: v_mul_hi_u32 v13, s6, v1 ; GFX10-NEXT: v_mul_hi_u32 v13, s6, v1
; GFX10-NEXT: v_add_nc_u32_e32 v5, v8, v5 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v8, v5
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s13
; GFX10-NEXT: v_mul_lo_u32 v11, s6, v1 ; GFX10-NEXT: v_mul_lo_u32 v11, s6, v1
; GFX10-NEXT: v_add_co_u32 v5, s0, v6, v5 ; GFX10-NEXT: v_add_co_u32 v5, s13, v6, v5
; GFX10-NEXT: v_add_nc_u32_e32 v7, v10, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v7, v10, v7
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s13
; GFX10-NEXT: v_add3_u32 v8, v12, v9, v13 ; GFX10-NEXT: v_add3_u32 v8, v12, v9, v13
; GFX10-NEXT: v_mul_lo_u32 v9, v4, v11 ; GFX10-NEXT: v_mul_lo_u32 v9, v4, v11
; GFX10-NEXT: v_mul_hi_u32 v10, v1, v11 ; GFX10-NEXT: v_mul_hi_u32 v10, v1, v11
; GFX10-NEXT: v_mul_hi_u32 v11, v4, v11 ; GFX10-NEXT: v_mul_hi_u32 v11, v4, v11
; GFX10-NEXT: v_add3_u32 v3, v7, v6, v3 ; GFX10-NEXT: v_add3_u32 v3, v7, v6, v3
; GFX10-NEXT: v_mul_lo_u32 v6, v1, v8 ; GFX10-NEXT: v_mul_lo_u32 v6, v1, v8
; GFX10-NEXT: v_mul_lo_u32 v7, v4, v8 ; GFX10-NEXT: v_mul_lo_u32 v7, v4, v8
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v5 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v5
; GFX10-NEXT: v_add_co_ci_u32_e64 v12, s0, v2, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v3, vcc_lo
; GFX10-NEXT: v_mul_hi_u32 v5, v1, v8 ; GFX10-NEXT: v_mul_hi_u32 v5, v1, v8
; GFX10-NEXT: v_mul_lo_u32 v14, s23, v0 ; GFX10-NEXT: v_mul_lo_u32 v12, s21, v0
; GFX10-NEXT: v_add_co_u32 v6, s0, v9, v6 ; GFX10-NEXT: v_add_co_u32 v6, s13, v9, v6
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0 ; GFX10-NEXT: v_mul_hi_u32 v13, s20, v0
; GFX10-NEXT: v_add_co_u32 v7, s0, v7, v11 ; GFX10-NEXT: v_mul_lo_u32 v14, s20, v2
; GFX10-NEXT: v_mul_hi_u32 v15, s22, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s13
; GFX10-NEXT: v_mul_lo_u32 v16, s22, v12 ; GFX10-NEXT: v_add_co_u32 v7, s13, v7, v11
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s13
; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v10 ; GFX10-NEXT: v_add_co_u32 v6, s13, v6, v10
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 ; GFX10-NEXT: v_mul_lo_u32 v3, s20, v0
; GFX10-NEXT: v_mul_lo_u32 v13, s22, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s13
; GFX10-NEXT: v_add_co_u32 v5, s0, v7, v5 ; GFX10-NEXT: v_add_co_u32 v5, s13, v7, v5
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s13
; GFX10-NEXT: v_add3_u32 v12, v12, v14, v13
; GFX10-NEXT: v_add_nc_u32_e32 v6, v9, v6 ; GFX10-NEXT: v_add_nc_u32_e32 v6, v9, v6
; GFX10-NEXT: v_add3_u32 v14, v14, v16, v15
; GFX10-NEXT: v_mul_hi_u32 v8, v4, v8 ; GFX10-NEXT: v_mul_hi_u32 v8, v4, v8
; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v3 ; GFX10-NEXT: v_mul_lo_u32 v10, v2, v3
; GFX10-NEXT: v_mul_lo_u32 v10, v12, v13
; GFX10-NEXT: v_add_nc_u32_e32 v7, v11, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v7, v11, v7
; GFX10-NEXT: v_add_co_u32 v5, s0, v5, v6 ; GFX10-NEXT: v_mul_lo_u32 v11, v0, v12
; GFX10-NEXT: v_mul_lo_u32 v11, v0, v14 ; GFX10-NEXT: v_add_co_u32 v5, s13, v5, v6
; GFX10-NEXT: v_mul_hi_u32 v9, v0, v13 ; GFX10-NEXT: v_mul_hi_u32 v9, v0, v3
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s13
; GFX10-NEXT: v_mul_hi_u32 v13, v12, v13 ; GFX10-NEXT: v_mul_hi_u32 v3, v2, v3
; GFX10-NEXT: v_mul_lo_u32 v15, v12, v14 ; GFX10-NEXT: v_mul_lo_u32 v13, v2, v12
; GFX10-NEXT: v_add_co_u32 v1, s0, v1, v5 ; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v5
; GFX10-NEXT: v_add_co_u32 v5, s13, v10, v11
; GFX10-NEXT: v_mul_hi_u32 v14, v0, v12
; GFX10-NEXT: v_add3_u32 v6, v7, v6, v8 ; GFX10-NEXT: v_add3_u32 v6, v7, v6, v8
; GFX10-NEXT: v_add_co_u32 v5, s1, v10, v11 ; GFX10-NEXT: v_mul_lo_u32 v10, s7, v1
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s1 ; GFX10-NEXT: v_add_co_u32 v5, s7, v5, v9
; GFX10-NEXT: v_mul_hi_u32 v16, v0, v14 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s13
; GFX10-NEXT: v_add_co_u32 v8, s1, v15, v13 ; GFX10-NEXT: v_add_co_u32 v3, s13, v13, v3
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s7
; GFX10-NEXT: v_add_co_ci_u32_e64 v11, s1, v4, v6, s0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
; GFX10-NEXT: v_add_co_u32 v5, s1, v5, v9 ; GFX10-NEXT: v_add_co_u32 v3, s7, v3, v14
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v8, s1, v8, v16
; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, 1, s1
; GFX10-NEXT: v_mul_lo_u32 v13, s7, v1
; GFX10-NEXT: v_add_nc_u32_e32 v5, v7, v5 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v7, v5
; GFX10-NEXT: v_mul_hi_u32 v15, s6, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s13
; GFX10-NEXT: v_mul_lo_u32 v9, s6, v11 ; GFX10-NEXT: v_mul_hi_u32 v11, s6, v1
; GFX10-NEXT: v_mul_hi_u32 v7, v12, v14 ; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s7
; GFX10-NEXT: v_add_nc_u32_e32 v10, v10, v16 ; GFX10-NEXT: v_mul_lo_u32 v13, s6, v4
; GFX10-NEXT: v_add_co_u32 v5, s1, v8, v5 ; GFX10-NEXT: v_mul_hi_u32 v7, v2, v12
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1 ; GFX10-NEXT: v_mul_lo_u32 v6, s6, v1
; GFX10-NEXT: v_mul_lo_u32 v3, s6, v1 ; GFX10-NEXT: v_add_co_u32 v3, s6, v3, v5
; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v6 ; GFX10-NEXT: v_add_nc_u32_e32 v8, v8, v9
; GFX10-NEXT: v_add3_u32 v9, v13, v9, v15 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6
; GFX10-NEXT: v_add3_u32 v9, v10, v13, v11
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
; GFX10-NEXT: v_add3_u32 v5, v8, v5, v7
; GFX10-NEXT: v_mul_lo_u32 v10, v4, v6
; GFX10-NEXT: v_mul_lo_u32 v7, v1, v9
; GFX10-NEXT: v_mul_hi_u32 v11, v1, v6
; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v3, v4, v9
; GFX10-NEXT: v_mul_lo_u32 v5, s1, v0
; GFX10-NEXT: v_mul_hi_u32 v12, s0, v0
; GFX10-NEXT: v_mul_lo_u32 v13, s0, v2
; GFX10-NEXT: v_add_co_u32 v7, s6, v10, v7
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6
; GFX10-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX10-NEXT: v_add_co_u32 v3, s6, v3, v6
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v7, s6, v7, v11
; GFX10-NEXT: v_mul_lo_u32 v14, s1, v2
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v5, s6, v5, v13
; GFX10-NEXT: v_mul_hi_u32 v15, s0, v2
; GFX10-NEXT: v_mul_hi_u32 v8, v1, v9
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v5, s7, v5, v12
; GFX10-NEXT: v_add_co_u32 v0, s6, v14, v0
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s7
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s6
; GFX10-NEXT: v_mul_hi_u32 v2, s1, v2
; GFX10-NEXT: v_add_co_u32 v0, s6, v0, v15
; GFX10-NEXT: v_add_nc_u32_e32 v5, v11, v5
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v3, s6, v3, v8
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v0, s6, v0, v5
; GFX10-NEXT: v_add_nc_u32_e32 v11, v12, v13
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6
; GFX10-NEXT: v_add_nc_u32_e32 v7, v10, v7
; GFX10-NEXT: v_mul_hi_u32 v9, v4, v9
; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v8
; GFX10-NEXT: v_mul_hi_u32 v8, s8, v0
; GFX10-NEXT: v_add3_u32 v2, v11, v5, v2
; GFX10-NEXT: v_add_co_u32 v3, s6, v3, v7
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6
; GFX10-NEXT: v_mul_lo_u32 v7, s9, v0
; GFX10-NEXT: v_mul_lo_u32 v10, s8, v2
; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3
; GFX10-NEXT: v_add3_u32 v5, v6, v5, v9
; GFX10-NEXT: v_mul_lo_u32 v6, s8, v0
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_add3_u32 v7, v10, v8, v7
; GFX10-NEXT: v_mul_lo_u32 v14, v1, v9
; GFX10-NEXT: v_mul_lo_u32 v12, v11, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v7, vcc_lo
; GFX10-NEXT: v_mul_hi_u32 v13, v1, v3
; GFX10-NEXT: v_mul_hi_u32 v3, v11, v3
; GFX10-NEXT: v_mul_lo_u32 v8, v11, v9
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v5
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
; GFX10-NEXT: v_mul_hi_u32 v10, v1, v9
; GFX10-NEXT: v_add_co_u32 v7, s1, v12, v14
; GFX10-NEXT: v_mul_hi_u32 v9, v11, v9
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v3, s1, v8, v3
; GFX10-NEXT: v_mul_lo_u32 v8, s15, v0
; GFX10-NEXT: v_mul_lo_u32 v14, s14, v2
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s1
; GFX10-NEXT: v_mul_hi_u32 v12, s14, v0
; GFX10-NEXT: v_mul_hi_u32 v0, s15, v0
; GFX10-NEXT: v_add_co_u32 v7, s1, v7, v13
; GFX10-NEXT: v_mul_lo_u32 v13, s15, v2
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v3, s1, v3, v10
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v8, s1, v8, v14
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v0, s1, v13, v0
; GFX10-NEXT: v_mul_hi_u32 v15, s14, v2
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v8, s1, v8, v12
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1
; GFX10-NEXT: v_add_nc_u32_e32 v7, v11, v7
; GFX10-NEXT: v_mul_hi_u32 v2, s15, v2
; GFX10-NEXT: v_add_nc_u32_e32 v5, v5, v10
; GFX10-NEXT: v_add_co_u32 v0, s1, v0, v15
; GFX10-NEXT: v_add_nc_u32_e32 v8, v14, v8
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v0, s1, v0, v8
; GFX10-NEXT: v_add_nc_u32_e32 v10, v13, v12
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v3, s1, v3, v7
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s1
; GFX10-NEXT: v_mul_lo_u32 v6, s9, v0
; GFX10-NEXT: v_add3_u32 v2, v10, v8, v2
; GFX10-NEXT: v_add3_u32 v5, v5, v7, v9
; GFX10-NEXT: v_mul_hi_u32 v7, s8, v0
; GFX10-NEXT: v_mul_lo_u32 v8, s8, v2
; GFX10-NEXT: v_mov_b32_e32 v9, 0 ; GFX10-NEXT: v_mov_b32_e32 v9, 0
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, vcc_lo, v4, v5, s0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v4, v5, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v5, s8, v0 ; GFX10-NEXT: v_add3_u32 v4, v7, v10, v8
; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v3 ; GFX10-NEXT: v_mul_lo_u32 v5, s11, v1
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo ; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, s0, v6
; GFX10-NEXT: v_add3_u32 v4, v6, v8, v7
; GFX10-NEXT: v_mul_lo_u32 v6, s11, v1
; GFX10-NEXT: v_mul_hi_u32 v7, s11, v1
; GFX10-NEXT: v_sub_co_u32 v5, vcc_lo, s14, v5
; GFX10-NEXT: v_sub_nc_u32_e32 v8, s15, v4
; GFX10-NEXT: v_sub_co_ci_u32_e64 v4, s0, s15, v4, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v5
; GFX10-NEXT: v_mul_lo_u32 v14, s10, v3 ; GFX10-NEXT: v_mul_lo_u32 v14, s10, v3
; GFX10-NEXT: v_sub_nc_u32_e32 v8, s1, v4
; GFX10-NEXT: v_sub_co_ci_u32_e64 v4, s0, s1, v4, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v6
; GFX10-NEXT: v_mul_hi_u32 v7, s11, v1
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s9, v4 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s9, v4
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, -1, s0
; GFX10-NEXT: v_mul_lo_u32 v15, s11, v3 ; GFX10-NEXT: v_mul_lo_u32 v15, s11, v3
; GFX10-NEXT: v_mul_hi_u32 v1, s10, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, s10, v1
; GFX10-NEXT: v_mul_hi_u32 v17, s10, v3 ; GFX10-NEXT: v_mul_hi_u32 v17, s10, v3
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v12, vcc_lo, v5, s8 ; GFX10-NEXT: v_sub_co_u32 v12, vcc_lo, v6, s8
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v13, s0, 0, v8, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v13, s0, 0, v8, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v4
; GFX10-NEXT: v_mul_hi_u32 v3, s11, v3 ; GFX10-NEXT: v_mul_hi_u32 v3, s11, v3
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v10, v11, v10, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v11, v10, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v13 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v13
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v12 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v12
; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, -1, s0
; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v14 ; GFX10-NEXT: v_add_co_u32 v5, s0, v5, v14
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v7, s0, v15, v7 ; GFX10-NEXT: v_add_co_u32 v7, s0, v15, v7
; GFX10-NEXT: v_add_co_u32 v1, s1, v6, v1 ; GFX10-NEXT: v_add_co_u32 v1, s1, v5, v1
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v7, s0, v7, v17 ; GFX10-NEXT: v_add_co_u32 v7, s0, v7, v17
; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v17, s0, v0, 1 ; GFX10-NEXT: v_add_co_u32 v17, s0, v0, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v18, s0, 0, v2, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v18, s0, 0, v2, s0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v14, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v14, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v13 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v13
; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v15 ; GFX10-NEXT: v_add_nc_u32_e32 v5, v5, v15
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v16, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v16, s0
; GFX10-NEXT: v_add_co_u32 v7, s0, v7, v1 ; GFX10-NEXT: v_add_co_u32 v7, s0, v7, v1
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v14, s0, v17, 1 ; GFX10-NEXT: v_add_co_u32 v14, s0, v17, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v15, s0, 0, v18, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v15, s0, 0, v18, s0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
; GFX10-NEXT: v_add3_u32 v3, v5, v1, v3
; GFX10-NEXT: v_sub_co_u32 v1, s0, v12, s8
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v5, s0, 0, v8, s0
; GFX10-NEXT: v_cndmask_b32_e32 v8, v17, v14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v14, v18, v15, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v15, s3, v7
; GFX10-NEXT: v_mul_lo_u32 v16, s2, v3
; GFX10-NEXT: v_mul_hi_u32 v17, s2, v7
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v10
; GFX10-NEXT: v_mul_lo_u32 v10, s2, v7
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v11 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v11
; GFX10-NEXT: v_add3_u32 v3, v6, v1, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v10, s3, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v16, s2, v7 ; GFX10-NEXT: v_add3_u32 v8, v15, v16, v17
; GFX10-NEXT: v_cndmask_b32_e64 v6, v18, v15, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v12, v1, s0
; GFX10-NEXT: v_mul_lo_u32 v11, s2, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v13, v5, s0
; GFX10-NEXT: v_mul_hi_u32 v15, s2, v7 ; GFX10-NEXT: v_sub_co_u32 v10, s0, s10, v10
; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, v14, s0 ; GFX10-NEXT: v_sub_co_ci_u32_e64 v11, s1, s11, v8, s0
; GFX10-NEXT: v_sub_co_u32 v14, s1, v12, s8 ; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v8, s1, 0, v8, s1 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo ; GFX10-NEXT: v_sub_nc_u32_e32 v1, s11, v8
; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc_lo ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v11
; GFX10-NEXT: v_add3_u32 v6, v10, v11, v15 ; GFX10-NEXT: v_xor_b32_e32 v0, s18, v0
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v14, s0 ; GFX10-NEXT: v_xor_b32_e32 v2, s19, v2
; GFX10-NEXT: v_cndmask_b32_e64 v2, v13, v8, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v8, s0, s10, v16 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v8, vcc_lo, s3, v1, s0
; GFX10-NEXT: v_sub_co_ci_u32_e64 v10, s1, s11, v6, s0 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v10
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo ; GFX10-NEXT: v_sub_co_u32 v13, vcc_lo, v10, s2
; GFX10-NEXT: v_sub_nc_u32_e32 v4, s11, v6 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v14, s0, 0, v8, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s3, v10 ; GFX10-NEXT: v_sub_co_u32 v0, s0, v0, s18
; GFX10-NEXT: v_xor_b32_e32 v0, s20, v0 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v1, s0, s19, v2, s0
; GFX10-NEXT: v_xor_b32_e32 v1, s21, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, v11
; GFX10-NEXT: v_xor_b32_e32 v5, s12, v5 ; GFX10-NEXT: v_xor_b32_e32 v2, s12, v6
; GFX10-NEXT: v_xor_b32_e32 v2, s12, v2 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v12, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v4, vcc_lo, s3, v4, s0 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s3, v14
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, -1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc_lo ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v13
; GFX10-NEXT: v_sub_co_u32 v12, vcc_lo, v8, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v13, s0, 0, v4, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v0, s0, v0, s20
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v1, s0, s21, v1, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, v10
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v11, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s3, v13
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s2, v12
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, -1, s0
; GFX10-NEXT: v_add_co_u32 v15, s0, v7, 1 ; GFX10-NEXT: v_add_co_u32 v15, s0, v7, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v16, s0, 0, v3, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v16, s0, 0, v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, v13 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s3, v14
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v14, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v12, s0
; GFX10-NEXT: v_add_co_u32 v14, s0, v15, 1 ; GFX10-NEXT: v_add_co_u32 v12, s0, v15, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v17, s0, 0, v16, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v17, s0, 0, v16, s0
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
; GFX10-NEXT: v_sub_co_u32 v11, s0, v12, s2 ; GFX10-NEXT: v_sub_co_u32 v6, s0, v13, s2
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v4, s0, 0, v4, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v8, s0, 0, v8, s0
; GFX10-NEXT: v_cndmask_b32_e32 v14, v15, v14, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v12, v15, v12, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v6 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v5
; GFX10-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v6, v12, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v14, s0 ; GFX10-NEXT: v_xor_b32_e32 v8, s12, v4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v12, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v15, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v15, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v8, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v5, s0
; GFX10-NEXT: v_cndmask_b32_e64 v8, v10, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v11, v6, s0
; GFX10-NEXT: s_xor_b64 s[0:1], s[16:17], s[18:19] ; GFX10-NEXT: s_xor_b64 s[0:1], s[14:15], s[16:17]
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v5, s12 ; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v2, s12
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s12, v2, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v2, s0, v7 ; GFX10-NEXT: v_xor_b32_e32 v2, s0, v7
; GFX10-NEXT: v_xor_b32_e32 v3, s1, v3 ; GFX10-NEXT: v_xor_b32_e32 v3, s1, v3
; GFX10-NEXT: v_xor_b32_e32 v6, s16, v6 ; GFX10-NEXT: v_xor_b32_e32 v7, s14, v10
; GFX10-NEXT: v_xor_b32_e32 v7, s16, v8 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s12, v8, vcc_lo
; GFX10-NEXT: v_xor_b32_e32 v8, s14, v6
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v2, s0 ; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v2, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, v6, s16 ; GFX10-NEXT: v_sub_co_u32 v6, vcc_lo, v7, s14
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s16, v7, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s14, v8, vcc_lo
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v9, v[0:3], s[4:5] ; GFX10-NEXT: global_store_dwordx4 v9, v[0:3], s[4:5]
; GFX10-NEXT: global_store_dwordx4 v9, v[4:7], s[6:7] ; GFX10-NEXT: global_store_dwordx4 v9, v[4:7], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = sdiv <2 x i64> %x, %y %div = sdiv <2 x i64> %x, %y
store <2 x i64> %div, <2 x i64> addrspace(1)* %out0 store <2 x i64> %div, <2 x i64> addrspace(1)* %out0
%rem = srem <2 x i64> %x, %y %rem = srem <2 x i64> %x, %y
store <2 x i64> %rem, <2 x i64> addrspace(1)* %out1 store <2 x i64> %rem, <2 x i64> addrspace(1)* %out1
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llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll

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; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB0_2 ; CHECK-NEXT: s_cbranch_execz BB0_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v0 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v0
; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v3, v0, vcc ; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v3, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v3, v1, v0 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v0
; CHECK-NEXT: v_xor_b32_e32 v0, v2, v0 ; CHECK-NEXT: v_xor_b32_e32 v0, v2, v0
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v3 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v1
; CHECK-NEXT: v_cvt_f32_u32_e32 v6, v0 ; CHECK-NEXT: v_cvt_f32_u32_e32 v3, v0
; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v5 ; CHECK-NEXT: v_ashrrev_i32_e32 v6, 31, v5
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v1 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v6
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v1, vcc ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v6
; CHECK-NEXT: v_sub_i32_e32 v7, vcc, 0, v3 ; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v5, v6, vcc
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v6, 0x2f800000, v2 ; CHECK-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v6, v6 ; CHECK-NEXT: v_trunc_f32_e32 v5, v5
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v6 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v6, v6 ; CHECK-NEXT: v_cvt_u32_f32_e32 v5, v5
; CHECK-NEXT: v_sub_i32_e32 v7, vcc, 0, v1
; CHECK-NEXT: v_subb_u32_e32 v8, vcc, 0, v0, vcc ; CHECK-NEXT: v_subb_u32_e32 v8, vcc, 0, v0, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v8, v2 ; CHECK-NEXT: v_mul_lo_u32 v9, v8, v2
; CHECK-NEXT: v_mul_lo_u32 v10, v7, v6 ; CHECK-NEXT: v_mul_lo_u32 v10, v7, v5
; CHECK-NEXT: v_mul_hi_u32 v12, v7, v2 ; CHECK-NEXT: v_mul_hi_u32 v12, v7, v2
; CHECK-NEXT: v_mul_lo_u32 v11, v7, v2 ; CHECK-NEXT: v_mul_lo_u32 v11, v7, v2
; CHECK-NEXT: v_xor_b32_e32 v4, v4, v1 ; CHECK-NEXT: v_xor_b32_e32 v3, v3, v6
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CHECK-NEXT: v_mul_lo_u32 v10, v6, v11 ; CHECK-NEXT: v_mul_lo_u32 v10, v5, v11
; CHECK-NEXT: v_mul_lo_u32 v12, v2, v9 ; CHECK-NEXT: v_mul_lo_u32 v12, v2, v9
; CHECK-NEXT: v_mul_hi_u32 v13, v2, v11 ; CHECK-NEXT: v_mul_hi_u32 v13, v2, v11
; CHECK-NEXT: v_mul_hi_u32 v11, v6, v11 ; CHECK-NEXT: v_mul_hi_u32 v11, v5, v11
; CHECK-NEXT: v_xor_b32_e32 v5, v5, v1 ; CHECK-NEXT: v_xor_b32_e32 v4, v4, v6
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v13 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v13, v6, v9 ; CHECK-NEXT: v_mul_lo_u32 v13, v5, v9
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v12, v10 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CHECK-NEXT: v_mul_hi_u32 v12, v2, v9 ; CHECK-NEXT: v_mul_hi_u32 v12, v2, v9
; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v11 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9 ; CHECK-NEXT: v_mul_hi_u32 v9, v5, v9
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v10 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v10
; CHECK-NEXT: v_addc_u32_e64 v10, s[4:5], v6, v9, vcc ; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc
; CHECK-NEXT: v_mul_lo_u32 v8, v8, v2 ; CHECK-NEXT: v_mul_lo_u32 v8, v8, v2
; CHECK-NEXT: v_mul_lo_u32 v11, v7, v10 ; CHECK-NEXT: v_mul_lo_u32 v9, v7, v5
; CHECK-NEXT: v_mul_lo_u32 v12, v7, v2 ; CHECK-NEXT: v_mul_lo_u32 v10, v7, v2
; CHECK-NEXT: v_mul_hi_u32 v7, v7, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, v7, v2
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v9 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v8, v7 ; CHECK-NEXT: v_mul_lo_u32 v8, v5, v10
; CHECK-NEXT: v_mul_lo_u32 v8, v10, v12 ; CHECK-NEXT: v_mul_lo_u32 v9, v2, v7
; CHECK-NEXT: v_mul_lo_u32 v11, v2, v7 ; CHECK-NEXT: v_mul_hi_u32 v11, v2, v10
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v12 ; CHECK-NEXT: v_mul_hi_u32 v10, v5, v10
; CHECK-NEXT: v_mul_hi_u32 v12, v10, v12 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CHECK-NEXT: v_mul_lo_u32 v11, v5, v7
; CHECK-NEXT: v_mul_lo_u32 v9, v10, v7 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8 ; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v11, v2, v7 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v11 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; CHECK-NEXT: v_mul_hi_u32 v7, v5, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v10, v7 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v11, v9 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v9
; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; CHECK-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, v5, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, v4, v2
; CHECK-NEXT: v_mul_lo_u32 v8, v4, v6 ; CHECK-NEXT: v_mul_lo_u32 v8, v3, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v4, v2 ; CHECK-NEXT: v_mul_hi_u32 v9, v3, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v5, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v4, v2
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v5, v6 ; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_mul_hi_u32 v8, v4, v6 ; CHECK-NEXT: v_mul_hi_u32 v8, v3, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_mul_hi_u32 v6, v5, v6 ; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_mul_lo_u32 v7, v0, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, v0, v2
; CHECK-NEXT: v_mul_lo_u32 v6, v3, v6 ; CHECK-NEXT: v_mul_lo_u32 v5, v1, v5
; CHECK-NEXT: v_mul_lo_u32 v8, v3, v2 ; CHECK-NEXT: v_mul_lo_u32 v8, v1, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v3, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v6, v2 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v4, v8 ; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v3, v8
; CHECK-NEXT: v_subb_u32_e64 v6, s[4:5], v5, v2, vcc ; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v4, v2, vcc
; CHECK-NEXT: v_sub_i32_e64 v2, s[4:5], v5, v2 ; CHECK-NEXT: v_sub_i32_e64 v2, s[4:5], v4, v2
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v0 ; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v0
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v3 ; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v1
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v0 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v0
; CHECK-NEXT: v_subb_u32_e32 v2, vcc, v2, v0, vcc ; CHECK-NEXT: v_subb_u32_e32 v2, vcc, v2, v0, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]
; CHECK-NEXT: v_sub_i32_e32 v7, vcc, v4, v3 ; CHECK-NEXT: v_sub_i32_e32 v7, vcc, v3, v1
; CHECK-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v2, vcc ; CHECK-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v2, vcc
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v0 ; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v0
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v3 ; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v1
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v0 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v0
; CHECK-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc ; CHECK-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc
; CHECK-NEXT: v_sub_i32_e32 v2, vcc, v7, v3 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v7, v1
; CHECK-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; CHECK-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v2, v2, v1 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v6
; CHECK-NEXT: v_xor_b32_e32 v3, v0, v1 ; CHECK-NEXT: v_xor_b32_e32 v2, v0, v6
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v2, v1 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v1, v6
; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc ; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v2, v6, vcc
; CHECK-NEXT: ; implicit-def: $vgpr2 ; CHECK-NEXT: ; implicit-def: $vgpr2
; CHECK-NEXT: ; implicit-def: $vgpr4 ; CHECK-NEXT: ; implicit-def: $vgpr4
; CHECK-NEXT: BB0_2: ; %Flow ; CHECK-NEXT: BB0_2: ; %Flow
; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB0_4 ; CHECK-NEXT: s_cbranch_execz BB0_4
; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: ; %bb.3:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v2
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; CHECK-NEXT: s_cmp_lg_u32 s3, 0 ; CHECK-NEXT: s_cmp_lg_u32 s3, 0
; CHECK-NEXT: s_mov_b32 s1, s0 ; CHECK-NEXT: s_mov_b32 s1, s0
; CHECK-NEXT: s_addc_u32 s9, s5, s0 ; CHECK-NEXT: s_addc_u32 s9, s5, s0
; CHECK-NEXT: s_xor_b64 s[8:9], s[8:9], s[0:1] ; CHECK-NEXT: s_xor_b64 s[8:9], s[8:9], s[0:1]
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s8 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s8
; CHECK-NEXT: v_cvt_f32_u32_e32 v1, s9 ; CHECK-NEXT: v_cvt_f32_u32_e32 v1, s9
; CHECK-NEXT: s_mov_b32 s7, s6 ; CHECK-NEXT: s_mov_b32 s7, s6
; CHECK-NEXT: s_xor_b64 s[10:11], s[10:11], s[6:7] ; CHECK-NEXT: s_xor_b64 s[10:11], s[10:11], s[6:7]
; CHECK-NEXT: s_sub_u32 s3, 0, s8 ; CHECK-NEXT: s_sub_u32 s0, 0, s8
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: s_cselect_b32 s0, 1, 0 ; CHECK-NEXT: s_cselect_b32 s1, 1, 0
; CHECK-NEXT: s_and_b32 s0, s0, 1 ; CHECK-NEXT: s_and_b32 s1, s1, 1
; CHECK-NEXT: s_cmp_lg_u32 s0, 0 ; CHECK-NEXT: s_cmp_lg_u32 s1, 0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; CHECK-NEXT: v_trunc_f32_e32 v1, v1 ; CHECK-NEXT: v_trunc_f32_e32 v1, v1
; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1 ; CHECK-NEXT: v_cvt_u32_f32_e32 v1, v1
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: s_subb_u32 s5, 0, s9 ; CHECK-NEXT: s_subb_u32 s1, 0, s9
; CHECK-NEXT: v_mul_lo_u32 v3, s0, v1
; CHECK-NEXT: v_mul_lo_u32 v2, s1, v0
; CHECK-NEXT: v_mul_hi_u32 v5, s0, v0
; CHECK-NEXT: v_mul_lo_u32 v4, s0, v0
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_mul_lo_u32 v3, v1, v4
; CHECK-NEXT: v_mul_lo_u32 v5, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v6, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v6, v1, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; CHECK-NEXT: v_mul_hi_u32 v5, v0, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CHECK-NEXT: v_mul_lo_u32 v2, s1, v0
; CHECK-NEXT: v_mul_lo_u32 v3, s0, v1
; CHECK-NEXT: v_mul_hi_u32 v5, s0, v0
; CHECK-NEXT: v_mul_lo_u32 v4, s0, v0
; CHECK-NEXT: v_mov_b32_e32 v6, s9 ; CHECK-NEXT: v_mov_b32_e32 v6, s9
; CHECK-NEXT: v_mul_lo_u32 v3, s3, v1
; CHECK-NEXT: v_mul_lo_u32 v2, s5, v0
; CHECK-NEXT: v_mul_hi_u32 v5, s3, v0
; CHECK-NEXT: v_mul_lo_u32 v4, s3, v0
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_mul_lo_u32 v3, v1, v4 ; CHECK-NEXT: v_mul_lo_u32 v3, v1, v4
; CHECK-NEXT: v_mul_lo_u32 v5, v0, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v7, v0, v4 ; CHECK-NEXT: v_mul_hi_u32 v7, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v7 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, v1, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, v1, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; CHECK-NEXT: v_mul_hi_u32 v5, v0, v2 ; CHECK-NEXT: v_mul_hi_u32 v5, v0, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_addc_u32_e64 v3, s[0:1], v1, v2, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CHECK-NEXT: v_mul_lo_u32 v4, s5, v0
; CHECK-NEXT: v_mul_lo_u32 v5, s3, v3
; CHECK-NEXT: v_mul_hi_u32 v8, s3, v0
; CHECK-NEXT: v_mul_lo_u32 v7, s3, v0
; CHECK-NEXT: v_add_i32_e64 v1, s[0:1], v1, v2
; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v4, v5
; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v4, v8
; CHECK-NEXT: v_mul_lo_u32 v5, v3, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v2, v0, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v3, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v5, v2
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; CHECK-NEXT: v_mul_lo_u32 v5, v3, v4
; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v8, v2
; CHECK-NEXT: v_mul_hi_u32 v8, v0, v4
; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v7
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
; CHECK-NEXT: v_add_i32_e64 v5, s[0:1], v5, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; CHECK-NEXT: v_add_i32_e64 v7, s[0:1], v7, v8
; CHECK-NEXT: v_mul_hi_u32 v3, v3, v4
; CHECK-NEXT: v_add_i32_e64 v2, s[0:1], v5, v2
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
; CHECK-NEXT: v_add_i32_e64 v4, s[0:1], v7, v5
; CHECK-NEXT: v_add_i32_e64 v3, s[0:1], v3, v4
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_mul_lo_u32 v2, s11, v0 ; CHECK-NEXT: v_mul_lo_u32 v2, s11, v0
; CHECK-NEXT: v_mul_lo_u32 v3, s10, v1 ; CHECK-NEXT: v_mul_lo_u32 v3, s10, v1
; CHECK-NEXT: v_mul_hi_u32 v5, s10, v0 ; CHECK-NEXT: v_mul_hi_u32 v5, s10, v0
; CHECK-NEXT: v_mul_hi_u32 v0, s11, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, s11, v0
; CHECK-NEXT: v_mov_b32_e32 v4, s11 ; CHECK-NEXT: v_mov_b32_e32 v4, s11
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16 ; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; GISEL-NEXT: v_mul_hi_u32 v13, v10, v13 ; GISEL-NEXT: v_mul_hi_u32 v13, v10, v13
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v16, v15 ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v14 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v14
; GISEL-NEXT: v_addc_u32_e64 v14, s[4:5], v10, v13, vcc ; GISEL-NEXT: v_addc_u32_e32 v10, vcc, v10, v13, vcc
; GISEL-NEXT: v_mul_lo_u32 v12, v12, v8 ; GISEL-NEXT: v_mul_lo_u32 v12, v12, v8
; GISEL-NEXT: v_mul_lo_u32 v15, v11, v14 ; GISEL-NEXT: v_mul_lo_u32 v13, v11, v10
; GISEL-NEXT: v_mul_lo_u32 v16, v11, v8 ; GISEL-NEXT: v_mul_lo_u32 v14, v11, v8
; GISEL-NEXT: v_mul_hi_u32 v11, v11, v8 ; GISEL-NEXT: v_mul_hi_u32 v11, v11, v8
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_mul_lo_u32 v12, v10, v14
; GISEL-NEXT: v_mul_lo_u32 v12, v14, v16 ; GISEL-NEXT: v_mul_lo_u32 v13, v8, v11
; GISEL-NEXT: v_mul_lo_u32 v15, v8, v11 ; GISEL-NEXT: v_mul_hi_u32 v15, v8, v14
; GISEL-NEXT: v_mul_hi_u32 v13, v8, v16 ; GISEL-NEXT: v_mul_hi_u32 v14, v10, v14
; GISEL-NEXT: v_mul_hi_u32 v16, v14, v16 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15 ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v15, v10, v11
; GISEL-NEXT: v_mul_lo_u32 v13, v14, v11 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v15, v12 ; GISEL-NEXT: v_mul_hi_u32 v13, v8, v11
; GISEL-NEXT: v_mul_hi_u32 v15, v8, v11 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v16 ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v15 ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v16, v15 ; GISEL-NEXT: v_mul_hi_u32 v11, v10, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v14, v11 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v15, v13 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, v10, v11, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc ; GISEL-NEXT: v_addc_u32_e32 v10, vcc, v10, v11, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, v1, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v1, v8
; GISEL-NEXT: v_mul_lo_u32 v12, v0, v10 ; GISEL-NEXT: v_mul_lo_u32 v12, v0, v10
; GISEL-NEXT: v_mul_hi_u32 v13, v0, v8 ; GISEL-NEXT: v_mul_hi_u32 v13, v0, v8
; GISEL-NEXT: v_mul_hi_u32 v8, v1, v8 ; GISEL-NEXT: v_mul_hi_u32 v8, v1, v8
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v16, v15 ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12 ; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v13 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v13
; GISEL-NEXT: v_addc_u32_e64 v13, s[4:5], v8, v12, vcc ; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v12, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, v11, v7 ; GISEL-NEXT: v_mul_lo_u32 v11, v11, v7
; GISEL-NEXT: v_mul_lo_u32 v14, v10, v13 ; GISEL-NEXT: v_mul_lo_u32 v12, v10, v8
; GISEL-NEXT: v_mul_lo_u32 v15, v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v13, v10, v7
; GISEL-NEXT: v_mul_hi_u32 v10, v10, v7 ; GISEL-NEXT: v_mul_hi_u32 v10, v10, v7
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v12
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10
; GISEL-NEXT: v_mul_lo_u32 v11, v13, v15
; GISEL-NEXT: v_mul_lo_u32 v14, v7, v10
; GISEL-NEXT: v_mul_hi_u32 v12, v7, v15
; GISEL-NEXT: v_mul_hi_u32 v15, v13, v15
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v9 ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v9
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; GISEL-NEXT: v_mul_lo_u32 v11, v8, v13
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v12, v7, v10
; GISEL-NEXT: v_mul_lo_u32 v12, v13, v10 ; GISEL-NEXT: v_mul_hi_u32 v14, v7, v13
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v14, v11 ; GISEL-NEXT: v_mul_hi_u32 v13, v8, v13
; GISEL-NEXT: v_mul_hi_u32 v14, v7, v10
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v15, v14
; GISEL-NEXT: v_mul_hi_u32 v10, v13, v10
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12
; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; GISEL-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v14, v8, v10
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_mul_hi_u32 v12, v7, v10
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_mul_hi_u32 v10, v8, v10
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; GISEL-NEXT: v_mul_lo_u32 v10, v3, v7 ; GISEL-NEXT: v_mul_lo_u32 v10, v3, v7
; GISEL-NEXT: v_mul_lo_u32 v11, v2, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v2, v8
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; GISEL-NEXT: v_mul_hi_u32 v4, v2, v7 ; GISEL-NEXT: v_mul_hi_u32 v4, v2, v7
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v10, v4 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v10, v4
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_2 ; CGP-NEXT: s_cbranch_execz BB2_2
; CGP-NEXT: ; %bb.1: ; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v5 ; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v0 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v4, v0
; CGP-NEXT: v_addc_u32_e32 v2, vcc, v5, v0, vcc ; CGP-NEXT: v_addc_u32_e32 v2, vcc, v5, v0, vcc
; CGP-NEXT: v_xor_b32_e32 v3, v1, v0 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v0
; CGP-NEXT: v_xor_b32_e32 v0, v2, v0 ; CGP-NEXT: v_xor_b32_e32 v0, v2, v0
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v3 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v0 ; CGP-NEXT: v_cvt_f32_u32_e32 v3, v0
; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v11 ; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v11
; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4 ; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_add_i32_e32 v4, vcc, v10, v1 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v10, v4
; CGP-NEXT: v_addc_u32_e32 v5, vcc, v11, v1, vcc ; CGP-NEXT: v_addc_u32_e32 v5, vcc, v11, v4, vcc
; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CGP-NEXT: v_mul_f32_e32 v10, 0x2f800000, v2 ; CGP-NEXT: v_mul_f32_e32 v10, 0x2f800000, v2
; CGP-NEXT: v_trunc_f32_e32 v10, v10 ; CGP-NEXT: v_trunc_f32_e32 v10, v10
; CGP-NEXT: v_mac_f32_e32 v2, 0xcf800000, v10 ; CGP-NEXT: v_mac_f32_e32 v2, 0xcf800000, v10
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v10, v10 ; CGP-NEXT: v_cvt_u32_f32_e32 v10, v10
; CGP-NEXT: v_sub_i32_e32 v11, vcc, 0, v3 ; CGP-NEXT: v_sub_i32_e32 v11, vcc, 0, v1
; CGP-NEXT: v_subb_u32_e32 v12, vcc, 0, v0, vcc ; CGP-NEXT: v_subb_u32_e32 v12, vcc, 0, v0, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v12, v2 ; CGP-NEXT: v_mul_lo_u32 v13, v12, v2
; CGP-NEXT: v_mul_lo_u32 v14, v11, v10 ; CGP-NEXT: v_mul_lo_u32 v14, v11, v10
; CGP-NEXT: v_mul_hi_u32 v16, v11, v2 ; CGP-NEXT: v_mul_hi_u32 v16, v11, v2
; CGP-NEXT: v_mul_lo_u32 v15, v11, v2 ; CGP-NEXT: v_mul_lo_u32 v15, v11, v2
; CGP-NEXT: v_xor_b32_e32 v4, v4, v1 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v4
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v16 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v16
; CGP-NEXT: v_mul_lo_u32 v14, v10, v15 ; CGP-NEXT: v_mul_lo_u32 v14, v10, v15
; CGP-NEXT: v_mul_lo_u32 v16, v2, v13 ; CGP-NEXT: v_mul_lo_u32 v16, v2, v13
; CGP-NEXT: v_mul_hi_u32 v17, v2, v15 ; CGP-NEXT: v_mul_hi_u32 v17, v2, v15
; CGP-NEXT: v_mul_hi_u32 v15, v10, v15 ; CGP-NEXT: v_mul_hi_u32 v15, v10, v15
; CGP-NEXT: v_xor_b32_e32 v5, v5, v1 ; CGP-NEXT: v_xor_b32_e32 v5, v5, v4
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v16 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v16
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v17 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v17
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v17, v10, v13 ; CGP-NEXT: v_mul_lo_u32 v17, v10, v13
; CGP-NEXT: v_add_i32_e32 v14, vcc, v16, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v16, v14
; CGP-NEXT: v_mul_hi_u32 v16, v2, v13 ; CGP-NEXT: v_mul_hi_u32 v16, v2, v13
; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v15 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v15
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v16 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16 ; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13 ; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v14 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v14
; CGP-NEXT: v_addc_u32_e64 v14, s[4:5], v10, v13, vcc ; CGP-NEXT: v_addc_u32_e32 v10, vcc, v10, v13, vcc
; CGP-NEXT: v_mul_lo_u32 v12, v12, v2 ; CGP-NEXT: v_mul_lo_u32 v12, v12, v2
; CGP-NEXT: v_mul_lo_u32 v15, v11, v14 ; CGP-NEXT: v_mul_lo_u32 v13, v11, v10
; CGP-NEXT: v_mul_lo_u32 v16, v11, v2 ; CGP-NEXT: v_mul_lo_u32 v14, v11, v2
; CGP-NEXT: v_mul_hi_u32 v11, v11, v2 ; CGP-NEXT: v_mul_hi_u32 v11, v11, v2
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v14
; CGP-NEXT: v_mul_lo_u32 v12, v14, v16 ; CGP-NEXT: v_mul_lo_u32 v13, v2, v11
; CGP-NEXT: v_mul_lo_u32 v15, v2, v11 ; CGP-NEXT: v_mul_hi_u32 v15, v2, v14
; CGP-NEXT: v_mul_hi_u32 v13, v2, v16 ; CGP-NEXT: v_mul_hi_u32 v14, v10, v14
; CGP-NEXT: v_mul_hi_u32 v16, v14, v16 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15 ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_mul_lo_u32 v15, v10, v11
; CGP-NEXT: v_mul_lo_u32 v13, v14, v11 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v15, v12 ; CGP-NEXT: v_mul_hi_u32 v13, v2, v11
; CGP-NEXT: v_mul_hi_u32 v15, v2, v11 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v16 ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v15 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e64 v15, s[4:5], v16, v15 ; CGP-NEXT: v_mul_hi_u32 v11, v10, v11
; CGP-NEXT: v_mul_hi_u32 v11, v14, v11 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v15, v13 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
; CGP-NEXT: v_addc_u32_e32 v10, vcc, v10, v11, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12
; CGP-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc ; CGP-NEXT: v_addc_u32_e32 v10, vcc, v10, v11, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v5, v2 ; CGP-NEXT: v_mul_lo_u32 v11, v5, v2
; CGP-NEXT: v_mul_lo_u32 v12, v4, v10 ; CGP-NEXT: v_mul_lo_u32 v12, v3, v10
; CGP-NEXT: v_mul_hi_u32 v13, v4, v2 ; CGP-NEXT: v_mul_hi_u32 v13, v3, v2
; CGP-NEXT: v_mul_hi_u32 v2, v5, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v5, v2
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v13 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v5, v10 ; CGP-NEXT: v_mul_lo_u32 v13, v5, v10
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_mul_hi_u32 v12, v4, v10 ; CGP-NEXT: v_mul_hi_u32 v12, v3, v10
; CGP-NEXT: v_add_i32_e32 v2, vcc, v13, v2 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v13, v2
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_mul_hi_u32 v10, v5, v10 ; CGP-NEXT: v_mul_hi_u32 v10, v5, v10
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v11 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CGP-NEXT: v_mul_lo_u32 v11, v0, v2 ; CGP-NEXT: v_mul_lo_u32 v11, v0, v2
; CGP-NEXT: v_mul_lo_u32 v10, v3, v10 ; CGP-NEXT: v_mul_lo_u32 v10, v1, v10
; CGP-NEXT: v_mul_lo_u32 v12, v3, v2 ; CGP-NEXT: v_mul_lo_u32 v12, v1, v2
; CGP-NEXT: v_mul_hi_u32 v2, v3, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v1, v2
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v2, vcc, v10, v2 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v10, v2
; CGP-NEXT: v_sub_i32_e32 v4, vcc, v4, v12 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v3, v12
; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v5, v2, vcc ; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v5, v2, vcc
; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v5, v2 ; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v5, v2
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v0 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v0
; CGP-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v3 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v1
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v10, v0 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v10, v0
; CGP-NEXT: v_subb_u32_e32 v2, vcc, v2, v0, vcc ; CGP-NEXT: v_subb_u32_e32 v2, vcc, v2, v0, vcc
; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[4:5]
; CGP-NEXT: v_sub_i32_e32 v11, vcc, v4, v3 ; CGP-NEXT: v_sub_i32_e32 v11, vcc, v3, v1
; CGP-NEXT: v_subbrev_u32_e64 v12, s[4:5], 0, v2, vcc ; CGP-NEXT: v_subbrev_u32_e64 v12, s[4:5], 0, v2, vcc
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v12, v0 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v12, v0
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v11, v3 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v11, v1
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v12, v0 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v12, v0
; CGP-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc ; CGP-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v11, v3 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v11, v1
; CGP-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[4:5]
; CGP-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc ; CGP-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; CGP-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v11, v1, vcc
; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CGP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; CGP-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc
; CGP-NEXT: v_xor_b32_e32 v2, v2, v1 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
; CGP-NEXT: v_xor_b32_e32 v3, v0, v1 ; CGP-NEXT: v_xor_b32_e32 v2, v0, v4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v2, v1 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v1, v4
; CGP-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc ; CGP-NEXT: v_subb_u32_e32 v1, vcc, v2, v4, vcc
; CGP-NEXT: ; implicit-def: $vgpr4 ; CGP-NEXT: ; implicit-def: $vgpr4
; CGP-NEXT: ; implicit-def: $vgpr10 ; CGP-NEXT: ; implicit-def: $vgpr10
; CGP-NEXT: BB2_2: ; %Flow2 ; CGP-NEXT: BB2_2: ; %Flow2
; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5] ; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_4 ; CGP-NEXT: s_cbranch_execz BB2_4
; CGP-NEXT: ; %bb.3: ; CGP-NEXT: ; %bb.3:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v4
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; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_6 ; CGP-NEXT: s_cbranch_execz BB2_6
; CGP-NEXT: ; %bb.5: ; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v7 ; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v7
; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v2 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v2
; CGP-NEXT: v_addc_u32_e32 v4, vcc, v7, v2, vcc ; CGP-NEXT: v_addc_u32_e32 v4, vcc, v7, v2, vcc
; CGP-NEXT: v_xor_b32_e32 v5, v3, v2 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v2
; CGP-NEXT: v_xor_b32_e32 v2, v4, v2 ; CGP-NEXT: v_xor_b32_e32 v2, v4, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v5 ; CGP-NEXT: v_cvt_f32_u32_e32 v4, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v5, v2
; CGP-NEXT: v_ashrrev_i32_e32 v3, 31, v9 ; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v9
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v3 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v8, v6
; CGP-NEXT: v_addc_u32_e32 v7, vcc, v9, v3, vcc ; CGP-NEXT: v_addc_u32_e32 v7, vcc, v9, v6, vcc
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v4 ; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v4
; CGP-NEXT: v_trunc_f32_e32 v8, v8 ; CGP-NEXT: v_trunc_f32_e32 v8, v8
; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v8 ; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 ; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_sub_i32_e32 v9, vcc, 0, v5 ; CGP-NEXT: v_sub_i32_e32 v9, vcc, 0, v3
; CGP-NEXT: v_subb_u32_e32 v10, vcc, 0, v2, vcc ; CGP-NEXT: v_subb_u32_e32 v10, vcc, 0, v2, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v10, v4 ; CGP-NEXT: v_mul_lo_u32 v11, v10, v4
; CGP-NEXT: v_mul_lo_u32 v12, v9, v8 ; CGP-NEXT: v_mul_lo_u32 v12, v9, v8
; CGP-NEXT: v_mul_hi_u32 v14, v9, v4 ; CGP-NEXT: v_mul_hi_u32 v14, v9, v4
; CGP-NEXT: v_mul_lo_u32 v13, v9, v4 ; CGP-NEXT: v_mul_lo_u32 v13, v9, v4
; CGP-NEXT: v_xor_b32_e32 v6, v6, v3 ; CGP-NEXT: v_xor_b32_e32 v5, v5, v6
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v14 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; CGP-NEXT: v_mul_lo_u32 v12, v8, v13 ; CGP-NEXT: v_mul_lo_u32 v12, v8, v13
; CGP-NEXT: v_mul_lo_u32 v14, v4, v11 ; CGP-NEXT: v_mul_lo_u32 v14, v4, v11
; CGP-NEXT: v_mul_hi_u32 v15, v4, v13 ; CGP-NEXT: v_mul_hi_u32 v15, v4, v13
; CGP-NEXT: v_mul_hi_u32 v13, v8, v13 ; CGP-NEXT: v_mul_hi_u32 v13, v8, v13
; CGP-NEXT: v_xor_b32_e32 v7, v7, v3 ; CGP-NEXT: v_xor_b32_e32 v7, v7, v6
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v15, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v15, v8, v11
; CGP-NEXT: v_add_i32_e32 v12, vcc, v14, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v14, v12
; CGP-NEXT: v_mul_hi_u32 v14, v4, v11 ; CGP-NEXT: v_mul_hi_u32 v14, v4, v11
; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v13 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v13
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v13 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v12
; CGP-NEXT: v_addc_u32_e64 v12, s[4:5], v8, v11, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v11, vcc
; CGP-NEXT: v_mul_lo_u32 v10, v10, v4 ; CGP-NEXT: v_mul_lo_u32 v10, v10, v4
; CGP-NEXT: v_mul_lo_u32 v13, v9, v12 ; CGP-NEXT: v_mul_lo_u32 v11, v9, v8
; CGP-NEXT: v_mul_lo_u32 v14, v9, v4 ; CGP-NEXT: v_mul_lo_u32 v12, v9, v4
; CGP-NEXT: v_mul_hi_u32 v9, v9, v4 ; CGP-NEXT: v_mul_hi_u32 v9, v9, v4
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v10, v9 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v12
; CGP-NEXT: v_mul_lo_u32 v10, v12, v14 ; CGP-NEXT: v_mul_lo_u32 v11, v4, v9
; CGP-NEXT: v_mul_lo_u32 v13, v4, v9 ; CGP-NEXT: v_mul_hi_u32 v13, v4, v12
; CGP-NEXT: v_mul_hi_u32 v11, v4, v14 ; CGP-NEXT: v_mul_hi_u32 v12, v8, v12
; CGP-NEXT: v_mul_hi_u32 v14, v12, v14 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_mul_lo_u32 v11, v12, v9 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v13, v10 ; CGP-NEXT: v_mul_hi_u32 v11, v4, v9
; CGP-NEXT: v_mul_hi_u32 v13, v4, v9 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_mul_hi_u32 v9, v12, v9 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v11
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v9, v7, v4 ; CGP-NEXT: v_mul_lo_u32 v9, v7, v4
; CGP-NEXT: v_mul_lo_u32 v10, v6, v8 ; CGP-NEXT: v_mul_lo_u32 v10, v5, v8
; CGP-NEXT: v_mul_hi_u32 v11, v6, v4 ; CGP-NEXT: v_mul_hi_u32 v11, v5, v4
; CGP-NEXT: v_mul_hi_u32 v4, v7, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v7, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v7, v8 ; CGP-NEXT: v_mul_lo_u32 v11, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_mul_hi_u32 v10, v6, v8 ; CGP-NEXT: v_mul_hi_u32 v10, v5, v8
; CGP-NEXT: v_add_i32_e32 v4, vcc, v11, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v11, v4
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_mul_hi_u32 v8, v7, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v7, v8
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_mul_lo_u32 v9, v2, v4 ; CGP-NEXT: v_mul_lo_u32 v9, v2, v4
; CGP-NEXT: v_mul_lo_u32 v8, v5, v8 ; CGP-NEXT: v_mul_lo_u32 v8, v3, v8
; CGP-NEXT: v_mul_lo_u32 v10, v5, v4 ; CGP-NEXT: v_mul_lo_u32 v10, v3, v4
; CGP-NEXT: v_mul_hi_u32 v4, v5, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_add_i32_e32 v4, vcc, v8, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v8, v4
; CGP-NEXT: v_sub_i32_e32 v6, vcc, v6, v10 ; CGP-NEXT: v_sub_i32_e32 v5, vcc, v5, v10
; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v7, v4, vcc ; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v7, v4, vcc
; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v7, v4 ; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v7, v4
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v2 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v2
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v5 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v3
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v2 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v2
; CGP-NEXT: v_subb_u32_e32 v4, vcc, v4, v2, vcc ; CGP-NEXT: v_subb_u32_e32 v4, vcc, v4, v2, vcc
; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5]
; CGP-NEXT: v_sub_i32_e32 v9, vcc, v6, v5 ; CGP-NEXT: v_sub_i32_e32 v9, vcc, v5, v3
; CGP-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v4, vcc ; CGP-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v4, vcc
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v2 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v2
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v5 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v3
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v10, v2 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v10, v2
; CGP-NEXT: v_subb_u32_e32 v2, vcc, v4, v2, vcc ; CGP-NEXT: v_subb_u32_e32 v2, vcc, v4, v2, vcc
; CGP-NEXT: v_sub_i32_e32 v4, vcc, v9, v5 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v9, v3
; CGP-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[4:5]
; CGP-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc ; CGP-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; CGP-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; CGP-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; CGP-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; CGP-NEXT: v_xor_b32_e32 v4, v4, v3 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v6
; CGP-NEXT: v_xor_b32_e32 v5, v2, v3 ; CGP-NEXT: v_xor_b32_e32 v4, v2, v6
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v4, v3 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v3, v6
; CGP-NEXT: v_subb_u32_e32 v3, vcc, v5, v3, vcc ; CGP-NEXT: v_subb_u32_e32 v3, vcc, v4, v6, vcc
; CGP-NEXT: ; implicit-def: $vgpr6 ; CGP-NEXT: ; implicit-def: $vgpr6
; CGP-NEXT: ; implicit-def: $vgpr8 ; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: BB2_6: ; %Flow ; CGP-NEXT: BB2_6: ; %Flow
; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5] ; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB2_8 ; CGP-NEXT: s_cbranch_execz BB2_8
; CGP-NEXT: ; %bb.7: ; CGP-NEXT: ; %bb.7:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v6
Show All 20 Lines; CGP-NEXT: s_setpc_b64 s[30:31]
%result = srem <2 x i64> %num, %den %result = srem <2 x i64> %num, %den
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_srem_i64_pow2k_denom(i64 %num) { define i64 @v_srem_i64_pow2k_denom(i64 %num) {
; CHECK-LABEL: v_srem_i64_pow2k_denom: ; CHECK-LABEL: v_srem_i64_pow2k_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, 0x1000 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x1000
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
; CHECK-NEXT: s_movk_i32 s6, 0xf000 ; CHECK-NEXT: s_movk_i32 s4, 0xf000
; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; CHECK-NEXT: s_movk_i32 s6, 0x1000
; CHECK-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 ; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v4, v4 ; CHECK-NEXT: v_trunc_f32_e32 v4, v4
; CHECK-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v2 ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v3 ; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4 ; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v8, s6, v3 ; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s6, v3 ; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000 ; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7 ; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v3, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v3, v7 ; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7 ; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5 ; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_mul_hi_u32 v8, v3, v5 ; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5 ; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e64 v6, s[4:5], v4, v5, vcc ; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, -1, v3 ; CHECK-NEXT: v_mul_lo_u32 v5, v1, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s6, v6
; CHECK-NEXT: v_mul_hi_u32 v10, s6, v3
; CHECK-NEXT: v_mul_lo_u32 v9, s6, v3
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v5
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v10
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v9
; CHECK-NEXT: v_mul_lo_u32 v10, v3, v7
; CHECK-NEXT: v_mul_hi_u32 v5, v3, v9
; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9
; CHECK-NEXT: s_movk_i32 s6, 0x1000
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
; CHECK-NEXT: v_mul_hi_u32 v10, v3, v7
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; CHECK-NEXT: v_mul_hi_u32 v6, v6, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v9, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, v1, v3
; CHECK-NEXT: v_mul_lo_u32 v6, v0, v4 ; CHECK-NEXT: v_mul_lo_u32 v6, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v7, v0, v3 ; CHECK-NEXT: v_mul_hi_u32 v7, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v3, v1, v3 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, v1, v4 ; CHECK-NEXT: v_mul_lo_u32 v7, v1, v4
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; CHECK-NEXT: v_mul_hi_u32 v6, v0, v4 ; CHECK-NEXT: v_mul_hi_u32 v6, v0, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v7, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CHECK-NEXT: v_mul_lo_u32 v5, 0, v3 ; CHECK-NEXT: v_mul_lo_u32 v5, 0, v2
; CHECK-NEXT: v_mul_lo_u32 v4, s6, v4 ; CHECK-NEXT: v_mul_lo_u32 v4, s6, v4
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v3 ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v2
; CHECK-NEXT: v_mul_hi_u32 v3, s6, v3 ; CHECK-NEXT: v_mul_hi_u32 v2, s6, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; CHECK-NEXT: v_subb_u32_e64 v4, s[4:5], v1, v3, vcc ; CHECK-NEXT: v_subb_u32_e64 v4, s[4:5], v1, v2, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v3 ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5]
; CHECK-NEXT: v_mov_b32_e32 v5, s7 ; CHECK-NEXT: v_mov_b32_e32 v5, s7
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5]
; CHECK-NEXT: v_subrev_i32_e32 v5, vcc, s6, v0 ; CHECK-NEXT: v_subrev_i32_e32 v5, vcc, s6, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 ; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v5 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v5
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; CHECK-NEXT: v_mov_b32_e32 v7, s4 ; CHECK-NEXT: v_mov_b32_e32 v7, s4
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s6, v5 ; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s6, v5
; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v2 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = srem i64 %num, 4096 %result = srem i64 %num, 4096
ret i64 %result ret i64 %result
} }
define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) { define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) {
; GISEL-LABEL: v_srem_v2i64_pow2k_denom: ; GISEL-LABEL: v_srem_v2i64_pow2k_denom:
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_movk_i32 s10, 0x1000 ; GISEL-NEXT: s_movk_i32 s10, 0x1000
; GISEL-NEXT: s_add_u32 s4, s10, 0 ; GISEL-NEXT: s_add_u32 s4, s10, 0
; GISEL-NEXT: s_cselect_b32 s5, 1, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-NEXT: s_and_b32 s5, s5, 1 ; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: s_mov_b32 s6, 0 ; GISEL-NEXT: s_mov_b32 s6, 0
; GISEL-NEXT: s_cmp_lg_u32 s5, 0 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: s_mov_b32 s7, s6 ; GISEL-NEXT: s_mov_b32 s7, s6
; GISEL-NEXT: s_addc_u32 s5, 0, 0 ; GISEL-NEXT: s_addc_u32 s5, 0, 0
; GISEL-NEXT: s_xor_b64 s[8:9], s[4:5], s[6:7] ; GISEL-NEXT: s_xor_b64 s[8:9], s[4:5], s[6:7]
; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s8 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s8
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s9 ; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s9
; GISEL-NEXT: s_sub_u32 s11, 0, s8 ; GISEL-NEXT: s_sub_u32 s4, 0, s8
; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: s_subb_u32 s12, 0, s9 ; GISEL-NEXT: s_subb_u32 s5, 0, s9
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v1 ; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; GISEL-NEXT: v_trunc_f32_e32 v6, v6 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6
; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_mul_lo_u32 v7, s12, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v8, s11, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v10, s11, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_mul_lo_u32 v9, s11, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7 ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
Show All 10 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v6, v7, vcc ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, s12, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v10, s11, v8 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v12, s11, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_mul_lo_u32 v11, s11, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v7, v5, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v12, v7 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v5, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v11, v6, v7
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v10, v5, v7
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v1, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, v1, v5
; GISEL-NEXT: v_mul_lo_u32 v8, v0, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, v0, v6
; GISEL-NEXT: v_mul_hi_u32 v10, v0, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5
; GISEL-NEXT: v_mov_b32_e32 v9, s9 ; GISEL-NEXT: v_mov_b32_e32 v9, s9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; GISEL-NEXT: s_addc_u32 s5, 0, 0 ; GISEL-NEXT: s_addc_u32 s5, 0, 0
; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7] ; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7]
; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s6 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s6
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s7 ; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s7
; GISEL-NEXT: s_sub_u32 s8, 0, s6 ; GISEL-NEXT: s_sub_u32 s4, 0, s6
; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; GISEL-NEXT: s_subb_u32 s9, 0, s7 ; GISEL-NEXT: s_subb_u32 s5, 0, s7
; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; GISEL-NEXT: v_trunc_f32_e32 v6, v6 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6
; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4
; GISEL-NEXT: v_mul_lo_u32 v7, s9, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v8, s8, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_mul_hi_u32 v10, s8, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GISEL-NEXT: v_mul_lo_u32 v9, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7 ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
Show All 11 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v6, v7, vcc ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, s9, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v10, s8, v8 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v12, s8, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_mul_lo_u32 v11, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v7, v5, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v4 ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v4
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v12, v7 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v5, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v11, v6, v7
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v10, v5, v7
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v3, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, v3, v5
; GISEL-NEXT: v_mul_lo_u32 v8, v2, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, v2, v6
; GISEL-NEXT: v_mul_hi_u32 v10, v2, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, v2, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5
; GISEL-NEXT: v_mov_b32_e32 v9, s7 ; GISEL-NEXT: v_mov_b32_e32 v9, s7
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_srem_v2i64_pow2k_denom: ; CGP-LABEL: v_srem_v2i64_pow2k_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x1000 ; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x1000
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0 ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
; CGP-NEXT: s_movk_i32 s6, 0xf000 ; CGP-NEXT: s_movk_i32 s6, 0xf000
; CGP-NEXT: s_movk_i32 s7, 0x1000
; CGP-NEXT: v_mov_b32_e32 v4, v5
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v4
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1 ; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; CGP-NEXT: v_mov_b32_e32 v7, v5
; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7 ; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7 ; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7
; CGP-NEXT: v_trunc_f32_e32 v8, v8 ; CGP-NEXT: v_trunc_f32_e32 v8, v8
; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8 ; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 ; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v7
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: v_xor_b32_e32 v0, v0, v4 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_xor_b32_e32 v1, v1, v4 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_mul_hi_u32 v12, v7, v9
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, -1, v7
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7 ; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: s_movk_i32 s7, 0x1000 ; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000 ; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v8, v9 ; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_mul_hi_u32 v12, v7, v9 ; CGP-NEXT: v_mul_hi_u32 v12, v7, v9
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_mul_hi_u32 v9, v8, v9 ; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v8, v9, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v11, -1, v7
; CGP-NEXT: v_mul_lo_u32 v12, s6, v10
; CGP-NEXT: v_mul_hi_u32 v14, s6, v7
; CGP-NEXT: v_mul_lo_u32 v13, s6, v7
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
; CGP-NEXT: v_mul_lo_u32 v12, v10, v13
; CGP-NEXT: v_mul_lo_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v9, v7, v13
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; CGP-NEXT: v_mul_lo_u32 v12, v10, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v14, v9
; CGP-NEXT: v_mul_hi_u32 v14, v7, v11
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; CGP-NEXT: v_mul_hi_u32 v10, v10, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v12
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v9, v1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, v1, v7
; CGP-NEXT: v_mul_lo_u32 v10, v0, v8 ; CGP-NEXT: v_mul_lo_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v11, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v11, v0, v7
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_mul_hi_u32 v8, v7, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v7, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v10, -1, v5 ; CGP-NEXT: v_mul_lo_u32 v8, -1, v5
; CGP-NEXT: v_mul_lo_u32 v11, s6, v9 ; CGP-NEXT: v_mul_lo_u32 v9, s6, v7
; CGP-NEXT: v_mul_hi_u32 v13, s6, v5 ; CGP-NEXT: v_mul_hi_u32 v11, s6, v5
; CGP-NEXT: v_mul_lo_u32 v12, s6, v5 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v5
; CGP-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
; CGP-NEXT: v_mul_lo_u32 v11, v9, v12
; CGP-NEXT: v_mul_lo_u32 v13, v5, v10
; CGP-NEXT: v_mul_hi_u32 v8, v5, v12
; CGP-NEXT: v_mul_hi_u32 v12, v9, v12
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8 ; CGP-NEXT: v_mul_lo_u32 v9, v7, v10
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CGP-NEXT: v_mul_lo_u32 v11, v5, v8
; CGP-NEXT: v_mul_lo_u32 v11, v9, v10 ; CGP-NEXT: v_mul_hi_u32 v12, v5, v10
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v13, v8 ; CGP-NEXT: v_mul_hi_u32 v10, v7, v10
; CGP-NEXT: v_mul_hi_u32 v13, v5, v10
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; CGP-NEXT: v_mul_hi_u32 v9, v9, v10
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v12, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CGP-NEXT: v_xor_b32_e32 v3, v3, v6 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v6
; CGP-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v12, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; CGP-NEXT: v_mul_hi_u32 v11, v5, v8
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_mul_hi_u32 v8, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
; CGP-NEXT: v_xor_b32_e32 v1, v1, v4 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
; CGP-NEXT: v_mul_lo_u32 v8, v3, v5 ; CGP-NEXT: v_mul_lo_u32 v8, v3, v5
; CGP-NEXT: v_mul_lo_u32 v9, v2, v7 ; CGP-NEXT: v_mul_lo_u32 v9, v2, v7
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_hi_u32 v4, v2, v5 ; CGP-NEXT: v_mul_hi_u32 v4, v2, v5
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines; CGP-NEXT: s_setpc_b64 s[30:31]
%result = srem <2 x i64> %num, <i64 4096, i64 4096> %result = srem <2 x i64> %num, <i64 4096, i64 4096>
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_srem_i64_oddk_denom(i64 %num) { define i64 @v_srem_i64_oddk_denom(i64 %num) {
; CHECK-LABEL: v_srem_i64_oddk_denom: ; CHECK-LABEL: v_srem_i64_oddk_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, 0x12d8fb ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x12d8fb
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
; CHECK-NEXT: s_mov_b32 s6, 0xffed2705 ; CHECK-NEXT: s_mov_b32 s4, 0xffed2705
; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb
; CHECK-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 ; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v4, v4 ; CHECK-NEXT: v_trunc_f32_e32 v4, v4
; CHECK-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v2 ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v3 ; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4 ; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v8, s6, v3 ; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s6, v3 ; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s4, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000 ; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7 ; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v3, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v3, v7 ; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7 ; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5 ; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_mul_hi_u32 v8, v3, v5 ; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5 ; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e64 v6, s[4:5], v4, v5, vcc ; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, -1, v3 ; CHECK-NEXT: v_mul_lo_u32 v5, v1, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s6, v6
; CHECK-NEXT: v_mul_hi_u32 v10, s6, v3
; CHECK-NEXT: v_mul_lo_u32 v9, s6, v3
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v5
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v10
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v9
; CHECK-NEXT: v_mul_lo_u32 v10, v3, v7
; CHECK-NEXT: v_mul_hi_u32 v5, v3, v9
; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9
; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
; CHECK-NEXT: v_mul_hi_u32 v10, v3, v7
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; CHECK-NEXT: v_mul_hi_u32 v6, v6, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v9, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
; CHECK-NEXT: v_mul_lo_u32 v5, v1, v3
; CHECK-NEXT: v_mul_lo_u32 v6, v0, v4 ; CHECK-NEXT: v_mul_lo_u32 v6, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v7, v0, v3 ; CHECK-NEXT: v_mul_hi_u32 v7, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v3, v1, v3 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, v1, v4 ; CHECK-NEXT: v_mul_lo_u32 v7, v1, v4
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; CHECK-NEXT: v_mul_hi_u32 v6, v0, v4 ; CHECK-NEXT: v_mul_hi_u32 v6, v0, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v7, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v1, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CHECK-NEXT: v_mul_lo_u32 v5, 0, v3 ; CHECK-NEXT: v_mul_lo_u32 v5, 0, v2
; CHECK-NEXT: v_mul_lo_u32 v4, s6, v4 ; CHECK-NEXT: v_mul_lo_u32 v4, s6, v4
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v3 ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v2
; CHECK-NEXT: v_mul_hi_u32 v3, s6, v3 ; CHECK-NEXT: v_mul_hi_u32 v2, s6, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; CHECK-NEXT: v_subb_u32_e64 v4, s[4:5], v1, v3, vcc ; CHECK-NEXT: v_subb_u32_e64 v4, s[4:5], v1, v2, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v3 ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5]
; CHECK-NEXT: v_mov_b32_e32 v5, s7 ; CHECK-NEXT: v_mov_b32_e32 v5, s7
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[4:5]
; CHECK-NEXT: v_subrev_i32_e32 v5, vcc, s6, v0 ; CHECK-NEXT: v_subrev_i32_e32 v5, vcc, s6, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000 ; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v5 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v5
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; CHECK-NEXT: v_mov_b32_e32 v7, s4 ; CHECK-NEXT: v_mov_b32_e32 v7, s4
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s6, v5 ; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s6, v5
; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v2 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = srem i64 %num, 1235195 %result = srem i64 %num, 1235195
ret i64 %result ret i64 %result
} }
define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) { define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-LABEL: v_srem_v2i64_oddk_denom: ; GISEL-LABEL: v_srem_v2i64_oddk_denom:
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_mov_b32 s10, 0x12d8fb ; GISEL-NEXT: s_mov_b32 s10, 0x12d8fb
; GISEL-NEXT: s_add_u32 s4, s10, 0 ; GISEL-NEXT: s_add_u32 s4, s10, 0
; GISEL-NEXT: s_cselect_b32 s5, 1, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-NEXT: s_and_b32 s5, s5, 1 ; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: s_mov_b32 s6, 0 ; GISEL-NEXT: s_mov_b32 s6, 0
; GISEL-NEXT: s_cmp_lg_u32 s5, 0 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: s_mov_b32 s7, s6 ; GISEL-NEXT: s_mov_b32 s7, s6
; GISEL-NEXT: s_addc_u32 s5, 0, 0 ; GISEL-NEXT: s_addc_u32 s5, 0, 0
; GISEL-NEXT: s_xor_b64 s[8:9], s[4:5], s[6:7] ; GISEL-NEXT: s_xor_b64 s[8:9], s[4:5], s[6:7]
; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s8 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s8
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s9 ; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s9
; GISEL-NEXT: s_sub_u32 s11, 0, s8 ; GISEL-NEXT: s_sub_u32 s4, 0, s8
; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: s_subb_u32 s12, 0, s9 ; GISEL-NEXT: s_subb_u32 s5, 0, s9
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v1 ; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; GISEL-NEXT: v_trunc_f32_e32 v6, v6 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6
; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_mul_lo_u32 v7, s12, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v8, s11, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v10, s11, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_mul_lo_u32 v9, s11, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7 ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
Show All 10 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v6, v7, vcc ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, s12, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v10, s11, v8 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v12, s11, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_mul_lo_u32 v11, s11, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v7, v5, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v12, v7 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v5, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v11, v6, v7
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v10, v5, v7
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v1, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, v1, v5
; GISEL-NEXT: v_mul_lo_u32 v8, v0, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, v0, v6
; GISEL-NEXT: v_mul_hi_u32 v10, v0, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5
; GISEL-NEXT: v_mov_b32_e32 v9, s9 ; GISEL-NEXT: v_mov_b32_e32 v9, s9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; GISEL-NEXT: s_addc_u32 s5, 0, 0 ; GISEL-NEXT: s_addc_u32 s5, 0, 0
; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7] ; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7]
; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s6 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s6
; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s7 ; GISEL-NEXT: v_cvt_f32_u32_e32 v6, s7
; GISEL-NEXT: s_sub_u32 s8, 0, s6 ; GISEL-NEXT: s_sub_u32 s4, 0, s6
; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: s_and_b32 s5, s5, 1
; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; GISEL-NEXT: s_subb_u32 s9, 0, s7 ; GISEL-NEXT: s_subb_u32 s5, 0, s7
; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
; GISEL-NEXT: v_trunc_f32_e32 v6, v6 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6
; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5
; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4 ; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4
; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4 ; GISEL-NEXT: v_xor_b32_e32 v1, v1, v4
; GISEL-NEXT: v_mul_lo_u32 v7, s9, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v8, s8, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_mul_hi_u32 v10, s8, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GISEL-NEXT: v_mul_lo_u32 v9, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7 ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
Show All 11 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e64 v8, s[4:5], v6, v7, vcc ; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, s9, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, s5, v5
; GISEL-NEXT: v_mul_lo_u32 v10, s8, v8 ; GISEL-NEXT: v_mul_lo_u32 v8, s4, v6
; GISEL-NEXT: v_mul_hi_u32 v12, s8, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, s4, v5
; GISEL-NEXT: v_mul_lo_u32 v11, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, s4, v5
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v5, v9
; GISEL-NEXT: v_mul_hi_u32 v7, v5, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v4 ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v4
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v8, v6, v9
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v10, v5, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v9
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v12, v7 ; GISEL-NEXT: v_mul_hi_u32 v9, v6, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v5, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v11, v6, v7
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v9 ; GISEL-NEXT: v_mul_hi_u32 v10, v5, v7
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v3, v5 ; GISEL-NEXT: v_mul_lo_u32 v7, v3, v5
; GISEL-NEXT: v_mul_lo_u32 v8, v2, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, v2, v6
; GISEL-NEXT: v_mul_hi_u32 v10, v2, v5 ; GISEL-NEXT: v_mul_hi_u32 v10, v2, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5 ; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5
; GISEL-NEXT: v_mov_b32_e32 v9, s7 ; GISEL-NEXT: v_mov_b32_e32 v9, s7
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v10
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_srem_v2i64_oddk_denom: ; CGP-LABEL: v_srem_v2i64_oddk_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x12d8fb ; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x12d8fb
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0 ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
; CGP-NEXT: s_mov_b32 s6, 0xffed2705 ; CGP-NEXT: s_mov_b32 s6, 0xffed2705
; CGP-NEXT: s_mov_b32 s7, 0x12d8fb
; CGP-NEXT: v_mov_b32_e32 v4, v5
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v4
; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1 ; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; CGP-NEXT: v_mov_b32_e32 v7, v5
; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7 ; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7 ; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7
; CGP-NEXT: v_trunc_f32_e32 v8, v8 ; CGP-NEXT: v_trunc_f32_e32 v8, v8
; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8 ; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 ; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v7
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: v_xor_b32_e32 v0, v0, v4 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_xor_b32_e32 v1, v1, v4 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_mul_hi_u32 v12, v7, v9
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v9, -1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, -1, v7
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7 ; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: s_mov_b32 s7, 0x12d8fb ; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000 ; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v8, v9 ; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_mul_hi_u32 v12, v7, v9 ; CGP-NEXT: v_mul_hi_u32 v12, v7, v9
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_mul_hi_u32 v9, v8, v9 ; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v8, v9, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v11, -1, v7
; CGP-NEXT: v_mul_lo_u32 v12, s6, v10
; CGP-NEXT: v_mul_hi_u32 v14, s6, v7
; CGP-NEXT: v_mul_lo_u32 v13, s6, v7
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
; CGP-NEXT: v_mul_lo_u32 v12, v10, v13
; CGP-NEXT: v_mul_lo_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v9, v7, v13
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; CGP-NEXT: v_mul_lo_u32 v12, v10, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v14, v9
; CGP-NEXT: v_mul_hi_u32 v14, v7, v11
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; CGP-NEXT: v_mul_hi_u32 v10, v10, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v12
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v9, v1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, v1, v7
; CGP-NEXT: v_mul_lo_u32 v10, v0, v8 ; CGP-NEXT: v_mul_lo_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v11, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v11, v0, v7
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5 ; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_mul_hi_u32 v8, v7, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v7, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v10, -1, v5 ; CGP-NEXT: v_mul_lo_u32 v8, -1, v5
; CGP-NEXT: v_mul_lo_u32 v11, s6, v9 ; CGP-NEXT: v_mul_lo_u32 v9, s6, v7
; CGP-NEXT: v_mul_hi_u32 v13, s6, v5 ; CGP-NEXT: v_mul_hi_u32 v11, s6, v5
; CGP-NEXT: v_mul_lo_u32 v12, s6, v5 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v5
; CGP-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
; CGP-NEXT: v_mul_lo_u32 v11, v9, v12
; CGP-NEXT: v_mul_lo_u32 v13, v5, v10
; CGP-NEXT: v_mul_hi_u32 v8, v5, v12
; CGP-NEXT: v_mul_hi_u32 v12, v9, v12
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8 ; CGP-NEXT: v_mul_lo_u32 v9, v7, v10
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CGP-NEXT: v_mul_lo_u32 v11, v5, v8
; CGP-NEXT: v_mul_lo_u32 v11, v9, v10 ; CGP-NEXT: v_mul_hi_u32 v12, v5, v10
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v13, v8 ; CGP-NEXT: v_mul_hi_u32 v10, v7, v10
; CGP-NEXT: v_mul_hi_u32 v13, v5, v10
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; CGP-NEXT: v_mul_hi_u32 v9, v9, v10
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v12, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10
; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CGP-NEXT: v_xor_b32_e32 v3, v3, v6 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v6
; CGP-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v12, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; CGP-NEXT: v_mul_hi_u32 v11, v5, v8
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_mul_hi_u32 v8, v7, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
; CGP-NEXT: v_xor_b32_e32 v1, v1, v4 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
; CGP-NEXT: v_mul_lo_u32 v8, v3, v5 ; CGP-NEXT: v_mul_lo_u32 v8, v3, v5
; CGP-NEXT: v_mul_lo_u32 v9, v2, v7 ; CGP-NEXT: v_mul_lo_u32 v9, v2, v7
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; CGP-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_hi_u32 v4, v2, v5 ; CGP-NEXT: v_mul_hi_u32 v4, v2, v5
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CHECK-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB7_2 ; CHECK-NEXT: s_cbranch_execz BB7_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v6 ; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v6
; CHECK-NEXT: v_add_i32_e32 v1, vcc, v5, v0 ; CHECK-NEXT: v_add_i32_e32 v1, vcc, v5, v0
; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v6, v0, vcc ; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v6, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v5, v1, v0 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v0
; CHECK-NEXT: v_xor_b32_e32 v0, v2, v0 ; CHECK-NEXT: v_xor_b32_e32 v0, v2, v0
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v5 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v1
; CHECK-NEXT: v_cvt_f32_u32_e32 v6, v0 ; CHECK-NEXT: v_cvt_f32_u32_e32 v5, v0
; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v4 ; CHECK-NEXT: v_ashrrev_i32_e32 v6, 31, v4
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v1 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v6 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v5
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v1, vcc ; CHECK-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc
; CHECK-NEXT: v_sub_i32_e32 v7, vcc, 0, v5 ; CHECK-NEXT: v_sub_i32_e32 v7, vcc, 0, v1
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v6, 0x2f800000, v2 ; CHECK-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v6, v6 ; CHECK-NEXT: v_trunc_f32_e32 v5, v5
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v6 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v6, v6 ; CHECK-NEXT: v_cvt_u32_f32_e32 v5, v5
; CHECK-NEXT: v_subb_u32_e32 v8, vcc, 0, v0, vcc ; CHECK-NEXT: v_subb_u32_e32 v8, vcc, 0, v0, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v8, v2 ; CHECK-NEXT: v_mul_lo_u32 v9, v8, v2
; CHECK-NEXT: v_mul_lo_u32 v10, v7, v6 ; CHECK-NEXT: v_mul_lo_u32 v10, v7, v5
; CHECK-NEXT: v_mul_hi_u32 v12, v7, v2 ; CHECK-NEXT: v_mul_hi_u32 v12, v7, v2
; CHECK-NEXT: v_mul_lo_u32 v11, v7, v2 ; CHECK-NEXT: v_mul_lo_u32 v11, v7, v2
; CHECK-NEXT: v_xor_b32_e32 v3, v3, v1 ; CHECK-NEXT: v_xor_b32_e32 v3, v3, v6
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CHECK-NEXT: v_mul_lo_u32 v10, v6, v11 ; CHECK-NEXT: v_mul_lo_u32 v10, v5, v11
; CHECK-NEXT: v_mul_lo_u32 v12, v2, v9 ; CHECK-NEXT: v_mul_lo_u32 v12, v2, v9
; CHECK-NEXT: v_mul_hi_u32 v13, v2, v11 ; CHECK-NEXT: v_mul_hi_u32 v13, v2, v11
; CHECK-NEXT: v_mul_hi_u32 v11, v6, v11 ; CHECK-NEXT: v_mul_hi_u32 v11, v5, v11
; CHECK-NEXT: v_xor_b32_e32 v4, v4, v1 ; CHECK-NEXT: v_xor_b32_e32 v4, v4, v6
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v13 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v13, v6, v9 ; CHECK-NEXT: v_mul_lo_u32 v13, v5, v9
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v12, v10 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CHECK-NEXT: v_mul_hi_u32 v12, v2, v9 ; CHECK-NEXT: v_mul_hi_u32 v12, v2, v9
; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v11 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CHECK-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9 ; CHECK-NEXT: v_mul_hi_u32 v9, v5, v9
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v10 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v10
; CHECK-NEXT: v_addc_u32_e64 v10, s[4:5], v6, v9, vcc ; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc
; CHECK-NEXT: v_mul_lo_u32 v8, v8, v2 ; CHECK-NEXT: v_mul_lo_u32 v8, v8, v2
; CHECK-NEXT: v_mul_lo_u32 v11, v7, v10 ; CHECK-NEXT: v_mul_lo_u32 v9, v7, v5
; CHECK-NEXT: v_mul_lo_u32 v12, v7, v2 ; CHECK-NEXT: v_mul_lo_u32 v10, v7, v2
; CHECK-NEXT: v_mul_hi_u32 v7, v7, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, v7, v2
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v9 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v8, v7 ; CHECK-NEXT: v_mul_lo_u32 v8, v5, v10
; CHECK-NEXT: v_mul_lo_u32 v8, v10, v12 ; CHECK-NEXT: v_mul_lo_u32 v9, v2, v7
; CHECK-NEXT: v_mul_lo_u32 v11, v2, v7 ; CHECK-NEXT: v_mul_hi_u32 v11, v2, v10
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v12 ; CHECK-NEXT: v_mul_hi_u32 v10, v5, v10
; CHECK-NEXT: v_mul_hi_u32 v12, v10, v12 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CHECK-NEXT: v_mul_lo_u32 v11, v5, v7
; CHECK-NEXT: v_mul_lo_u32 v9, v10, v7 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8 ; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v11, v2, v7 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v9, v11 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; CHECK-NEXT: v_mul_hi_u32 v7, v5, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v10, v7 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v11, v9 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v9
; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; CHECK-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, v4, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, v4, v2
; CHECK-NEXT: v_mul_lo_u32 v8, v3, v6 ; CHECK-NEXT: v_mul_lo_u32 v8, v3, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v3, v2 ; CHECK-NEXT: v_mul_hi_u32 v9, v3, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v4, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v4, v2
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_mul_lo_u32 v9, v4, v6 ; CHECK-NEXT: v_mul_lo_u32 v9, v4, v5
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_mul_hi_u32 v8, v3, v6 ; CHECK-NEXT: v_mul_hi_u32 v8, v3, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_mul_hi_u32 v6, v4, v6 ; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_mul_lo_u32 v7, v0, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, v0, v2
; CHECK-NEXT: v_mul_lo_u32 v6, v5, v6 ; CHECK-NEXT: v_mul_lo_u32 v5, v1, v5
; CHECK-NEXT: v_mul_lo_u32 v8, v5, v2 ; CHECK-NEXT: v_mul_lo_u32 v8, v1, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v5, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v6, v2 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v3, v8 ; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v3, v8
; CHECK-NEXT: v_subb_u32_e64 v6, s[4:5], v4, v2, vcc ; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v4, v2, vcc
; CHECK-NEXT: v_sub_i32_e64 v2, s[4:5], v4, v2 ; CHECK-NEXT: v_sub_i32_e64 v2, s[4:5], v4, v2
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v0 ; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v0
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v5 ; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v1
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v0 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v0
; CHECK-NEXT: v_subb_u32_e32 v2, vcc, v2, v0, vcc ; CHECK-NEXT: v_subb_u32_e32 v2, vcc, v2, v0, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]
; CHECK-NEXT: v_sub_i32_e32 v7, vcc, v3, v5 ; CHECK-NEXT: v_sub_i32_e32 v7, vcc, v3, v1
; CHECK-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v2, vcc ; CHECK-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v2, vcc
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v0 ; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v0
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v5 ; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v1
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v0 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v0
; CHECK-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc ; CHECK-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc
; CHECK-NEXT: v_sub_i32_e32 v2, vcc, v7, v5 ; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v7, v1
; CHECK-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; CHECK-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CHECK-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; CHECK-NEXT: v_xor_b32_e32 v2, v2, v1 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v6
; CHECK-NEXT: v_xor_b32_e32 v3, v0, v1 ; CHECK-NEXT: v_xor_b32_e32 v2, v0, v6
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v2, v1 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v1, v6
; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc ; CHECK-NEXT: v_subb_u32_e32 v1, vcc, v2, v6, vcc
; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6 ; CHECK-NEXT: ; implicit-def: $vgpr5_vgpr6
; CHECK-NEXT: ; implicit-def: $vgpr3 ; CHECK-NEXT: ; implicit-def: $vgpr3
; CHECK-NEXT: BB7_2: ; %Flow ; CHECK-NEXT: BB7_2: ; %Flow
; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CHECK-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_xor_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_cbranch_execz BB7_4 ; CHECK-NEXT: s_cbranch_execz BB7_4
; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: ; %bb.3:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, v5
Show All 21 Lines; CHECK-NEXT: s_setpc_b64 s[30:31]
%r = srem i64 %x, %shl.y %r = srem i64 %x, %shl.y
ret i64 %r ret i64 %r
} }
define <2 x i64> @v_srem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @v_srem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
; GISEL-LABEL: v_srem_v2i64_pow2_shl_denom: ; GISEL-LABEL: v_srem_v2i64_pow2_shl_denom:
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_mov_b64 s[6:7], 0x1000 ; GISEL-NEXT: s_mov_b64 s[4:5], 0x1000
; GISEL-NEXT: v_lshl_b64 v[4:5], s[6:7], v4 ; GISEL-NEXT: v_lshl_b64 v[4:5], s[4:5], v4
; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v5 ; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v5
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc ; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
; GISEL-NEXT: v_xor_b32_e32 v8, v4, v7 ; GISEL-NEXT: v_xor_b32_e32 v8, v4, v7
; GISEL-NEXT: v_xor_b32_e32 v5, v5, v7 ; GISEL-NEXT: v_xor_b32_e32 v5, v5, v7
; GISEL-NEXT: v_cvt_f32_u32_e32 v7, v8 ; GISEL-NEXT: v_cvt_f32_u32_e32 v7, v8
; GISEL-NEXT: v_cvt_f32_u32_e32 v9, v5 ; GISEL-NEXT: v_cvt_f32_u32_e32 v9, v5
; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v1 ; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v1
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GISEL-NEXT: v_mac_f32_e32 v7, 0x4f800000, v9 ; GISEL-NEXT: v_mac_f32_e32 v7, 0x4f800000, v9
; GISEL-NEXT: v_rcp_iflag_f32_e32 v7, v7 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GISEL-NEXT: v_xor_b32_e32 v9, v0, v4
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; GISEL-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v7
; GISEL-NEXT: v_mul_f32_e32 v7, 0x2f800000, v0
; GISEL-NEXT: v_trunc_f32_e32 v7, v7
; GISEL-NEXT: v_mac_f32_e32 v0, 0xcf800000, v7
; GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
; GISEL-NEXT: v_sub_i32_e32 v10, vcc, 0, v8 ; GISEL-NEXT: v_sub_i32_e32 v10, vcc, 0, v8
; GISEL-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
; GISEL-NEXT: v_mul_f32_e32 v9, 0x2f800000, v7
; GISEL-NEXT: v_trunc_f32_e32 v9, v9
; GISEL-NEXT: v_mac_f32_e32 v7, 0xcf800000, v9
; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
; GISEL-NEXT: v_cvt_u32_f32_e32 v9, v9
; GISEL-NEXT: v_subb_u32_e32 v11, vcc, 0, v5, vcc ; GISEL-NEXT: v_subb_u32_e32 v11, vcc, 0, v5, vcc
; GISEL-NEXT: v_mul_lo_u32 v12, v11, v0 ; GISEL-NEXT: v_mul_lo_u32 v12, v11, v7
; GISEL-NEXT: v_mul_lo_u32 v13, v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v13, v10, v9
; GISEL-NEXT: v_mul_hi_u32 v15, v10, v0 ; GISEL-NEXT: v_mul_hi_u32 v15, v10, v7
; GISEL-NEXT: v_mul_lo_u32 v14, v10, v0 ; GISEL-NEXT: v_mul_lo_u32 v14, v10, v7
; GISEL-NEXT: v_xor_b32_e32 v16, v1, v4 ; GISEL-NEXT: v_xor_b32_e32 v16, v0, v4
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; GISEL-NEXT: v_mul_lo_u32 v13, v7, v14 ; GISEL-NEXT: v_mul_lo_u32 v13, v9, v14
; GISEL-NEXT: v_mul_lo_u32 v15, v0, v12 ; GISEL-NEXT: v_mul_lo_u32 v15, v7, v12
; GISEL-NEXT: v_mul_hi_u32 v1, v0, v14 ; GISEL-NEXT: v_mul_hi_u32 v0, v7, v14
; GISEL-NEXT: v_mul_hi_u32 v14, v7, v14 ; GISEL-NEXT: v_mul_hi_u32 v14, v9, v14
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v13, v1 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v13, v0
; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v13, v7, v12 ; GISEL-NEXT: v_mul_lo_u32 v13, v9, v12
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v15, v1 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v15, v0
; GISEL-NEXT: v_mul_hi_u32 v15, v0, v12 ; GISEL-NEXT: v_mul_hi_u32 v15, v7, v12
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v15 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v15
; GISEL-NEXT: v_mul_hi_u32 v12, v7, v12 ; GISEL-NEXT: v_mul_hi_u32 v12, v9, v12
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v13, v1 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v13, v0
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v7, v0
; GISEL-NEXT: v_addc_u32_e64 v1, s[4:5], v7, v12, vcc ; GISEL-NEXT: v_addc_u32_e32 v7, vcc, v9, v12, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, v11, v0 ; GISEL-NEXT: v_mul_lo_u32 v9, v11, v0
; GISEL-NEXT: v_mul_lo_u32 v13, v10, v1 ; GISEL-NEXT: v_mul_lo_u32 v11, v10, v7
; GISEL-NEXT: v_mul_lo_u32 v14, v10, v0 ; GISEL-NEXT: v_mul_lo_u32 v12, v10, v0
; GISEL-NEXT: v_mul_hi_u32 v10, v10, v0 ; GISEL-NEXT: v_mul_hi_u32 v10, v10, v0
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v7, v12 ; GISEL-NEXT: v_xor_b32_e32 v13, v1, v4
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_mul_lo_u32 v11, v1, v14 ; GISEL-NEXT: v_mul_lo_u32 v10, v7, v12
; GISEL-NEXT: v_mul_lo_u32 v13, v0, v10 ; GISEL-NEXT: v_mul_lo_u32 v11, v0, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v0, v14 ; GISEL-NEXT: v_mul_hi_u32 v1, v0, v12
; GISEL-NEXT: v_mul_hi_u32 v14, v1, v14 ; GISEL-NEXT: v_mul_hi_u32 v12, v7, v12
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v10, v1
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v12, v1, v10 ; GISEL-NEXT: v_mul_lo_u32 v10, v7, v9
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v13, v11 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v11, v1
; GISEL-NEXT: v_mul_hi_u32 v13, v0, v10 ; GISEL-NEXT: v_mul_hi_u32 v11, v0, v9
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13
; GISEL-NEXT: v_mul_hi_u32 v1, v1, v10
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v13, v12
; GISEL-NEXT: v_add_i32_e64 v1, s[4:5], v1, v10
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v0, v11
; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, v16, v7
; GISEL-NEXT: v_mul_lo_u32 v12, v9, v10
; GISEL-NEXT: v_lshl_b64 v[0:1], s[6:7], v6
; GISEL-NEXT: v_mul_hi_u32 v6, v9, v7
; GISEL-NEXT: v_mul_hi_u32 v7, v16, v7
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v11, v6 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_mul_hi_u32 v9, v7, v9
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v10, v1
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v0, v1
; GISEL-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, v13, v10
; GISEL-NEXT: v_mul_lo_u32 v11, v16, v7
; GISEL-NEXT: v_lshl_b64 v[0:1], s[4:5], v6
; GISEL-NEXT: v_mul_hi_u32 v6, v16, v10
; GISEL-NEXT: v_mul_hi_u32 v10, v13, v10
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, v16, v10 ; GISEL-NEXT: v_mul_lo_u32 v9, v13, v7
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v12, v6 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v11, v6
; GISEL-NEXT: v_mul_hi_u32 v12, v9, v10 ; GISEL-NEXT: v_mul_hi_u32 v11, v16, v7
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v11, v7 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v12 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_mul_hi_u32 v7, v13, v7
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GISEL-NEXT: v_mul_hi_u32 v10, v16, v10 ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v11, v7 ; GISEL-NEXT: v_mul_lo_u32 v9, v5, v6
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v6
; GISEL-NEXT: v_mul_lo_u32 v7, v8, v7 ; GISEL-NEXT: v_mul_lo_u32 v7, v8, v7
; GISEL-NEXT: v_mul_lo_u32 v11, v8, v6 ; GISEL-NEXT: v_mul_lo_u32 v10, v8, v6
; GISEL-NEXT: v_mul_hi_u32 v6, v8, v6 ; GISEL-NEXT: v_mul_hi_u32 v6, v8, v6
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v10, v7 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v9, v11 ; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v16, v10
; GISEL-NEXT: v_subb_u32_e64 v9, s[4:5], v16, v6, vcc ; GISEL-NEXT: v_subb_u32_e64 v9, s[4:5], v13, v6, vcc
; GISEL-NEXT: v_sub_i32_e64 v6, s[4:5], v16, v6 ; GISEL-NEXT: v_sub_i32_e64 v6, s[4:5], v13, v6
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v5 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v5
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v8 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v5 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v5
; GISEL-NEXT: v_subb_u32_e32 v6, vcc, v6, v5, vcc ; GISEL-NEXT: v_subb_u32_e32 v6, vcc, v6, v5, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v7, v8 ; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v7, v8
Show All 23 Lines
; GISEL-NEXT: v_ashrrev_i32_e32 v9, 31, v3 ; GISEL-NEXT: v_ashrrev_i32_e32 v9, 31, v3
; GISEL-NEXT: v_xor_b32_e32 v6, v6, v4 ; GISEL-NEXT: v_xor_b32_e32 v6, v6, v4
; GISEL-NEXT: v_xor_b32_e32 v5, v5, v4 ; GISEL-NEXT: v_xor_b32_e32 v5, v5, v4
; GISEL-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GISEL-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GISEL-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v2, v9 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v2, v9
; GISEL-NEXT: v_addc_u32_e32 v2, vcc, v3, v9, vcc ; GISEL-NEXT: v_addc_u32_e32 v2, vcc, v3, v9, vcc
; GISEL-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GISEL-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GISEL-NEXT: v_xor_b32_e32 v3, v1, v9 ; GISEL-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
; GISEL-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GISEL-NEXT: v_trunc_f32_e32 v3, v3
; GISEL-NEXT: v_trunc_f32_e32 v1, v1 ; GISEL-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
; GISEL-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GISEL-NEXT: v_cvt_u32_f32_e32 v0, v0
; GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GISEL-NEXT: v_cvt_u32_f32_e32 v3, v3
; GISEL-NEXT: v_sub_i32_e32 v10, vcc, 0, v8 ; GISEL-NEXT: v_sub_i32_e32 v10, vcc, 0, v8
; GISEL-NEXT: v_subb_u32_e32 v11, vcc, 0, v7, vcc ; GISEL-NEXT: v_subb_u32_e32 v11, vcc, 0, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v12, v11, v0 ; GISEL-NEXT: v_mul_lo_u32 v12, v11, v0
; GISEL-NEXT: v_mul_lo_u32 v13, v10, v1 ; GISEL-NEXT: v_mul_lo_u32 v13, v10, v3
; GISEL-NEXT: v_mul_hi_u32 v15, v10, v0 ; GISEL-NEXT: v_mul_hi_u32 v15, v10, v0
; GISEL-NEXT: v_mul_lo_u32 v14, v10, v0 ; GISEL-NEXT: v_mul_lo_u32 v14, v10, v0
; GISEL-NEXT: v_xor_b32_e32 v2, v2, v9 ; GISEL-NEXT: v_xor_b32_e32 v16, v1, v9
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; GISEL-NEXT: v_mul_lo_u32 v13, v1, v14 ; GISEL-NEXT: v_mul_lo_u32 v13, v3, v14
; GISEL-NEXT: v_mul_lo_u32 v15, v0, v12 ; GISEL-NEXT: v_mul_lo_u32 v15, v0, v12
; GISEL-NEXT: v_mul_hi_u32 v16, v0, v14 ; GISEL-NEXT: v_mul_hi_u32 v1, v0, v14
; GISEL-NEXT: v_mul_hi_u32 v14, v1, v14 ; GISEL-NEXT: v_mul_hi_u32 v14, v3, v14
; GISEL-NEXT: v_xor_b32_e32 v2, v2, v9
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v16 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v13, v1
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v16, v1, v12 ; GISEL-NEXT: v_mul_lo_u32 v13, v3, v12
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v15, v13 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, v15, v1
; GISEL-NEXT: v_mul_hi_u32 v15, v0, v12 ; GISEL-NEXT: v_mul_hi_u32 v15, v0, v12
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v16, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v15 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v16, v15 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v15
; GISEL-NEXT: v_mul_hi_u32 v12, v1, v12 ; GISEL-NEXT: v_mul_hi_u32 v12, v3, v12
; GISEL-NEXT: v_add_i32_e32 v1, vcc, v13, v1
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v3, v12, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v13 ; GISEL-NEXT: v_mul_lo_u32 v3, v11, v0
; GISEL-NEXT: v_addc_u32_e64 v13, s[4:5], v1, v12, vcc ; GISEL-NEXT: v_mul_lo_u32 v11, v10, v1
; GISEL-NEXT: v_mul_lo_u32 v11, v11, v0 ; GISEL-NEXT: v_mul_lo_u32 v12, v10, v0
; GISEL-NEXT: v_mul_lo_u32 v14, v10, v13
; GISEL-NEXT: v_mul_lo_u32 v15, v10, v0
; GISEL-NEXT: v_mul_hi_u32 v10, v10, v0 ; GISEL-NEXT: v_mul_hi_u32 v10, v10, v0
; GISEL-NEXT: v_add_i32_e64 v1, s[4:5], v1, v12 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v11
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; GISEL-NEXT: v_mul_lo_u32 v10, v1, v12
; GISEL-NEXT: v_mul_lo_u32 v11, v13, v15 ; GISEL-NEXT: v_mul_lo_u32 v11, v0, v3
; GISEL-NEXT: v_mul_lo_u32 v14, v0, v10 ; GISEL-NEXT: v_mul_hi_u32 v13, v0, v12
; GISEL-NEXT: v_mul_hi_u32 v12, v0, v15 ; GISEL-NEXT: v_mul_hi_u32 v12, v1, v12
; GISEL-NEXT: v_mul_hi_u32 v15, v13, v15 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v13, v1, v3
; GISEL-NEXT: v_mul_lo_u32 v12, v13, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v14, v11 ; GISEL-NEXT: v_mul_hi_u32 v11, v0, v3
; GISEL-NEXT: v_mul_hi_u32 v14, v0, v10 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15 ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v15, v14 ; GISEL-NEXT: v_mul_hi_u32 v3, v1, v3
; GISEL-NEXT: v_mul_hi_u32 v10, v13, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v11
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v0, v10
; GISEL-NEXT: v_addc_u32_e32 v1, vcc, v1, v10, vcc ; GISEL-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v0, v11 ; GISEL-NEXT: v_mul_lo_u32 v11, v2, v10
; GISEL-NEXT: v_addc_u32_e32 v11, vcc, 0, v1, vcc ; GISEL-NEXT: v_mul_lo_u32 v12, v16, v3
; GISEL-NEXT: v_mul_lo_u32 v12, v2, v10
; GISEL-NEXT: v_mul_lo_u32 v13, v3, v11
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v6, v4 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v6, v4
; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v5, v4, vcc ; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v5, v4, vcc
; GISEL-NEXT: v_mul_hi_u32 v4, v3, v10 ; GISEL-NEXT: v_mul_hi_u32 v4, v16, v10
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v12, v13 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v11, v12
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v5, v2, v11 ; GISEL-NEXT: v_mul_lo_u32 v5, v2, v3
; GISEL-NEXT: v_mul_hi_u32 v10, v2, v10 ; GISEL-NEXT: v_mul_hi_u32 v10, v2, v10
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GISEL-NEXT: v_mul_hi_u32 v6, v3, v11 ; GISEL-NEXT: v_mul_hi_u32 v6, v16, v3
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v10 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v10
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v10, v6 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v10, v6
; GISEL-NEXT: v_mul_hi_u32 v10, v2, v11 ; GISEL-NEXT: v_mul_hi_u32 v3, v2, v3
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v10, v5 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GISEL-NEXT: v_mul_lo_u32 v6, v7, v4 ; GISEL-NEXT: v_mul_lo_u32 v5, v7, v4
; GISEL-NEXT: v_mul_lo_u32 v5, v8, v5 ; GISEL-NEXT: v_mul_lo_u32 v3, v8, v3
; GISEL-NEXT: v_mul_lo_u32 v10, v8, v4 ; GISEL-NEXT: v_mul_lo_u32 v6, v8, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v8, v4 ; GISEL-NEXT: v_mul_hi_u32 v4, v8, v4
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v3, v10 ; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v16, v6
; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v2, v4, vcc ; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v2, v3, vcc
; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v4 ; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v3
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v7 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v7
; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v8 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v8
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v7 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v7
; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v3, v8 ; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v4, v8
; GISEL-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v2, vcc ; GISEL-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v2, vcc
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v7 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v7
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v8 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v8
; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v10, v7 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v10, v7
; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v6, v8 ; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v6, v8
; GISEL-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[4:5]
; GISEL-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v3, v4, v6, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v9 ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v9
; GISEL-NEXT: v_xor_b32_e32 v4, v2, v9 ; GISEL-NEXT: v_xor_b32_e32 v4, v2, v9
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v3, v9 ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v3, v9
; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v4, v9, vcc ; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v4, v9, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_srem_v2i64_pow2_shl_denom: ; CGP-LABEL: v_srem_v2i64_pow2_shl_denom:
Show All 12 Lines
; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1 ; CGP-NEXT: ; implicit-def: $vgpr0_vgpr1
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_2 ; CGP-NEXT: s_cbranch_execz BB8_2
; CGP-NEXT: ; %bb.1: ; CGP-NEXT: ; %bb.1:
; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; CGP-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; CGP-NEXT: v_add_i32_e32 v1, vcc, v2, v0 ; CGP-NEXT: v_add_i32_e32 v1, vcc, v2, v0
; CGP-NEXT: v_addc_u32_e32 v2, vcc, v3, v0, vcc ; CGP-NEXT: v_addc_u32_e32 v2, vcc, v3, v0, vcc
; CGP-NEXT: v_xor_b32_e32 v3, v1, v0 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v0
; CGP-NEXT: v_xor_b32_e32 v0, v2, v0 ; CGP-NEXT: v_xor_b32_e32 v0, v2, v0
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v3 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v0 ; CGP-NEXT: v_cvt_f32_u32_e32 v3, v0
; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v9 ; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v9
; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4 ; CGP-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CGP-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CGP-NEXT: v_add_i32_e32 v4, vcc, v8, v1 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v8, v4
; CGP-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc ; CGP-NEXT: v_addc_u32_e32 v6, vcc, v9, v4, vcc
; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CGP-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v2 ; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v2
; CGP-NEXT: v_trunc_f32_e32 v8, v8 ; CGP-NEXT: v_trunc_f32_e32 v8, v8
; CGP-NEXT: v_mac_f32_e32 v2, 0xcf800000, v8 ; CGP-NEXT: v_mac_f32_e32 v2, 0xcf800000, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 ; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_sub_i32_e32 v9, vcc, 0, v3 ; CGP-NEXT: v_sub_i32_e32 v9, vcc, 0, v1
; CGP-NEXT: v_subb_u32_e32 v12, vcc, 0, v0, vcc ; CGP-NEXT: v_subb_u32_e32 v12, vcc, 0, v0, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v12, v2 ; CGP-NEXT: v_mul_lo_u32 v13, v12, v2
; CGP-NEXT: v_mul_lo_u32 v14, v9, v8 ; CGP-NEXT: v_mul_lo_u32 v14, v9, v8
; CGP-NEXT: v_mul_hi_u32 v16, v9, v2 ; CGP-NEXT: v_mul_hi_u32 v16, v9, v2
; CGP-NEXT: v_mul_lo_u32 v15, v9, v2 ; CGP-NEXT: v_mul_lo_u32 v15, v9, v2
; CGP-NEXT: v_xor_b32_e32 v4, v4, v1 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v4
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v16 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v16
; CGP-NEXT: v_mul_lo_u32 v14, v8, v15 ; CGP-NEXT: v_mul_lo_u32 v14, v8, v15
; CGP-NEXT: v_mul_lo_u32 v16, v2, v13 ; CGP-NEXT: v_mul_lo_u32 v16, v2, v13
; CGP-NEXT: v_mul_hi_u32 v17, v2, v15 ; CGP-NEXT: v_mul_hi_u32 v17, v2, v15
; CGP-NEXT: v_mul_hi_u32 v15, v8, v15 ; CGP-NEXT: v_mul_hi_u32 v15, v8, v15
; CGP-NEXT: v_xor_b32_e32 v6, v6, v1 ; CGP-NEXT: v_xor_b32_e32 v6, v6, v4
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v16 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v16
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v17 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v17
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v17, v8, v13 ; CGP-NEXT: v_mul_lo_u32 v17, v8, v13
; CGP-NEXT: v_add_i32_e32 v14, vcc, v16, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v16, v14
; CGP-NEXT: v_mul_hi_u32 v16, v2, v13 ; CGP-NEXT: v_mul_hi_u32 v16, v2, v13
; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v15 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v15
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v16 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16 ; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; CGP-NEXT: v_mul_hi_u32 v13, v8, v13 ; CGP-NEXT: v_mul_hi_u32 v13, v8, v13
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v16, v15
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v14 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v14
; CGP-NEXT: v_addc_u32_e64 v14, s[4:5], v8, v13, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc
; CGP-NEXT: v_mul_lo_u32 v12, v12, v2 ; CGP-NEXT: v_mul_lo_u32 v12, v12, v2
; CGP-NEXT: v_mul_lo_u32 v15, v9, v14 ; CGP-NEXT: v_mul_lo_u32 v13, v9, v8
; CGP-NEXT: v_mul_lo_u32 v16, v9, v2 ; CGP-NEXT: v_mul_lo_u32 v14, v9, v2
; CGP-NEXT: v_mul_hi_u32 v9, v9, v2 ; CGP-NEXT: v_mul_hi_u32 v9, v9, v2
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v13 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v12, v9
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; CGP-NEXT: v_mul_lo_u32 v12, v8, v14
; CGP-NEXT: v_mul_lo_u32 v12, v14, v16 ; CGP-NEXT: v_mul_lo_u32 v13, v2, v9
; CGP-NEXT: v_mul_lo_u32 v15, v2, v9 ; CGP-NEXT: v_mul_hi_u32 v15, v2, v14
; CGP-NEXT: v_mul_hi_u32 v13, v2, v16 ; CGP-NEXT: v_mul_hi_u32 v14, v8, v14
; CGP-NEXT: v_mul_hi_u32 v16, v14, v16 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v15 ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_mul_lo_u32 v15, v8, v9
; CGP-NEXT: v_mul_lo_u32 v13, v14, v9 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v15, v12 ; CGP-NEXT: v_mul_hi_u32 v13, v2, v9
; CGP-NEXT: v_mul_hi_u32 v15, v2, v9 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v16 ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v15 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e64 v15, s[4:5], v16, v15 ; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_mul_hi_u32 v9, v14, v9 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v15, v13 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v13
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12
; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v9, v6, v2 ; CGP-NEXT: v_mul_lo_u32 v9, v6, v2
; CGP-NEXT: v_mul_lo_u32 v12, v4, v8 ; CGP-NEXT: v_mul_lo_u32 v12, v3, v8
; CGP-NEXT: v_mul_hi_u32 v13, v4, v2 ; CGP-NEXT: v_mul_hi_u32 v13, v3, v2
; CGP-NEXT: v_mul_hi_u32 v2, v6, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v6, v2
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v13 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v13
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v6, v8 ; CGP-NEXT: v_mul_lo_u32 v13, v6, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v12, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v12, v9
; CGP-NEXT: v_mul_hi_u32 v12, v4, v8 ; CGP-NEXT: v_mul_hi_u32 v12, v3, v8
; CGP-NEXT: v_add_i32_e32 v2, vcc, v13, v2 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v13, v2
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_mul_hi_u32 v8, v6, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v6, v8
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v9 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v12, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v12, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_mul_lo_u32 v9, v0, v2 ; CGP-NEXT: v_mul_lo_u32 v9, v0, v2
; CGP-NEXT: v_mul_lo_u32 v8, v3, v8 ; CGP-NEXT: v_mul_lo_u32 v8, v1, v8
; CGP-NEXT: v_mul_lo_u32 v12, v3, v2 ; CGP-NEXT: v_mul_lo_u32 v12, v1, v2
; CGP-NEXT: v_mul_hi_u32 v2, v3, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v1, v2
; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_add_i32_e32 v2, vcc, v8, v2 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v8, v2
; CGP-NEXT: v_sub_i32_e32 v4, vcc, v4, v12 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v3, v12
; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v6, v2, vcc ; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v6, v2, vcc
; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v6, v2 ; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v6, v2
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v0 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v0
; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v3 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v1
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v0 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v0
; CGP-NEXT: v_subb_u32_e32 v2, vcc, v2, v0, vcc ; CGP-NEXT: v_subb_u32_e32 v2, vcc, v2, v0, vcc
; CGP-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[4:5]
; CGP-NEXT: v_sub_i32_e32 v9, vcc, v4, v3 ; CGP-NEXT: v_sub_i32_e32 v9, vcc, v3, v1
; CGP-NEXT: v_subbrev_u32_e64 v12, s[4:5], 0, v2, vcc ; CGP-NEXT: v_subbrev_u32_e64 v12, s[4:5], 0, v2, vcc
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v12, v0 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v12, v0
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v3 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v1
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v12, v0 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v12, v0
; CGP-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc ; CGP-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v9, v3 ; CGP-NEXT: v_sub_i32_e32 v1, vcc, v9, v1
; CGP-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[4:5]
; CGP-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc ; CGP-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; CGP-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CGP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; CGP-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
; CGP-NEXT: v_xor_b32_e32 v2, v2, v1 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v4
; CGP-NEXT: v_xor_b32_e32 v3, v0, v1 ; CGP-NEXT: v_xor_b32_e32 v2, v0, v4
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v2, v1 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v1, v4
; CGP-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc ; CGP-NEXT: v_subb_u32_e32 v1, vcc, v2, v4, vcc
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: ; implicit-def: $vgpr8 ; CGP-NEXT: ; implicit-def: $vgpr8
; CGP-NEXT: BB8_2: ; %Flow2 ; CGP-NEXT: BB8_2: ; %Flow2
; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5] ; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_4 ; CGP-NEXT: s_cbranch_execz BB8_4
; CGP-NEXT: ; %bb.3: ; CGP-NEXT: ; %bb.3:
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v0, v2
Show All 22 Lines
; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3 ; CGP-NEXT: ; implicit-def: $vgpr2_vgpr3
; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CGP-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5] ; CGP-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_6 ; CGP-NEXT: s_cbranch_execz BB8_6
; CGP-NEXT: ; %bb.5: ; CGP-NEXT: ; %bb.5:
; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v11 ; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v11
; CGP-NEXT: v_add_i32_e32 v3, vcc, v10, v2 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v10, v2
; CGP-NEXT: v_addc_u32_e32 v4, vcc, v11, v2, vcc ; CGP-NEXT: v_addc_u32_e32 v4, vcc, v11, v2, vcc
; CGP-NEXT: v_xor_b32_e32 v6, v3, v2 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v2
; CGP-NEXT: v_xor_b32_e32 v2, v4, v2 ; CGP-NEXT: v_xor_b32_e32 v2, v4, v2
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v6 ; CGP-NEXT: v_cvt_f32_u32_e32 v4, v3
; CGP-NEXT: v_cvt_f32_u32_e32 v8, v2 ; CGP-NEXT: v_cvt_f32_u32_e32 v6, v2
; CGP-NEXT: v_ashrrev_i32_e32 v3, 31, v7 ; CGP-NEXT: v_ashrrev_i32_e32 v8, 31, v7
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v3 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v8 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v3, vcc ; CGP-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc
; CGP-NEXT: v_sub_i32_e32 v9, vcc, 0, v6 ; CGP-NEXT: v_sub_i32_e32 v9, vcc, 0, v3
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v4 ; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4
; CGP-NEXT: v_trunc_f32_e32 v8, v8 ; CGP-NEXT: v_trunc_f32_e32 v7, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v8 ; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_subb_u32_e32 v10, vcc, 0, v2, vcc ; CGP-NEXT: v_subb_u32_e32 v10, vcc, 0, v2, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v10, v4 ; CGP-NEXT: v_mul_lo_u32 v11, v10, v4
; CGP-NEXT: v_mul_lo_u32 v12, v9, v8 ; CGP-NEXT: v_mul_lo_u32 v12, v9, v7
; CGP-NEXT: v_mul_hi_u32 v14, v9, v4 ; CGP-NEXT: v_mul_hi_u32 v14, v9, v4
; CGP-NEXT: v_mul_lo_u32 v13, v9, v4 ; CGP-NEXT: v_mul_lo_u32 v13, v9, v4
; CGP-NEXT: v_xor_b32_e32 v5, v5, v3 ; CGP-NEXT: v_xor_b32_e32 v5, v5, v8
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v14 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; CGP-NEXT: v_mul_lo_u32 v12, v8, v13 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v13
; CGP-NEXT: v_mul_lo_u32 v14, v4, v11 ; CGP-NEXT: v_mul_lo_u32 v14, v4, v11
; CGP-NEXT: v_mul_hi_u32 v15, v4, v13 ; CGP-NEXT: v_mul_hi_u32 v15, v4, v13
; CGP-NEXT: v_mul_hi_u32 v13, v8, v13 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v13
; CGP-NEXT: v_xor_b32_e32 v7, v7, v3 ; CGP-NEXT: v_xor_b32_e32 v6, v6, v8
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v15, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v15, v7, v11
; CGP-NEXT: v_add_i32_e32 v12, vcc, v14, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v14, v12
; CGP-NEXT: v_mul_hi_u32 v14, v4, v11 ; CGP-NEXT: v_mul_hi_u32 v14, v4, v11
; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v13 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v13
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v7, v11
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v13 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v12
; CGP-NEXT: v_addc_u32_e64 v12, s[4:5], v8, v11, vcc ; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v11, vcc
; CGP-NEXT: v_mul_lo_u32 v10, v10, v4 ; CGP-NEXT: v_mul_lo_u32 v10, v10, v4
; CGP-NEXT: v_mul_lo_u32 v13, v9, v12 ; CGP-NEXT: v_mul_lo_u32 v11, v9, v7
; CGP-NEXT: v_mul_lo_u32 v14, v9, v4 ; CGP-NEXT: v_mul_lo_u32 v12, v9, v4
; CGP-NEXT: v_mul_hi_u32 v9, v9, v4 ; CGP-NEXT: v_mul_hi_u32 v9, v9, v4
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v10, v9 ; CGP-NEXT: v_mul_lo_u32 v10, v7, v12
; CGP-NEXT: v_mul_lo_u32 v10, v12, v14 ; CGP-NEXT: v_mul_lo_u32 v11, v4, v9
; CGP-NEXT: v_mul_lo_u32 v13, v4, v9 ; CGP-NEXT: v_mul_hi_u32 v13, v4, v12
; CGP-NEXT: v_mul_hi_u32 v11, v4, v14 ; CGP-NEXT: v_mul_hi_u32 v12, v7, v12
; CGP-NEXT: v_mul_hi_u32 v14, v12, v14 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CGP-NEXT: v_mul_lo_u32 v13, v7, v9
; CGP-NEXT: v_mul_lo_u32 v11, v12, v9 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v13, v10 ; CGP-NEXT: v_mul_hi_u32 v11, v4, v9
; CGP-NEXT: v_mul_hi_u32 v13, v4, v9 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; CGP-NEXT: v_mul_hi_u32 v9, v7, v9
; CGP-NEXT: v_mul_hi_u32 v9, v12, v9 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v11
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v9, vcc
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v9, v7, v4 ; CGP-NEXT: v_mul_lo_u32 v9, v6, v4
; CGP-NEXT: v_mul_lo_u32 v10, v5, v8 ; CGP-NEXT: v_mul_lo_u32 v10, v5, v7
; CGP-NEXT: v_mul_hi_u32 v11, v5, v4 ; CGP-NEXT: v_mul_hi_u32 v11, v5, v4
; CGP-NEXT: v_mul_hi_u32 v4, v7, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v6, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v7, v8 ; CGP-NEXT: v_mul_lo_u32 v11, v6, v7
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_mul_hi_u32 v10, v5, v8 ; CGP-NEXT: v_mul_hi_u32 v10, v5, v7
; CGP-NEXT: v_add_i32_e32 v4, vcc, v11, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v11, v4
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_mul_hi_u32 v8, v7, v8 ; CGP-NEXT: v_mul_hi_u32 v7, v6, v7
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_mul_lo_u32 v9, v2, v4 ; CGP-NEXT: v_mul_lo_u32 v9, v2, v4
; CGP-NEXT: v_mul_lo_u32 v8, v6, v8 ; CGP-NEXT: v_mul_lo_u32 v7, v3, v7
; CGP-NEXT: v_mul_lo_u32 v10, v6, v4 ; CGP-NEXT: v_mul_lo_u32 v10, v3, v4
; CGP-NEXT: v_mul_hi_u32 v4, v6, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; CGP-NEXT: v_add_i32_e32 v4, vcc, v8, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CGP-NEXT: v_sub_i32_e32 v5, vcc, v5, v10 ; CGP-NEXT: v_sub_i32_e32 v5, vcc, v5, v10
; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v7, v4, vcc ; CGP-NEXT: v_subb_u32_e64 v7, s[4:5], v6, v4, vcc
; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v7, v4 ; CGP-NEXT: v_sub_i32_e64 v4, s[4:5], v6, v4
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v2 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v2
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v6 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v3
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v8, v2 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v2
; CGP-NEXT: v_subb_u32_e32 v4, vcc, v4, v2, vcc ; CGP-NEXT: v_subb_u32_e32 v4, vcc, v4, v2, vcc
; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[4:5]
; CGP-NEXT: v_sub_i32_e32 v9, vcc, v5, v6 ; CGP-NEXT: v_sub_i32_e32 v9, vcc, v5, v3
; CGP-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v4, vcc ; CGP-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v4, vcc
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v2 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v2
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v6 ; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v3
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v10, v2 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], v10, v2
; CGP-NEXT: v_subb_u32_e32 v2, vcc, v4, v2, vcc ; CGP-NEXT: v_subb_u32_e32 v2, vcc, v4, v2, vcc
; CGP-NEXT: v_sub_i32_e32 v4, vcc, v9, v6 ; CGP-NEXT: v_sub_i32_e32 v3, vcc, v9, v3
; CGP-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[4:5]
; CGP-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc ; CGP-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; CGP-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; CGP-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; CGP-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
; CGP-NEXT: v_xor_b32_e32 v4, v4, v3 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v8
; CGP-NEXT: v_xor_b32_e32 v5, v2, v3 ; CGP-NEXT: v_xor_b32_e32 v4, v2, v8
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v4, v3 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v3, v8
; CGP-NEXT: v_subb_u32_e32 v3, vcc, v5, v3, vcc ; CGP-NEXT: v_subb_u32_e32 v3, vcc, v4, v8, vcc
; CGP-NEXT: ; implicit-def: $vgpr10_vgpr11 ; CGP-NEXT: ; implicit-def: $vgpr10_vgpr11
; CGP-NEXT: ; implicit-def: $vgpr5 ; CGP-NEXT: ; implicit-def: $vgpr5
; CGP-NEXT: BB8_6: ; %Flow ; CGP-NEXT: BB8_6: ; %Flow
; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7] ; CGP-NEXT: s_or_saveexec_b64 s[4:5], s[6:7]
; CGP-NEXT: s_xor_b64 exec, exec, s[4:5] ; CGP-NEXT: s_xor_b64 exec, exec, s[4:5]
; CGP-NEXT: s_cbranch_execz BB8_8 ; CGP-NEXT: s_cbranch_execz BB8_8
; CGP-NEXT: ; %bb.7: ; CGP-NEXT: ; %bb.7:
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10 ; CGP-NEXT: v_cvt_f32_u32_e32 v2, v10
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_mov_b32 s6, 0xffffff ; GISEL-NEXT: s_mov_b32 s6, 0xffffff
; GISEL-NEXT: v_and_b32_e32 v1, s6, v4 ; GISEL-NEXT: v_and_b32_e32 v1, s6, v4
; GISEL-NEXT: v_add_i32_e32 v1, vcc, 0, v1 ; GISEL-NEXT: v_add_i32_e32 v1, vcc, 0, v1
; GISEL-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc ; GISEL-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v1 ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v1
; GISEL-NEXT: v_cvt_f32_u32_e32 v5, v3 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, v3
; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v1 ; GISEL-NEXT: v_sub_i32_e32 v8, vcc, 0, v1
; GISEL-NEXT: v_subb_u32_e32 v8, vcc, 0, v3, vcc ; GISEL-NEXT: v_subb_u32_e32 v9, vcc, 0, v3, vcc
; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GISEL-NEXT: v_and_b32_e32 v5, s6, v0 ; GISEL-NEXT: v_and_b32_e32 v5, s6, v0
; GISEL-NEXT: v_and_b32_e32 v0, s6, v2
; GISEL-NEXT: v_and_b32_e32 v6, s6, v6 ; GISEL-NEXT: v_and_b32_e32 v6, s6, v6
; GISEL-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v4 ; GISEL-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v4
; GISEL-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x2f800000, v0
; GISEL-NEXT: v_trunc_f32_e32 v4, v4 ; GISEL-NEXT: v_trunc_f32_e32 v4, v4
; GISEL-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4 ; GISEL-NEXT: v_mac_f32_e32 v0, 0xcf800000, v4
; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v0
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
; GISEL-NEXT: v_mul_lo_u32 v9, v8, v2 ; GISEL-NEXT: v_mul_lo_u32 v0, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v7, v4 ; GISEL-NEXT: v_mul_lo_u32 v10, v8, v4
; GISEL-NEXT: v_mul_hi_u32 v12, v7, v2 ; GISEL-NEXT: v_mul_hi_u32 v12, v8, v7
; GISEL-NEXT: v_mul_lo_u32 v11, v7, v2 ; GISEL-NEXT: v_mul_lo_u32 v11, v8, v7
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v10
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v0, v12
; GISEL-NEXT: v_mul_lo_u32 v10, v4, v11 ; GISEL-NEXT: v_mul_lo_u32 v12, v4, v11
; GISEL-NEXT: v_mul_lo_u32 v12, v2, v9 ; GISEL-NEXT: v_mul_lo_u32 v13, v7, v10
; GISEL-NEXT: v_mul_hi_u32 v14, v2, v11 ; GISEL-NEXT: v_and_b32_e32 v0, s6, v2
; GISEL-NEXT: v_add_i32_e32 v5, vcc, 0, v5 ; GISEL-NEXT: v_mul_hi_u32 v2, v7, v11
; GISEL-NEXT: v_addc_u32_e64 v13, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v14
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v14, v4, v9
; GISEL-NEXT: v_mul_hi_u32 v11, v4, v11 ; GISEL-NEXT: v_mul_hi_u32 v11, v4, v11
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_mul_hi_u32 v12, v2, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v14, v11 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v12, v2
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_mul_lo_u32 v12, v4, v10
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v13, v2
; GISEL-NEXT: v_mul_hi_u32 v13, v7, v10
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v14, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_mul_hi_u32 v9, v4, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_mul_hi_u32 v10, v4, v10
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v11, v2
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v10 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; GISEL-NEXT: v_addc_u32_e64 v10, s[4:5], v4, v9, vcc ; GISEL-NEXT: v_addc_u32_e32 v4, vcc, v4, v10, vcc
; GISEL-NEXT: v_mul_lo_u32 v8, v8, v2 ; GISEL-NEXT: v_mul_lo_u32 v7, v9, v2
; GISEL-NEXT: v_mul_lo_u32 v11, v7, v10 ; GISEL-NEXT: v_mul_lo_u32 v9, v8, v4
; GISEL-NEXT: v_mul_lo_u32 v12, v7, v2 ; GISEL-NEXT: v_mul_lo_u32 v10, v8, v2
; GISEL-NEXT: v_mul_hi_u32 v7, v7, v2 ; GISEL-NEXT: v_mul_hi_u32 v8, v8, v2
; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v4, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v8, v7 ; GISEL-NEXT: v_mul_lo_u32 v8, v4, v10
; GISEL-NEXT: v_mul_lo_u32 v8, v10, v12 ; GISEL-NEXT: v_mul_lo_u32 v9, v2, v7
; GISEL-NEXT: v_mul_lo_u32 v11, v2, v7 ; GISEL-NEXT: v_mul_hi_u32 v12, v2, v10
; GISEL-NEXT: v_mul_hi_u32 v9, v2, v12 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, 0, v5
; GISEL-NEXT: v_mul_hi_u32 v12, v10, v12 ; GISEL-NEXT: v_addc_u32_e64 v11, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v12, v4, v7
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v11, v8 ; GISEL-NEXT: v_mul_hi_u32 v10, v4, v10
; GISEL-NEXT: v_mul_hi_u32 v11, v2, v7 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; GISEL-NEXT: v_mul_hi_u32 v9, v2, v7
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_mul_hi_u32 v7, v10, v7 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; GISEL-NEXT: v_mul_hi_u32 v7, v4, v7
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v9 ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v7, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; GISEL-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc ; GISEL-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v13, v2 ; GISEL-NEXT: v_mul_lo_u32 v7, v11, v2
; GISEL-NEXT: v_mul_lo_u32 v8, v5, v4 ; GISEL-NEXT: v_mul_lo_u32 v8, v5, v4
; GISEL-NEXT: v_mul_hi_u32 v9, v5, v2 ; GISEL-NEXT: v_mul_hi_u32 v9, v5, v2
; GISEL-NEXT: v_mul_hi_u32 v2, v13, v2 ; GISEL-NEXT: v_mul_hi_u32 v2, v11, v2
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, v13, v4 ; GISEL-NEXT: v_mul_lo_u32 v9, v11, v4
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GISEL-NEXT: v_mul_hi_u32 v8, v5, v4 ; GISEL-NEXT: v_mul_hi_u32 v8, v5, v4
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v9, v2 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v9, v2
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_mul_hi_u32 v4, v13, v4 ; GISEL-NEXT: v_mul_hi_u32 v4, v11, v4
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v7 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v7
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GISEL-NEXT: v_mul_lo_u32 v7, v3, v2 ; GISEL-NEXT: v_mul_lo_u32 v7, v3, v2
; GISEL-NEXT: v_mul_lo_u32 v4, v1, v4 ; GISEL-NEXT: v_mul_lo_u32 v4, v1, v4
; GISEL-NEXT: v_mul_lo_u32 v8, v1, v2 ; GISEL-NEXT: v_mul_lo_u32 v8, v1, v2
; GISEL-NEXT: v_mul_hi_u32 v2, v1, v2 ; GISEL-NEXT: v_mul_hi_u32 v2, v1, v2
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v5, v8 ; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v5, v8
; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v13, v2, vcc ; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v11, v2, vcc
; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v13, v2 ; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v11, v2
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v3 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v3
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v1 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v1
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v3 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v3
; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v3, vcc ; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v3, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v8, vcc, v4, v1 ; GISEL-NEXT: v_sub_i32_e32 v8, vcc, v4, v1
; GISEL-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v2, vcc ; GISEL-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v2, vcc
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v3 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v3
; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v3, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v1 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v1
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v8, v1 ; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v3, vcc
; GISEL-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v3 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v3
; GISEL-NEXT: v_add_i32_e32 v3, vcc, 0, v6 ; GISEL-NEXT: v_add_i32_e32 v3, vcc, 0, v6
; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[4:5]
; GISEL-NEXT: v_addc_u32_e64 v6, s[4:5], 0, 0, vcc ; GISEL-NEXT: v_addc_u32_e64 v6, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_cvt_f32_u32_e32 v11, v3 ; GISEL-NEXT: v_cvt_f32_u32_e32 v11, v3
; GISEL-NEXT: v_cvt_f32_u32_e32 v12, v6 ; GISEL-NEXT: v_cvt_f32_u32_e32 v12, v6
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v8, v1
; GISEL-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc
; GISEL-NEXT: v_mac_f32_e32 v11, 0x4f800000, v12 ; GISEL-NEXT: v_mac_f32_e32 v11, 0x4f800000, v12
; GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; GISEL-NEXT: v_rcp_iflag_f32_e32 v8, v11 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v8, v11
; GISEL-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v8 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v8
; GISEL-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 ; GISEL-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4
; GISEL-NEXT: v_trunc_f32_e32 v5, v5 ; GISEL-NEXT: v_trunc_f32_e32 v7, v7
; GISEL-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5 ; GISEL-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3 ; GISEL-NEXT: v_sub_i32_e64 v8, s[4:5], 0, v3
; GISEL-NEXT: v_subb_u32_e32 v8, vcc, 0, v6, vcc ; GISEL-NEXT: v_subb_u32_e64 v9, s[4:5], 0, v6, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v9, v8, v4 ; GISEL-NEXT: v_mul_lo_u32 v10, v9, v4
; GISEL-NEXT: v_mul_lo_u32 v10, v7, v5 ; GISEL-NEXT: v_mul_lo_u32 v11, v8, v7
; GISEL-NEXT: v_mul_hi_u32 v12, v7, v4 ; GISEL-NEXT: v_mul_hi_u32 v13, v8, v4
; GISEL-NEXT: v_mul_lo_u32 v11, v7, v4 ; GISEL-NEXT: v_mul_lo_u32 v12, v8, v4
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v11 ; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
; GISEL-NEXT: v_mul_lo_u32 v12, v4, v9 ; GISEL-NEXT: v_mul_lo_u32 v11, v7, v12
; GISEL-NEXT: v_add_i32_e32 v13, vcc, 0, v0 ; GISEL-NEXT: v_mul_lo_u32 v13, v4, v10
; GISEL-NEXT: v_mul_hi_u32 v0, v4, v11 ; GISEL-NEXT: v_mul_hi_u32 v5, v4, v12
; GISEL-NEXT: v_addc_u32_e64 v14, s[4:5], 0, 0, vcc ; GISEL-NEXT: v_mul_hi_u32 v12, v7, v12
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v11, v5
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, v7, v10
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v13, v5
; GISEL-NEXT: v_mul_hi_u32 v13, v4, v10
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v10, v0 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v10, v5, v9 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_mul_hi_u32 v11, v5, v11 ; GISEL-NEXT: v_mul_hi_u32 v10, v7, v10
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v12, v0 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v11, v5
; GISEL-NEXT: v_mul_hi_u32 v12, v4, v9
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GISEL-NEXT: v_mul_hi_u32 v9, v5, v9 ; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v7, v10, vcc
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v10, v0 ; GISEL-NEXT: v_mul_lo_u32 v7, v9, v4
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_mul_lo_u32 v9, v8, v5
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_mul_lo_u32 v10, v8, v4
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; GISEL-NEXT: v_mul_hi_u32 v8, v8, v4
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v4, v0 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_addc_u32_e64 v4, s[4:5], v5, v9, vcc ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_mul_lo_u32 v8, v8, v0 ; GISEL-NEXT: v_mul_lo_u32 v8, v5, v10
; GISEL-NEXT: v_mul_lo_u32 v10, v7, v4
; GISEL-NEXT: v_mul_lo_u32 v11, v7, v0
; GISEL-NEXT: v_mul_hi_u32 v7, v7, v0
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v9
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v8, v7
; GISEL-NEXT: v_mul_lo_u32 v8, v4, v11
; GISEL-NEXT: v_mul_lo_u32 v10, v0, v7
; GISEL-NEXT: v_mul_hi_u32 v9, v0, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v4, v11
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v9, v4, v7 ; GISEL-NEXT: v_mul_lo_u32 v9, v4, v7
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v10, v8 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, 0, v0
; GISEL-NEXT: v_mul_hi_u32 v10, v0, v7 ; GISEL-NEXT: v_mul_hi_u32 v0, v4, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v11 ; GISEL-NEXT: v_addc_u32_e64 v12, s[4:5], 0, 0, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10 ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v8, v0
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GISEL-NEXT: v_mul_hi_u32 v4, v4, v7 ; GISEL-NEXT: v_mul_lo_u32 v8, v5, v7
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; GISEL-NEXT: v_mul_hi_u32 v10, v5, v10
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v0, vcc, v9, v0
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v9 ; GISEL-NEXT: v_mul_hi_u32 v9, v4, v7
; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v4, v7 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v0, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v14, v5 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_mul_lo_u32 v8, v13, v4 ; GISEL-NEXT: v_mul_hi_u32 v7, v5, v7
; GISEL-NEXT: v_add_i32_e32 v0, vcc, v8, v0
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v0
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v12, v4
; GISEL-NEXT: v_mul_lo_u32 v8, v11, v5
; GISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0, v1 ; GISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0, v1
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v2, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v2, vcc
; GISEL-NEXT: v_mul_hi_u32 v2, v13, v5 ; GISEL-NEXT: v_mul_hi_u32 v2, v11, v4
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v7, v2 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v7, v14, v4 ; GISEL-NEXT: v_mul_lo_u32 v7, v12, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v14, v5 ; GISEL-NEXT: v_mul_hi_u32 v4, v12, v4
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v8, v2 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v8, v2
; GISEL-NEXT: v_mul_hi_u32 v8, v13, v4 ; GISEL-NEXT: v_mul_hi_u32 v8, v11, v5
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GISEL-NEXT: v_mul_hi_u32 v4, v14, v4 ; GISEL-NEXT: v_mul_hi_u32 v5, v12, v5
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v5, v2 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GISEL-NEXT: v_mul_lo_u32 v5, v6, v2 ; GISEL-NEXT: v_mul_lo_u32 v5, v6, v2
; GISEL-NEXT: v_mul_lo_u32 v4, v3, v4 ; GISEL-NEXT: v_mul_lo_u32 v4, v3, v4
; GISEL-NEXT: v_mul_lo_u32 v7, v3, v2 ; GISEL-NEXT: v_mul_lo_u32 v7, v3, v2
; GISEL-NEXT: v_mul_hi_u32 v2, v3, v2 ; GISEL-NEXT: v_mul_hi_u32 v2, v3, v2
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GISEL-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GISEL-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v13, v7 ; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v11, v7
; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v14, v2, vcc ; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v12, v2, vcc
; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v14, v2 ; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v12, v2
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v6 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v6
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v3 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v3
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v6 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v6
; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v6, vcc ; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v6, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v8, vcc, v4, v3 ; GISEL-NEXT: v_sub_i32_e32 v8, vcc, v4, v3
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v12 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v12
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9
; CHECK-NEXT: v_addc_u32_e64 v9, s[4:5], v1, v8, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v8, vcc
; CHECK-NEXT: v_add_i32_e64 v1, s[4:5], v1, v8
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v0 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v0
; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0 ; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0
; CHECK-NEXT: v_mul_hi_u32 v10, v6, v0 ; CHECK-NEXT: v_mul_hi_u32 v9, v6, v0
; CHECK-NEXT: v_mul_lo_u32 v6, v6, v9 ; CHECK-NEXT: v_mul_lo_u32 v6, v6, v1
; CHECK-NEXT: v_mul_lo_u32 v11, v9, v8 ; CHECK-NEXT: v_mul_lo_u32 v10, v1, v8
; CHECK-NEXT: v_mul_hi_u32 v12, v0, v8 ; CHECK-NEXT: v_mul_hi_u32 v11, v0, v8
; CHECK-NEXT: v_mul_hi_u32 v8, v9, v8 ; CHECK-NEXT: v_mul_hi_u32 v8, v1, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v10 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_mul_lo_u32 v7, v0, v6 ; CHECK-NEXT: v_mul_lo_u32 v7, v0, v6
; CHECK-NEXT: v_mul_lo_u32 v10, v9, v6 ; CHECK-NEXT: v_mul_lo_u32 v9, v1, v6
; CHECK-NEXT: v_mul_hi_u32 v13, v0, v6 ; CHECK-NEXT: v_mul_hi_u32 v12, v0, v6
; CHECK-NEXT: v_mul_hi_u32 v6, v9, v6 ; CHECK-NEXT: v_mul_hi_u32 v6, v1, v6
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v11, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v10, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v12 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v13 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v9, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v10, v11 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v6, vcc
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v6, vcc
; CHECK-NEXT: v_mul_lo_u32 v6, v5, v0 ; CHECK-NEXT: v_mul_lo_u32 v6, v5, v0
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v0 ; CHECK-NEXT: v_mul_hi_u32 v7, v4, v0
; CHECK-NEXT: v_mul_hi_u32 v0, v5, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, v5, v0
; CHECK-NEXT: v_mul_lo_u32 v8, v4, v1 ; CHECK-NEXT: v_mul_lo_u32 v8, v4, v1
; CHECK-NEXT: v_mul_lo_u32 v9, v5, v1 ; CHECK-NEXT: v_mul_lo_u32 v9, v5, v1
; CHECK-NEXT: v_mul_hi_u32 v10, v4, v1 ; CHECK-NEXT: v_mul_hi_u32 v10, v4, v1
; CHECK-NEXT: v_mul_hi_u32 v1, v5, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v5, v1
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; CHECK-NEXT: s_mov_b32 s5, -1 ; CHECK-NEXT: s_mov_b32 s5, -1
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[4:5] ; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[4:5]
; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0 ; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0
; CHECK-NEXT: s_cbranch_vccz BB1_2 ; CHECK-NEXT: s_cbranch_vccz BB1_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2
; CHECK-NEXT: v_mov_b32_e32 v1, s3 ; CHECK-NEXT: v_mov_b32_e32 v1, s3
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s3 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s3
; CHECK-NEXT: s_sub_u32 s6, 0, s2 ; CHECK-NEXT: s_sub_u32 s4, 0, s2
; CHECK-NEXT: s_cselect_b32 s4, 1, 0 ; CHECK-NEXT: s_cselect_b32 s5, 1, 0
; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: v_mov_b32_e32 v3, s1
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v2 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v2
; CHECK-NEXT: s_and_b32 s4, s4, 1 ; CHECK-NEXT: s_and_b32 s5, s5, 1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; CHECK-NEXT: s_cmp_lg_u32 s4, 0 ; CHECK-NEXT: s_cmp_lg_u32 s5, 0
; CHECK-NEXT: s_subb_u32 s7, 0, s3 ; CHECK-NEXT: s_subb_u32 s5, 0, s3
; CHECK-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
; CHECK-NEXT: v_trunc_f32_e32 v2, v2 ; CHECK-NEXT: v_trunc_f32_e32 v2, v2
; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 ; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v4, s6, v2 ; CHECK-NEXT: v_mul_lo_u32 v4, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v5, s6, v0 ; CHECK-NEXT: v_mul_lo_u32 v5, s4, v0
; CHECK-NEXT: v_mul_lo_u32 v6, s7, v0 ; CHECK-NEXT: v_mul_lo_u32 v6, s5, v0
; CHECK-NEXT: v_mul_hi_u32 v7, s6, v0 ; CHECK-NEXT: v_mul_hi_u32 v7, s4, v0
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_mul_lo_u32 v6, v2, v5 ; CHECK-NEXT: v_mul_lo_u32 v6, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v8, v0, v5 ; CHECK-NEXT: v_mul_hi_u32 v8, v0, v5
; CHECK-NEXT: v_mul_hi_u32 v5, v2, v5 ; CHECK-NEXT: v_mul_hi_u32 v5, v2, v5
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v7, v0, v4 ; CHECK-NEXT: v_mul_lo_u32 v7, v0, v4
; CHECK-NEXT: v_mul_lo_u32 v9, v2, v4 ; CHECK-NEXT: v_mul_lo_u32 v9, v2, v4
; CHECK-NEXT: v_mul_hi_u32 v10, v0, v4 ; CHECK-NEXT: v_mul_hi_u32 v10, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v2, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v2, v4
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v9, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v9, v5
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v10 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v10
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v5 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v5
; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v2, v4, vcc ; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; CHECK-NEXT: v_add_i32_e64 v2, s[4:5], v2, v4 ; CHECK-NEXT: v_mul_lo_u32 v4, s4, v0
; CHECK-NEXT: v_mul_lo_u32 v4, s6, v0 ; CHECK-NEXT: v_mul_lo_u32 v5, s5, v0
; CHECK-NEXT: v_mul_lo_u32 v6, s7, v0 ; CHECK-NEXT: v_mul_hi_u32 v6, s4, v0
; CHECK-NEXT: v_mul_hi_u32 v7, s6, v0 ; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s6, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v4
; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4 ; CHECK-NEXT: v_mul_hi_u32 v9, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v10, v0, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v2, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7 ; CHECK-NEXT: v_mul_lo_u32 v6, v0, v5
; CHECK-NEXT: v_mul_lo_u32 v7, v0, v6 ; CHECK-NEXT: v_mul_lo_u32 v7, v2, v5
; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6 ; CHECK-NEXT: v_mul_hi_u32 v10, v0, v5
; CHECK-NEXT: v_mul_hi_u32 v11, v0, v6 ; CHECK-NEXT: v_mul_hi_u32 v5, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v5, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v9, v7 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v8, v4 ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v10 ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v11 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v8, v9 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v6 ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v5, v6
; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; CHECK-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v4, s1, v0 ; CHECK-NEXT: v_mul_lo_u32 v4, s1, v0
; CHECK-NEXT: v_mul_hi_u32 v5, s0, v0 ; CHECK-NEXT: v_mul_hi_u32 v5, s0, v0
; CHECK-NEXT: v_mul_hi_u32 v0, s1, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, s1, v0
; CHECK-NEXT: v_mul_lo_u32 v6, s0, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, s0, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s1, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, s1, v2
; CHECK-NEXT: v_mul_hi_u32 v8, s0, v2 ; CHECK-NEXT: v_mul_hi_u32 v8, s0, v2
; CHECK-NEXT: v_mul_hi_u32 v2, s1, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, s1, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16 ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13 ; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; GISEL-NEXT: v_addc_u32_e64 v12, s[4:5], v9, v13, vcc ; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v13, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 ; GISEL-NEXT: v_mul_lo_u32 v12, v10, v8
; GISEL-NEXT: v_mul_lo_u32 v13, v10, v8
; GISEL-NEXT: v_mul_lo_u32 v11, v11, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v11, v8
; GISEL-NEXT: v_mul_lo_u32 v14, v10, v12 ; GISEL-NEXT: v_mul_lo_u32 v13, v10, v9
; GISEL-NEXT: v_mul_hi_u32 v10, v10, v8 ; GISEL-NEXT: v_mul_hi_u32 v10, v10, v8
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_lo_u32 v11, v12, v13 ; GISEL-NEXT: v_mul_lo_u32 v11, v9, v12
; GISEL-NEXT: v_mul_lo_u32 v14, v8, v10 ; GISEL-NEXT: v_mul_lo_u32 v13, v8, v10
; GISEL-NEXT: v_mul_hi_u32 v15, v8, v13 ; GISEL-NEXT: v_mul_hi_u32 v14, v8, v12
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v15 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v14, v11 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; GISEL-NEXT: v_mul_lo_u32 v14, v12, v10 ; GISEL-NEXT: v_mul_lo_u32 v13, v9, v10
; GISEL-NEXT: v_mul_hi_u32 v13, v12, v13 ; GISEL-NEXT: v_mul_hi_u32 v12, v9, v12
; GISEL-NEXT: v_mul_hi_u32 v15, v8, v10 ; GISEL-NEXT: v_mul_hi_u32 v14, v8, v10
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v15 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v15 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v13, v11 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_mul_hi_u32 v10, v12, v10 ; GISEL-NEXT: v_mul_hi_u32 v10, v9, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v10, vcc ; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v10, vcc
; GISEL-NEXT: v_addc_u32_e64 v9, vcc, 0, v9, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v10, v1, v8 ; GISEL-NEXT: v_mul_lo_u32 v10, v1, v8
; GISEL-NEXT: v_mul_lo_u32 v11, v0, v9 ; GISEL-NEXT: v_mul_lo_u32 v11, v0, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v0, v8 ; GISEL-NEXT: v_mul_hi_u32 v12, v0, v8
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_mul_hi_u32 v11, v5, v11 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v11
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; GISEL-NEXT: v_addc_u32_e64 v10, s[4:5], v5, v11, vcc ; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v11, vcc
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v11 ; GISEL-NEXT: v_mul_lo_u32 v10, v8, v4
; GISEL-NEXT: v_mul_lo_u32 v11, v8, v4
; GISEL-NEXT: v_mul_lo_u32 v9, v9, v4 ; GISEL-NEXT: v_mul_lo_u32 v9, v9, v4
; GISEL-NEXT: v_mul_lo_u32 v12, v8, v10 ; GISEL-NEXT: v_mul_lo_u32 v11, v8, v5
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v4 ; GISEL-NEXT: v_mul_hi_u32 v8, v8, v4
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_mul_lo_u32 v9, v10, v11 ; GISEL-NEXT: v_mul_lo_u32 v9, v5, v10
; GISEL-NEXT: v_mul_lo_u32 v12, v4, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v4, v8
; GISEL-NEXT: v_mul_hi_u32 v13, v4, v11 ; GISEL-NEXT: v_mul_hi_u32 v12, v4, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_mul_lo_u32 v12, v10, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v5, v8
; GISEL-NEXT: v_mul_hi_u32 v11, v10, v11 ; GISEL-NEXT: v_mul_hi_u32 v10, v5, v10
; GISEL-NEXT: v_mul_hi_u32 v13, v4, v8 ; GISEL-NEXT: v_mul_hi_u32 v12, v4, v8
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v8, v10, v8 ; GISEL-NEXT: v_mul_hi_u32 v8, v5, v8
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v4, v9 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v8, vcc ; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v8, vcc
; GISEL-NEXT: v_addc_u32_e64 v5, vcc, 0, v5, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v8, v3, v4 ; GISEL-NEXT: v_mul_lo_u32 v8, v3, v4
; GISEL-NEXT: v_mul_lo_u32 v9, v2, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, v2, v5
; GISEL-NEXT: v_mul_hi_u32 v10, v2, v4 ; GISEL-NEXT: v_mul_hi_u32 v10, v2, v4
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v16 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v16
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13
; CGP-NEXT: v_addc_u32_e64 v13, s[4:5], v1, v12, vcc ; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v12, vcc
; CGP-NEXT: v_add_i32_e64 v1, s[4:5], v1, v12
; CGP-NEXT: v_mul_lo_u32 v12, v2, v0 ; CGP-NEXT: v_mul_lo_u32 v12, v2, v0
; CGP-NEXT: v_mul_lo_u32 v3, v3, v0 ; CGP-NEXT: v_mul_lo_u32 v3, v3, v0
; CGP-NEXT: v_mul_hi_u32 v14, v2, v0 ; CGP-NEXT: v_mul_hi_u32 v13, v2, v0
; CGP-NEXT: v_mul_lo_u32 v2, v2, v13 ; CGP-NEXT: v_mul_lo_u32 v2, v2, v1
; CGP-NEXT: v_mul_lo_u32 v15, v13, v12 ; CGP-NEXT: v_mul_lo_u32 v14, v1, v12
; CGP-NEXT: v_mul_hi_u32 v16, v0, v12 ; CGP-NEXT: v_mul_hi_u32 v15, v0, v12
; CGP-NEXT: v_mul_hi_u32 v12, v13, v12 ; CGP-NEXT: v_mul_hi_u32 v12, v1, v12
; CGP-NEXT: v_add_i32_e64 v2, s[4:5], v3, v2 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; CGP-NEXT: v_add_i32_e64 v2, s[4:5], v2, v14 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v13
; CGP-NEXT: v_mul_lo_u32 v3, v0, v2 ; CGP-NEXT: v_mul_lo_u32 v3, v0, v2
; CGP-NEXT: v_mul_lo_u32 v14, v13, v2 ; CGP-NEXT: v_mul_lo_u32 v13, v1, v2
; CGP-NEXT: v_mul_hi_u32 v17, v0, v2 ; CGP-NEXT: v_mul_hi_u32 v16, v0, v2
; CGP-NEXT: v_mul_hi_u32 v2, v13, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v1, v2
; CGP-NEXT: v_add_i32_e64 v3, s[4:5], v15, v3 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v14, v3
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v3, s[4:5], v3, v16 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v15
; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v17 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v16
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v3, s[4:5], v13, v3 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v14, v3
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v14, v15 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; CGP-NEXT: v_add_i32_e64 v3, s[4:5], v12, v3 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v12, v3
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v2, s[4:5], v2, v12 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CGP-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CGP-NEXT: v_mul_lo_u32 v2, v11, v0 ; CGP-NEXT: v_mul_lo_u32 v2, v11, v0
; CGP-NEXT: v_mul_hi_u32 v3, v10, v0 ; CGP-NEXT: v_mul_hi_u32 v3, v10, v0
; CGP-NEXT: v_mul_hi_u32 v0, v11, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v11, v0
; CGP-NEXT: v_mul_lo_u32 v12, v10, v1 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v1
; CGP-NEXT: v_mul_lo_u32 v13, v11, v1 ; CGP-NEXT: v_mul_lo_u32 v13, v11, v1
; CGP-NEXT: v_mul_hi_u32 v14, v10, v1 ; CGP-NEXT: v_mul_hi_u32 v14, v10, v1
; CGP-NEXT: v_mul_hi_u32 v1, v11, v1 ; CGP-NEXT: v_mul_hi_u32 v1, v11, v1
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v11 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v11
; CGP-NEXT: v_addc_u32_e64 v11, s[4:5], v3, v10, vcc ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v10, vcc
; CGP-NEXT: v_add_i32_e64 v3, s[4:5], v3, v10
; CGP-NEXT: v_mul_lo_u32 v10, v4, v2 ; CGP-NEXT: v_mul_lo_u32 v10, v4, v2
; CGP-NEXT: v_mul_lo_u32 v5, v5, v2 ; CGP-NEXT: v_mul_lo_u32 v5, v5, v2
; CGP-NEXT: v_mul_hi_u32 v12, v4, v2 ; CGP-NEXT: v_mul_hi_u32 v11, v4, v2
; CGP-NEXT: v_mul_lo_u32 v4, v4, v11 ; CGP-NEXT: v_mul_lo_u32 v4, v4, v3
; CGP-NEXT: v_mul_lo_u32 v13, v11, v10 ; CGP-NEXT: v_mul_lo_u32 v12, v3, v10
; CGP-NEXT: v_mul_hi_u32 v14, v2, v10 ; CGP-NEXT: v_mul_hi_u32 v13, v2, v10
; CGP-NEXT: v_mul_hi_u32 v10, v11, v10 ; CGP-NEXT: v_mul_hi_u32 v10, v3, v10
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v5, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v11
; CGP-NEXT: v_mul_lo_u32 v5, v2, v4 ; CGP-NEXT: v_mul_lo_u32 v5, v2, v4
; CGP-NEXT: v_mul_lo_u32 v12, v11, v4 ; CGP-NEXT: v_mul_lo_u32 v11, v3, v4
; CGP-NEXT: v_mul_hi_u32 v15, v2, v4 ; CGP-NEXT: v_mul_hi_u32 v14, v2, v4
; CGP-NEXT: v_mul_hi_u32 v4, v11, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v13, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v12, v5
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v12, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v5, v14 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v13
; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v15 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v14
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v11, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v12, v5
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v12, v13 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v10, v5
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v10 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CGP-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v4, v9, v2 ; CGP-NEXT: v_mul_lo_u32 v4, v9, v2
; CGP-NEXT: v_mul_hi_u32 v5, v8, v2 ; CGP-NEXT: v_mul_hi_u32 v5, v8, v2
; CGP-NEXT: v_mul_hi_u32 v2, v9, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v9, v2
; CGP-NEXT: v_mul_lo_u32 v10, v8, v3 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v3
; CGP-NEXT: v_mul_lo_u32 v11, v9, v3 ; CGP-NEXT: v_mul_lo_u32 v11, v9, v3
; CGP-NEXT: v_mul_hi_u32 v12, v8, v3 ; CGP-NEXT: v_mul_hi_u32 v12, v8, v3
; CGP-NEXT: v_mul_hi_u32 v3, v9, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v9, v3
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
▲ Show 20 Lines • Show All 238 Lines • ▼ Show 20 Lines
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v12 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v12
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9
; CHECK-NEXT: v_addc_u32_e64 v9, s[4:5], v1, v8, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v8, vcc
; CHECK-NEXT: v_add_i32_e64 v1, s[4:5], v1, v8
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v0 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v0
; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0 ; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v0 ; CHECK-NEXT: v_mul_hi_u32 v9, v2, v0
; CHECK-NEXT: v_mul_lo_u32 v2, v2, v9 ; CHECK-NEXT: v_mul_lo_u32 v2, v2, v1
; CHECK-NEXT: v_mul_lo_u32 v11, v9, v8 ; CHECK-NEXT: v_mul_lo_u32 v10, v1, v8
; CHECK-NEXT: v_mul_hi_u32 v12, v0, v8 ; CHECK-NEXT: v_mul_hi_u32 v11, v0, v8
; CHECK-NEXT: v_mul_hi_u32 v8, v9, v8 ; CHECK-NEXT: v_mul_hi_u32 v8, v1, v8
; CHECK-NEXT: v_add_i32_e64 v2, s[4:5], v7, v2 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; CHECK-NEXT: v_add_i32_e64 v2, s[4:5], v2, v10 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v9
; CHECK-NEXT: v_mul_lo_u32 v7, v0, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, v0, v2
; CHECK-NEXT: v_mul_lo_u32 v10, v9, v2 ; CHECK-NEXT: v_mul_lo_u32 v9, v1, v2
; CHECK-NEXT: v_mul_hi_u32 v13, v0, v2 ; CHECK-NEXT: v_mul_hi_u32 v12, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v9, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v11, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v10, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v12 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v13 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v9, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v10, v11 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e64 v2, s[4:5], v2, v8 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CHECK-NEXT: v_mul_lo_u32 v2, v4, v0 ; CHECK-NEXT: v_mul_lo_u32 v2, v4, v0
; CHECK-NEXT: v_mul_hi_u32 v7, v3, v0 ; CHECK-NEXT: v_mul_hi_u32 v7, v3, v0
; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0
; CHECK-NEXT: v_mul_lo_u32 v8, v3, v1 ; CHECK-NEXT: v_mul_lo_u32 v8, v3, v1
; CHECK-NEXT: v_mul_lo_u32 v9, v4, v1 ; CHECK-NEXT: v_mul_lo_u32 v9, v4, v1
; CHECK-NEXT: v_mul_hi_u32 v10, v3, v1 ; CHECK-NEXT: v_mul_hi_u32 v10, v3, v1
; CHECK-NEXT: v_mul_hi_u32 v1, v4, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v4, v1
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16 ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13 ; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v12 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v12
; GISEL-NEXT: v_addc_u32_e64 v12, s[4:5], v9, v13, vcc ; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v13, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 ; GISEL-NEXT: v_mul_lo_u32 v12, v10, v6
; GISEL-NEXT: v_mul_lo_u32 v13, v10, v6
; GISEL-NEXT: v_mul_lo_u32 v11, v11, v6 ; GISEL-NEXT: v_mul_lo_u32 v11, v11, v6
; GISEL-NEXT: v_mul_lo_u32 v14, v10, v12 ; GISEL-NEXT: v_mul_lo_u32 v13, v10, v9
; GISEL-NEXT: v_mul_hi_u32 v10, v10, v6 ; GISEL-NEXT: v_mul_hi_u32 v10, v10, v6
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_lo_u32 v11, v12, v13 ; GISEL-NEXT: v_mul_lo_u32 v11, v9, v12
; GISEL-NEXT: v_mul_lo_u32 v14, v6, v10 ; GISEL-NEXT: v_mul_lo_u32 v13, v6, v10
; GISEL-NEXT: v_mul_hi_u32 v15, v6, v13 ; GISEL-NEXT: v_mul_hi_u32 v14, v6, v12
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v15 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v14, v11 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; GISEL-NEXT: v_mul_lo_u32 v14, v12, v10 ; GISEL-NEXT: v_mul_lo_u32 v13, v9, v10
; GISEL-NEXT: v_mul_hi_u32 v13, v12, v13 ; GISEL-NEXT: v_mul_hi_u32 v12, v9, v12
; GISEL-NEXT: v_mul_hi_u32 v15, v6, v10 ; GISEL-NEXT: v_mul_hi_u32 v14, v6, v10
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v15 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v15 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v13, v11 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_mul_hi_u32 v10, v12, v10 ; GISEL-NEXT: v_mul_hi_u32 v10, v9, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v11 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v11
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v10, vcc ; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v10, vcc
; GISEL-NEXT: v_addc_u32_e64 v9, vcc, 0, v9, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v10, v1, v6 ; GISEL-NEXT: v_mul_lo_u32 v10, v1, v6
; GISEL-NEXT: v_mul_lo_u32 v11, v0, v9 ; GISEL-NEXT: v_mul_lo_u32 v11, v0, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v0, v6 ; GISEL-NEXT: v_mul_hi_u32 v12, v0, v6
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_mul_hi_u32 v11, v7, v11 ; GISEL-NEXT: v_mul_hi_u32 v11, v7, v11
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v10 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; GISEL-NEXT: v_addc_u32_e64 v10, s[4:5], v7, v11, vcc ; GISEL-NEXT: v_addc_u32_e32 v7, vcc, v7, v11, vcc
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v7, v11 ; GISEL-NEXT: v_mul_lo_u32 v10, v8, v6
; GISEL-NEXT: v_mul_lo_u32 v11, v8, v6
; GISEL-NEXT: v_mul_lo_u32 v9, v9, v6 ; GISEL-NEXT: v_mul_lo_u32 v9, v9, v6
; GISEL-NEXT: v_mul_lo_u32 v12, v8, v10 ; GISEL-NEXT: v_mul_lo_u32 v11, v8, v7
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v6 ; GISEL-NEXT: v_mul_hi_u32 v8, v8, v6
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_mul_lo_u32 v9, v10, v11 ; GISEL-NEXT: v_mul_lo_u32 v9, v7, v10
; GISEL-NEXT: v_mul_lo_u32 v12, v6, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v6, v8
; GISEL-NEXT: v_mul_hi_u32 v13, v6, v11 ; GISEL-NEXT: v_mul_hi_u32 v12, v6, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_mul_lo_u32 v12, v10, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v7, v8
; GISEL-NEXT: v_mul_hi_u32 v11, v10, v11 ; GISEL-NEXT: v_mul_hi_u32 v10, v7, v10
; GISEL-NEXT: v_mul_hi_u32 v13, v6, v8 ; GISEL-NEXT: v_mul_hi_u32 v12, v6, v8
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v8, v10, v8 ; GISEL-NEXT: v_mul_hi_u32 v8, v7, v8
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v9 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; GISEL-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc ; GISEL-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
; GISEL-NEXT: v_addc_u32_e64 v7, vcc, 0, v7, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v8, v3, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, v3, v6
; GISEL-NEXT: v_mul_lo_u32 v9, v2, v7 ; GISEL-NEXT: v_mul_lo_u32 v9, v2, v7
; GISEL-NEXT: v_mul_hi_u32 v10, v2, v6 ; GISEL-NEXT: v_mul_hi_u32 v10, v2, v6
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v16 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v16
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13
; CGP-NEXT: v_addc_u32_e64 v13, s[4:5], v1, v12, vcc ; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v12, vcc
; CGP-NEXT: v_add_i32_e64 v1, s[4:5], v1, v12
; CGP-NEXT: v_mul_lo_u32 v12, v4, v0 ; CGP-NEXT: v_mul_lo_u32 v12, v4, v0
; CGP-NEXT: v_mul_lo_u32 v6, v6, v0 ; CGP-NEXT: v_mul_lo_u32 v6, v6, v0
; CGP-NEXT: v_mul_hi_u32 v14, v4, v0 ; CGP-NEXT: v_mul_hi_u32 v13, v4, v0
; CGP-NEXT: v_mul_lo_u32 v4, v4, v13 ; CGP-NEXT: v_mul_lo_u32 v4, v4, v1
; CGP-NEXT: v_mul_lo_u32 v15, v13, v12 ; CGP-NEXT: v_mul_lo_u32 v14, v1, v12
; CGP-NEXT: v_mul_hi_u32 v16, v0, v12 ; CGP-NEXT: v_mul_hi_u32 v15, v0, v12
; CGP-NEXT: v_mul_hi_u32 v12, v13, v12 ; CGP-NEXT: v_mul_hi_u32 v12, v1, v12
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v6, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v14 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v13
; CGP-NEXT: v_mul_lo_u32 v6, v0, v4 ; CGP-NEXT: v_mul_lo_u32 v6, v0, v4
; CGP-NEXT: v_mul_lo_u32 v14, v13, v4 ; CGP-NEXT: v_mul_lo_u32 v13, v1, v4
; CGP-NEXT: v_mul_hi_u32 v17, v0, v4 ; CGP-NEXT: v_mul_hi_u32 v16, v0, v4
; CGP-NEXT: v_mul_hi_u32 v4, v13, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v1, v4
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v15, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v14, v6
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v6, v16 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v15
; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v17 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v16
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v13, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v14, v6
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v14, v15 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v12, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v12
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6
; CGP-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v4, v9, v0 ; CGP-NEXT: v_mul_lo_u32 v4, v9, v0
; CGP-NEXT: v_mul_hi_u32 v6, v8, v0 ; CGP-NEXT: v_mul_hi_u32 v6, v8, v0
; CGP-NEXT: v_mul_hi_u32 v0, v9, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v9, v0
; CGP-NEXT: v_mul_lo_u32 v12, v8, v1 ; CGP-NEXT: v_mul_lo_u32 v12, v8, v1
; CGP-NEXT: v_mul_lo_u32 v13, v9, v1 ; CGP-NEXT: v_mul_lo_u32 v13, v9, v1
; CGP-NEXT: v_mul_hi_u32 v14, v8, v1 ; CGP-NEXT: v_mul_hi_u32 v14, v8, v1
; CGP-NEXT: v_mul_hi_u32 v1, v9, v1 ; CGP-NEXT: v_mul_hi_u32 v1, v9, v1
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v12
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v9 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v9
; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v3, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
; CGP-NEXT: v_add_i32_e64 v3, s[4:5], v3, v8
; CGP-NEXT: v_mul_lo_u32 v8, v4, v2 ; CGP-NEXT: v_mul_lo_u32 v8, v4, v2
; CGP-NEXT: v_mul_lo_u32 v6, v6, v2 ; CGP-NEXT: v_mul_lo_u32 v6, v6, v2
; CGP-NEXT: v_mul_hi_u32 v12, v4, v2 ; CGP-NEXT: v_mul_hi_u32 v9, v4, v2
; CGP-NEXT: v_mul_lo_u32 v4, v4, v9 ; CGP-NEXT: v_mul_lo_u32 v4, v4, v3
; CGP-NEXT: v_mul_lo_u32 v13, v9, v8 ; CGP-NEXT: v_mul_lo_u32 v12, v3, v8
; CGP-NEXT: v_mul_hi_u32 v14, v2, v8 ; CGP-NEXT: v_mul_hi_u32 v13, v2, v8
; CGP-NEXT: v_mul_hi_u32 v8, v9, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v3, v8
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v6, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_mul_lo_u32 v6, v2, v4 ; CGP-NEXT: v_mul_lo_u32 v6, v2, v4
; CGP-NEXT: v_mul_lo_u32 v12, v9, v4 ; CGP-NEXT: v_mul_lo_u32 v9, v3, v4
; CGP-NEXT: v_mul_hi_u32 v15, v2, v4 ; CGP-NEXT: v_mul_hi_u32 v14, v2, v4
; CGP-NEXT: v_mul_hi_u32 v4, v9, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v13, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v12, v8 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v6, v14 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v13
; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v15 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v14
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v9, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v13 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v13
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v8, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v8 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CGP-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v4, v7, v2 ; CGP-NEXT: v_mul_lo_u32 v4, v7, v2
; CGP-NEXT: v_mul_hi_u32 v6, v5, v2 ; CGP-NEXT: v_mul_hi_u32 v6, v5, v2
; CGP-NEXT: v_mul_hi_u32 v2, v7, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v7, v2
; CGP-NEXT: v_mul_lo_u32 v8, v5, v3 ; CGP-NEXT: v_mul_lo_u32 v8, v5, v3
; CGP-NEXT: v_mul_lo_u32 v9, v7, v3 ; CGP-NEXT: v_mul_lo_u32 v9, v7, v3
; CGP-NEXT: v_mul_hi_u32 v12, v5, v3 ; CGP-NEXT: v_mul_hi_u32 v12, v5, v3
; CGP-NEXT: v_mul_hi_u32 v3, v7, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v7, v3
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8
▲ Show 20 Lines • Show All 202 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18 ; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18
; GISEL-NEXT: v_mul_lo_u32 v19, v11, v13 ; GISEL-NEXT: v_mul_lo_u32 v19, v11, v13
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v19, v17 ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v19, v17
; GISEL-NEXT: v_mul_hi_u32 v19, v7, v13 ; GISEL-NEXT: v_mul_hi_u32 v19, v7, v13
; GISEL-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v19 ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v19
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v19, vcc, v20, v19 ; GISEL-NEXT: v_add_i32_e32 v19, vcc, v20, v19
; GISEL-NEXT: s_bfe_i32 s10, -1, 0x10000 ; GISEL-NEXT: s_bfe_i32 s4, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s11, -1, 0x10000 ; GISEL-NEXT: s_bfe_i32 s5, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s12, -1, 0x10000 ; GISEL-NEXT: s_bfe_i32 s7, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s13, -1, 0x10000 ; GISEL-NEXT: s_bfe_i32 s8, -1, 0x10000
; GISEL-NEXT: v_and_b32_e32 v0, s6, v0 ; GISEL-NEXT: v_and_b32_e32 v0, s6, v0
; GISEL-NEXT: v_and_b32_e32 v2, s6, v2 ; GISEL-NEXT: v_and_b32_e32 v2, s6, v2
; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_mul_hi_u32 v13, v11, v13
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; GISEL-NEXT: v_mov_b32_e32 v16, s4
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v18 ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16 ; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v19, v18 ; GISEL-NEXT: v_mov_b32_e32 v19, s5
; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v16 ; GISEL-NEXT: v_mov_b32_e32 v15, s7
; GISEL-NEXT: v_mul_hi_u32 v13, v11, v13
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v18
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v14 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v14
; GISEL-NEXT: v_addc_u32_e64 v14, s[4:5], v8, v12, vcc ; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v12, vcc
; GISEL-NEXT: v_mul_lo_u32 v15, v4, v6 ; GISEL-NEXT: v_mul_lo_u32 v12, v4, v6
; GISEL-NEXT: v_mul_lo_u32 v5, v5, v6 ; GISEL-NEXT: v_mul_lo_u32 v5, v5, v6
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v7, v17 ; GISEL-NEXT: v_mul_hi_u32 v14, v4, v6
; GISEL-NEXT: v_addc_u32_e64 v16, s[6:7], v11, v13, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v17
; GISEL-NEXT: v_mul_lo_u32 v17, v9, v7 ; GISEL-NEXT: v_addc_u32_e32 v11, vcc, v11, v13, vcc
; GISEL-NEXT: v_mul_lo_u32 v13, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v10, v10, v7
; GISEL-NEXT: v_mul_hi_u32 v18, v9, v7 ; GISEL-NEXT: v_mul_hi_u32 v17, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v9, v9, v16 ; GISEL-NEXT: v_mul_lo_u32 v4, v4, v8
; GISEL-NEXT: v_mul_lo_u32 v19, v16, v17 ; GISEL-NEXT: v_mul_lo_u32 v18, v8, v12
; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v10, v9 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GISEL-NEXT: v_mul_hi_u32 v10, v7, v17 ; GISEL-NEXT: v_mul_hi_u32 v5, v6, v12
; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v18 ; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_mul_lo_u32 v18, v7, v9 ; GISEL-NEXT: v_mul_lo_u32 v9, v9, v11
; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] ; GISEL-NEXT: v_mul_lo_u32 v10, v11, v13
; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v18, v10 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v14
; GISEL-NEXT: v_mul_hi_u32 v10, v4, v6 ; GISEL-NEXT: v_mul_hi_u32 v14, v7, v13
; GISEL-NEXT: v_mul_lo_u32 v4, v4, v14 ; GISEL-NEXT: v_mul_hi_u32 v13, v11, v13
; GISEL-NEXT: v_mul_lo_u32 v18, v14, v15 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v17
; GISEL-NEXT: v_add_i32_e64 v4, s[8:9], v5, v4 ; GISEL-NEXT: v_mul_lo_u32 v17, v7, v9
; GISEL-NEXT: v_mul_hi_u32 v5, v6, v15 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
; GISEL-NEXT: v_add_i32_e64 v4, s[8:9], v4, v10 ; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v14
; GISEL-NEXT: v_mul_lo_u32 v10, v6, v4 ; GISEL-NEXT: v_mul_lo_u32 v10, v6, v4
; GISEL-NEXT: v_add_i32_e64 v10, s[8:9], v18, v10 ; GISEL-NEXT: v_mul_lo_u32 v14, v8, v4
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] ; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v18, v10
; GISEL-NEXT: v_add_i32_e64 v5, s[8:9], v10, v5 ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
; GISEL-NEXT: v_mov_b32_e32 v5, s10 ; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
; GISEL-NEXT: v_mov_b32_e32 v10, s11 ; GISEL-NEXT: v_mul_hi_u32 v5, v6, v4
; GISEL-NEXT: v_add_i32_e64 v8, s[10:11], v8, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; GISEL-NEXT: v_mov_b32_e32 v12, s12 ; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v18, v10
; GISEL-NEXT: v_add_i32_e64 v11, s[10:11], v11, v13 ; GISEL-NEXT: v_mul_lo_u32 v18, v11, v9
; GISEL-NEXT: v_mul_hi_u32 v13, v14, v15 ; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12
; GISEL-NEXT: v_mul_hi_u32 v15, v16, v17 ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[8:9] ; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v12, v5
; GISEL-NEXT: v_add_i32_e64 v17, s[8:9], v18, v17 ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v18, v14, v4 ; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12
; GISEL-NEXT: v_mul_hi_u32 v14, v14, v4 ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_mul_hi_u32 v4, v6, v4 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v17, v14
; GISEL-NEXT: v_add_i32_e64 v13, s[8:9], v18, v13 ; GISEL-NEXT: v_mul_hi_u32 v17, v7, v9
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v18, v13
; GISEL-NEXT: v_add_i32_e64 v4, s[8:9], v13, v4
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[8:9]
; GISEL-NEXT: v_add_i32_e64 v13, s[8:9], v18, v13
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18
; GISEL-NEXT: v_mul_lo_u32 v19, v16, v9
; GISEL-NEXT: v_mul_hi_u32 v16, v16, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v7, v9
; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v19, v15
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v15, v9
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v19, v15
; GISEL-NEXT: v_mov_b32_e32 v19, s13
; GISEL-NEXT: v_add_i32_e64 v4, s[6:7], v4, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v13, s[6:7], v13, v17
; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v15, v18
; GISEL-NEXT: v_add_i32_e64 v13, s[6:7], v14, v13
; GISEL-NEXT: v_add_i32_e64 v14, s[6:7], v16, v15
; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc
; GISEL-NEXT: v_addc_u32_e64 v11, vcc, v11, v14, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc
; GISEL-NEXT: v_mul_lo_u32 v8, 0, v4
; GISEL-NEXT: v_mul_hi_u32 v13, v0, v4
; GISEL-NEXT: v_mul_hi_u32 v4, 0, v4
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v11, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, 0, v7
; GISEL-NEXT: v_mul_hi_u32 v14, v2, v7
; GISEL-NEXT: v_mul_hi_u32 v7, 0, v7
; GISEL-NEXT: v_mul_lo_u32 v15, v0, v6
; GISEL-NEXT: v_mul_lo_u32 v16, 0, v6
; GISEL-NEXT: v_mul_hi_u32 v17, v0, v6
; GISEL-NEXT: v_mul_hi_u32 v6, 0, v6
; GISEL-NEXT: v_mul_lo_u32 v18, v2, v9
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v17
; GISEL-NEXT: v_mul_lo_u32 v11, 0, v9
; GISEL-NEXT: v_mul_hi_u32 v14, v2, v9
; GISEL-NEXT: v_mul_hi_u32 v9, 0, v9
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v16, v4
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v11, v7
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v13
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v4, v17
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v14 ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v18, v17
; GISEL-NEXT: v_mov_b32_e32 v18, s8
; GISEL-NEXT: v_mul_hi_u32 v4, v8, v4
; GISEL-NEXT: v_mul_hi_u32 v9, v11, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v10
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v15, v8 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v16, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v17, v14
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v18, v17 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v15 ; GISEL-NEXT: v_mul_lo_u32 v6, 0, v5
; GISEL-NEXT: v_mul_hi_u32 v8, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, 0, v5
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v13
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v11, v9, vcc
; GISEL-NEXT: v_mul_lo_u32 v10, 0, v7
; GISEL-NEXT: v_mul_hi_u32 v11, v2, v7
; GISEL-NEXT: v_mul_hi_u32 v7, 0, v7
; GISEL-NEXT: v_mul_lo_u32 v12, v0, v4
; GISEL-NEXT: v_mul_lo_u32 v13, 0, v4
; GISEL-NEXT: v_mul_hi_u32 v14, v0, v4
; GISEL-NEXT: v_mul_hi_u32 v4, 0, v4
; GISEL-NEXT: v_mul_lo_u32 v17, v2, v9
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_mul_lo_u32 v10, 0, v9
; GISEL-NEXT: v_mul_hi_u32 v11, v2, v9
; GISEL-NEXT: v_mul_hi_u32 v9, 0, v9
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v13, v5
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v14
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v13, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v13, v8
; GISEL-NEXT: v_mul_lo_u32 v13, v1, v4 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v17, v14
; GISEL-NEXT: v_mul_lo_u32 v15, 0, v4 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_mul_hi_u32 v16, v1, v4 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 ; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v14, v3, v7 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v12
; GISEL-NEXT: v_mul_lo_u32 v17, 0, v7 ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_mul_hi_u32 v18, v3, v7 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; GISEL-NEXT: v_mul_lo_u32 v8, v1, v5
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v11 ; GISEL-NEXT: v_mul_lo_u32 v12, 0, v5
; GISEL-NEXT: v_mul_lo_u32 v9, v1, v6 ; GISEL-NEXT: v_mul_hi_u32 v13, v1, v5
; GISEL-NEXT: v_mul_lo_u32 v11, v3, v8 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v15, v9 ; GISEL-NEXT: v_mul_lo_u32 v11, v3, v7
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v17, v11 ; GISEL-NEXT: v_mul_lo_u32 v14, 0, v7
; GISEL-NEXT: v_add_i32_e32 v15, vcc, 1, v4 ; GISEL-NEXT: v_mul_hi_u32 v17, v3, v7
; GISEL-NEXT: v_addc_u32_e32 v17, vcc, 0, v6, vcc ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v16 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v10
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18 ; GISEL-NEXT: v_mul_lo_u32 v9, v1, v4
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v13 ; GISEL-NEXT: v_mul_lo_u32 v10, v3, v6
; GISEL-NEXT: v_subb_u32_e64 v13, s[4:5], 0, v9, vcc ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v12, v9
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v14, v10
; GISEL-NEXT: v_add_i32_e32 v12, vcc, 1, v5
; GISEL-NEXT: v_addc_u32_e32 v14, vcc, 0, v4, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v13
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], 0, v9, vcc
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v1 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v1
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
; GISEL-NEXT: v_add_i32_e64 v13, s[6:7], 1, v7 ; GISEL-NEXT: v_add_i32_e64 v8, s[6:7], 1, v7
; GISEL-NEXT: v_addc_u32_e64 v18, s[6:7], 0, v8, s[6:7] ; GISEL-NEXT: v_addc_u32_e64 v17, s[6:7], 0, v6, s[6:7]
; GISEL-NEXT: v_sub_i32_e64 v2, s[6:7], v2, v14 ; GISEL-NEXT: v_sub_i32_e64 v2, s[6:7], v2, v11
; GISEL-NEXT: v_subb_u32_e64 v14, s[8:9], 0, v11, s[6:7] ; GISEL-NEXT: v_subb_u32_e64 v11, s[8:9], 0, v10, s[6:7]
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, v16, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v13, v16, v13, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v3 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v3
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, v12, v16, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, v15, v16, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], 1, v15 ; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], 1, v12
; GISEL-NEXT: v_addc_u32_e64 v16, s[4:5], 0, v17, s[4:5] ; GISEL-NEXT: v_addc_u32_e64 v16, s[4:5], 0, v14, s[4:5]
; GISEL-NEXT: v_sub_i32_e64 v11, s[4:5], 0, v11 ; GISEL-NEXT: v_sub_i32_e64 v10, s[4:5], 0, v10
; GISEL-NEXT: v_subbrev_u32_e64 v11, s[4:5], 0, v11, s[6:7] ; GISEL-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[6:7]
; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v3 ; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v3
; GISEL-NEXT: v_subbrev_u32_e64 v11, s[4:5], 0, v11, s[4:5] ; GISEL-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[4:5]
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v3 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v3
; GISEL-NEXT: v_add_i32_e64 v2, s[6:7], 1, v13 ; GISEL-NEXT: v_add_i32_e64 v2, s[6:7], 1, v8
; GISEL-NEXT: v_addc_u32_e64 v3, s[6:7], 0, v18, s[6:7] ; GISEL-NEXT: v_addc_u32_e64 v3, s[6:7], 0, v17, s[6:7]
; GISEL-NEXT: v_sub_i32_e64 v9, s[6:7], 0, v9 ; GISEL-NEXT: v_sub_i32_e64 v9, s[6:7], 0, v9
; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[4:5]
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9 ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GISEL-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v19, v0, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v11 ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
; GISEL-NEXT: v_cndmask_b32_e32 v1, v19, v1, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GISEL-NEXT: v_cndmask_b32_e32 v0, v15, v14, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v12, v15, vcc
; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v1 ; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v1
; GISEL-NEXT: v_cndmask_b32_e64 v1, v13, v2, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, v8, v2, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v9, v17, v16, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v8, v14, v16, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v3, v18, v3, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v3, v17, v3, s[4:5]
; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v12 ; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v11
; GISEL-NEXT: v_cndmask_b32_e64 v2, v7, v1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v2, v7, v1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v8, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[4:5]
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_udiv_v2i64_24bit: ; CGP-LABEL: v_udiv_v2i64_24bit:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s6, 0xffffff ; CGP-NEXT: s_mov_b32 s6, 0xffffff
; CGP-NEXT: v_and_b32_e32 v0, s6, v0 ; CGP-NEXT: v_and_b32_e32 v0, s6, v0
; CGP-NEXT: v_and_b32_e32 v1, s6, v2 ; CGP-NEXT: v_and_b32_e32 v1, s6, v2
Show All 32 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @udivrem_i64(i64 addrspace(1)* %out0, i64 addrspace(1)* %out1, i64 %x, i64 %y) { define amdgpu_kernel void @udivrem_i64(i64 addrspace(1)* %out0, i64 addrspace(1)* %out1, i64 %x, i64 %y) {
; GFX8-LABEL: udivrem_i64: ; GFX8-LABEL: udivrem_i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0 ; GFX8-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s11 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s11
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s10 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s10
; GFX8-NEXT: s_sub_u32 s2, 0, s10 ; GFX8-NEXT: s_sub_u32 s0, 0, s10
; GFX8-NEXT: s_cselect_b32 s0, 1, 0 ; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s0, s0, 1 ; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: s_cmp_lg_u32 s0, 0 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_subb_u32 s3, 0, s11 ; GFX8-NEXT: s_subb_u32 s1, 0, s11
; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX8-NEXT: v_trunc_f32_e32 v1, v1 ; GFX8-NEXT: v_trunc_f32_e32 v1, v1
; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX8-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX8-NEXT: v_add_f32_e32 v0, v2, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: v_mov_b32_e32 v6, s11 ; GFX8-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX8-NEXT: v_mul_lo_u32 v2, s2, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX8-NEXT: v_mul_hi_u32 v5, s0, v0
; GFX8-NEXT: v_mul_hi_u32 v5, s2, v0 ; GFX8-NEXT: v_mul_lo_u32 v4, s0, v0
; GFX8-NEXT: v_mul_lo_u32 v4, s2, v0
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4 ; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4
; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v6, v0, v4
; GFX8-NEXT: v_mul_lo_u32 v7, v1, v2
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v6
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3
; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v6, v5
; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX8-NEXT: v_mul_hi_u32 v5, s0, v0
; GFX8-NEXT: v_mul_lo_u32 v4, s0, v0
; GFX8-NEXT: v_mov_b32_e32 v6, s11
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4
; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v7, v0, v4 ; GFX8-NEXT: v_mul_hi_u32 v7, v0, v4
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v7 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v7
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v7, v1, v2 ; GFX8-NEXT: v_mul_lo_u32 v7, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3
; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2 ; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v5 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v5
; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_addc_u32_e64 v3, s[0:1], v1, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX8-NEXT: v_mul_lo_u32 v4, s3, v0
; GFX8-NEXT: v_mul_lo_u32 v5, s2, v3
; GFX8-NEXT: v_mul_hi_u32 v8, s2, v0
; GFX8-NEXT: v_mul_lo_u32 v7, s2, v0
; GFX8-NEXT: v_add_u32_e64 v1, s[0:1], v1, v2
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], v4, v5
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], v4, v8
; GFX8-NEXT: v_mul_lo_u32 v5, v3, v7
; GFX8-NEXT: v_mul_lo_u32 v8, v0, v4
; GFX8-NEXT: v_mul_hi_u32 v2, v0, v7
; GFX8-NEXT: v_mul_hi_u32 v7, v3, v7
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v8
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], v5, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX8-NEXT: v_mul_lo_u32 v5, v3, v4
; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], v8, v2
; GFX8-NEXT: v_mul_hi_u32 v8, v0, v4
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v7
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v8
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v7, s[0:1], v7, v8
; GFX8-NEXT: v_mul_hi_u32 v3, v3, v4
; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], v5, v2
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], v7, v5
; GFX8-NEXT: v_add_u32_e64 v3, s[0:1], v3, v4
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, s9, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s9, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX8-NEXT: v_mul_hi_u32 v5, s8, v0 ; GFX8-NEXT: v_mul_hi_u32 v5, s8, v0
; GFX8-NEXT: v_mul_hi_u32 v0, s9, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s9, v0
; GFX8-NEXT: v_mov_b32_e32 v4, s9 ; GFX8-NEXT: v_mov_b32_e32 v4, s9
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
Show All 29 Lines
; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[0:1]
; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, s10, v3 ; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, s10, v3
; GFX8-NEXT: v_subbrev_u32_e64 v8, s[0:1], 0, v2, vcc ; GFX8-NEXT: v_subbrev_u32_e64 v8, s[0:1], 0, v2, vcc
; GFX8-NEXT: v_add_u32_e64 v9, s[0:1], 1, v0 ; GFX8-NEXT: v_add_u32_e64 v9, s[0:1], 1, v0
; GFX8-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1] ; GFX8-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1]
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v8 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v8
; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v7 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v7
; GFX8-NEXT: v_subb_u32_e32 v2, vcc, v2, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v8 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v8
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s10, v7 ; GFX8-NEXT: v_subb_u32_e32 v2, vcc, v2, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v12, s[0:1], 1, v9 ; GFX8-NEXT: v_add_u32_e64 v12, s[0:1], 1, v9
; GFX8-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s10, v7
; GFX8-NEXT: v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1] ; GFX8-NEXT: v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1]
; GFX8-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11
; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v5, s[0:1] ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX8-NEXT: v_cndmask_b32_e64 v3, v4, v6, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v6, v8, v2, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v6, vcc
; GFX8-NEXT: v_mov_b32_e32 v4, s4 ; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v10, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
; GFX8-NEXT: v_mov_b32_e32 v5, s5 ; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: flat_store_dwordx2 v[4:5], v[0:1] ; GFX8-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX9-LABEL: udivrem_i64: ; GFX9-LABEL: udivrem_i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s11 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s11
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s10 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s10
; GFX9-NEXT: s_sub_u32 s2, 0, s10 ; GFX9-NEXT: s_sub_u32 s0, 0, s10
; GFX9-NEXT: s_cselect_b32 s0, 1, 0 ; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_subb_u32 s3, 0, s11 ; GFX9-NEXT: s_subb_u32 s1, 0, s11
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX9-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v2, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s2, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: v_add3_u32 v2, v3, v2, v4 ; GFX9-NEXT: v_add3_u32 v2, v3, v2, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v4, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v5 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v5
; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX9-NEXT: v_add_u32_e32 v3, v6, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v6, v3
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_add_u32_e32 v5, v5, v6 ; GFX9-NEXT: v_add_u32_e32 v5, v5, v6
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2 ; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[0:1], v1, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s3, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s2, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX9-NEXT: v_mul_lo_u32 v7, s2, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
; GFX9-NEXT: v_mov_b32_e32 v8, s9 ; GFX9-NEXT: v_mov_b32_e32 v8, s9
; GFX9-NEXT: v_add3_u32 v4, v4, v5, v6 ; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4
; GFX9-NEXT: v_mul_lo_u32 v5, v3, v7 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v4 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v7 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v3, v7 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v5, v2 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, v3, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, v1, v2
; GFX9-NEXT: v_add_u32_e32 v2, v6, v2 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_mul_hi_u32 v6, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v3, v3, v4 ; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v7 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v5, v2 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_add_u32_e32 v6, v7, v6 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v3, v6, v4, v3 ; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, s9, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s9, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX9-NEXT: v_mul_hi_u32 v5, s8, v0 ; GFX9-NEXT: v_mul_hi_u32 v5, s8, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s9, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s9, v0
; GFX9-NEXT: v_mov_b32_e32 v4, s11 ; GFX9-NEXT: v_mov_b32_e32 v4, s11
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5
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; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s10, v8 ; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s10, v8
; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v13, s[0:1], 1, v10 ; GFX9-NEXT: v_add_co_u32_e64 v13, s[0:1], 1, v10
; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v14, s[0:1], 0, v11, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v14, s[0:1], 0, v11, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v10, s[0:1] ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v12
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v11, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v2, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v7, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc
; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[4:5]
; GFX9-NEXT: global_store_dwordx2 v6, v[2:3], s[6:7] ; GFX9-NEXT: global_store_dwordx2 v6, v[2:3], s[6:7]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udivrem_i64: ; GFX10-LABEL: udivrem_i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s11 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s11
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s10 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s10
; GFX10-NEXT: s_sub_u32 s1, 0, s10 ; GFX10-NEXT: s_sub_u32 s0, 0, s10
; GFX10-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_and_b32 s1, s1, 1
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: s_subb_u32 s2, 0, s11 ; GFX10-NEXT: s_subb_u32 s1, 0, s11
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX10-NEXT: v_trunc_f32_e32 v1, v1 ; GFX10-NEXT: v_trunc_f32_e32 v1, v1
; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX10-NEXT: v_add_f32_e32 v0, v2, v0
; GFX10-NEXT: v_mul_lo_u32 v2, s1, v1 ; GFX10-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s2, v0 ; GFX10-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX10-NEXT: v_mul_hi_u32 v4, s1, v0 ; GFX10-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX10-NEXT: v_mul_lo_u32 v5, s1, v0 ; GFX10-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX10-NEXT: v_add3_u32 v2, v3, v2, v4 ; GFX10-NEXT: v_add3_u32 v2, v3, v2, v4
; GFX10-NEXT: v_mul_lo_u32 v3, v1, v5 ; GFX10-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX10-NEXT: v_mul_hi_u32 v6, v1, v5 ; GFX10-NEXT: v_mul_hi_u32 v6, v1, v5
; GFX10-NEXT: v_mul_hi_u32 v5, v0, v5 ; GFX10-NEXT: v_mul_hi_u32 v5, v0, v5
; GFX10-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX10-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX10-NEXT: v_mul_lo_u32 v7, v1, v2 ; GFX10-NEXT: v_mul_lo_u32 v7, v1, v2
; GFX10-NEXT: v_mul_hi_u32 v8, v0, v2 ; GFX10-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX10-NEXT: v_add_co_u32 v3, s2, v3, v4
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s2
; GFX10-NEXT: v_add_co_u32 v6, s2, v7, v6
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s2
; GFX10-NEXT: v_add_co_u32 v3, s2, v3, v5
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2
; GFX10-NEXT: v_add_co_u32 v5, s2, v6, v8
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s2
; GFX10-NEXT: v_add_nc_u32_e32 v3, v4, v3
; GFX10-NEXT: v_add_nc_u32_e32 v4, v7, v6
; GFX10-NEXT: v_add_co_u32 v3, s2, v5, v3
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s2
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
; GFX10-NEXT: v_add3_u32 v2, v4, v5, v2
; GFX10-NEXT: v_mul_hi_u32 v3, s0, v0
; GFX10-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v2, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX10-NEXT: v_mul_lo_u32 v4, s0, v1
; GFX10-NEXT: v_mul_hi_u32 v6, v1, v5
; GFX10-NEXT: v_add3_u32 v2, v2, v4, v3
; GFX10-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX10-NEXT: v_mul_hi_u32 v5, v0, v5
; GFX10-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX10-NEXT: v_mul_lo_u32 v7, v1, v2
; GFX10-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX10-NEXT: v_add_co_u32 v3, s0, v3, v4 ; GFX10-NEXT: v_add_co_u32 v3, s0, v3, v4
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v6, s0, v7, v6 ; GFX10-NEXT: v_add_co_u32 v6, s0, v7, v6
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v3, s0, v3, v5 ; GFX10-NEXT: v_add_co_u32 v3, s0, v3, v5
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v5, s0, v6, v8 ; GFX10-NEXT: v_add_co_u32 v5, s0, v6, v8
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v3, v4, v3 ; GFX10-NEXT: v_add_nc_u32_e32 v3, v4, v3
; GFX10-NEXT: v_add_nc_u32_e32 v4, v7, v6 ; GFX10-NEXT: v_add_nc_u32_e32 v4, v7, v6
; GFX10-NEXT: v_add_co_u32 v3, s0, v5, v3 ; GFX10-NEXT: v_add_co_u32 v3, s0, v5, v3
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
; GFX10-NEXT: v_add3_u32 v2, v4, v5, v2 ; GFX10-NEXT: v_add3_u32 v2, v4, v5, v2
; GFX10-NEXT: v_mul_lo_u32 v4, s2, v0 ; GFX10-NEXT: v_mul_hi_u32 v4, s9, v0
; GFX10-NEXT: v_mul_hi_u32 v5, s1, v0
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, v1, v2, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v7, s1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: v_mul_lo_u32 v6, s1, v3
; GFX10-NEXT: v_mul_hi_u32 v8, v3, v7
; GFX10-NEXT: v_add3_u32 v4, v4, v6, v5
; GFX10-NEXT: v_mul_lo_u32 v5, v3, v7
; GFX10-NEXT: v_mul_hi_u32 v7, v0, v7
; GFX10-NEXT: v_mul_lo_u32 v6, v0, v4
; GFX10-NEXT: v_mul_lo_u32 v9, v3, v4
; GFX10-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX10-NEXT: v_mul_hi_u32 v3, v3, v4
; GFX10-NEXT: v_add_co_u32 v5, s0, v5, v6
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v8, s0, v9, v8
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v5, s0, v5, v7
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v7, s0, v8, v10
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v5, v6, v5
; GFX10-NEXT: v_add_nc_u32_e32 v4, v9, v8
; GFX10-NEXT: v_add_co_u32 v5, s0, v7, v5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_add3_u32 v2, v4, v6, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v2, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v2, vcc_lo
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v5
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v2, s9, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s9, v0
; GFX10-NEXT: v_mul_hi_u32 v4, s9, v0
; GFX10-NEXT: v_mul_hi_u32 v0, s8, v0 ; GFX10-NEXT: v_mul_hi_u32 v0, s8, v0
; GFX10-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX10-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX10-NEXT: v_mul_lo_u32 v5, s9, v1 ; GFX10-NEXT: v_mul_lo_u32 v5, s9, v1
; GFX10-NEXT: v_mul_hi_u32 v6, s8, v1 ; GFX10-NEXT: v_mul_hi_u32 v6, s8, v1
; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1 ; GFX10-NEXT: v_mul_hi_u32 v1, s9, v1
; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v2, v3
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s0, v5, v4 ; GFX10-NEXT: v_add_co_u32 v4, s0, v5, v4
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v0, s0, v2, v0 ; GFX10-NEXT: v_add_co_u32 v0, s0, v2, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v2, s0, v4, v6 ; GFX10-NEXT: v_add_co_u32 v2, s0, v4, v6
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v0, v3, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v3, v0
; GFX10-NEXT: v_add_nc_u32_e32 v3, v5, v4 ; GFX10-NEXT: v_add_nc_u32_e32 v3, v5, v4
; GFX10-NEXT: v_add_co_u32 v0, s0, v2, v0 ; GFX10-NEXT: v_add_co_u32 v0, s0, v2, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
; GFX10-NEXT: v_mul_lo_u32 v5, s10, v0 ; GFX10-NEXT: v_mul_lo_u32 v5, s10, v0
; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v0, 1
; GFX10-NEXT: v_add3_u32 v1, v3, v2, v1 ; GFX10-NEXT: v_add3_u32 v1, v3, v2, v1
; GFX10-NEXT: v_mul_lo_u32 v2, s11, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, s11, v0
; GFX10-NEXT: v_mul_hi_u32 v3, s10, v0 ; GFX10-NEXT: v_mul_hi_u32 v3, s10, v0
; GFX10-NEXT: v_mul_lo_u32 v4, s10, v1 ; GFX10-NEXT: v_mul_lo_u32 v4, s10, v1
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add3_u32 v2, v2, v4, v3 ; GFX10-NEXT: v_add3_u32 v2, v2, v4, v3
; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v0, 1 ; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v6, 1
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v7, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v6, s9, v2 ; GFX10-NEXT: v_sub_nc_u32_e32 v8, s9, v2
; GFX10-NEXT: v_sub_co_u32 v5, vcc_lo, s8, v5 ; GFX10-NEXT: v_sub_co_u32 v5, vcc_lo, s8, v5
; GFX10-NEXT: v_sub_co_ci_u32_e64 v7, s0, s9, v2, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e64 v9, s0, s9, v2, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v2, vcc_lo, s11, v6, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v2, vcc_lo, s11, v8, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s10, v5 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s10, v5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v5, s10 ; GFX10-NEXT: v_sub_co_u32 v10, vcc_lo, v5, s10
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v9, s0, 0, v2, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v11, s0, 0, v2, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v7
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v8
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v9 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v9
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s11, v11
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, s0
; GFX10-NEXT: v_add_co_u32 v13, s0, v3, 1 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v10
; GFX10-NEXT: v_add_co_ci_u32_e64 v14, s0, 0, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s11, v11
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, -1, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s11, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s11, v9
; GFX10-NEXT: v_cndmask_b32_e64 v11, v12, v11, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v12, v8, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s11, v7 ; GFX10-NEXT: v_cndmask_b32_e32 v12, v14, v13, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11 ; GFX10-NEXT: v_sub_co_u32 v13, vcc_lo, v10, s10
; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v6, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v10, s0, v8, s10 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s0, 0, v2, s0 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v12
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v8
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v6 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v6, v8, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v8, v9, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v13, s0
; GFX10-NEXT: v_mov_b32_e32 v9, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v3, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v3, s1
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, v4, s1
; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v6, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v5, v6, s1
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v8, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v9, v7, s1
; GFX10-NEXT: global_store_dwordx2 v9, v[0:1], s[4:5] ; GFX10-NEXT: global_store_dwordx2 v8, v[0:1], s[4:5]
; GFX10-NEXT: global_store_dwordx2 v9, v[2:3], s[6:7] ; GFX10-NEXT: global_store_dwordx2 v8, v[2:3], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = udiv i64 %x, %y %div = udiv i64 %x, %y
store i64 %div, i64 addrspace(1)* %out0 store i64 %div, i64 addrspace(1)* %out0
%rem = urem i64 %x, %y %rem = urem i64 %x, %y
store i64 %rem, i64 addrspace(1)* %out1 store i64 %rem, i64 addrspace(1)* %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 474 Lines • ▼ Show 20 Lines
; GFX8-LABEL: udivrem_v2i64: ; GFX8-LABEL: udivrem_v2i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20 ; GFX8-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20
; GFX8-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x10 ; GFX8-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x10
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX8-NEXT: s_sub_u32 s2, 0, s8 ; GFX8-NEXT: s_sub_u32 s0, 0, s8
; GFX8-NEXT: s_cselect_b32 s0, 1, 0 ; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s0, s0, 1 ; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: s_cmp_lg_u32 s0, 0 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_subb_u32 s3, 0, s9 ; GFX8-NEXT: s_subb_u32 s1, 0, s9
; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX8-NEXT: v_trunc_f32_e32 v1, v1 ; GFX8-NEXT: v_trunc_f32_e32 v1, v1
; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX8-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX8-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX8-NEXT: v_add_f32_e32 v0, v2, v0
; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: v_mov_b32_e32 v6, s9 ; GFX8-NEXT: s_sub_u32 s2, 0, s10
; GFX8-NEXT: v_mul_lo_u32 v2, s2, v1 ; GFX8-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX8-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX8-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX8-NEXT: v_mul_hi_u32 v5, s2, v0 ; GFX8-NEXT: v_mul_hi_u32 v5, s0, v0
; GFX8-NEXT: v_mul_lo_u32 v4, s2, v0 ; GFX8-NEXT: v_mul_lo_u32 v4, s0, v0
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4 ; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4
; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v6, v0, v4
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v6
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3
; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v6, v4
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v6, v5
; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX8-NEXT: v_mul_hi_u32 v5, s0, v0
; GFX8-NEXT: v_mul_lo_u32 v4, s0, v0
; GFX8-NEXT: v_mov_b32_e32 v6, s9
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
; GFX8-NEXT: v_mul_lo_u32 v3, v1, v4
; GFX8-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX8-NEXT: v_mul_hi_u32 v7, v0, v4 ; GFX8-NEXT: v_mul_hi_u32 v7, v0, v4
; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v7 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v7
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v7, v1, v2 ; GFX8-NEXT: v_mul_lo_u32 v7, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3
; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2 ; GFX8-NEXT: v_mul_hi_u32 v5, v0, v2
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v5 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, v7, v5
; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_addc_u32_e64 v3, s[0:1], v1, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX8-NEXT: v_mul_lo_u32 v4, s3, v0
; GFX8-NEXT: v_mul_lo_u32 v5, s2, v3
; GFX8-NEXT: v_mul_hi_u32 v8, s2, v0
; GFX8-NEXT: v_mul_lo_u32 v7, s2, v0
; GFX8-NEXT: v_add_u32_e64 v1, s[0:1], v1, v2
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], v4, v5
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], v4, v8
; GFX8-NEXT: v_mul_lo_u32 v5, v3, v7
; GFX8-NEXT: v_mul_lo_u32 v8, v0, v4
; GFX8-NEXT: v_mul_hi_u32 v2, v0, v7
; GFX8-NEXT: v_mul_hi_u32 v7, v3, v7
; GFX8-NEXT: s_sub_u32 s2, 0, s10
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v8
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], v5, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX8-NEXT: v_mul_lo_u32 v5, v3, v4
; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], v8, v2
; GFX8-NEXT: v_mul_hi_u32 v8, v0, v4
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v7
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v5, s[0:1], v5, v8
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v7, s[0:1], v7, v8
; GFX8-NEXT: v_mul_hi_u32 v3, v3, v4
; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], v5, v2
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], v7, v5
; GFX8-NEXT: v_add_u32_e64 v3, s[0:1], v3, v4
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_mul_lo_u32 v2, s13, v0 ; GFX8-NEXT: v_mul_lo_u32 v2, s13, v0
; GFX8-NEXT: v_mul_lo_u32 v3, s12, v1 ; GFX8-NEXT: v_mul_lo_u32 v3, s12, v1
; GFX8-NEXT: v_mul_hi_u32 v5, s12, v0 ; GFX8-NEXT: v_mul_hi_u32 v5, s12, v0
; GFX8-NEXT: v_mul_hi_u32 v0, s13, v0 ; GFX8-NEXT: v_mul_hi_u32 v0, s13, v0
; GFX8-NEXT: v_mov_b32_e32 v4, s13 ; GFX8-NEXT: v_mov_b32_e32 v4, s13
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
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; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v8 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v8
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s8, v7 ; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s8, v7
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v12, s[0:1], 1, v9 ; GFX8-NEXT: v_add_u32_e64 v12, s[0:1], 1, v9
; GFX8-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
; GFX8-NEXT: v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1] ; GFX8-NEXT: v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1]
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX8-NEXT: v_cvt_f32_u32_e32 v4, s11
; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[0:1]
; GFX8-NEXT: v_cvt_f32_u32_e32 v9, s10
; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX8-NEXT: v_mul_f32_e32 v4, 0x4f800000, v4
; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX8-NEXT: v_add_f32_e32 v4, v4, v9
; GFX8-NEXT: v_rcp_iflag_f32_e32 v7, v4
; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v2, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v4, v3, v6, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX8-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v7 ; GFX8-NEXT: v_cvt_f32_u32_e32 v13, s11
; GFX8-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 ; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX8-NEXT: v_trunc_f32_e32 v3, v3 ; GFX8-NEXT: v_cvt_f32_u32_e32 v12, s10
; GFX8-NEXT: v_mul_f32_e32 v6, 0xcf800000, v3 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX8-NEXT: v_add_f32_e32 v2, v6, v2 ; GFX8-NEXT: v_mul_f32_e32 v4, 0x4f800000, v13
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v10, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX8-NEXT: v_add_f32_e32 v4, v4, v12
; GFX8-NEXT: v_rcp_iflag_f32_e32 v9, v4
; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11
; GFX8-NEXT: v_cndmask_b32_e64 v4, v7, v6, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v4, v3, v4, vcc
; GFX8-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v9
; GFX8-NEXT: v_mul_f32_e32 v6, 0x2f800000, v3
; GFX8-NEXT: v_trunc_f32_e32 v6, v6
; GFX8-NEXT: v_mul_f32_e32 v7, 0xcf800000, v6
; GFX8-NEXT: v_add_f32_e32 v3, v7, v3
; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1]
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX8-NEXT: s_cselect_b32 s0, 1, 0 ; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: s_and_b32 s0, s0, 1 ; GFX8-NEXT: s_and_b32 s0, s0, 1
; GFX8-NEXT: s_cmp_lg_u32 s0, 0 ; GFX8-NEXT: s_cmp_lg_u32 s0, 0
; GFX8-NEXT: s_subb_u32 s3, 0, s11 ; GFX8-NEXT: s_subb_u32 s3, 0, s11
; GFX8-NEXT: v_mul_lo_u32 v7, s3, v3
; GFX8-NEXT: v_mul_lo_u32 v8, s2, v6
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
; GFX8-NEXT: v_mul_hi_u32 v10, s2, v3
; GFX8-NEXT: v_mul_lo_u32 v9, s2, v3
; GFX8-NEXT: v_add_u32_e64 v7, s[0:1], v7, v8
; GFX8-NEXT: v_add_u32_e64 v7, s[0:1], v7, v10
; GFX8-NEXT: v_mul_lo_u32 v8, v6, v9
; GFX8-NEXT: v_mul_lo_u32 v10, v3, v7
; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc
; GFX8-NEXT: v_mul_hi_u32 v2, v3, v9
; GFX8-NEXT: v_mul_hi_u32 v9, v6, v9
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v10
; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v8, v2
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_mul_lo_u32 v8, v6, v7
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v10, v2
; GFX8-NEXT: v_mul_hi_u32 v10, v3, v7
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v9
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v10
; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v10
; GFX8-NEXT: v_mul_hi_u32 v7, v6, v7
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v8, v2
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v9, v8
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v8
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v3, v2
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v6, v7, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, s3, v2 ; GFX8-NEXT: v_mul_lo_u32 v6, s3, v2
; GFX8-NEXT: v_mul_lo_u32 v7, s2, v3 ; GFX8-NEXT: v_mul_lo_u32 v7, s2, v3
; GFX8-NEXT: v_mul_hi_u32 v9, s2, v2 ; GFX8-NEXT: v_mul_hi_u32 v9, s2, v2
; GFX8-NEXT: v_mul_lo_u32 v8, s2, v2 ; GFX8-NEXT: v_mul_lo_u32 v8, s2, v2
; GFX8-NEXT: v_mov_b32_e32 v10, s11 ; GFX8-NEXT: v_mov_b32_e32 v10, s11
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9
; GFX8-NEXT: v_mul_lo_u32 v7, v3, v8 ; GFX8-NEXT: v_mul_lo_u32 v7, v3, v8
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; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v9, vcc, v11, v9 ; GFX8-NEXT: v_add_u32_e32 v9, vcc, v11, v9
; GFX8-NEXT: v_mul_hi_u32 v6, v3, v6 ; GFX8-NEXT: v_mul_hi_u32 v6, v3, v6
; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v8, v7
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v9, v8 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v9, v8
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v7
; GFX8-NEXT: v_addc_u32_e64 v7, s[0:1], v3, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc
; GFX8-NEXT: v_mul_lo_u32 v8, s3, v2
; GFX8-NEXT: v_mul_lo_u32 v9, s2, v7
; GFX8-NEXT: v_mul_hi_u32 v12, s2, v2
; GFX8-NEXT: v_mul_lo_u32 v11, s2, v2
; GFX8-NEXT: v_add_u32_e64 v3, s[0:1], v3, v6
; GFX8-NEXT: v_add_u32_e64 v8, s[0:1], v8, v9
; GFX8-NEXT: v_add_u32_e64 v8, s[0:1], v8, v12
; GFX8-NEXT: v_mul_lo_u32 v9, v7, v11
; GFX8-NEXT: v_mul_lo_u32 v12, v2, v8
; GFX8-NEXT: v_mul_hi_u32 v6, v2, v11
; GFX8-NEXT: v_mul_hi_u32 v11, v7, v11
; GFX8-NEXT: v_add_u32_e64 v9, s[0:1], v9, v12
; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v6, s[0:1], v9, v6
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1]
; GFX8-NEXT: v_mul_lo_u32 v9, v7, v8
; GFX8-NEXT: v_add_u32_e64 v6, s[0:1], v12, v6
; GFX8-NEXT: v_mul_hi_u32 v12, v2, v8
; GFX8-NEXT: v_add_u32_e64 v9, s[0:1], v9, v11
; GFX8-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v9, s[0:1], v9, v12
; GFX8-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v11, s[0:1], v11, v12
; GFX8-NEXT: v_mul_hi_u32 v7, v7, v8
; GFX8-NEXT: v_add_u32_e64 v6, s[0:1], v9, v6
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[0:1]
; GFX8-NEXT: v_add_u32_e64 v8, s[0:1], v11, v9
; GFX8-NEXT: v_add_u32_e64 v7, s[0:1], v7, v8
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GFX8-NEXT: v_mul_lo_u32 v6, s15, v2 ; GFX8-NEXT: v_mul_lo_u32 v6, s15, v2
; GFX8-NEXT: v_mul_lo_u32 v7, s14, v3 ; GFX8-NEXT: v_mul_lo_u32 v7, s14, v3
; GFX8-NEXT: v_mul_hi_u32 v9, s14, v2 ; GFX8-NEXT: v_mul_hi_u32 v9, s14, v2
; GFX8-NEXT: v_mul_hi_u32 v2, s15, v2 ; GFX8-NEXT: v_mul_hi_u32 v2, s15, v2
; GFX8-NEXT: v_mov_b32_e32 v8, s15 ; GFX8-NEXT: v_mov_b32_e32 v8, s15
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v9
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; ;
; GFX9-LABEL: udivrem_v2i64: ; GFX9-LABEL: udivrem_v2i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20 ; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20
; GFX9-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x10 ; GFX9-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x10
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX9-NEXT: s_sub_u32 s2, 0, s8 ; GFX9-NEXT: s_sub_u32 s0, 0, s8
; GFX9-NEXT: s_cselect_b32 s0, 1, 0 ; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_subb_u32 s3, 0, s9 ; GFX9-NEXT: s_subb_u32 s1, 0, s9
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1 ; GFX9-NEXT: v_mul_f32_e32 v2, 0xcf800000, v1
; GFX9-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v2, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_u32_e32 v14, s11 ; GFX9-NEXT: v_cvt_f32_u32_e32 v14, s11
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v1 ; GFX9-NEXT: s_sub_u32 s2, 0, s10
; GFX9-NEXT: v_mul_lo_u32 v3, s3, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s2, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: v_mul_f32_e32 v14, 0x4f800000, v14 ; GFX9-NEXT: v_mul_f32_e32 v14, 0x4f800000, v14
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX9-NEXT: v_add3_u32 v2, v3, v2, v4 ; GFX9-NEXT: v_add3_u32 v2, v3, v2, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v4, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v5 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v5
; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX9-NEXT: v_add_u32_e32 v3, v6, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v6, v3
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_add_u32_e32 v5, v5, v6 ; GFX9-NEXT: v_add_u32_e32 v5, v5, v6
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2 ; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[0:1], v1, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s3, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s2, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX9-NEXT: v_mul_lo_u32 v7, s2, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX9-NEXT: v_add_u32_e32 v1, v1, v2 ; GFX9-NEXT: v_mov_b32_e32 v7, s13
; GFX9-NEXT: v_add3_u32 v4, v4, v5, v6 ; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4
; GFX9-NEXT: v_mul_lo_u32 v5, v3, v7 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v4 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v2, v0, v7 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v3, v7 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v5, v2 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, v3, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, v1, v2
; GFX9-NEXT: v_add_u32_e32 v2, v6, v2 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_mul_hi_u32 v6, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v3, v3, v4 ; GFX9-NEXT: v_mul_hi_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v7 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e64 v2, s[0:1], v5, v2 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_add_u32_e32 v6, v7, v6 ; GFX9-NEXT: v_add_u32_e32 v5, v6, v5
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v3, v6, v4, v3 ; GFX9-NEXT: v_add3_u32 v2, v5, v4, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, s13, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s13, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s12, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s12, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s12, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s12, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s13, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s13, v0
; GFX9-NEXT: v_mov_b32_e32 v7, s13 ; GFX9-NEXT: v_mov_b32_e32 v5, s9
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s13, v1 ; GFX9-NEXT: v_mul_lo_u32 v4, s13, v1
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_mul_hi_u32 v3, s12, v1 ; GFX9-NEXT: v_mul_hi_u32 v3, s12, v1
; GFX9-NEXT: v_mul_hi_u32 v1, s13, v1 ; GFX9-NEXT: v_mul_hi_u32 v1, s13, v1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v1, v3, v2, v1 ; GFX9-NEXT: v_add3_u32 v1, v3, v2, v1
; GFX9-NEXT: v_mul_lo_u32 v2, s9, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, s9, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s8, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s8, v0
; GFX9-NEXT: v_mul_lo_u32 v6, s8, v0 ; GFX9-NEXT: v_mul_lo_u32 v6, s8, v0
; GFX9-NEXT: v_mov_b32_e32 v5, s9
; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4 ; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4
; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s12, v6 ; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s12, v6
; GFX9-NEXT: v_subb_co_u32_e64 v6, s[0:1], v7, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e64 v6, s[0:1], v7, v2, vcc
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v6 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v6
; GFX9-NEXT: v_sub_u32_e32 v2, s13, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, s13, v2
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v3
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v6 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v6
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1]
; GFX9-NEXT: v_subrev_co_u32_e32 v7, vcc, s8, v3 ; GFX9-NEXT: v_subrev_co_u32_e32 v7, vcc, s8, v3
; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[0:1], 0, v2, vcc ; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[0:1], 0, v2, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s10 ; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s10
; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], 1, v0 ; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], 1, v0
; GFX9-NEXT: v_addc_co_u32_e64 v10, s[0:1], 0, v1, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v10, s[0:1], 0, v1, s[0:1]
; GFX9-NEXT: v_add_f32_e32 v5, v14, v5 ; GFX9-NEXT: v_add_f32_e32 v5, v14, v5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v8 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v8
; GFX9-NEXT: v_rcp_iflag_f32_e32 v5, v5
; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v7 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v7
; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v8 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v8
; GFX9-NEXT: v_subrev_co_u32_e32 v15, vcc, s8, v7 ; GFX9-NEXT: v_subrev_co_u32_e32 v15, vcc, s8, v7
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[0:1]
; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX9-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT: v_mul_f32_e32 v11, 0x2f800000, v5
; GFX9-NEXT: v_add_co_u32_e64 v12, s[0:1], 1, v9 ; GFX9-NEXT: v_add_co_u32_e64 v12, s[0:1], 1, v9
; GFX9-NEXT: v_trunc_f32_e32 v11, v11 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GFX9-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
; GFX9-NEXT: v_mul_f32_e32 v12, 0xcf800000, v11 ; GFX9-NEXT: v_mul_f32_e32 v12, 0x2f800000, v5
; GFX9-NEXT: v_addc_co_u32_e64 v13, s[0:1], 0, v10, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[0:1], 0, v10, s[0:1]
; GFX9-NEXT: v_add_f32_e32 v5, v12, v5 ; GFX9-NEXT: v_trunc_f32_e32 v12, v12
; GFX9-NEXT: s_sub_u32 s8, 0, s10 ; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
; GFX9-NEXT: v_mul_f32_e32 v13, 0xcf800000, v12
; GFX9-NEXT: v_add_f32_e32 v5, v13, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v11, v11 ; GFX9-NEXT: v_cvt_u32_f32_e32 v12, v12
; GFX9-NEXT: s_cselect_b32 s0, 1, 0 ; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s0, s0, 1
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_subb_u32 s9, 0, s11 ; GFX9-NEXT: s_subb_u32 s3, 0, s11
; GFX9-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc ; GFX9-NEXT: v_mul_lo_u32 v13, s3, v5
; GFX9-NEXT: v_mul_lo_u32 v13, s9, v5 ; GFX9-NEXT: v_mul_lo_u32 v14, s2, v12
; GFX9-NEXT: v_mul_lo_u32 v14, s8, v11 ; GFX9-NEXT: v_mul_hi_u32 v16, s2, v5
; GFX9-NEXT: v_mul_hi_u32 v16, s8, v5 ; GFX9-NEXT: v_mul_lo_u32 v17, s2, v5
; GFX9-NEXT: v_mul_lo_u32 v12, s8, v5 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[0:1]
; GFX9-NEXT: v_add3_u32 v4, v13, v14, v16 ; GFX9-NEXT: v_add3_u32 v4, v13, v14, v16
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v10, s[0:1] ; GFX9-NEXT: v_mul_lo_u32 v9, v12, v17
; GFX9-NEXT: v_mul_lo_u32 v9, v11, v12 ; GFX9-NEXT: v_mul_lo_u32 v13, v5, v4
; GFX9-NEXT: v_mul_lo_u32 v10, v5, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
; GFX9-NEXT: v_mul_hi_u32 v13, v5, v12 ; GFX9-NEXT: v_mul_hi_u32 v10, v5, v17
; GFX9-NEXT: v_mul_hi_u32 v12, v11, v12 ; GFX9-NEXT: v_mul_hi_u32 v14, v12, v17
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc ; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], v9, v13
; GFX9-NEXT: v_add_co_u32_e64 v9, s[2:3], v9, v10 ; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[2:3] ; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], v9, v10
; GFX9-NEXT: v_add_co_u32_e64 v9, s[2:3], v9, v13 ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[2:3] ; GFX9-NEXT: v_mul_lo_u32 v10, v12, v4
; GFX9-NEXT: v_mul_lo_u32 v13, v11, v4 ; GFX9-NEXT: v_add_u32_e32 v9, v13, v9
; GFX9-NEXT: v_add_u32_e32 v9, v10, v9 ; GFX9-NEXT: v_mul_hi_u32 v13, v5, v4
; GFX9-NEXT: v_mul_hi_u32 v10, v5, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v12, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v11, v4 ; GFX9-NEXT: v_add_co_u32_e64 v10, s[0:1], v10, v14
; GFX9-NEXT: v_add_co_u32_e64 v12, s[2:3], v13, v12 ; GFX9-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[2:3] ; GFX9-NEXT: v_add_co_u32_e64 v10, s[0:1], v10, v13
; GFX9-NEXT: v_add_co_u32_e64 v10, s[2:3], v12, v10 ; GFX9-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[2:3] ; GFX9-NEXT: v_add_co_u32_e64 v9, s[0:1], v10, v9
; GFX9-NEXT: v_add_co_u32_e64 v9, s[2:3], v10, v9 ; GFX9-NEXT: v_add_u32_e32 v13, v14, v13
; GFX9-NEXT: v_add_u32_e32 v12, v13, v12 ; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[2:3] ; GFX9-NEXT: v_add3_u32 v4, v13, v10, v4
; GFX9-NEXT: v_add3_u32 v10, v12, v10, v4 ; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v5, v9
; GFX9-NEXT: v_add_co_u32_e64 v5, s[2:3], v5, v9 ; GFX9-NEXT: v_addc_co_u32_e64 v9, s[0:1], v12, v4, s[0:1]
; GFX9-NEXT: v_addc_co_u32_e64 v9, s[6:7], v11, v10, s[2:3] ; GFX9-NEXT: v_mul_lo_u32 v4, s3, v5
; GFX9-NEXT: v_mul_lo_u32 v12, s9, v5 ; GFX9-NEXT: v_mul_lo_u32 v12, s2, v9
; GFX9-NEXT: v_mul_lo_u32 v13, s8, v9 ; GFX9-NEXT: v_mul_hi_u32 v13, s2, v5
; GFX9-NEXT: v_mul_hi_u32 v14, s8, v5 ; GFX9-NEXT: v_mul_lo_u32 v10, s2, v5
; GFX9-NEXT: v_mul_lo_u32 v15, s8, v5 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11
; GFX9-NEXT: v_cndmask_b32_e64 v4, v3, v7, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v8, v2, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; GFX9-NEXT: v_add3_u32 v8, v4, v12, v13
; GFX9-NEXT: v_add3_u32 v3, v12, v13, v14 ; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v15, s[0:1]
; GFX9-NEXT: v_mul_lo_u32 v7, v9, v15 ; GFX9-NEXT: v_mul_lo_u32 v11, v9, v10
; GFX9-NEXT: v_mul_lo_u32 v8, v5, v3 ; GFX9-NEXT: v_mul_lo_u32 v12, v5, v8
; GFX9-NEXT: v_add_u32_e32 v10, v11, v10 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v3, v7, vcc
; GFX9-NEXT: v_mul_hi_u32 v11, v5, v15 ; GFX9-NEXT: v_mul_hi_u32 v3, v5, v10
; GFX9-NEXT: v_mul_hi_u32 v12, v9, v15 ; GFX9-NEXT: v_mul_hi_u32 v10, v9, v10
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8 ; GFX9-NEXT: v_add_co_u32_e64 v7, s[0:1], v11, v12
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[0:1]
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v11 ; GFX9-NEXT: v_add_co_u32_e64 v3, s[0:1], v7, v3
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[0:1]
; GFX9-NEXT: v_mul_lo_u32 v11, v9, v3 ; GFX9-NEXT: v_mul_lo_u32 v7, v9, v8
; GFX9-NEXT: v_add_u32_e32 v7, v8, v7 ; GFX9-NEXT: v_add_u32_e32 v3, v11, v3
; GFX9-NEXT: v_mul_hi_u32 v8, v5, v3 ; GFX9-NEXT: v_mul_hi_u32 v11, v5, v8
; GFX9-NEXT: v_mul_hi_u32 v3, v9, v3 ; GFX9-NEXT: v_mul_hi_u32 v8, v9, v8
; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v11, v12 ; GFX9-NEXT: v_add_co_u32_e64 v7, s[0:1], v7, v10
; GFX9-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[0:1]
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v11, v8 ; GFX9-NEXT: v_add_co_u32_e64 v7, s[0:1], v7, v11
; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[0:1]
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 ; GFX9-NEXT: v_add_co_u32_e64 v3, s[0:1], v7, v3
; GFX9-NEXT: v_add_u32_e32 v11, v12, v11 ; GFX9-NEXT: v_add_u32_e32 v10, v10, v11
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
; GFX9-NEXT: v_add3_u32 v3, v11, v8, v3 ; GFX9-NEXT: v_add3_u32 v7, v10, v7, v8
; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v10, v3, s[2:3] ; GFX9-NEXT: v_add_co_u32_e64 v3, s[0:1], v5, v3
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v5, v7 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], v9, v7, s[0:1]
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, s15, v3
; GFX9-NEXT: v_mul_lo_u32 v8, s15, v7 ; GFX9-NEXT: v_mul_lo_u32 v9, s14, v7
; GFX9-NEXT: v_mul_lo_u32 v9, s14, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v5, v6, v2, s[0:1] ; GFX9-NEXT: v_mul_hi_u32 v2, s14, v3
; GFX9-NEXT: v_mul_hi_u32 v2, s14, v7 ; GFX9-NEXT: v_mul_hi_u32 v3, s15, v3
; GFX9-NEXT: v_mul_hi_u32 v7, s15, v7
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v8, v9 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v8, v9
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, s15, v3 ; GFX9-NEXT: v_mul_lo_u32 v6, s15, v7
; GFX9-NEXT: v_add_u32_e32 v2, v8, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v8, v2
; GFX9-NEXT: v_mul_hi_u32 v8, s14, v3 ; GFX9-NEXT: v_mul_hi_u32 v8, s14, v7
; GFX9-NEXT: v_mul_hi_u32 v3, s15, v3 ; GFX9-NEXT: v_mul_hi_u32 v7, s15, v7
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v6, v3
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v8
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2
; GFX9-NEXT: v_add_u32_e32 v7, v7, v8
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v3, v7, v6, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX9-NEXT: v_add3_u32 v3, v6, v3, v7
; GFX9-NEXT: v_mul_lo_u32 v6, s11, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, s11, v2
; GFX9-NEXT: v_mul_lo_u32 v7, s10, v3 ; GFX9-NEXT: v_mul_lo_u32 v7, s10, v3
; GFX9-NEXT: v_mul_hi_u32 v8, s10, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, s10, v2
; GFX9-NEXT: v_mul_lo_u32 v10, s10, v2 ; GFX9-NEXT: v_mul_lo_u32 v10, s10, v2
; GFX9-NEXT: v_mov_b32_e32 v11, s15 ; GFX9-NEXT: v_mov_b32_e32 v11, s15
; GFX9-NEXT: v_mov_b32_e32 v9, s11 ; GFX9-NEXT: v_mov_b32_e32 v9, s11
; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8 ; GFX9-NEXT: v_add3_u32 v6, v6, v7, v8
; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, s14, v10 ; GFX9-NEXT: v_sub_co_u32_e32 v7, vcc, s14, v10
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; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v12 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v12
; GFX9-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v13, v13, v14, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v14, s[0:1], 1, v2 ; GFX9-NEXT: v_add_co_u32_e64 v14, s[0:1], 1, v2
; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v9, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v15, s[0:1], 0, v3, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v15, s[0:1], 0, v3, s[0:1]
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, 1, v14 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, 1, v14
; GFX9-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v15, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v15, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX9-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v9, v14, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
; GFX9-NEXT: v_subrev_co_u32_e64 v15, s[0:1], s10, v11 ; GFX9-NEXT: v_subrev_co_u32_e64 v15, s[0:1], s10, v11
; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[0:1], 0, v6, s[0:1] ; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[0:1], 0, v6, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v10 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v10
; GFX9-NEXT: v_mov_b32_e32 v13, 0 ; GFX9-NEXT: v_mov_b32_e32 v13, 0
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v9, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v15, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v10, v12, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v10, v12, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v9, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v9, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v7, v8, v10, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, v8, v10, s[0:1]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v13, v[0:3], s[4:5] ; GFX9-NEXT: global_store_dwordx4 v13, v[0:3], s[4:5]
; GFX9-NEXT: global_store_dwordx4 v13, v[4:7], s[6:7] ; GFX9-NEXT: global_store_dwordx4 v13, v[4:7], s[6:7]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udivrem_v2i64: ; GFX10-LABEL: udivrem_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20 ; GFX10-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x20
; GFX10-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x0
; GFX10-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x10
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s9
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s11 ; GFX10-NEXT: v_cvt_f32_u32_e32 v2, s11
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s8
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s10 ; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s10
; GFX10-NEXT: s_sub_u32 s2, 0, s8 ; GFX10-NEXT: s_sub_u32 s6, 0, s8
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0
; GFX10-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2 ; GFX10-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2
; GFX10-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_and_b32 s0, s0, 1
; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
; GFX10-NEXT: v_add_f32_e32 v1, v2, v3 ; GFX10-NEXT: v_add_f32_e32 v1, v2, v3
; GFX10-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-NEXT: s_subb_u32 s1, 0, s9 ; GFX10-NEXT: s_subb_u32 s7, 0, s9
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
; GFX10-NEXT: s_sub_u32 s3, 0, s10 ; GFX10-NEXT: s_sub_u32 s12, 0, s10
; GFX10-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_and_b32 s0, s0, 1
; GFX10-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-NEXT: s_cmp_lg_u32 s0, 0
; GFX10-NEXT: s_subb_u32 s6, 0, s11 ; GFX10-NEXT: s_subb_u32 s13, 0, s11
; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX10-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
; GFX10-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
; GFX10-NEXT: v_mul_f32_e32 v3, 0x2f800000, v1 ; GFX10-NEXT: v_mul_f32_e32 v3, 0x2f800000, v1
; GFX10-NEXT: v_trunc_f32_e32 v2, v2 ; GFX10-NEXT: v_trunc_f32_e32 v2, v2
; GFX10-NEXT: v_trunc_f32_e32 v3, v3 ; GFX10-NEXT: v_trunc_f32_e32 v3, v3
; GFX10-NEXT: v_mul_f32_e32 v4, 0xcf800000, v2 ; GFX10-NEXT: v_mul_f32_e32 v4, 0xcf800000, v2
; GFX10-NEXT: v_mul_f32_e32 v5, 0xcf800000, v3 ; GFX10-NEXT: v_mul_f32_e32 v5, 0xcf800000, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX10-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX10-NEXT: v_add_f32_e32 v0, v4, v0 ; GFX10-NEXT: v_add_f32_e32 v0, v4, v0
; GFX10-NEXT: v_add_f32_e32 v1, v5, v1 ; GFX10-NEXT: v_add_f32_e32 v1, v5, v1
; GFX10-NEXT: v_mul_lo_u32 v4, s2, v2 ; GFX10-NEXT: v_mul_lo_u32 v4, s6, v2
; GFX10-NEXT: v_mul_lo_u32 v8, s3, v3 ; GFX10-NEXT: v_mul_lo_u32 v8, s12, v3
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: v_mul_lo_u32 v5, s1, v0 ; GFX10-NEXT: v_mul_lo_u32 v5, s7, v0
; GFX10-NEXT: v_mul_hi_u32 v6, s2, v0 ; GFX10-NEXT: v_mul_hi_u32 v6, s6, v0
; GFX10-NEXT: v_mul_lo_u32 v9, s6, v1 ; GFX10-NEXT: v_mul_lo_u32 v9, s13, v1
; GFX10-NEXT: v_mul_hi_u32 v10, s3, v1 ; GFX10-NEXT: v_mul_hi_u32 v10, s12, v1
; GFX10-NEXT: v_mul_lo_u32 v7, s2, v0 ; GFX10-NEXT: v_mul_lo_u32 v7, s6, v0
; GFX10-NEXT: v_mul_lo_u32 v11, s3, v1 ; GFX10-NEXT: v_mul_lo_u32 v11, s12, v1
; GFX10-NEXT: v_add3_u32 v4, v5, v4, v6 ; GFX10-NEXT: v_add3_u32 v4, v5, v4, v6
; GFX10-NEXT: v_add3_u32 v8, v9, v8, v10 ; GFX10-NEXT: v_add3_u32 v8, v9, v8, v10
; GFX10-NEXT: v_mul_lo_u32 v5, v2, v7 ; GFX10-NEXT: v_mul_lo_u32 v5, v2, v7
; GFX10-NEXT: v_mul_hi_u32 v6, v0, v7 ; GFX10-NEXT: v_mul_hi_u32 v6, v0, v7
; GFX10-NEXT: v_mul_lo_u32 v12, v0, v4 ; GFX10-NEXT: v_mul_lo_u32 v12, v0, v4
; GFX10-NEXT: v_mul_hi_u32 v7, v2, v7 ; GFX10-NEXT: v_mul_hi_u32 v7, v2, v7
; GFX10-NEXT: v_mul_lo_u32 v13, v2, v4 ; GFX10-NEXT: v_mul_lo_u32 v13, v2, v4
; GFX10-NEXT: v_mul_lo_u32 v9, v3, v11 ; GFX10-NEXT: v_mul_lo_u32 v9, v3, v11
Show All 26 Lines
; GFX10-NEXT: v_add_nc_u32_e32 v7, v13, v7 ; GFX10-NEXT: v_add_nc_u32_e32 v7, v13, v7
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_mul_hi_u32 v8, v3, v8 ; GFX10-NEXT: v_mul_hi_u32 v8, v3, v8
; GFX10-NEXT: v_add_co_u32 v9, s0, v10, v9 ; GFX10-NEXT: v_add_co_u32 v9, s0, v10, v9
; GFX10-NEXT: v_add_nc_u32_e32 v11, v16, v11 ; GFX10-NEXT: v_add_nc_u32_e32 v11, v16, v11
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
; GFX10-NEXT: v_add3_u32 v4, v7, v6, v4 ; GFX10-NEXT: v_add3_u32 v4, v7, v6, v4
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v5 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v5
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x10
; GFX10-NEXT: v_add3_u32 v5, v11, v10, v8 ; GFX10-NEXT: v_add3_u32 v5, v11, v10, v8
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s0, v2, v4, vcc_lo
; GFX10-NEXT: v_add_co_u32 v1, s0, v1, v9
; GFX10-NEXT: v_mul_lo_u32 v8, s1, v0
; GFX10-NEXT: v_add_co_ci_u32_e64 v10, s1, v3, v5, s0
; GFX10-NEXT: v_mul_hi_u32 v9, s2, v0
; GFX10-NEXT: v_mul_lo_u32 v11, s2, v6
; GFX10-NEXT: v_mul_lo_u32 v13, s6, v1
; GFX10-NEXT: v_mul_hi_u32 v14, s3, v1
; GFX10-NEXT: v_mul_lo_u32 v15, s3, v10
; GFX10-NEXT: v_mul_lo_u32 v7, s2, v0
; GFX10-NEXT: v_mul_lo_u32 v12, s3, v1
; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v4
; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v5
; GFX10-NEXT: v_add3_u32 v8, v8, v11, v9
; GFX10-NEXT: v_add3_u32 v13, v13, v15, v14
; GFX10-NEXT: v_mul_lo_u32 v16, v6, v7
; GFX10-NEXT: v_mul_lo_u32 v14, v0, v8
; GFX10-NEXT: v_mul_hi_u32 v17, v0, v7
; GFX10-NEXT: v_mul_hi_u32 v7, v6, v7
; GFX10-NEXT: v_mul_lo_u32 v15, v6, v8
; GFX10-NEXT: v_mul_lo_u32 v9, v10, v12
; GFX10-NEXT: v_mul_hi_u32 v18, v0, v8
; GFX10-NEXT: v_mul_hi_u32 v6, v6, v8
; GFX10-NEXT: v_mul_lo_u32 v8, v1, v13
; GFX10-NEXT: v_add_co_u32 v14, s1, v16, v14
; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v7, s1, v15, v7
; GFX10-NEXT: v_mul_hi_u32 v11, v1, v12
; GFX10-NEXT: v_mul_hi_u32 v12, v10, v12
; GFX10-NEXT: v_mul_lo_u32 v19, v10, v13
; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v8, s1, v9, v8
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v14, s1, v14, v17
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v12, s1, v19, v12
; GFX10-NEXT: v_cndmask_b32_e64 v17, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v7, s1, v7, v18
; GFX10-NEXT: v_add_nc_u32_e32 v14, v16, v14
; GFX10-NEXT: v_cndmask_b32_e64 v18, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v8, s1, v8, v11
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1
; GFX10-NEXT: v_add_co_u32 v7, s1, v7, v14
; GFX10-NEXT: v_mul_hi_u32 v20, v1, v13
; GFX10-NEXT: v_add_nc_u32_e32 v11, v15, v18
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, 1, s1
; GFX10-NEXT: v_add_nc_u32_e32 v8, v9, v8
; GFX10-NEXT: v_add3_u32 v4, v11, v14, v6
; GFX10-NEXT: v_add_co_u32 v12, s1, v12, v20
; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s1
; GFX10-NEXT: v_mul_hi_u32 v6, v10, v13
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, s1, v12, v8 ; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v9
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v7 ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
; GFX10-NEXT: v_add_nc_u32_e32 v9, v17, v15 ; GFX10-NEXT: v_mul_lo_u32 v6, s7, v0
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1 ; GFX10-NEXT: v_mul_hi_u32 v7, s6, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo ; GFX10-NEXT: v_mul_lo_u32 v5, s6, v2
; GFX10-NEXT: v_mul_lo_u32 v9, s13, v1
; GFX10-NEXT: v_mul_hi_u32 v10, s12, v1
; GFX10-NEXT: v_mul_lo_u32 v11, s12, v3
; GFX10-NEXT: v_mul_lo_u32 v4, s6, v0
; GFX10-NEXT: v_mul_lo_u32 v8, s12, v1
; GFX10-NEXT: v_add3_u32 v5, v6, v5, v7
; GFX10-NEXT: v_add3_u32 v9, v9, v11, v10
; GFX10-NEXT: v_mul_lo_u32 v12, v2, v4
; GFX10-NEXT: v_mul_lo_u32 v10, v0, v5
; GFX10-NEXT: v_mul_hi_u32 v13, v0, v4
; GFX10-NEXT: v_mul_hi_u32 v4, v2, v4
; GFX10-NEXT: v_mul_lo_u32 v11, v2, v5
; GFX10-NEXT: v_mul_lo_u32 v6, v3, v8
; GFX10-NEXT: v_mul_lo_u32 v15, v1, v9
; GFX10-NEXT: v_mul_hi_u32 v7, v1, v8
; GFX10-NEXT: v_mul_hi_u32 v8, v3, v8
; GFX10-NEXT: v_add_co_u32 v10, s6, v12, v10
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v4, s6, v11, v4
; GFX10-NEXT: v_mul_lo_u32 v16, v3, v9
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v6, s6, v6, v15
; GFX10-NEXT: v_mul_hi_u32 v14, v0, v5
; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v10, s6, v10, v13
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v8, s6, v16, v8
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v4, s6, v4, v14
; GFX10-NEXT: v_add_nc_u32_e32 v10, v12, v10
; GFX10-NEXT: v_cndmask_b32_e64 v14, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v6, s6, v6, v7
; GFX10-NEXT: v_mul_hi_u32 v5, v2, v5
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s6
; GFX10-NEXT: v_add_co_u32 v4, s6, v4, v10
; GFX10-NEXT: v_add_nc_u32_e32 v7, v11, v14
; GFX10-NEXT: v_cndmask_b32_e64 v10, 0, 1, s6
; GFX10-NEXT: v_mul_hi_u32 v17, v1, v9
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v4
; GFX10-NEXT: v_add_nc_u32_e32 v6, v15, v6
; GFX10-NEXT: v_add3_u32 v5, v7, v10, v5
; GFX10-NEXT: v_mul_hi_u32 v9, v3, v9
; GFX10-NEXT: v_mov_b32_e32 v10, 0 ; GFX10-NEXT: v_mov_b32_e32 v10, 0
; GFX10-NEXT: v_add3_u32 v5, v9, v8, v6 ; GFX10-NEXT: v_add_co_u32 v8, s6, v8, v17
; GFX10-NEXT: v_mul_lo_u32 v6, s17, v0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v2, v5, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v7, s16, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, 1, s6
; GFX10-NEXT: v_mul_hi_u32 v8, s17, v0 ; GFX10-NEXT: v_add_co_u32 v4, s12, v8, v6
; GFX10-NEXT: v_mul_hi_u32 v0, s16, v0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_mul_lo_u32 v9, s17, v2 ; GFX10-NEXT: v_mul_lo_u32 v6, s1, v0
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, vcc_lo, v3, v5, s0 ; GFX10-NEXT: v_mul_lo_u32 v8, s0, v2
; GFX10-NEXT: v_mul_hi_u32 v5, s16, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v7, v13, v11
; GFX10-NEXT: v_mul_hi_u32 v2, s17, v2 ; GFX10-NEXT: v_mul_hi_u32 v11, s1, v0
; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v7 ; GFX10-NEXT: v_mul_hi_u32 v0, s0, v0
; GFX10-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s12
; GFX10-NEXT: v_add_co_u32 v8, s0, v9, v8 ; GFX10-NEXT: v_mul_lo_u32 v12, s1, v2
; GFX10-NEXT: v_add_co_u32 v0, s1, v6, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v5, s0, v8, v5
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v0, v7, v0
; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v4 ; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo ; GFX10-NEXT: v_add_co_u32 v6, s12, v6, v8
; GFX10-NEXT: v_add_co_u32 v0, s0, v5, v0 ; GFX10-NEXT: v_add3_u32 v5, v7, v5, v9
; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v8 ; GFX10-NEXT: v_mul_hi_u32 v7, s0, v2
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s12
; GFX10-NEXT: v_mul_lo_u32 v6, s19, v1 ; GFX10-NEXT: v_add_co_u32 v0, s13, v6, v0
; GFX10-NEXT: v_mul_hi_u32 v7, s18, v1 ; GFX10-NEXT: v_add_co_u32 v9, s12, v12, v11
; GFX10-NEXT: v_mul_hi_u32 v1, s19, v1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s13
; GFX10-NEXT: v_mul_lo_u32 v8, s9, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s12
; GFX10-NEXT: v_mul_hi_u32 v2, s1, v2
; GFX10-NEXT: v_add_co_u32 v7, s12, v9, v7
; GFX10-NEXT: v_add_nc_u32_e32 v0, v8, v0
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s12
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX10-NEXT: v_add_co_u32 v0, s12, v7, v0
; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v9
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s12
; GFX10-NEXT: v_mul_lo_u32 v6, s3, v1
; GFX10-NEXT: v_mul_lo_u32 v8, s2, v3
; GFX10-NEXT: v_mul_lo_u32 v9, s9, v0
; GFX10-NEXT: v_mul_hi_u32 v11, s8, v0
; GFX10-NEXT: v_add3_u32 v2, v4, v5, v2 ; GFX10-NEXT: v_add3_u32 v2, v4, v5, v2
; GFX10-NEXT: v_mul_lo_u32 v4, s18, v3 ; GFX10-NEXT: v_mul_hi_u32 v7, s2, v1
; GFX10-NEXT: v_mul_lo_u32 v5, s19, v3
; GFX10-NEXT: v_mul_hi_u32 v9, s8, v0
; GFX10-NEXT: v_mul_lo_u32 v13, s8, v0 ; GFX10-NEXT: v_mul_lo_u32 v13, s8, v0
; GFX10-NEXT: v_mul_lo_u32 v11, s8, v2 ; GFX10-NEXT: v_mul_hi_u32 v1, s3, v1
; GFX10-NEXT: v_mul_hi_u32 v12, s18, v3 ; GFX10-NEXT: v_mul_lo_u32 v4, s3, v3
; GFX10-NEXT: v_mul_hi_u32 v3, s19, v3 ; GFX10-NEXT: v_mul_lo_u32 v12, s8, v2
; GFX10-NEXT: v_add_co_u32 v4, s0, v6, v4 ; GFX10-NEXT: v_add_co_u32 v6, s12, v6, v8
; GFX10-NEXT: v_add_co_u32 v1, s1, v5, v1 ; GFX10-NEXT: v_mul_hi_u32 v5, s2, v3
; GFX10-NEXT: v_add3_u32 v5, v8, v11, v9 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s12
; GFX10-NEXT: v_mul_hi_u32 v3, s3, v3
; GFX10-NEXT: v_add_co_u32 v1, s12, v4, v1
; GFX10-NEXT: v_add3_u32 v9, v9, v12, v11
; GFX10-NEXT: v_sub_co_u32 v11, vcc_lo, s0, v13
; GFX10-NEXT: v_add_co_u32 v6, s0, v6, v7
; GFX10-NEXT: v_sub_nc_u32_e32 v7, s1, v9
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s0
; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, s16, v13 ; GFX10-NEXT: v_sub_co_ci_u32_e64 v9, s0, s1, v9, vcc_lo
; GFX10-NEXT: v_add_co_u32 v4, s0, v4, v7 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v11
; GFX10-NEXT: v_sub_nc_u32_e32 v7, s17, v5
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
; GFX10-NEXT: v_sub_co_ci_u32_e64 v5, s0, s17, v5, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v8
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s9, v5 ; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s9, v9
; GFX10-NEXT: v_cndmask_b32_e64 v16, 0, 1, s1 ; GFX10-NEXT: v_add_nc_u32_e32 v6, v8, v6
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, -1, s0
; GFX10-NEXT: v_add_nc_u32_e32 v4, v6, v4 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s12
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v13, vcc_lo, v8, s8 ; GFX10-NEXT: v_sub_co_u32 v14, vcc_lo, v11, s8
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v14, s0, 0, v7, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v15, s0, 0, v7, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v5 ; GFX10-NEXT: v_add_co_u32 v1, s0, v1, v5
; GFX10-NEXT: v_cndmask_b32_e64 v9, v11, v9, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v13 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v9
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s0 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v14 ; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v5
; GFX10-NEXT: v_cndmask_b32_e64 v15, 0, -1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v12, v13, v12, s0
; GFX10-NEXT: v_add_co_u32 v1, s0, v1, v12 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s9, v15
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, -1, s0
; GFX10-NEXT: v_add_co_u32 v17, s0, v0, 1 ; GFX10-NEXT: v_cmp_le_u32_e64 s0, s8, v14
; GFX10-NEXT: v_add_co_ci_u32_e64 v18, s0, 0, v2, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v14 ; GFX10-NEXT: v_add_co_u32 v6, s0, v1, v6
; GFX10-NEXT: v_cndmask_b32_e64 v6, v15, v11, s0
; GFX10-NEXT: v_add_nc_u32_e32 v11, v16, v12
; GFX10-NEXT: v_add_co_u32 v12, s0, v1, v4
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: v_add_co_u32 v4, s0, v17, 1 ; GFX10-NEXT: v_add_co_u32 v5, s0, v0, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v15, s0, 0, v18, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v16, s0, 0, v2, s0
; GFX10-NEXT: v_add3_u32 v3, v11, v1, v3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s9, v15
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, s9, v7, vcc_lo ; GFX10-NEXT: v_add3_u32 v3, v4, v1, v3
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 ; GFX10-NEXT: v_mul_hi_u32 v18, s10, v6
; GFX10-NEXT: v_mul_lo_u32 v6, s11, v12 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v13, v8, s0
; GFX10-NEXT: v_mul_lo_u32 v7, s10, v3 ; GFX10-NEXT: v_mul_lo_u32 v13, s11, v6
; GFX10-NEXT: v_mul_hi_u32 v11, s10, v12 ; GFX10-NEXT: v_mul_lo_u32 v17, s10, v3
; GFX10-NEXT: v_sub_co_u32 v19, s0, v13, s8 ; GFX10-NEXT: v_add_co_u32 v1, s0, v5, 1
; GFX10-NEXT: v_mul_lo_u32 v16, s10, v12
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v20, s0, 0, v1, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v18, v15, vcc_lo
; GFX10-NEXT: v_add3_u32 v6, v6, v7, v11
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v9
; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v20, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v7, s1, s18, v16
; GFX10-NEXT: v_sub_co_ci_u32_e64 v9, s2, s19, v6, s1
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, v4, s0
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s19, v6
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s11, v9
; GFX10-NEXT: v_cndmask_b32_e32 v4, v13, v19, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s11, v9
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v14, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s1, s11, v2, s1
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s10, v7
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, -1, s2
; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v4, s0
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s1
; GFX10-NEXT: v_sub_co_u32 v13, s1, v7, s10
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v15, s2, 0, v2, s1
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s11, v15
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc_lo
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, s10, v13
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v16, vcc_lo, v12, 1
; GFX10-NEXT: v_add_co_ci_u32_e32 v17, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, s11, v15
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX10-NEXT: v_add_co_u32 v11, vcc_lo, v16, 1
; GFX10-NEXT: v_add_co_ci_u32_e32 v18, vcc_lo, 0, v17, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, vcc_lo, s11, v2, s1
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, 0, v16, s0
; GFX10-NEXT: v_sub_co_u32 v19, s0, v14, s8
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: v_mul_lo_u32 v5, s10, v6
; GFX10-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc_lo
; GFX10-NEXT: v_add3_u32 v13, v13, v17, v18
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v7, s0, 0, v7, s0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX10-NEXT: v_sub_nc_u32_e32 v2, s3, v13
; GFX10-NEXT: v_sub_co_u32 v12, s0, s2, v5
; GFX10-NEXT: v_sub_co_ci_u32_e64 v16, s1, s3, v13, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s0, s11, v2, s0
; GFX10-NEXT: v_cmp_le_u32_e64 s0, s10, v12
; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v8
; GFX10-NEXT: v_cmp_le_u32_e64 s2, s11, v16
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s0
; GFX10-NEXT: v_sub_co_u32 v13, s0, v12, s10
; GFX10-NEXT: v_cndmask_b32_e64 v4, v14, v19, s1
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, -1, s2
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v14, s2, 0, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v15, v7, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s11, v16
; GFX10-NEXT: v_cndmask_b32_e32 v4, v11, v4, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s0, s11, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v8, s1
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s11, v14
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, -1, s1
; GFX10-NEXT: v_cmp_le_u32_e64 s1, s10, v13
; GFX10-NEXT: v_cndmask_b32_e64 v11, 0, -1, s1
; GFX10-NEXT: v_add_co_u32 v15, s1, v6, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v17, s1, 0, v3, s1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s11, v14
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v11, s1
; GFX10-NEXT: v_add_co_u32 v11, s1, v15, 1
; GFX10-NEXT: v_add_co_ci_u32_e64 v18, s1, 0, v17, s1
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v8
; GFX10-NEXT: v_sub_co_u32 v8, s1, v13, s10 ; GFX10-NEXT: v_sub_co_u32 v8, s1, v13, s10
; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s1, 0, v2, s1 ; GFX10-NEXT: v_subrev_co_ci_u32_e64 v2, s1, 0, v2, s1
; GFX10-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v11, v15, v11, s0
; GFX10-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v15, v17, v18, s0
; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v6 ; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v13, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v8, v13, v8, s0
; GFX10-NEXT: v_cndmask_b32_e32 v8, v15, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v13, v14, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v12, v11, s1 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v16, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v11, s1
; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, v6, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v15, s1
; GFX10-NEXT: v_cndmask_b32_e64 v7, v9, v8, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v12, v8, s1
; GFX10-NEXT: global_store_dwordx4 v10, v[0:3], s[12:13] ; GFX10-NEXT: v_cndmask_b32_e64 v7, v16, v13, s1
; GFX10-NEXT: global_store_dwordx4 v10, v[4:7], s[14:15] ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v10, v[0:3], s[4:5]
; GFX10-NEXT: global_store_dwordx4 v10, v[4:7], s[6:7]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%div = udiv <2 x i64> %x, %y %div = udiv <2 x i64> %x, %y
store <2 x i64> %div, <2 x i64> addrspace(1)* %out0 store <2 x i64> %div, <2 x i64> addrspace(1)* %out0
%rem = urem <2 x i64> %x, %y %rem = urem <2 x i64> %x, %y
store <2 x i64> %rem, <2 x i64> addrspace(1)* %out1 store <2 x i64> %rem, <2 x i64> addrspace(1)* %out1
ret void ret void
} }
▲ Show 20 Lines • Show All 866 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v12 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v12
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9
; CHECK-NEXT: v_addc_u32_e64 v9, s[4:5], v1, v8, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v8, vcc
; CHECK-NEXT: v_add_i32_e64 v1, s[4:5], v1, v8
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v0 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v0
; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0 ; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0
; CHECK-NEXT: v_mul_hi_u32 v10, v6, v0 ; CHECK-NEXT: v_mul_hi_u32 v9, v6, v0
; CHECK-NEXT: v_mul_lo_u32 v6, v6, v9 ; CHECK-NEXT: v_mul_lo_u32 v6, v6, v1
; CHECK-NEXT: v_mul_lo_u32 v11, v9, v8 ; CHECK-NEXT: v_mul_lo_u32 v10, v1, v8
; CHECK-NEXT: v_mul_hi_u32 v12, v0, v8 ; CHECK-NEXT: v_mul_hi_u32 v11, v0, v8
; CHECK-NEXT: v_mul_hi_u32 v8, v9, v8 ; CHECK-NEXT: v_mul_hi_u32 v8, v1, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v10 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_mul_lo_u32 v7, v0, v6 ; CHECK-NEXT: v_mul_lo_u32 v7, v0, v6
; CHECK-NEXT: v_mul_lo_u32 v10, v9, v6 ; CHECK-NEXT: v_mul_lo_u32 v9, v1, v6
; CHECK-NEXT: v_mul_hi_u32 v13, v0, v6 ; CHECK-NEXT: v_mul_hi_u32 v12, v0, v6
; CHECK-NEXT: v_mul_hi_u32 v6, v9, v6 ; CHECK-NEXT: v_mul_hi_u32 v6, v1, v6
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v11, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v10, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v12 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v13 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v9, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v10, v11 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v6, vcc
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v6, vcc
; CHECK-NEXT: v_mul_lo_u32 v6, v5, v0 ; CHECK-NEXT: v_mul_lo_u32 v6, v5, v0
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v0 ; CHECK-NEXT: v_mul_hi_u32 v7, v4, v0
; CHECK-NEXT: v_mul_hi_u32 v0, v5, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, v5, v0
; CHECK-NEXT: v_mul_lo_u32 v8, v4, v1 ; CHECK-NEXT: v_mul_lo_u32 v8, v4, v1
; CHECK-NEXT: v_mul_lo_u32 v9, v5, v1 ; CHECK-NEXT: v_mul_lo_u32 v9, v5, v1
; CHECK-NEXT: v_mul_hi_u32 v10, v4, v1 ; CHECK-NEXT: v_mul_hi_u32 v10, v4, v1
; CHECK-NEXT: v_mul_hi_u32 v1, v5, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v5, v1
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; CHECK-NEXT: s_mov_b32 s5, -1 ; CHECK-NEXT: s_mov_b32 s5, -1
; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[4:5] ; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[4:5]
; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0 ; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0
; CHECK-NEXT: s_cbranch_vccz BB1_2 ; CHECK-NEXT: s_cbranch_vccz BB1_2
; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2 ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2
; CHECK-NEXT: v_mov_b32_e32 v1, s3 ; CHECK-NEXT: v_mov_b32_e32 v1, s3
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s3 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s3
; CHECK-NEXT: s_sub_u32 s6, 0, s2 ; CHECK-NEXT: s_sub_u32 s4, 0, s2
; CHECK-NEXT: s_cselect_b32 s4, 1, 0 ; CHECK-NEXT: s_cselect_b32 s5, 1, 0
; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: v_mov_b32_e32 v3, s1
; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v2 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v2
; CHECK-NEXT: s_and_b32 s4, s4, 1 ; CHECK-NEXT: s_and_b32 s5, s5, 1
; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0
; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; CHECK-NEXT: s_cmp_lg_u32 s4, 0 ; CHECK-NEXT: s_cmp_lg_u32 s5, 0
; CHECK-NEXT: s_subb_u32 s7, 0, s3 ; CHECK-NEXT: s_subb_u32 s5, 0, s3
; CHECK-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
; CHECK-NEXT: v_trunc_f32_e32 v2, v2 ; CHECK-NEXT: v_trunc_f32_e32 v2, v2
; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 ; CHECK-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0 ; CHECK-NEXT: v_cvt_u32_f32_e32 v0, v0
; CHECK-NEXT: v_mul_lo_u32 v4, s6, v2 ; CHECK-NEXT: v_mul_lo_u32 v4, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v5, s6, v0 ; CHECK-NEXT: v_mul_lo_u32 v5, s4, v0
; CHECK-NEXT: v_mul_lo_u32 v6, s7, v0 ; CHECK-NEXT: v_mul_lo_u32 v6, s5, v0
; CHECK-NEXT: v_mul_hi_u32 v7, s6, v0 ; CHECK-NEXT: v_mul_hi_u32 v7, s4, v0
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_mul_lo_u32 v6, v2, v5 ; CHECK-NEXT: v_mul_lo_u32 v6, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v8, v0, v5 ; CHECK-NEXT: v_mul_hi_u32 v8, v0, v5
; CHECK-NEXT: v_mul_hi_u32 v5, v2, v5 ; CHECK-NEXT: v_mul_hi_u32 v5, v2, v5
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v7, v0, v4 ; CHECK-NEXT: v_mul_lo_u32 v7, v0, v4
; CHECK-NEXT: v_mul_lo_u32 v9, v2, v4 ; CHECK-NEXT: v_mul_lo_u32 v9, v2, v4
; CHECK-NEXT: v_mul_hi_u32 v10, v0, v4 ; CHECK-NEXT: v_mul_hi_u32 v10, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v2, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v2, v4
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v9, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v9, v5
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v10 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v10
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v5 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v5
; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v2, v4, vcc ; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; CHECK-NEXT: v_add_i32_e64 v2, s[4:5], v2, v4 ; CHECK-NEXT: v_mul_lo_u32 v4, s4, v0
; CHECK-NEXT: v_mul_lo_u32 v4, s6, v0 ; CHECK-NEXT: v_mul_lo_u32 v5, s5, v0
; CHECK-NEXT: v_mul_lo_u32 v6, s7, v0 ; CHECK-NEXT: v_mul_hi_u32 v6, s4, v0
; CHECK-NEXT: v_mul_hi_u32 v7, s6, v0 ; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s6, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v4
; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4 ; CHECK-NEXT: v_mul_hi_u32 v9, v0, v4
; CHECK-NEXT: v_mul_hi_u32 v10, v0, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v2, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7 ; CHECK-NEXT: v_mul_lo_u32 v6, v0, v5
; CHECK-NEXT: v_mul_lo_u32 v7, v0, v6 ; CHECK-NEXT: v_mul_lo_u32 v7, v2, v5
; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6 ; CHECK-NEXT: v_mul_hi_u32 v10, v0, v5
; CHECK-NEXT: v_mul_hi_u32 v11, v0, v6 ; CHECK-NEXT: v_mul_hi_u32 v5, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v5, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v9, v7 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v8, v4 ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v10 ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v11 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v8, v9 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v6 ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v7, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v5, v6
; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; CHECK-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; CHECK-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v4, s1, v0 ; CHECK-NEXT: v_mul_lo_u32 v4, s1, v0
; CHECK-NEXT: v_mul_hi_u32 v5, s0, v0 ; CHECK-NEXT: v_mul_hi_u32 v5, s0, v0
; CHECK-NEXT: v_mul_hi_u32 v0, s1, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, s1, v0
; CHECK-NEXT: v_mul_lo_u32 v6, s0, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, s0, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s1, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, s1, v2
; CHECK-NEXT: v_mul_hi_u32 v8, s0, v2 ; CHECK-NEXT: v_mul_hi_u32 v8, s0, v2
; CHECK-NEXT: v_mul_hi_u32 v2, s1, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, s1, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16 ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13 ; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; GISEL-NEXT: v_addc_u32_e64 v12, s[4:5], v9, v13, vcc ; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v13, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 ; GISEL-NEXT: v_mul_lo_u32 v12, v10, v8
; GISEL-NEXT: v_mul_lo_u32 v13, v10, v8
; GISEL-NEXT: v_mul_lo_u32 v11, v11, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v11, v8
; GISEL-NEXT: v_mul_lo_u32 v14, v10, v12 ; GISEL-NEXT: v_mul_lo_u32 v13, v10, v9
; GISEL-NEXT: v_mul_hi_u32 v10, v10, v8 ; GISEL-NEXT: v_mul_hi_u32 v10, v10, v8
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_lo_u32 v11, v12, v13 ; GISEL-NEXT: v_mul_lo_u32 v11, v9, v12
; GISEL-NEXT: v_mul_lo_u32 v14, v8, v10 ; GISEL-NEXT: v_mul_lo_u32 v13, v8, v10
; GISEL-NEXT: v_mul_hi_u32 v15, v8, v13 ; GISEL-NEXT: v_mul_hi_u32 v14, v8, v12
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v15 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v14, v11 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; GISEL-NEXT: v_mul_lo_u32 v14, v12, v10 ; GISEL-NEXT: v_mul_lo_u32 v13, v9, v10
; GISEL-NEXT: v_mul_hi_u32 v13, v12, v13 ; GISEL-NEXT: v_mul_hi_u32 v12, v9, v12
; GISEL-NEXT: v_mul_hi_u32 v15, v8, v10 ; GISEL-NEXT: v_mul_hi_u32 v14, v8, v10
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v15 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v15 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v13, v11 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_mul_hi_u32 v10, v12, v10 ; GISEL-NEXT: v_mul_hi_u32 v10, v9, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v10, vcc ; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v10, vcc
; GISEL-NEXT: v_addc_u32_e64 v9, vcc, 0, v9, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v10, v1, v8 ; GISEL-NEXT: v_mul_lo_u32 v10, v1, v8
; GISEL-NEXT: v_mul_lo_u32 v11, v0, v9 ; GISEL-NEXT: v_mul_lo_u32 v11, v0, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v0, v8 ; GISEL-NEXT: v_mul_hi_u32 v12, v0, v8
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_mul_hi_u32 v11, v5, v11 ; GISEL-NEXT: v_mul_hi_u32 v11, v5, v11
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; GISEL-NEXT: v_addc_u32_e64 v10, s[4:5], v5, v11, vcc ; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v11, vcc
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v11 ; GISEL-NEXT: v_mul_lo_u32 v10, v8, v4
; GISEL-NEXT: v_mul_lo_u32 v11, v8, v4
; GISEL-NEXT: v_mul_lo_u32 v9, v9, v4 ; GISEL-NEXT: v_mul_lo_u32 v9, v9, v4
; GISEL-NEXT: v_mul_lo_u32 v12, v8, v10 ; GISEL-NEXT: v_mul_lo_u32 v11, v8, v5
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v4 ; GISEL-NEXT: v_mul_hi_u32 v8, v8, v4
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_mul_lo_u32 v9, v10, v11 ; GISEL-NEXT: v_mul_lo_u32 v9, v5, v10
; GISEL-NEXT: v_mul_lo_u32 v12, v4, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v4, v8
; GISEL-NEXT: v_mul_hi_u32 v13, v4, v11 ; GISEL-NEXT: v_mul_hi_u32 v12, v4, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_mul_lo_u32 v12, v10, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v5, v8
; GISEL-NEXT: v_mul_hi_u32 v11, v10, v11 ; GISEL-NEXT: v_mul_hi_u32 v10, v5, v10
; GISEL-NEXT: v_mul_hi_u32 v13, v4, v8 ; GISEL-NEXT: v_mul_hi_u32 v12, v4, v8
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v8, v10, v8 ; GISEL-NEXT: v_mul_hi_u32 v8, v5, v8
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v4, v9 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v8, vcc ; GISEL-NEXT: v_addc_u32_e32 v5, vcc, v5, v8, vcc
; GISEL-NEXT: v_addc_u32_e64 v5, vcc, 0, v5, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v8, v3, v4 ; GISEL-NEXT: v_mul_lo_u32 v8, v3, v4
; GISEL-NEXT: v_mul_lo_u32 v9, v2, v5 ; GISEL-NEXT: v_mul_lo_u32 v9, v2, v5
; GISEL-NEXT: v_mul_hi_u32 v10, v2, v4 ; GISEL-NEXT: v_mul_hi_u32 v10, v2, v4
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v16 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v16
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13
; CGP-NEXT: v_addc_u32_e64 v13, s[4:5], v1, v12, vcc ; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v12, vcc
; CGP-NEXT: v_add_i32_e64 v1, s[4:5], v1, v12
; CGP-NEXT: v_mul_lo_u32 v12, v2, v0 ; CGP-NEXT: v_mul_lo_u32 v12, v2, v0
; CGP-NEXT: v_mul_lo_u32 v3, v3, v0 ; CGP-NEXT: v_mul_lo_u32 v3, v3, v0
; CGP-NEXT: v_mul_hi_u32 v14, v2, v0 ; CGP-NEXT: v_mul_hi_u32 v13, v2, v0
; CGP-NEXT: v_mul_lo_u32 v2, v2, v13 ; CGP-NEXT: v_mul_lo_u32 v2, v2, v1
; CGP-NEXT: v_mul_lo_u32 v15, v13, v12 ; CGP-NEXT: v_mul_lo_u32 v14, v1, v12
; CGP-NEXT: v_mul_hi_u32 v16, v0, v12 ; CGP-NEXT: v_mul_hi_u32 v15, v0, v12
; CGP-NEXT: v_mul_hi_u32 v12, v13, v12 ; CGP-NEXT: v_mul_hi_u32 v12, v1, v12
; CGP-NEXT: v_add_i32_e64 v2, s[4:5], v3, v2 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; CGP-NEXT: v_add_i32_e64 v2, s[4:5], v2, v14 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v13
; CGP-NEXT: v_mul_lo_u32 v3, v0, v2 ; CGP-NEXT: v_mul_lo_u32 v3, v0, v2
; CGP-NEXT: v_mul_lo_u32 v14, v13, v2 ; CGP-NEXT: v_mul_lo_u32 v13, v1, v2
; CGP-NEXT: v_mul_hi_u32 v17, v0, v2 ; CGP-NEXT: v_mul_hi_u32 v16, v0, v2
; CGP-NEXT: v_mul_hi_u32 v2, v13, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v1, v2
; CGP-NEXT: v_add_i32_e64 v3, s[4:5], v15, v3 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v14, v3
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v3, s[4:5], v3, v16 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v15
; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v17 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v16
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v3, s[4:5], v13, v3 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v14, v3
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v14, v15 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; CGP-NEXT: v_add_i32_e64 v3, s[4:5], v12, v3 ; CGP-NEXT: v_add_i32_e32 v3, vcc, v12, v3
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v2, s[4:5], v2, v12 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CGP-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CGP-NEXT: v_mul_lo_u32 v2, v11, v0 ; CGP-NEXT: v_mul_lo_u32 v2, v11, v0
; CGP-NEXT: v_mul_hi_u32 v3, v10, v0 ; CGP-NEXT: v_mul_hi_u32 v3, v10, v0
; CGP-NEXT: v_mul_hi_u32 v0, v11, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v11, v0
; CGP-NEXT: v_mul_lo_u32 v12, v10, v1 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v1
; CGP-NEXT: v_mul_lo_u32 v13, v11, v1 ; CGP-NEXT: v_mul_lo_u32 v13, v11, v1
; CGP-NEXT: v_mul_hi_u32 v14, v10, v1 ; CGP-NEXT: v_mul_hi_u32 v14, v10, v1
; CGP-NEXT: v_mul_hi_u32 v1, v11, v1 ; CGP-NEXT: v_mul_hi_u32 v1, v11, v1
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v12
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; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v11 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v11
; CGP-NEXT: v_addc_u32_e64 v11, s[4:5], v3, v10, vcc ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v10, vcc
; CGP-NEXT: v_add_i32_e64 v3, s[4:5], v3, v10
; CGP-NEXT: v_mul_lo_u32 v10, v4, v2 ; CGP-NEXT: v_mul_lo_u32 v10, v4, v2
; CGP-NEXT: v_mul_lo_u32 v5, v5, v2 ; CGP-NEXT: v_mul_lo_u32 v5, v5, v2
; CGP-NEXT: v_mul_hi_u32 v12, v4, v2 ; CGP-NEXT: v_mul_hi_u32 v11, v4, v2
; CGP-NEXT: v_mul_lo_u32 v4, v4, v11 ; CGP-NEXT: v_mul_lo_u32 v4, v4, v3
; CGP-NEXT: v_mul_lo_u32 v13, v11, v10 ; CGP-NEXT: v_mul_lo_u32 v12, v3, v10
; CGP-NEXT: v_mul_hi_u32 v14, v2, v10 ; CGP-NEXT: v_mul_hi_u32 v13, v2, v10
; CGP-NEXT: v_mul_hi_u32 v10, v11, v10 ; CGP-NEXT: v_mul_hi_u32 v10, v3, v10
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v5, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v11
; CGP-NEXT: v_mul_lo_u32 v5, v2, v4 ; CGP-NEXT: v_mul_lo_u32 v5, v2, v4
; CGP-NEXT: v_mul_lo_u32 v12, v11, v4 ; CGP-NEXT: v_mul_lo_u32 v11, v3, v4
; CGP-NEXT: v_mul_hi_u32 v15, v2, v4 ; CGP-NEXT: v_mul_hi_u32 v14, v2, v4
; CGP-NEXT: v_mul_hi_u32 v4, v11, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v13, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v12, v5
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v12, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v5, v14 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v13
; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v15 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v14
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v11, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v12, v5
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v12, v13 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v10, v5
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v10 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CGP-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v4, v9, v2 ; CGP-NEXT: v_mul_lo_u32 v4, v9, v2
; CGP-NEXT: v_mul_hi_u32 v5, v8, v2 ; CGP-NEXT: v_mul_hi_u32 v5, v8, v2
; CGP-NEXT: v_mul_hi_u32 v2, v9, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v9, v2
; CGP-NEXT: v_mul_lo_u32 v10, v8, v3 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v3
; CGP-NEXT: v_mul_lo_u32 v11, v9, v3 ; CGP-NEXT: v_mul_lo_u32 v11, v9, v3
; CGP-NEXT: v_mul_hi_u32 v12, v8, v3 ; CGP-NEXT: v_mul_hi_u32 v12, v8, v3
; CGP-NEXT: v_mul_hi_u32 v3, v9, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v9, v3
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10
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} }
define i64 @v_urem_i64_oddk_denom(i64 %num) { define i64 @v_urem_i64_oddk_denom(i64 %num) {
; CHECK-LABEL: v_urem_i64_oddk_denom: ; CHECK-LABEL: v_urem_i64_oddk_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x12d8fb ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x12d8fb
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
; CHECK-NEXT: s_mov_b32 s6, 0xffed2705 ; CHECK-NEXT: s_mov_b32 s4, 0xffed2705
; CHECK-NEXT: s_mov_b32 s7, 0x12d8fb ; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb
; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000
; CHECK-NEXT: s_bfe_i32 s5, -1, 0x10000 ; CHECK-NEXT: s_bfe_i32 s5, -1, 0x10000
; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000
; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CHECK-NEXT: v_mov_b32_e32 v3, s4 ; CHECK-NEXT: v_mov_b32_e32 v3, s5
; CHECK-NEXT: v_mov_b32_e32 v4, s5 ; CHECK-NEXT: v_mov_b32_e32 v4, s7
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2 ; CHECK-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v5, v5 ; CHECK-NEXT: v_trunc_f32_e32 v5, v5
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5
; CHECK-NEXT: v_cvt_u32_f32_e32 v5, v5 ; CHECK-NEXT: v_cvt_u32_f32_e32 v5, v5
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v5 ; CHECK-NEXT: v_mul_lo_u32 v6, s4, v5
; CHECK-NEXT: v_mul_lo_u32 v7, s6, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v8, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v8, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v9, s6, v2 ; CHECK-NEXT: v_mul_hi_u32 v9, s4, v2
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_mul_lo_u32 v8, v5, v7 ; CHECK-NEXT: v_mul_lo_u32 v8, v5, v7
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v5, v7 ; CHECK-NEXT: v_mul_hi_u32 v7, v5, v7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; CHECK-NEXT: v_mul_lo_u32 v9, v2, v6 ; CHECK-NEXT: v_mul_lo_u32 v9, v2, v6
; CHECK-NEXT: v_mul_lo_u32 v11, v5, v6 ; CHECK-NEXT: v_mul_lo_u32 v11, v5, v6
; CHECK-NEXT: v_mul_hi_u32 v12, v2, v6 ; CHECK-NEXT: v_mul_hi_u32 v12, v2, v6
; CHECK-NEXT: v_mul_hi_u32 v6, v5, v6 ; CHECK-NEXT: v_mul_hi_u32 v6, v5, v6
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v11, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v12 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v12
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v11, v10 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v7
; CHECK-NEXT: v_addc_u32_e64 v7, s[4:5], v5, v6, vcc ; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v5, v6 ; CHECK-NEXT: v_mul_lo_u32 v6, s4, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s6, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v8, -1, v2 ; CHECK-NEXT: v_mul_hi_u32 v8, s4, v2
; CHECK-NEXT: v_mul_hi_u32 v9, s6, v2 ; CHECK-NEXT: v_mul_lo_u32 v9, s4, v5
; CHECK-NEXT: v_mul_lo_u32 v10, s6, v7 ; CHECK-NEXT: v_mul_lo_u32 v10, v5, v6
; CHECK-NEXT: v_mul_lo_u32 v11, v7, v6 ; CHECK-NEXT: v_mul_hi_u32 v11, v2, v6
; CHECK-NEXT: v_mul_hi_u32 v12, v2, v6 ; CHECK-NEXT: v_mul_hi_u32 v6, v5, v6
; CHECK-NEXT: v_mul_hi_u32 v6, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v7
; CHECK-NEXT: v_mul_lo_u32 v9, v2, v8 ; CHECK-NEXT: v_mul_lo_u32 v9, v5, v7
; CHECK-NEXT: v_mul_lo_u32 v10, v7, v8 ; CHECK-NEXT: v_mul_hi_u32 v12, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v13, v2, v8 ; CHECK-NEXT: v_mul_hi_u32 v7, v5, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v7, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v11, v9 ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v10, v6 ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v12 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v12
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v13 ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v10, v8
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v10, v11 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
; CHECK-NEXT: v_mul_lo_u32 v6, v1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, v1, v2
; CHECK-NEXT: v_mul_hi_u32 v7, v0, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_mul_lo_u32 v8, v0, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, v0, v5
; CHECK-NEXT: v_mul_lo_u32 v9, v1, v5 ; CHECK-NEXT: v_mul_lo_u32 v9, v1, v5
; CHECK-NEXT: v_mul_hi_u32 v10, v0, v5 ; CHECK-NEXT: v_mul_hi_u32 v10, v0, v5
; CHECK-NEXT: v_mul_hi_u32 v5, v1, v5 ; CHECK-NEXT: v_mul_hi_u32 v5, v1, v5
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v9, v2
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v10 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v10
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_mul_lo_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v8, 0, v2 ; CHECK-NEXT: v_mul_lo_u32 v8, 0, v2
; CHECK-NEXT: v_mul_hi_u32 v2, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, s6, v2
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_mul_lo_u32 v5, s7, v5 ; CHECK-NEXT: v_mul_lo_u32 v5, s6, v5
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v2, vcc ; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v2, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2 ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5 ; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
; CHECK-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s7, v0 ; CHECK-NEXT: v_subrev_i32_e32 v3, vcc, s6, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s7, v3 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v3
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; CHECK-NEXT: v_subrev_i32_e32 v6, vcc, s7, v3 ; CHECK-NEXT: v_subrev_i32_e32 v6, vcc, s6, v3
; CHECK-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = urem i64 %num, 1235195 %result = urem i64 %num, 1235195
ret i64 %result ret i64 %result
} }
define <2 x i64> @v_urem_v2i64_oddk_denom(<2 x i64> %num) { define <2 x i64> @v_urem_v2i64_oddk_denom(<2 x i64> %num) {
; GISEL-LABEL: v_urem_v2i64_oddk_denom: ; GISEL-LABEL: v_urem_v2i64_oddk_denom:
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: s_mov_b32 s12, 0x12d8fb ; GISEL-NEXT: s_mov_b32 s8, 0x12d8fb
; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s12 ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s8
; GISEL-NEXT: s_sub_u32 s8, 0, s12 ; GISEL-NEXT: s_sub_u32 s6, 0, s8
; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: s_cselect_b32 s4, 1, 0
; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v5, 0 ; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
; GISEL-NEXT: v_mov_b32_e32 v6, v4 ; GISEL-NEXT: v_mov_b32_e32 v6, v4
; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: s_and_b32 s4, s4, 1
; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; GISEL-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5 ; GISEL-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5
; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v6 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v6
; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GISEL-NEXT: s_subb_u32 s9, 0, 0 ; GISEL-NEXT: s_subb_u32 s7, 0, 0
; GISEL-NEXT: s_bfe_i32 s10, -1, 0x10000 ; GISEL-NEXT: s_bfe_i32 s4, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s11, -1, 0x10000 ; GISEL-NEXT: s_bfe_i32 s5, -1, 0x10000
; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x5f7ffffc, v4
; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v5
; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 ; GISEL-NEXT: v_mov_b32_e32 v5, s4
; GISEL-NEXT: s_sub_u32 s13, 0, s12 ; GISEL-NEXT: v_mov_b32_e32 v4, s5
; GISEL-NEXT: v_mul_f32_e32 v8, 0x2f800000, v6
; GISEL-NEXT: s_sub_u32 s9, 0, s8
; GISEL-NEXT: s_cselect_b32 s4, 1, 0 ; GISEL-NEXT: s_cselect_b32 s4, 1, 0
; GISEL-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5 ; GISEL-NEXT: v_mul_f32_e32 v9, 0x2f800000, v7
; GISEL-NEXT: v_trunc_f32_e32 v6, v6 ; GISEL-NEXT: v_trunc_f32_e32 v8, v8
; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: s_and_b32 s4, s4, 1
; GISEL-NEXT: v_trunc_f32_e32 v7, v7 ; GISEL-NEXT: v_trunc_f32_e32 v9, v9
; GISEL-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6 ; GISEL-NEXT: v_mac_f32_e32 v6, 0xcf800000, v8
; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v8
; GISEL-NEXT: v_mac_f32_e32 v7, 0xcf800000, v9
; GISEL-NEXT: v_cvt_u32_f32_e32 v9, v9
; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v7
; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
; GISEL-NEXT: s_cmp_lg_u32 s4, 0 ; GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GISEL-NEXT: s_subb_u32 s6, 0, 0 ; GISEL-NEXT: s_subb_u32 s10, 0, 0
; GISEL-NEXT: v_mul_lo_u32 v8, s13, v6 ; GISEL-NEXT: v_mul_lo_u32 v10, s9, v8
; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GISEL-NEXT: s_bfe_i32 s4, -1, 0x10000
; GISEL-NEXT: v_mul_lo_u32 v9, s8, v7 ; GISEL-NEXT: s_bfe_i32 s11, -1, 0x10000
; GISEL-NEXT: v_mul_lo_u32 v10, s13, v4 ; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
; GISEL-NEXT: v_mul_lo_u32 v11, s6, v4 ; GISEL-NEXT: v_mul_lo_u32 v11, s6, v9
; GISEL-NEXT: v_mul_hi_u32 v12, s13, v4 ; GISEL-NEXT: v_mul_lo_u32 v12, s9, v6
; GISEL-NEXT: v_mul_lo_u32 v13, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v13, s10, v6
; GISEL-NEXT: v_mul_lo_u32 v14, s9, v5 ; GISEL-NEXT: v_mul_hi_u32 v14, s9, v6
; GISEL-NEXT: v_mul_hi_u32 v15, s8, v5 ; GISEL-NEXT: v_mov_b32_e32 v15, s4
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v11, v8 ; GISEL-NEXT: v_mul_lo_u32 v16, s6, v7
; GISEL-NEXT: v_mul_lo_u32 v11, v6, v10 ; GISEL-NEXT: v_mul_lo_u32 v17, s7, v7
; GISEL-NEXT: v_mul_hi_u32 v16, v4, v10 ; GISEL-NEXT: v_mul_hi_u32 v18, s6, v7
; GISEL-NEXT: v_mul_hi_u32 v10, v6, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v13, v10
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v14, v9 ; GISEL-NEXT: v_mul_lo_u32 v13, v8, v12
; GISEL-NEXT: v_mul_lo_u32 v14, v7, v13 ; GISEL-NEXT: v_mul_hi_u32 v19, v6, v12
; GISEL-NEXT: v_mul_hi_u32 v17, v5, v13 ; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_mul_hi_u32 v13, v7, v13 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v17, v11
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; GISEL-NEXT: v_mul_lo_u32 v17, v9, v16
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v15 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v14
; GISEL-NEXT: v_mul_lo_u32 v12, v4, v8 ; GISEL-NEXT: v_mul_hi_u32 v14, v7, v16
; GISEL-NEXT: v_mul_lo_u32 v15, v6, v8 ; GISEL-NEXT: v_mul_hi_u32 v16, v9, v16
; GISEL-NEXT: v_mul_hi_u32 v18, v4, v8 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18
; GISEL-NEXT: v_mul_hi_u32 v8, v6, v8 ; GISEL-NEXT: v_mul_lo_u32 v18, v7, v11
; GISEL-NEXT: v_mul_lo_u32 v19, v5, v9 ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v18
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v19 ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v17, v14
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v17 ; GISEL-NEXT: v_mul_lo_u32 v14, v6, v10
; GISEL-NEXT: v_mul_lo_u32 v14, v7, v9 ; GISEL-NEXT: v_mul_lo_u32 v17, v8, v10
; GISEL-NEXT: v_mul_hi_u32 v17, v5, v9 ; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; GISEL-NEXT: v_mul_hi_u32 v9, v7, v9
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v15, v10
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v16 ; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v19
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_hi_u32 v13, v6, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v18 ; GISEL-NEXT: v_mul_hi_u32 v10, v8, v10
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v19
; GISEL-NEXT: v_mul_lo_u32 v19, v9, v11
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v17, v12
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v17, v13
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v18, v17
; GISEL-NEXT: v_mul_hi_u32 v18, v7, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v9, v11
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v19, v16
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v16, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v17 ; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v16, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v15, v16 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v18, v17
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v19, v18 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v12
; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; GISEL-NEXT: v_mul_lo_u32 v10, s9, v6
; GISEL-NEXT: v_mul_lo_u32 v12, s10, v6
; GISEL-NEXT: v_mul_hi_u32 v13, s9, v6
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v16
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v11, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, s6, v7
; GISEL-NEXT: v_mul_lo_u32 v14, s7, v7
; GISEL-NEXT: v_mul_hi_u32 v16, s6, v7
; GISEL-NEXT: v_mul_lo_u32 v17, s9, v8
; GISEL-NEXT: v_mul_lo_u32 v18, v8, v10
; GISEL-NEXT: v_mul_hi_u32 v19, v6, v10
; GISEL-NEXT: v_mul_hi_u32 v10, v8, v10
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v17
; GISEL-NEXT: v_mul_lo_u32 v17, s6, v9
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v17 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v17
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; GISEL-NEXT: v_mul_lo_u32 v17, v9, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15 ; GISEL-NEXT: v_mul_hi_u32 v13, v7, v11
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; GISEL-NEXT: v_mul_hi_u32 v11, v9, v11
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v14, v15 ; GISEL-NEXT: v_mul_lo_u32 v16, v7, v14
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11 ; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v16, v13
; GISEL-NEXT: v_addc_u32_e64 v10, s[4:5], v6, v8, vcc ; GISEL-NEXT: v_mul_lo_u32 v13, v6, v12
; GISEL-NEXT: v_mul_lo_u32 v11, s13, v4 ; GISEL-NEXT: v_mul_lo_u32 v16, v8, v12
; GISEL-NEXT: v_mul_lo_u32 v12, s6, v4 ; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v18, v13
; GISEL-NEXT: v_mul_hi_u32 v14, s13, v4 ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v13 ; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v19
; GISEL-NEXT: v_addc_u32_e64 v13, s[6:7], v7, v9, s[4:5] ; GISEL-NEXT: v_mul_hi_u32 v13, v6, v12
; GISEL-NEXT: v_mul_lo_u32 v15, s8, v5 ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v16, s9, v5 ; GISEL-NEXT: v_add_i32_e64 v18, s[4:5], v18, v19
; GISEL-NEXT: v_mul_hi_u32 v17, s8, v5 ; GISEL-NEXT: v_mul_lo_u32 v19, v9, v14
; GISEL-NEXT: v_mul_lo_u32 v18, s8, v13 ; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v16, v10
; GISEL-NEXT: v_mul_lo_u32 v19, v13, v15 ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v16, v18 ; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
; GISEL-NEXT: v_mul_hi_u32 v18, v5, v15 ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v16, v17 ; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v16, v13
; GISEL-NEXT: v_mul_lo_u32 v17, v5, v16 ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v17, s[6:7], v19, v17 ; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] ; GISEL-NEXT: v_mul_hi_u32 v17, v7, v14
; GISEL-NEXT: v_add_i32_e64 v17, s[6:7], v17, v18 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v19, v11
; GISEL-NEXT: v_mul_lo_u32 v17, s13, v10 ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v18, v10, v11 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v17
; GISEL-NEXT: v_add_i32_e64 v12, s[8:9], v12, v17 ; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_mul_hi_u32 v17, v4, v11 ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v19, v17
; GISEL-NEXT: v_add_i32_e64 v12, s[8:9], v12, v14 ; GISEL-NEXT: v_mov_b32_e32 v19, s11
; GISEL-NEXT: v_mul_lo_u32 v14, v4, v12 ; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v18, v14 ; GISEL-NEXT: v_mul_hi_u32 v14, v9, v14
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v18
; GISEL-NEXT: v_add_i32_e64 v14, s[8:9], v14, v17
; GISEL-NEXT: v_mov_b32_e32 v14, s10
; GISEL-NEXT: v_mov_b32_e32 v17, s11
; GISEL-NEXT: s_bfe_i32 s13, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s14, -1, 0x10000
; GISEL-NEXT: v_add_i32_e64 v6, s[10:11], v6, v8
; GISEL-NEXT: v_mov_b32_e32 v8, s13
; GISEL-NEXT: v_add_i32_e64 v7, s[10:11], v7, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v10, v11
; GISEL-NEXT: v_mul_hi_u32 v11, v13, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[8:9]
; GISEL-NEXT: v_add_i32_e64 v15, s[8:9], v18, v15
; GISEL-NEXT: v_mul_lo_u32 v18, v10, v12
; GISEL-NEXT: v_mul_hi_u32 v10, v10, v12
; GISEL-NEXT: v_mul_hi_u32 v12, v4, v12
; GISEL-NEXT: v_add_i32_e64 v9, s[8:9], v18, v9
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9]
; GISEL-NEXT: v_add_i32_e64 v9, s[8:9], v9, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[8:9]
; GISEL-NEXT: v_add_i32_e64 v12, s[8:9], v18, v12
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18
; GISEL-NEXT: v_mul_lo_u32 v19, v13, v16
; GISEL-NEXT: v_mul_hi_u32 v13, v13, v16
; GISEL-NEXT: v_mul_hi_u32 v16, v5, v16
; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v19, v11
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v16, s[6:7], v19, v16
; GISEL-NEXT: v_mov_b32_e32 v19, s14
; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v11, s[6:7], v11, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v12, v15
; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v16, v18
; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v10, v12
; GISEL-NEXT: v_add_i32_e64 v12, s[6:7], v13, v15
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc
; GISEL-NEXT: v_addc_u32_e64 v7, vcc, v7, v12, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
; GISEL-NEXT: v_mul_lo_u32 v9, v3, v4
; GISEL-NEXT: v_mul_hi_u32 v10, v2, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v3, v4
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v11
; GISEL-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, v1, v5
; GISEL-NEXT: v_mul_hi_u32 v12, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5
; GISEL-NEXT: v_mul_lo_u32 v13, v2, v6
; GISEL-NEXT: v_mul_lo_u32 v15, v3, v6
; GISEL-NEXT: v_mul_hi_u32 v16, v2, v6
; GISEL-NEXT: v_mul_hi_u32 v6, v3, v6
; GISEL-NEXT: v_mul_lo_u32 v18, v0, v7
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v16
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v18
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v16
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v12, vcc
; GISEL-NEXT: v_mul_lo_u32 v10, v3, v6
; GISEL-NEXT: v_mul_hi_u32 v12, v2, v6
; GISEL-NEXT: v_mul_hi_u32 v6, v3, v6
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v13, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, v1, v7 ; GISEL-NEXT: v_mul_lo_u32 v11, v1, v7
; GISEL-NEXT: v_mul_hi_u32 v12, v0, v7 ; GISEL-NEXT: v_mul_hi_u32 v13, v0, v7
; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 ; GISEL-NEXT: v_mul_lo_u32 v14, v2, v8
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_lo_u32 v16, v3, v8
; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v15, v4 ; GISEL-NEXT: v_mul_hi_u32 v17, v2, v8
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; GISEL-NEXT: v_mul_hi_u32 v8, v3, v8
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v11, v5 ; GISEL-NEXT: v_mul_lo_u32 v18, v0, v9
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_mul_lo_u32 v11, v1, v9
; GISEL-NEXT: v_mul_hi_u32 v13, v0, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v1, v9
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v16, v6
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v11, v7
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10 ; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v4, v16
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v17
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v13, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v13
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v15, v10 ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v18, v16 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v14, v10
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v16, v12
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v18, v17
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v13 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v14
; GISEL-NEXT: v_mul_lo_u32 v10, s12, v4 ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v13, 0, v4 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; GISEL-NEXT: v_mul_hi_u32 v4, s12, v4 ; GISEL-NEXT: v_mul_lo_u32 v12, s8, v6
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_mul_lo_u32 v14, 0, v6
; GISEL-NEXT: v_mul_lo_u32 v12, s12, v5 ; GISEL-NEXT: v_mul_hi_u32 v6, s8, v6
; GISEL-NEXT: v_mul_lo_u32 v15, 0, v5 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_mul_hi_u32 v5, s12, v5 ; GISEL-NEXT: v_mul_lo_u32 v13, s8, v7
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v9 ; GISEL-NEXT: v_mul_lo_u32 v16, 0, v7
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11 ; GISEL-NEXT: v_mul_hi_u32 v7, s8, v7
; GISEL-NEXT: v_mul_lo_u32 v6, s12, v6 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_mul_lo_u32 v7, s12, v7 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v13, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, s8, v8
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v15, v7 ; GISEL-NEXT: v_mul_lo_u32 v9, s8, v9
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v14, v8
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v16, v9
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v10 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GISEL-NEXT: v_subb_u32_e64 v6, s[4:5], v3, v4, vcc ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v9, v7
; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4 ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v12
; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s12, v2 ; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v6, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] ; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v6
; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v12 ; GISEL-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v2
; GISEL-NEXT: v_subb_u32_e64 v7, s[6:7], v1, v5, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
; GISEL-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v5 ; GISEL-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v13
; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], s12, v0 ; GISEL-NEXT: v_subb_u32_e64 v9, s[6:7], v1, v7, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[6:7] ; GISEL-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v7
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v6 ; GISEL-NEXT: v_cmp_le_u32_e64 s[6:7], s8, v0
; GISEL-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[6:7] ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v8
; GISEL-NEXT: v_cndmask_b32_e64 v6, v15, v6, s[6:7]
; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7 ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GISEL-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GISEL-NEXT: v_subbrev_u32_e64 v1, vcc, 0, v1, s[4:5] ; GISEL-NEXT: v_subbrev_u32_e64 v1, vcc, 0, v1, s[4:5]
; GISEL-NEXT: v_subrev_i32_e32 v8, vcc, s12, v2 ; GISEL-NEXT: v_subrev_i32_e32 v7, vcc, s8, v2
; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s12, v8 ; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s8, v7
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; GISEL-NEXT: v_subrev_i32_e32 v10, vcc, s12, v0 ; GISEL-NEXT: v_subrev_i32_e32 v11, vcc, s8, v0
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s12, v10 ; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s8, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GISEL-NEXT: v_cndmask_b32_e32 v9, v19, v9, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v10, v19, v10, vcc
; GISEL-NEXT: v_subrev_i32_e32 v12, vcc, s12, v8 ; GISEL-NEXT: v_subrev_i32_e32 v13, vcc, s8, v7
; GISEL-NEXT: v_subbrev_u32_e32 v13, vcc, 0, v3, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v3, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GISEL-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
; GISEL-NEXT: v_subrev_i32_e32 v14, vcc, s12, v10 ; GISEL-NEXT: v_subrev_i32_e32 v12, vcc, s8, v11
; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v1, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v1, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v13, vcc
; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v11 ; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v4
; GISEL-NEXT: v_cndmask_b32_e64 v9, v10, v14, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v4, v11, v12, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v14, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v15, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v15, s[4:5]
; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 ; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_urem_v2i64_oddk_denom: ; CGP-LABEL: v_urem_v2i64_oddk_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb ; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0 ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
; CGP-NEXT: s_mov_b32 s8, 0xffed2705 ; CGP-NEXT: s_mov_b32 s6, 0xffed2705
; CGP-NEXT: s_mov_b32 s12, 0x12d8fb ; CGP-NEXT: s_mov_b32 s8, 0x12d8fb
; CGP-NEXT: s_bfe_i32 s10, -1, 0x10000 ; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
; CGP-NEXT: s_bfe_i32 s11, -1, 0x10000 ; CGP-NEXT: s_bfe_i32 s5, -1, 0x10000
; CGP-NEXT: s_bfe_i32 s13, -1, 0x10000 ; CGP-NEXT: s_bfe_i32 s7, -1, 0x10000
; CGP-NEXT: s_bfe_i32 s14, -1, 0x10000 ; CGP-NEXT: s_bfe_i32 s9, -1, 0x10000
; CGP-NEXT: v_mov_b32_e32 v6, v4 ; CGP-NEXT: v_mov_b32_e32 v6, v4
; CGP-NEXT: v_mov_b32_e32 v7, s4
; CGP-NEXT: v_mov_b32_e32 v8, s5
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; CGP-NEXT: v_mov_b32_e32 v9, s7
; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5 ; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v6 ; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v6
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 ; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4
; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5 ; CGP-NEXT: v_mul_f32_e32 v10, 0x2f800000, v5
; CGP-NEXT: v_trunc_f32_e32 v6, v6 ; CGP-NEXT: v_trunc_f32_e32 v6, v6
; CGP-NEXT: v_trunc_f32_e32 v7, v7 ; CGP-NEXT: v_trunc_f32_e32 v10, v10
; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6 ; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6 ; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6
; CGP-NEXT: v_mac_f32_e32 v5, 0xcf800000, v7 ; CGP-NEXT: v_mac_f32_e32 v5, 0xcf800000, v10
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v10, v10
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
; CGP-NEXT: v_mul_lo_u32 v8, s8, v6 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v6
; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5 ; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5
; CGP-NEXT: v_mul_lo_u32 v9, s8, v7 ; CGP-NEXT: v_mul_lo_u32 v12, s6, v10
; CGP-NEXT: v_mul_lo_u32 v10, s8, v4 ; CGP-NEXT: v_mul_lo_u32 v13, s6, v4
; CGP-NEXT: v_mul_lo_u32 v11, -1, v4 ; CGP-NEXT: v_mul_lo_u32 v14, -1, v4
; CGP-NEXT: v_mul_hi_u32 v12, s8, v4 ; CGP-NEXT: v_mul_hi_u32 v15, s6, v4
; CGP-NEXT: v_mul_lo_u32 v13, s8, v5 ; CGP-NEXT: v_mul_lo_u32 v16, s6, v5
; CGP-NEXT: v_mul_lo_u32 v14, -1, v5 ; CGP-NEXT: v_mul_lo_u32 v17, -1, v5
; CGP-NEXT: v_mul_hi_u32 v15, s8, v5 ; CGP-NEXT: v_mul_hi_u32 v18, s6, v5
; CGP-NEXT: v_add_i32_e32 v8, vcc, v11, v8 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v14, v11
; CGP-NEXT: v_mul_lo_u32 v11, v6, v10 ; CGP-NEXT: v_mul_lo_u32 v14, v6, v13
; CGP-NEXT: v_mul_hi_u32 v16, v4, v10 ; CGP-NEXT: v_mul_hi_u32 v19, v4, v13
; CGP-NEXT: v_mul_hi_u32 v10, v6, v10 ; CGP-NEXT: v_mul_hi_u32 v13, v6, v13
; CGP-NEXT: v_add_i32_e32 v9, vcc, v14, v9 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v17, v12
; CGP-NEXT: v_mul_lo_u32 v14, v7, v13 ; CGP-NEXT: v_mul_lo_u32 v17, v10, v16
; CGP-NEXT: v_mul_hi_u32 v17, v5, v13 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v15
; CGP-NEXT: v_mul_hi_u32 v13, v7, v13 ; CGP-NEXT: v_mul_hi_u32 v15, v5, v16
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; CGP-NEXT: v_mul_hi_u32 v16, v10, v16
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v15 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v18
; CGP-NEXT: v_mul_lo_u32 v12, v4, v8 ; CGP-NEXT: v_mul_lo_u32 v18, v5, v12
; CGP-NEXT: v_mul_lo_u32 v15, v6, v8 ; CGP-NEXT: v_add_i32_e32 v17, vcc, v17, v18
; CGP-NEXT: v_mul_hi_u32 v18, v4, v8 ; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; CGP-NEXT: v_mul_hi_u32 v8, v6, v8 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v15
; CGP-NEXT: v_mul_lo_u32 v19, v5, v9 ; CGP-NEXT: v_mul_lo_u32 v15, v4, v11
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v19 ; CGP-NEXT: v_mul_lo_u32 v17, v6, v11
; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc ; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v15
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v17
; CGP-NEXT: v_mul_lo_u32 v14, v7, v9
; CGP-NEXT: v_mul_hi_u32 v17, v5, v9
; CGP-NEXT: v_mul_hi_u32 v9, v7, v9
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v15, v10
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v19
; CGP-NEXT: v_mul_hi_u32 v14, v4, v11
; CGP-NEXT: v_mul_hi_u32 v11, v6, v11
; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v15, s[4:5], v15, v19
; CGP-NEXT: v_mul_lo_u32 v19, v10, v12
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v17, v13
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v16 ; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v17, v14
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v18
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v17
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v17, vcc, v18, v17
; CGP-NEXT: v_add_i32_e32 v12, vcc, v15, v16 ; CGP-NEXT: v_mul_hi_u32 v18, v5, v12
; CGP-NEXT: v_add_i32_e32 v15, vcc, v19, v18 ; CGP-NEXT: v_mul_hi_u32 v12, v10, v12
; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v17 ; CGP-NEXT: v_add_i32_e32 v16, vcc, v19, v16
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v16, vcc, v16, v18
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v18, vcc, v19, v18
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v16, vcc, v16, v17
; CGP-NEXT: v_add_i32_e32 v12, vcc, v14, v15 ; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v15
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v18, v17
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v6, v8, vcc ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; CGP-NEXT: v_mul_lo_u32 v11, s8, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v13
; CGP-NEXT: v_mul_lo_u32 v12, -1, v4 ; CGP-NEXT: v_addc_u32_e32 v6, vcc, v6, v11, vcc
; CGP-NEXT: v_mul_hi_u32 v14, s8, v4 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v4
; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v5, v13 ; CGP-NEXT: v_mul_lo_u32 v13, -1, v4
; CGP-NEXT: v_addc_u32_e64 v13, s[6:7], v7, v9, s[4:5] ; CGP-NEXT: v_mul_hi_u32 v14, s6, v4
; CGP-NEXT: v_mul_lo_u32 v15, s8, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v16
; CGP-NEXT: v_mul_lo_u32 v16, -1, v5 ; CGP-NEXT: v_addc_u32_e32 v10, vcc, v10, v12, vcc
; CGP-NEXT: v_mul_hi_u32 v17, s8, v5 ; CGP-NEXT: v_mul_lo_u32 v12, s6, v5
; CGP-NEXT: v_mul_lo_u32 v18, s8, v13 ; CGP-NEXT: v_mul_lo_u32 v15, -1, v5
; CGP-NEXT: v_mul_lo_u32 v19, v13, v15 ; CGP-NEXT: v_mul_hi_u32 v16, s6, v5
; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v16, v18 ; CGP-NEXT: v_mul_lo_u32 v17, s6, v6
; CGP-NEXT: v_mul_hi_u32 v18, v5, v15 ; CGP-NEXT: v_mul_lo_u32 v18, v6, v11
; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v16, v17 ; CGP-NEXT: v_mul_hi_u32 v19, v4, v11
; CGP-NEXT: v_mul_lo_u32 v17, v5, v16 ; CGP-NEXT: v_mul_hi_u32 v11, v6, v11
; CGP-NEXT: v_add_i32_e64 v17, s[6:7], v19, v17 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v17
; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] ; CGP-NEXT: v_mul_lo_u32 v17, s6, v10
; CGP-NEXT: v_add_i32_e64 v17, s[6:7], v17, v18 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v17
; CGP-NEXT: v_mul_lo_u32 v17, s8, v10 ; CGP-NEXT: v_mul_lo_u32 v17, v10, v12
; CGP-NEXT: v_mul_lo_u32 v18, v10, v11 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_add_i32_e64 v12, s[8:9], v12, v17 ; CGP-NEXT: v_mul_hi_u32 v14, v5, v12
; CGP-NEXT: v_mul_hi_u32 v17, v4, v11 ; CGP-NEXT: v_mul_hi_u32 v12, v10, v12
; CGP-NEXT: v_add_i32_e64 v12, s[8:9], v12, v14 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; CGP-NEXT: v_mul_lo_u32 v14, v4, v12 ; CGP-NEXT: v_mul_lo_u32 v16, v5, v15
; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v18, v14 ; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] ; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v14, s[8:9], v14, v17 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v16, v14
; CGP-NEXT: v_mov_b32_e32 v14, s10 ; CGP-NEXT: v_mul_lo_u32 v14, v4, v13
; CGP-NEXT: v_mov_b32_e32 v17, s11 ; CGP-NEXT: v_mul_lo_u32 v16, v6, v13
; CGP-NEXT: v_add_i32_e64 v6, s[10:11], v6, v8 ; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v18, v14
; CGP-NEXT: v_mov_b32_e32 v8, s13 ; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v7, s[10:11], v7, v9 ; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v19
; CGP-NEXT: v_mul_hi_u32 v9, v10, v11 ; CGP-NEXT: v_mul_hi_u32 v14, v4, v13
; CGP-NEXT: v_mul_hi_u32 v11, v13, v15 ; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[8:9] ; CGP-NEXT: v_add_i32_e64 v18, s[4:5], v18, v19
; CGP-NEXT: v_add_i32_e64 v15, s[8:9], v18, v15 ; CGP-NEXT: v_mul_lo_u32 v19, v10, v15
; CGP-NEXT: v_mul_lo_u32 v18, v10, v12 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v16, v11
; CGP-NEXT: v_mul_hi_u32 v10, v10, v12 ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
; CGP-NEXT: v_mul_hi_u32 v12, v4, v12 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
; CGP-NEXT: v_add_i32_e64 v9, s[8:9], v18, v9 ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] ; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v16, v14
; CGP-NEXT: v_add_i32_e64 v9, s[8:9], v9, v12 ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[8:9] ; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; CGP-NEXT: v_add_i32_e64 v12, s[8:9], v18, v12 ; CGP-NEXT: v_mul_hi_u32 v17, v5, v15
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] ; CGP-NEXT: v_add_i32_e32 v12, vcc, v19, v12
; CGP-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 ; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v19, v13, v16 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v17
; CGP-NEXT: v_mul_hi_u32 v13, v13, v16 ; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; CGP-NEXT: v_mul_hi_u32 v16, v5, v16 ; CGP-NEXT: v_add_i32_e32 v17, vcc, v19, v17
; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v19, v11 ; CGP-NEXT: v_mov_b32_e32 v19, s9
; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] ; CGP-NEXT: v_mul_hi_u32 v13, v6, v13
; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v16 ; CGP-NEXT: v_mul_hi_u32 v15, v10, v15
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[6:7] ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v18
; CGP-NEXT: v_add_i32_e64 v16, s[6:7], v19, v16 ; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; CGP-NEXT: v_mov_b32_e32 v19, s14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v16
; CGP-NEXT: v_add_i32_e64 v9, s[6:7], v9, v15 ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[6:7] ; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v18
; CGP-NEXT: v_add_i32_e64 v11, s[6:7], v11, v18 ; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7] ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v12, v15 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v16
; CGP-NEXT: v_add_i32_e64 v15, s[6:7], v16, v18 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v11
; CGP-NEXT: v_add_i32_e64 v10, s[6:7], v10, v12 ; CGP-NEXT: v_addc_u32_e32 v6, vcc, v6, v13, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[6:7], v13, v15 ; CGP-NEXT: v_mul_lo_u32 v11, v3, v4
; CGP-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc ; CGP-NEXT: v_mul_hi_u32 v13, v2, v4
; CGP-NEXT: v_addc_u32_e64 v7, vcc, v7, v12, s[4:5]
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
; CGP-NEXT: v_mul_lo_u32 v9, v3, v4
; CGP-NEXT: v_mul_hi_u32 v10, v2, v4
; CGP-NEXT: v_mul_hi_u32 v4, v3, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v11 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v12
; CGP-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc ; CGP-NEXT: v_addc_u32_e32 v10, vcc, v10, v14, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v1, v5 ; CGP-NEXT: v_mul_lo_u32 v12, v1, v5
; CGP-NEXT: v_mul_hi_u32 v12, v0, v5 ; CGP-NEXT: v_mul_hi_u32 v14, v0, v5
; CGP-NEXT: v_mul_hi_u32 v5, v1, v5 ; CGP-NEXT: v_mul_hi_u32 v5, v1, v5
; CGP-NEXT: v_mul_lo_u32 v13, v2, v6 ; CGP-NEXT: v_mul_lo_u32 v15, v2, v6
; CGP-NEXT: v_mul_lo_u32 v15, v3, v6 ; CGP-NEXT: v_mul_lo_u32 v16, v3, v6
; CGP-NEXT: v_mul_hi_u32 v16, v2, v6 ; CGP-NEXT: v_mul_hi_u32 v17, v2, v6
; CGP-NEXT: v_mul_hi_u32 v6, v3, v6 ; CGP-NEXT: v_mul_hi_u32 v6, v3, v6
; CGP-NEXT: v_mul_lo_u32 v18, v0, v7 ; CGP-NEXT: v_mul_lo_u32 v18, v0, v10
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v18 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v18
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_mul_lo_u32 v11, v1, v7 ; CGP-NEXT: v_mul_lo_u32 v12, v1, v10
; CGP-NEXT: v_mul_hi_u32 v12, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v14, v0, v10
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 ; CGP-NEXT: v_mul_hi_u32 v10, v1, v10
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v15
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v15, v4
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v11, v5 ; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v16, v4
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v5, s[4:5], v12, v5
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v9, v10 ; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v17
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v16 ; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v14
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v15, v11
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_add_i32_e32 v13, vcc, v16, v13
; CGP-NEXT: v_add_i32_e32 v9, vcc, v13, v9 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v18, v17
; CGP-NEXT: v_add_i32_e32 v10, vcc, v15, v10 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_add_i32_e32 v13, vcc, v18, v16 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v11
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v15
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v13 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_mul_lo_u32 v13, s8, v4
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_mul_lo_u32 v15, 0, v4
; CGP-NEXT: v_mul_lo_u32 v10, s12, v4 ; CGP-NEXT: v_mul_hi_u32 v4, s8, v4
; CGP-NEXT: v_mul_lo_u32 v13, 0, v4 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_mul_hi_u32 v4, s12, v4 ; CGP-NEXT: v_mul_lo_u32 v14, s8, v5
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_mul_lo_u32 v16, 0, v5
; CGP-NEXT: v_mul_lo_u32 v12, s12, v5 ; CGP-NEXT: v_mul_hi_u32 v5, s8, v5
; CGP-NEXT: v_mul_lo_u32 v15, 0, v5 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v11
; CGP-NEXT: v_mul_hi_u32 v5, s12, v5 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v9 ; CGP-NEXT: v_mul_lo_u32 v6, s8, v6
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v11 ; CGP-NEXT: v_mul_lo_u32 v10, s8, v10
; CGP-NEXT: v_mul_lo_u32 v6, s12, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v15, v6
; CGP-NEXT: v_mul_lo_u32 v7, s12, v7 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v16, v10
; CGP-NEXT: v_add_i32_e32 v6, vcc, v13, v6
; CGP-NEXT: v_add_i32_e32 v7, vcc, v15, v7
; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v10, v5
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v10 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v13
; CGP-NEXT: v_subb_u32_e64 v6, s[4:5], v3, v4, vcc ; CGP-NEXT: v_subb_u32_e64 v6, s[4:5], v3, v4, vcc
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4 ; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s12, v2 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s8, v2
; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v12 ; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v0, v14
; CGP-NEXT: v_subb_u32_e64 v7, s[6:7], v1, v5, s[4:5] ; CGP-NEXT: v_subb_u32_e64 v10, s[6:7], v1, v5, s[4:5]
; CGP-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v5 ; CGP-NEXT: v_sub_i32_e64 v1, s[6:7], v1, v5
; CGP-NEXT: v_cmp_le_u32_e64 s[6:7], s12, v0 ; CGP-NEXT: v_cmp_le_u32_e64 s[6:7], s8, v0
; CGP-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[6:7] ; CGP-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[6:7]
; CGP-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v6 ; CGP-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v6
; CGP-NEXT: v_cndmask_b32_e64 v4, v8, v4, s[6:7] ; CGP-NEXT: v_cndmask_b32_e64 v4, v9, v4, s[6:7]
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
; CGP-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc ; CGP-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
; CGP-NEXT: v_subbrev_u32_e64 v1, vcc, 0, v1, s[4:5] ; CGP-NEXT: v_subbrev_u32_e64 v1, vcc, 0, v1, s[4:5]
; CGP-NEXT: v_subrev_i32_e32 v8, vcc, s12, v2 ; CGP-NEXT: v_subrev_i32_e32 v7, vcc, s8, v2
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s12, v8 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s8, v7
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
; CGP-NEXT: v_subrev_i32_e32 v10, vcc, s12, v0 ; CGP-NEXT: v_subrev_i32_e32 v11, vcc, s8, v0
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s12, v10 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s8, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v9, v19, v9, vcc ; CGP-NEXT: v_cndmask_b32_e32 v9, v19, v9, vcc
; CGP-NEXT: v_subrev_i32_e32 v12, vcc, s12, v8 ; CGP-NEXT: v_subrev_i32_e32 v13, vcc, s8, v7
; CGP-NEXT: v_subbrev_u32_e32 v13, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc ; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc
; CGP-NEXT: v_subrev_i32_e32 v14, vcc, s12, v10 ; CGP-NEXT: v_subrev_i32_e32 v12, vcc, s8, v11
; CGP-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v1, vcc ; CGP-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc ; CGP-NEXT: v_cndmask_b32_e32 v7, v7, v13, vcc
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v11 ; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_cndmask_b32_e64 v9, v10, v14, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v8, v11, v12, s[4:5]
; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v14, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v15, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v15, s[4:5]
; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 ; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
; CGP-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v0, v0, v8, s[4:5]
; CGP-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v1, v10, v1, s[4:5]
; CGP-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = urem <2 x i64> %num, <i64 1235195, i64 1235195> %result = urem <2 x i64> %num, <i64 1235195, i64 1235195>
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_urem_i64_pow2_shl_denom(i64 %x, i64 %y) { define i64 @v_urem_i64_pow2_shl_denom(i64 %x, i64 %y) {
; CHECK-LABEL: v_urem_i64_pow2_shl_denom: ; CHECK-LABEL: v_urem_i64_pow2_shl_denom:
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v12 ; CHECK-NEXT: v_add_i32_e32 v11, vcc, v13, v12
; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CHECK-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v9
; CHECK-NEXT: v_addc_u32_e64 v9, s[4:5], v1, v8, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v8, vcc
; CHECK-NEXT: v_add_i32_e64 v1, s[4:5], v1, v8
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v0 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v0
; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0 ; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v0 ; CHECK-NEXT: v_mul_hi_u32 v9, v2, v0
; CHECK-NEXT: v_mul_lo_u32 v2, v2, v9 ; CHECK-NEXT: v_mul_lo_u32 v2, v2, v1
; CHECK-NEXT: v_mul_lo_u32 v11, v9, v8 ; CHECK-NEXT: v_mul_lo_u32 v10, v1, v8
; CHECK-NEXT: v_mul_hi_u32 v12, v0, v8 ; CHECK-NEXT: v_mul_hi_u32 v11, v0, v8
; CHECK-NEXT: v_mul_hi_u32 v8, v9, v8 ; CHECK-NEXT: v_mul_hi_u32 v8, v1, v8
; CHECK-NEXT: v_add_i32_e64 v2, s[4:5], v7, v2 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; CHECK-NEXT: v_add_i32_e64 v2, s[4:5], v2, v10 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v9
; CHECK-NEXT: v_mul_lo_u32 v7, v0, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, v0, v2
; CHECK-NEXT: v_mul_lo_u32 v10, v9, v2 ; CHECK-NEXT: v_mul_lo_u32 v9, v1, v2
; CHECK-NEXT: v_mul_hi_u32 v13, v0, v2 ; CHECK-NEXT: v_mul_hi_u32 v12, v0, v2
; CHECK-NEXT: v_mul_hi_u32 v2, v9, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v11, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v10, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v12 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v13 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v9, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; CHECK-NEXT: v_add_i32_e64 v9, s[4:5], v10, v11 ; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e64 v2, s[4:5], v2, v8 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v7
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; CHECK-NEXT: v_mul_lo_u32 v2, v4, v0 ; CHECK-NEXT: v_mul_lo_u32 v2, v4, v0
; CHECK-NEXT: v_mul_hi_u32 v7, v3, v0 ; CHECK-NEXT: v_mul_hi_u32 v7, v3, v0
; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0 ; CHECK-NEXT: v_mul_hi_u32 v0, v4, v0
; CHECK-NEXT: v_mul_lo_u32 v8, v3, v1 ; CHECK-NEXT: v_mul_lo_u32 v8, v3, v1
; CHECK-NEXT: v_mul_lo_u32 v9, v4, v1 ; CHECK-NEXT: v_mul_lo_u32 v9, v4, v1
; CHECK-NEXT: v_mul_hi_u32 v10, v3, v1 ; CHECK-NEXT: v_mul_hi_u32 v10, v3, v1
; CHECK-NEXT: v_mul_hi_u32 v1, v4, v1 ; CHECK-NEXT: v_mul_hi_u32 v1, v4, v1
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16 ; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13 ; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v12 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v12
; GISEL-NEXT: v_addc_u32_e64 v12, s[4:5], v9, v13, vcc ; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v13, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 ; GISEL-NEXT: v_mul_lo_u32 v12, v10, v6
; GISEL-NEXT: v_mul_lo_u32 v13, v10, v6
; GISEL-NEXT: v_mul_lo_u32 v11, v11, v6 ; GISEL-NEXT: v_mul_lo_u32 v11, v11, v6
; GISEL-NEXT: v_mul_lo_u32 v14, v10, v12 ; GISEL-NEXT: v_mul_lo_u32 v13, v10, v9
; GISEL-NEXT: v_mul_hi_u32 v10, v10, v6 ; GISEL-NEXT: v_mul_hi_u32 v10, v10, v6
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_lo_u32 v11, v12, v13 ; GISEL-NEXT: v_mul_lo_u32 v11, v9, v12
; GISEL-NEXT: v_mul_lo_u32 v14, v6, v10 ; GISEL-NEXT: v_mul_lo_u32 v13, v6, v10
; GISEL-NEXT: v_mul_hi_u32 v15, v6, v13 ; GISEL-NEXT: v_mul_hi_u32 v14, v6, v12
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v15 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v14, v11 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; GISEL-NEXT: v_mul_lo_u32 v14, v12, v10 ; GISEL-NEXT: v_mul_lo_u32 v13, v9, v10
; GISEL-NEXT: v_mul_hi_u32 v13, v12, v13 ; GISEL-NEXT: v_mul_hi_u32 v12, v9, v12
; GISEL-NEXT: v_mul_hi_u32 v15, v6, v10 ; GISEL-NEXT: v_mul_hi_u32 v14, v6, v10
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v15 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v15 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v13, v11 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v14, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_mul_hi_u32 v10, v12, v10 ; GISEL-NEXT: v_mul_hi_u32 v10, v9, v10
; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v11 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v11
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v10, vcc ; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v10, vcc
; GISEL-NEXT: v_addc_u32_e64 v9, vcc, 0, v9, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v10, v1, v6 ; GISEL-NEXT: v_mul_lo_u32 v10, v1, v6
; GISEL-NEXT: v_mul_lo_u32 v11, v0, v9 ; GISEL-NEXT: v_mul_lo_u32 v11, v0, v9
; GISEL-NEXT: v_mul_hi_u32 v12, v0, v6 ; GISEL-NEXT: v_mul_hi_u32 v12, v0, v6
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; GISEL-NEXT: v_mul_hi_u32 v11, v7, v11 ; GISEL-NEXT: v_mul_hi_u32 v11, v7, v11
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v10 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; GISEL-NEXT: v_addc_u32_e64 v10, s[4:5], v7, v11, vcc ; GISEL-NEXT: v_addc_u32_e32 v7, vcc, v7, v11, vcc
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v7, v11 ; GISEL-NEXT: v_mul_lo_u32 v10, v8, v6
; GISEL-NEXT: v_mul_lo_u32 v11, v8, v6
; GISEL-NEXT: v_mul_lo_u32 v9, v9, v6 ; GISEL-NEXT: v_mul_lo_u32 v9, v9, v6
; GISEL-NEXT: v_mul_lo_u32 v12, v8, v10 ; GISEL-NEXT: v_mul_lo_u32 v11, v8, v7
; GISEL-NEXT: v_mul_hi_u32 v8, v8, v6 ; GISEL-NEXT: v_mul_hi_u32 v8, v8, v6
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GISEL-NEXT: v_mul_lo_u32 v9, v10, v11 ; GISEL-NEXT: v_mul_lo_u32 v9, v7, v10
; GISEL-NEXT: v_mul_lo_u32 v12, v6, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v6, v8
; GISEL-NEXT: v_mul_hi_u32 v13, v6, v11 ; GISEL-NEXT: v_mul_hi_u32 v12, v6, v10
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v12 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v9, v13 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
; GISEL-NEXT: v_mul_lo_u32 v12, v10, v8 ; GISEL-NEXT: v_mul_lo_u32 v11, v7, v8
; GISEL-NEXT: v_mul_hi_u32 v11, v10, v11 ; GISEL-NEXT: v_mul_hi_u32 v10, v7, v10
; GISEL-NEXT: v_mul_hi_u32 v13, v6, v8 ; GISEL-NEXT: v_mul_hi_u32 v12, v6, v8
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v13 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v11, v9 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GISEL-NEXT: v_mul_hi_u32 v8, v10, v8 ; GISEL-NEXT: v_mul_hi_u32 v8, v7, v8
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v11 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v9 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; GISEL-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc ; GISEL-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc
; GISEL-NEXT: v_addc_u32_e64 v7, vcc, 0, v7, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v8, v3, v6 ; GISEL-NEXT: v_mul_lo_u32 v8, v3, v6
; GISEL-NEXT: v_mul_lo_u32 v9, v2, v7 ; GISEL-NEXT: v_mul_lo_u32 v9, v2, v7
; GISEL-NEXT: v_mul_hi_u32 v10, v2, v6 ; GISEL-NEXT: v_mul_hi_u32 v10, v2, v6
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v16 ; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v16
; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v14, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v14
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v13
; CGP-NEXT: v_addc_u32_e64 v13, s[4:5], v1, v12, vcc ; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v12, vcc
; CGP-NEXT: v_add_i32_e64 v1, s[4:5], v1, v12
; CGP-NEXT: v_mul_lo_u32 v12, v4, v0 ; CGP-NEXT: v_mul_lo_u32 v12, v4, v0
; CGP-NEXT: v_mul_lo_u32 v6, v6, v0 ; CGP-NEXT: v_mul_lo_u32 v6, v6, v0
; CGP-NEXT: v_mul_hi_u32 v14, v4, v0 ; CGP-NEXT: v_mul_hi_u32 v13, v4, v0
; CGP-NEXT: v_mul_lo_u32 v4, v4, v13 ; CGP-NEXT: v_mul_lo_u32 v4, v4, v1
; CGP-NEXT: v_mul_lo_u32 v15, v13, v12 ; CGP-NEXT: v_mul_lo_u32 v14, v1, v12
; CGP-NEXT: v_mul_hi_u32 v16, v0, v12 ; CGP-NEXT: v_mul_hi_u32 v15, v0, v12
; CGP-NEXT: v_mul_hi_u32 v12, v13, v12 ; CGP-NEXT: v_mul_hi_u32 v12, v1, v12
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v6, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v14 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v13
; CGP-NEXT: v_mul_lo_u32 v6, v0, v4 ; CGP-NEXT: v_mul_lo_u32 v6, v0, v4
; CGP-NEXT: v_mul_lo_u32 v14, v13, v4 ; CGP-NEXT: v_mul_lo_u32 v13, v1, v4
; CGP-NEXT: v_mul_hi_u32 v17, v0, v4 ; CGP-NEXT: v_mul_hi_u32 v16, v0, v4
; CGP-NEXT: v_mul_hi_u32 v4, v13, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v1, v4
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v15, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v14, v6
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v6, v16 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v15
; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v17 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v16
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v13, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v14, v6
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v14, v15 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v12, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v12
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6
; CGP-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v4, v9, v0 ; CGP-NEXT: v_mul_lo_u32 v4, v9, v0
; CGP-NEXT: v_mul_hi_u32 v6, v8, v0 ; CGP-NEXT: v_mul_hi_u32 v6, v8, v0
; CGP-NEXT: v_mul_hi_u32 v0, v9, v0 ; CGP-NEXT: v_mul_hi_u32 v0, v9, v0
; CGP-NEXT: v_mul_lo_u32 v12, v8, v1 ; CGP-NEXT: v_mul_lo_u32 v12, v8, v1
; CGP-NEXT: v_mul_lo_u32 v13, v9, v1 ; CGP-NEXT: v_mul_lo_u32 v13, v9, v1
; CGP-NEXT: v_mul_hi_u32 v14, v8, v1 ; CGP-NEXT: v_mul_hi_u32 v14, v8, v1
; CGP-NEXT: v_mul_hi_u32 v1, v9, v1 ; CGP-NEXT: v_mul_hi_u32 v1, v9, v1
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v12
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v14 ; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v14
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v12 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v12
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v9 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v9
; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v3, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
; CGP-NEXT: v_add_i32_e64 v3, s[4:5], v3, v8
; CGP-NEXT: v_mul_lo_u32 v8, v4, v2 ; CGP-NEXT: v_mul_lo_u32 v8, v4, v2
; CGP-NEXT: v_mul_lo_u32 v6, v6, v2 ; CGP-NEXT: v_mul_lo_u32 v6, v6, v2
; CGP-NEXT: v_mul_hi_u32 v12, v4, v2 ; CGP-NEXT: v_mul_hi_u32 v9, v4, v2
; CGP-NEXT: v_mul_lo_u32 v4, v4, v9 ; CGP-NEXT: v_mul_lo_u32 v4, v4, v3
; CGP-NEXT: v_mul_lo_u32 v13, v9, v8 ; CGP-NEXT: v_mul_lo_u32 v12, v3, v8
; CGP-NEXT: v_mul_hi_u32 v14, v2, v8 ; CGP-NEXT: v_mul_hi_u32 v13, v2, v8
; CGP-NEXT: v_mul_hi_u32 v8, v9, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v3, v8
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v6, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v12 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_mul_lo_u32 v6, v2, v4 ; CGP-NEXT: v_mul_lo_u32 v6, v2, v4
; CGP-NEXT: v_mul_lo_u32 v12, v9, v4 ; CGP-NEXT: v_mul_lo_u32 v9, v3, v4
; CGP-NEXT: v_mul_hi_u32 v15, v2, v4 ; CGP-NEXT: v_mul_hi_u32 v14, v2, v4
; CGP-NEXT: v_mul_hi_u32 v4, v9, v4 ; CGP-NEXT: v_mul_hi_u32 v4, v3, v4
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v13, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v12, v8 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v6, v14 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v13
; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v15 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v14
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v9, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v13 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v13
; CGP-NEXT: v_add_i32_e64 v6, s[4:5], v8, v6 ; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v9, v8 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_add_i32_e64 v4, s[4:5], v4, v8 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CGP-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; CGP-NEXT: v_mul_lo_u32 v4, v7, v2 ; CGP-NEXT: v_mul_lo_u32 v4, v7, v2
; CGP-NEXT: v_mul_hi_u32 v6, v5, v2 ; CGP-NEXT: v_mul_hi_u32 v6, v5, v2
; CGP-NEXT: v_mul_hi_u32 v2, v7, v2 ; CGP-NEXT: v_mul_hi_u32 v2, v7, v2
; CGP-NEXT: v_mul_lo_u32 v8, v5, v3 ; CGP-NEXT: v_mul_lo_u32 v8, v5, v3
; CGP-NEXT: v_mul_lo_u32 v9, v7, v3 ; CGP-NEXT: v_mul_lo_u32 v9, v7, v3
; CGP-NEXT: v_mul_hi_u32 v12, v5, v3 ; CGP-NEXT: v_mul_hi_u32 v12, v5, v3
; CGP-NEXT: v_mul_hi_u32 v3, v7, v3 ; CGP-NEXT: v_mul_hi_u32 v3, v7, v3
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v8
▲ Show 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18 ; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18
; GISEL-NEXT: v_mul_lo_u32 v19, v11, v13 ; GISEL-NEXT: v_mul_lo_u32 v19, v11, v13
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v19, v17 ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v19, v17
; GISEL-NEXT: v_mul_hi_u32 v19, v7, v13 ; GISEL-NEXT: v_mul_hi_u32 v19, v7, v13
; GISEL-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v19 ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v19
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v19, vcc, v20, v19 ; GISEL-NEXT: v_add_i32_e32 v19, vcc, v20, v19
; GISEL-NEXT: s_bfe_i32 s10, -1, 0x10000 ; GISEL-NEXT: s_bfe_i32 s4, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s11, -1, 0x10000 ; GISEL-NEXT: s_bfe_i32 s5, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s12, -1, 0x10000 ; GISEL-NEXT: s_bfe_i32 s7, -1, 0x10000
; GISEL-NEXT: s_bfe_i32 s13, -1, 0x10000 ; GISEL-NEXT: s_bfe_i32 s8, -1, 0x10000
; GISEL-NEXT: v_and_b32_e32 v0, s6, v0 ; GISEL-NEXT: v_and_b32_e32 v0, s6, v0
; GISEL-NEXT: v_and_b32_e32 v2, s6, v2 ; GISEL-NEXT: v_and_b32_e32 v2, s6, v2
; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_mul_hi_u32 v13, v11, v13
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
; GISEL-NEXT: v_mov_b32_e32 v16, s4
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v18 ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16 ; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v19, v18 ; GISEL-NEXT: v_mov_b32_e32 v19, s5
; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v16 ; GISEL-NEXT: v_mov_b32_e32 v15, s7
; GISEL-NEXT: v_mul_hi_u32 v13, v11, v13
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v18
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v14 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v14
; GISEL-NEXT: v_addc_u32_e64 v14, s[4:5], v8, v12, vcc ; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v12, vcc
; GISEL-NEXT: v_mul_lo_u32 v15, v4, v6 ; GISEL-NEXT: v_mul_lo_u32 v12, v4, v6
; GISEL-NEXT: v_mul_lo_u32 v5, v5, v6 ; GISEL-NEXT: v_mul_lo_u32 v5, v5, v6
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v7, v17 ; GISEL-NEXT: v_mul_hi_u32 v14, v4, v6
; GISEL-NEXT: v_addc_u32_e64 v16, s[6:7], v11, v13, s[4:5] ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v17
; GISEL-NEXT: v_mul_lo_u32 v17, v9, v7 ; GISEL-NEXT: v_addc_u32_e32 v11, vcc, v11, v13, vcc
; GISEL-NEXT: v_mul_lo_u32 v13, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v10, v7 ; GISEL-NEXT: v_mul_lo_u32 v10, v10, v7
; GISEL-NEXT: v_mul_hi_u32 v18, v9, v7 ; GISEL-NEXT: v_mul_hi_u32 v17, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v9, v9, v16 ; GISEL-NEXT: v_mul_lo_u32 v4, v4, v8
; GISEL-NEXT: v_mul_lo_u32 v19, v16, v17 ; GISEL-NEXT: v_mul_lo_u32 v18, v8, v12
; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v10, v9 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GISEL-NEXT: v_mul_hi_u32 v10, v7, v17 ; GISEL-NEXT: v_mul_hi_u32 v5, v6, v12
; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v18 ; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_mul_lo_u32 v18, v7, v9 ; GISEL-NEXT: v_mul_lo_u32 v9, v9, v11
; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7] ; GISEL-NEXT: v_mul_lo_u32 v10, v11, v13
; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v18, v10 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v14
; GISEL-NEXT: v_mul_hi_u32 v10, v4, v6 ; GISEL-NEXT: v_mul_hi_u32 v14, v7, v13
; GISEL-NEXT: v_mul_lo_u32 v4, v4, v14 ; GISEL-NEXT: v_mul_hi_u32 v13, v11, v13
; GISEL-NEXT: v_mul_lo_u32 v18, v14, v15 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v17
; GISEL-NEXT: v_add_i32_e64 v4, s[8:9], v5, v4 ; GISEL-NEXT: v_mul_lo_u32 v17, v7, v9
; GISEL-NEXT: v_mul_hi_u32 v5, v6, v15 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
; GISEL-NEXT: v_add_i32_e64 v4, s[8:9], v4, v10 ; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v14
; GISEL-NEXT: v_mul_lo_u32 v10, v6, v4 ; GISEL-NEXT: v_mul_lo_u32 v10, v6, v4
; GISEL-NEXT: v_add_i32_e64 v10, s[8:9], v18, v10 ; GISEL-NEXT: v_mul_lo_u32 v14, v8, v4
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] ; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v18, v10
; GISEL-NEXT: v_add_i32_e64 v5, s[8:9], v10, v5 ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
; GISEL-NEXT: v_mov_b32_e32 v5, s10 ; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
; GISEL-NEXT: v_mov_b32_e32 v10, s11 ; GISEL-NEXT: v_mul_hi_u32 v5, v6, v4
; GISEL-NEXT: v_add_i32_e64 v8, s[10:11], v8, v12 ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; GISEL-NEXT: v_mov_b32_e32 v12, s12 ; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v18, v10
; GISEL-NEXT: v_add_i32_e64 v11, s[10:11], v11, v13 ; GISEL-NEXT: v_mul_lo_u32 v18, v11, v9
; GISEL-NEXT: v_mul_hi_u32 v13, v14, v15 ; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12
; GISEL-NEXT: v_mul_hi_u32 v15, v16, v17 ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[8:9] ; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v12, v5
; GISEL-NEXT: v_add_i32_e64 v17, s[8:9], v18, v17 ; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; GISEL-NEXT: v_mul_lo_u32 v18, v14, v4 ; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12
; GISEL-NEXT: v_mul_hi_u32 v14, v14, v4 ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_mul_hi_u32 v4, v6, v4 ; GISEL-NEXT: v_add_i32_e32 v14, vcc, v17, v14
; GISEL-NEXT: v_add_i32_e64 v13, s[8:9], v18, v13 ; GISEL-NEXT: v_mul_hi_u32 v17, v7, v9
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[8:9] ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v18, v13
; GISEL-NEXT: v_add_i32_e64 v4, s[8:9], v13, v4
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[8:9]
; GISEL-NEXT: v_add_i32_e64 v13, s[8:9], v18, v13
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v18, s[6:7], v19, v18
; GISEL-NEXT: v_mul_lo_u32 v19, v16, v9
; GISEL-NEXT: v_mul_hi_u32 v16, v16, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v7, v9
; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v19, v15
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v15, v9
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v19, v15
; GISEL-NEXT: v_mov_b32_e32 v19, s13
; GISEL-NEXT: v_add_i32_e64 v4, s[6:7], v4, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], v9, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[6:7]
; GISEL-NEXT: v_add_i32_e64 v13, s[6:7], v13, v17
; GISEL-NEXT: v_add_i32_e64 v15, s[6:7], v15, v18
; GISEL-NEXT: v_add_i32_e64 v13, s[6:7], v14, v13
; GISEL-NEXT: v_add_i32_e64 v14, s[6:7], v16, v15
; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc
; GISEL-NEXT: v_addc_u32_e64 v11, vcc, v11, v14, s[4:5]
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GISEL-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc
; GISEL-NEXT: v_mul_lo_u32 v8, 0, v4
; GISEL-NEXT: v_mul_hi_u32 v13, v0, v4
; GISEL-NEXT: v_mul_hi_u32 v4, 0, v4
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, 0, v11, vcc
; GISEL-NEXT: v_mul_lo_u32 v11, 0, v7
; GISEL-NEXT: v_mul_hi_u32 v14, v2, v7
; GISEL-NEXT: v_mul_hi_u32 v7, 0, v7
; GISEL-NEXT: v_mul_lo_u32 v15, v0, v6
; GISEL-NEXT: v_mul_lo_u32 v16, 0, v6
; GISEL-NEXT: v_mul_hi_u32 v17, v0, v6
; GISEL-NEXT: v_mul_hi_u32 v6, 0, v6
; GISEL-NEXT: v_mul_lo_u32 v18, v2, v9
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 ; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v17
; GISEL-NEXT: v_mul_lo_u32 v11, 0, v9
; GISEL-NEXT: v_mul_hi_u32 v14, v2, v9
; GISEL-NEXT: v_mul_hi_u32 v9, 0, v9
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v16, v4
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v11, v7
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v8, s[4:5], v8, v13
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v4, s[4:5], v4, v17
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v14 ; GISEL-NEXT: v_add_i32_e32 v17, vcc, v18, v17
; GISEL-NEXT: v_mov_b32_e32 v18, s8
; GISEL-NEXT: v_mul_hi_u32 v4, v8, v4
; GISEL-NEXT: v_mul_hi_u32 v9, v11, v9
; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v10
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v15, v8 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v16, v13 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v17, v14
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v18, v17 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 ; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GISEL-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v15 ; GISEL-NEXT: v_mul_lo_u32 v6, 0, v5
; GISEL-NEXT: v_mul_hi_u32 v8, v0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, 0, v5
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v13
; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v11, v9, vcc
; GISEL-NEXT: v_mul_lo_u32 v10, 0, v7
; GISEL-NEXT: v_mul_hi_u32 v11, v2, v7
; GISEL-NEXT: v_mul_hi_u32 v7, 0, v7
; GISEL-NEXT: v_mul_lo_u32 v12, v0, v4
; GISEL-NEXT: v_mul_lo_u32 v13, 0, v4
; GISEL-NEXT: v_mul_hi_u32 v14, v0, v4
; GISEL-NEXT: v_mul_hi_u32 v4, 0, v4
; GISEL-NEXT: v_mul_lo_u32 v17, v2, v9
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_mul_lo_u32 v10, 0, v9
; GISEL-NEXT: v_mul_hi_u32 v11, v2, v9
; GISEL-NEXT: v_mul_hi_u32 v9, 0, v9
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v13, v5
; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8
; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v14
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v13, v8 ; GISEL-NEXT: v_add_i32_e32 v8, vcc, v13, v8
; GISEL-NEXT: v_mul_lo_u32 v13, v3, v4 ; GISEL-NEXT: v_add_i32_e32 v12, vcc, v17, v14
; GISEL-NEXT: v_mul_lo_u32 v15, 0, v4 ; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_mul_hi_u32 v4, v3, v4 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14 ; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GISEL-NEXT: v_mul_lo_u32 v14, v1, v7 ; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v12
; GISEL-NEXT: v_mul_lo_u32 v16, 0, v7 ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GISEL-NEXT: v_mul_lo_u32 v8, v3, v5
; GISEL-NEXT: v_mul_lo_u32 v12, 0, v5
; GISEL-NEXT: v_mul_hi_u32 v5, v3, v5
; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GISEL-NEXT: v_mul_lo_u32 v11, v1, v7
; GISEL-NEXT: v_mul_lo_u32 v13, 0, v7
; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7 ; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v11 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v10
; GISEL-NEXT: v_mul_lo_u32 v6, v3, v6 ; GISEL-NEXT: v_mul_lo_u32 v4, v3, v4
; GISEL-NEXT: v_mul_lo_u32 v8, v1, v8 ; GISEL-NEXT: v_mul_lo_u32 v6, v1, v6
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v15, v6 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v12, v4
; GISEL-NEXT: v_add_i32_e32 v8, vcc, v16, v8 ; GISEL-NEXT: v_add_i32_e32 v6, vcc, v13, v6
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GISEL-NEXT: v_add_i32_e32 v6, vcc, v8, v7 ; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v13 ; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
; GISEL-NEXT: v_subb_u32_e64 v7, s[4:5], 0, v4, vcc ; GISEL-NEXT: v_subb_u32_e64 v6, s[4:5], 0, v4, vcc
; GISEL-NEXT: v_sub_i32_e64 v4, s[4:5], 0, v4 ; GISEL-NEXT: v_sub_i32_e64 v4, s[4:5], 0, v4
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3
; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v14 ; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v11
; GISEL-NEXT: v_subb_u32_e64 v9, s[6:7], 0, v6, s[4:5] ; GISEL-NEXT: v_subb_u32_e64 v8, s[6:7], 0, v5, s[4:5]
; GISEL-NEXT: v_sub_i32_e64 v6, s[6:7], 0, v6 ; GISEL-NEXT: v_sub_i32_e64 v5, s[6:7], 0, v5
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v2, v1 ; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v2, v1
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[6:7] ; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v7 ; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v6
; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[6:7] ; GISEL-NEXT: v_cndmask_b32_e64 v7, v16, v7, s[6:7]
; GISEL-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9 ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
; GISEL-NEXT: v_cndmask_b32_e32 v8, v12, v11, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v9, v15, v9, vcc
; GISEL-NEXT: v_subbrev_u32_e64 v6, vcc, 0, v6, s[4:5] ; GISEL-NEXT: v_subbrev_u32_e64 v5, vcc, 0, v5, s[4:5]
; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v0, v3 ; GISEL-NEXT: v_sub_i32_e32 v10, vcc, v0, v3
; GISEL-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v11, v3 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v10, v3
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
; GISEL-NEXT: v_sub_i32_e32 v13, vcc, v2, v1 ; GISEL-NEXT: v_sub_i32_e32 v12, vcc, v2, v1
; GISEL-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v6, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v13, v1 ; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v12, v1
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, -1, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GISEL-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v11, v19, v11, vcc
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v11, v3 ; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v10, v3
; GISEL-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v4, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v4, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; GISEL-NEXT: v_cndmask_b32_e32 v14, v19, v14, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v13, v18, v13, vcc
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v13, v1 ; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v12, v1
; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v6, vcc ; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v5, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v14 ; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v13
; GISEL-NEXT: v_cndmask_b32_e64 v1, v13, v1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, v12, v1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v3, v6, v15, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v3, v5, v15, s[4:5]
; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8 ; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9
; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v1, v7, v4, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v4, vcc
; GISEL-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_urem_v2i64_24bit: ; CGP-LABEL: v_urem_v2i64_24bit:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s6, 0xffffff ; CGP-NEXT: s_mov_b32 s6, 0xffffff
; CGP-NEXT: v_and_b32_e32 v0, s6, v0 ; CGP-NEXT: v_and_b32_e32 v0, s6, v0
; CGP-NEXT: v_and_b32_e32 v1, s6, v2 ; CGP-NEXT: v_and_b32_e32 v1, s6, v2
Show All 36 Lines

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

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; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: udiv_i64_oddk_denom: ; GFX6-LABEL: udiv_i64_oddk_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f176a73 ; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f176a73
; GFX6-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX6-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GFX6-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0 ; GFX6-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_movk_i32 s2, 0xfee0 ; GFX6-NEXT: s_movk_i32 s4, 0xfee0
; GFX6-NEXT: s_mov_b32 s3, 0x68958c89 ; GFX6-NEXT: s_mov_b32 s5, 0x68958c89
; GFX6-NEXT: v_mov_b32_e32 v8, 0 ; GFX6-NEXT: v_mov_b32_e32 v8, 0
; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_mov_b32_e32 v7, 0 ; GFX6-NEXT: v_mov_b32_e32 v7, 0
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s4
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s5
; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s5
; GFX6-NEXT: s_mov_b32 s11, 0xf000 ; GFX6-NEXT: s_movk_i32 s8, 0x11f
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_mov_b32 s9, 0x976a7377
; GFX6-NEXT: s_mov_b32 s8, s4
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s5
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v3 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v3
; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s4
; GFX6-NEXT: v_mul_lo_u32 v6, v2, s3 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s5
; GFX6-NEXT: v_mul_lo_u32 v4, v1, s5
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_lo_u32 v3, v0, s5
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_mul_lo_u32 v5, v0, s3 ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: s_mov_b32 s5, s1
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_mul_lo_u32 v6, v0, v4 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; GFX6-NEXT: v_mul_hi_u32 v9, v0, v5 ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_mul_hi_u32 v10, v0, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_hi_u32 v11, v2, v4 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: s_movk_i32 s2, 0x11f
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v10, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX6-NEXT: s_mov_b32 s3, 0x976a7377
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX6-NEXT: v_mul_hi_u32 v4, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s3, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
; GFX6-NEXT: s_mov_b32 s4, 0x976a7376
; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s8
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s9
; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s9
; GFX6-NEXT: v_mov_b32_e32 v5, s2 ; GFX6-NEXT: v_mov_b32_e32 v5, s8
; GFX6-NEXT: s_mov_b32 s9, s5
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s9
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s7, v2 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s3, v2
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s6, v3 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s2, v3
; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc ; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s3, v3 ; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s9, v3
; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
; GFX6-NEXT: s_movk_i32 s3, 0x11e ; GFX6-NEXT: s_movk_i32 s2, 0x11e
; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s3, v4 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s2, v4
; GFX6-NEXT: s_mov_b32 s9, 0x976a7376
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s4, v5 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s9, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s2, v4 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s8, v4
; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 ; GFX6-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0
; GFX6-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 ; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0
; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v6, s7 ; GFX6-NEXT: v_mov_b32_e32 v6, s3
; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s3, v2 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s2, v2
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s4, v3 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s9, v3
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s2, v2 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s8, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: udiv_i64_oddk_denom: ; GFX9-LABEL: udiv_i64_oddk_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f176a73 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f176a73
; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GFX9-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0 ; GFX9-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_movk_i32 s4, 0xfee0 ; GFX9-NEXT: s_movk_i32 s2, 0xfee0
; GFX9-NEXT: s_mov_b32 s5, 0x68958c89 ; GFX9-NEXT: s_mov_b32 s3, 0x68958c89
; GFX9-NEXT: v_mov_b32_e32 v8, 0 ; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s4 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s5 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX9-NEXT: v_mul_lo_u32 v4, v1, s5 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3
; GFX9-NEXT: v_mul_lo_u32 v6, v0, s5 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3
; GFX9-NEXT: v_mul_lo_u32 v6, v0, s3
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v4, v0, v6 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v6
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v6 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v6
; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6 ; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4
; GFX9-NEXT: v_mul_hi_u32 v6, v0, s5
; GFX9-NEXT: v_mul_lo_u32 v7, v2, s5
; GFX9-NEXT: v_mul_lo_u32 v9, v0, s5
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_add_u32_e32 v4, v6, v4
; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v9
; GFX9-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v11, v2, v4
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v8, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v2, v9
; GFX9-NEXT: v_mul_hi_u32 v9, v2, v9
; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v10
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3
; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3
; GFX9-NEXT: v_mul_lo_u32 v6, v0, s3
; GFX9-NEXT: s_movk_i32 s2, 0x11f
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v4, v0, v6
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v6
; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6
; GFX9-NEXT: s_mov_b32 s3, 0x976a7377
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: s_movk_i32 s2, 0x11f
; GFX9-NEXT: s_mov_b32 s3, 0x976a7377
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3
; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3
Show All 34 Lines
; ;
; GFX90A-LABEL: udiv_i64_oddk_denom: ; GFX90A-LABEL: udiv_i64_oddk_denom:
; GFX90A: ; %bb.0: ; GFX90A: ; %bb.0:
; GFX90A-NEXT: v_mov_b32_e32 v0, 0x4f176a73 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0x4f176a73
; GFX90A-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GFX90A-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0 ; GFX90A-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
; GFX90A-NEXT: v_rcp_f32_e32 v0, v0 ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0
; GFX90A-NEXT: s_movk_i32 s2, 0xfee0 ; GFX90A-NEXT: s_movk_i32 s2, 0xfee0
; GFX90A-NEXT: s_mov_b32 s3, 0x68958c89 ; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX90A-NEXT: v_mov_b32_e32 v8, 0 ; GFX90A-NEXT: s_mov_b32 s0, 0x68958c89
; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX90A-NEXT: v_trunc_f32_e32 v1, v1 ; GFX90A-NEXT: v_trunc_f32_e32 v1, v1
; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX90A-NEXT: v_mul_lo_u32 v3, v0, s2 ; GFX90A-NEXT: v_mul_lo_u32 v3, v0, s2
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s3 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s0
; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3
; GFX90A-NEXT: v_mul_lo_u32 v4, v1, s3 ; GFX90A-NEXT: v_mul_lo_u32 v4, v1, s0
; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4 ; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4
; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s3 ; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s0
; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 ; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e64 v0, s[0:1], v0, v3
; GFX90A-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[0:1]
; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s2
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, s3
; GFX90A-NEXT: v_mul_lo_u32 v5, v3, s3
; GFX90A-NEXT: v_add_u32_e32 v6, v7, v6
; GFX90A-NEXT: v_add_u32_e32 v5, v6, v5
; GFX90A-NEXT: v_mul_lo_u32 v9, v0, s3
; GFX90A-NEXT: v_mul_lo_u32 v7, v0, v5
; GFX90A-NEXT: v_mul_hi_u32 v10, v0, v9
; GFX90A-NEXT: v_mul_hi_u32 v6, v0, v5
; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v10, v7
; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, v8, v6, vcc
; GFX90A-NEXT: v_mul_hi_u32 v11, v3, v9
; GFX90A-NEXT: v_mul_lo_u32 v9, v3, v9
; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9
; GFX90A-NEXT: v_mul_hi_u32 v10, v3, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v11, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v3, v5
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v6, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v7, vcc
; GFX90A-NEXT: v_add_u32_e32 v1, v1, v4
; GFX90A-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[0:1]
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v4, v0, s2
; GFX90A-NEXT: v_mul_hi_u32 v5, v0, s0
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s0
; GFX90A-NEXT: v_add_u32_e32 v4, v5, v4
; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3
; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s0
; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_mul_lo_u32 v4, s6, v1 ; GFX90A-NEXT: v_mul_lo_u32 v4, s6, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0
; GFX90A-NEXT: v_mul_hi_u32 v3, s6, v1 ; GFX90A-NEXT: v_mul_hi_u32 v3, s6, v1
; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
; GFX90A-NEXT: v_mul_hi_u32 v6, s7, v0 ; GFX90A-NEXT: v_mul_hi_u32 v6, s7, v0
; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0
▲ Show 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16 ; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: udiv_v2i64_mixed_pow2k_denom: ; GFX6-LABEL: udiv_v2i64_mixed_pow2k_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000 ; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000
; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_movk_i32 s2, 0xf001 ; GFX6-NEXT: s_movk_i32 s6, 0xf001
; GFX6-NEXT: v_mov_b32_e32 v8, 0 ; GFX6-NEXT: v_mov_b32_e32 v8, 0
; GFX6-NEXT: v_mov_b32_e32 v7, 0 ; GFX6-NEXT: v_mov_b32_e32 v7, 0
; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_mul_hi_u32 v2, v0, s2 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, s6
; GFX6-NEXT: v_mul_lo_u32 v3, v1, s2 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, s6
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s6
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshr_b64 s[8:9], s[0:1], 12
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX6-NEXT: v_mul_hi_u32 v4, v0, s2
; GFX6-NEXT: v_mul_lo_u32 v5, v2, s2
; GFX6-NEXT: v_mul_lo_u32 v6, v0, s2
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshr_b64 s[2:3], s[8:9], 12
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v9, v0, v6
; GFX6-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v11, v2, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v10, v2, v6
; GFX6-NEXT: v_mul_hi_u32 v6, v2, v6
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v10
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s10, v1 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, s6
; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, s6
; GFX6-NEXT: v_mul_hi_u32 v4, s10, v1 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s6
; GFX6-NEXT: v_mul_hi_u32 v5, s11, v1 ; GFX6-NEXT: s_movk_i32 s0, 0xfff
; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v5, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s11, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: s_movk_i32 s0, 0xfff ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX6-NEXT: v_mul_hi_u32 v4, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v5, s3, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v1, s0 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s0
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s0 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, s0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v0
; GFX6-NEXT: v_mul_lo_u32 v8, v0, s0 ; GFX6-NEXT: v_mul_lo_u32 v8, v0, s0
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v0
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_mov_b32_e32 v5, s11 ; GFX6-NEXT: v_mov_b32_e32 v5, s3
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s10, v8 ; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s2, v8
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc ; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s0, v8 ; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s0, v8
; GFX6-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc ; GFX6-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
; GFX6-NEXT: s_movk_i32 s0, 0xffe ; GFX6-NEXT: s_movk_i32 s0, 0xffe
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v5 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GFX6-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v8 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v8
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_cndmask_b32_e64 v4, -1, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, -1, v5, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v0, s2 ; GFX6-NEXT: v_mov_b32_e32 v0, s8
; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v1, s9
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom: ; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000 ; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_movk_i32 s4, 0xf001 ; GFX9-NEXT: s_movk_i32 s2, 0xf001
; GFX9-NEXT: v_mov_b32_e32 v7, 0 ; GFX9-NEXT: v_mov_b32_e32 v7, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX9-NEXT: s_movk_i32 s8, 0xfff ; GFX9-NEXT: s_movk_i32 s8, 0xfff
; GFX9-NEXT: v_mul_hi_u32 v2, v0, s4 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, s2
; GFX9-NEXT: v_mul_lo_u32 v4, v1, s4 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s2
; GFX9-NEXT: v_mul_lo_u32 v3, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, s2
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
; GFX9-NEXT: v_mul_hi_u32 v6, v0, v3 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v3
; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, v1, v3 ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v3
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_hi_u32 v4, v0, s4
; GFX9-NEXT: v_mul_lo_u32 v6, v2, s4
; GFX9-NEXT: v_mul_lo_u32 v8, v0, s4
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX9-NEXT: v_sub_u32_e32 v4, v4, v0
; GFX9-NEXT: v_add_u32_e32 v4, v4, v6
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v9, v0, v8
; GFX9-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v11, v2, v4
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v9, v6
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v7, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v2, v8
; GFX9-NEXT: v_mul_hi_u32 v8, v2, v8
; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v10
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: v_mul_hi_u32 v2, v0, s2
; GFX9-NEXT: v_mul_lo_u32 v3, v1, s2
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshr_b64 s[2:3], s[4:5], 12
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v6, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v6, v3
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX9-NEXT: s_movk_i32 s4, 0xffe
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: s_lshr_b64 s[2:3], s[4:5], 12
; GFX9-NEXT: s_movk_i32 s4, 0xffe
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8
Show All 23 Lines
; GFX9-NEXT: global_store_dwordx4 v5, v[0:3], s[0:1] ; GFX9-NEXT: global_store_dwordx4 v5, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX90A-LABEL: udiv_v2i64_mixed_pow2k_denom: ; GFX90A-LABEL: udiv_v2i64_mixed_pow2k_denom:
; GFX90A: ; %bb.0: ; GFX90A: ; %bb.0:
; GFX90A-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GFX90A-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000 ; GFX90A-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000
; GFX90A-NEXT: v_rcp_f32_e32 v0, v0 ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0
; GFX90A-NEXT: s_movk_i32 s8, 0xf001 ; GFX90A-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX90A-NEXT: v_mov_b32_e32 v8, 0 ; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v4, 0 ; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX90A-NEXT: v_trunc_f32_e32 v1, v1 ; GFX90A-NEXT: v_trunc_f32_e32 v1, v1
; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX90A-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX90A-NEXT: s_lshr_b64 s[0:1], s[4:5], 12
; GFX90A-NEXT: v_mul_hi_u32 v2, v0, s8 ; GFX90A-NEXT: s_movk_i32 s4, 0xf001
; GFX90A-NEXT: v_mul_hi_u32 v2, v0, s4
; GFX90A-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX90A-NEXT: v_sub_u32_e32 v2, v2, v0
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s8 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s4
; GFX90A-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX90A-NEXT: v_add_u32_e32 v2, v2, v3
; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s8 ; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s4
; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v3, v0, v2 ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, v2
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 ; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v2 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e64 v0, s[0:1], v0, v2
; GFX90A-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX90A-NEXT: v_mul_hi_u32 v6, v0, s8
; GFX90A-NEXT: v_mul_lo_u32 v5, v2, s8
; GFX90A-NEXT: v_sub_u32_e32 v6, v6, v0
; GFX90A-NEXT: v_add_u32_e32 v5, v6, v5
; GFX90A-NEXT: v_mul_lo_u32 v9, v0, s8
; GFX90A-NEXT: v_mul_lo_u32 v7, v0, v5
; GFX90A-NEXT: v_mul_hi_u32 v10, v0, v9
; GFX90A-NEXT: v_mul_hi_u32 v6, v0, v5
; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v10, v7
; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, v8, v6, vcc
; GFX90A-NEXT: v_mul_hi_u32 v11, v2, v9
; GFX90A-NEXT: v_mul_lo_u32 v9, v2, v9
; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9
; GFX90A-NEXT: v_mul_hi_u32 v10, v2, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v11, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v2, v2, v5
; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v7, vcc
; GFX90A-NEXT: v_add_u32_e32 v1, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[0:1]
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, s4
; GFX90A-NEXT: v_mul_lo_u32 v2, v1, s4
; GFX90A-NEXT: v_sub_u32_e32 v3, v3, v0
; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2
; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s4
; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v3, v0, v2
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, s6, v1 ; GFX90A-NEXT: v_mul_lo_u32 v3, s6, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0
; GFX90A-NEXT: v_mul_hi_u32 v2, s6, v1 ; GFX90A-NEXT: v_mul_hi_u32 v2, s6, v1
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v8, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v8, v2, vcc
; GFX90A-NEXT: v_mul_hi_u32 v6, s7, v0 ; GFX90A-NEXT: v_mul_hi_u32 v6, s7, v0
; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0
; GFX90A-NEXT: v_mul_hi_u32 v5, s7, v1 ; GFX90A-NEXT: v_mul_hi_u32 v5, s7, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v2, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v2, v6, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX90A-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v2, vcc
; GFX90A-NEXT: s_movk_i32 s0, 0xfff ; GFX90A-NEXT: s_movk_i32 s4, 0xfff
; GFX90A-NEXT: v_mul_lo_u32 v2, v1, s0 ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, s4
; GFX90A-NEXT: v_mul_hi_u32 v3, v0, s0 ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, s4
; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2
; GFX90A-NEXT: v_mul_lo_u32 v3, v0, s0 ; GFX90A-NEXT: v_mul_lo_u32 v3, v0, s4
; GFX90A-NEXT: v_mov_b32_e32 v5, s7 ; GFX90A-NEXT: v_mov_b32_e32 v5, s7
; GFX90A-NEXT: v_sub_co_u32_e32 v3, vcc, s6, v3 ; GFX90A-NEXT: v_sub_co_u32_e32 v3, vcc, s6, v3
; GFX90A-NEXT: v_subb_co_u32_e32 v2, vcc, v5, v2, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v2, vcc, v5, v2, vcc
; GFX90A-NEXT: v_subrev_co_u32_e32 v5, vcc, s0, v3 ; GFX90A-NEXT: v_subrev_co_u32_e32 v5, vcc, s4, v3
; GFX90A-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc ; GFX90A-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
; GFX90A-NEXT: s_movk_i32 s0, 0xffe ; GFX90A-NEXT: s_movk_i32 s4, 0xffe
; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s0, v5 ; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s4, v5
; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX90A-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX90A-NEXT: v_cndmask_b32_e64 v5, 1, 2, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v5, 1, 2, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v0, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v0, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc
; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3 ; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s4, v3
; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX90A-NEXT: v_cndmask_b32_e32 v2, -1, v3, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v2, -1, v3, vcc
; GFX90A-NEXT: s_lshr_b64 s[4:5], s[4:5], 12
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX90A-NEXT: v_cndmask_b32_e32 v2, v0, v5, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v2, v0, v5, vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v1, v6, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v3, v1, v6, vcc
; GFX90A-NEXT: v_mov_b32_e32 v0, s4 ; GFX90A-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NEXT: v_mov_b32_e32 v1, s5 ; GFX90A-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
%r = udiv <2 x i64> %x, <i64 4096, i64 4095> %r = udiv <2 x i64> %x, <i64 4096, i64 4095>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX6-NEXT: v_mul_lo_u32 v6, v2, s3 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3
; GFX6-NEXT: v_mul_lo_u32 v5, v0, s3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_mul_lo_u32 v6, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v9, v0, v5
; GFX6-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v11, v2, v4
; GFX6-NEXT: s_movk_i32 s4, 0x11f ; GFX6-NEXT: s_movk_i32 s4, 0x11f
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v10, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX6-NEXT: s_mov_b32 s9, s5 ; GFX6-NEXT: s_mov_b32 s9, s5
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v10 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc ; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1] ; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: s_movk_i32 s5, 0x11e
; GFX6-NEXT: s_mov_b32 s11, 0xf000
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX6-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX6-NEXT: s_movk_i32 s5, 0x11e ; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: s_mov_b32 s11, 0xf000
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v0, s4 ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s4
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s12 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s12
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s12 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s12
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s12 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s12
; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s7, v1 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s7, v1
; GFX6-NEXT: v_mov_b32_e32 v3, s4 ; GFX6-NEXT: v_mov_b32_e32 v3, s4
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s6, v0
; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc ; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0 ; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0
; GFX6-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
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; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: urem_i64_oddk_denom: ; GFX9-LABEL: urem_i64_oddk_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f1761f8 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f1761f8
; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GFX9-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0 ; GFX9-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_movk_i32 s4, 0xfee0 ; GFX9-NEXT: s_movk_i32 s2, 0xfee0
; GFX9-NEXT: s_mov_b32 s5, 0x689e0837 ; GFX9-NEXT: s_mov_b32 s3, 0x689e0837
; GFX9-NEXT: v_mov_b32_e32 v8, 0 ; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3
; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3
; GFX9-NEXT: v_mul_lo_u32 v6, v0, s3
; GFX9-NEXT: s_movk_i32 s8, 0x11f ; GFX9-NEXT: s_movk_i32 s8, 0x11f
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s4
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s5
; GFX9-NEXT: v_mul_lo_u32 v4, v1, s5
; GFX9-NEXT: v_mul_lo_u32 v6, v0, s5
; GFX9-NEXT: s_mov_b32 s9, 0x9761f7c9
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v4, v0, v6 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v6
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v6 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v6
; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6 ; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6
; GFX9-NEXT: s_mov_b32 s9, 0x9761f7c9
; GFX9-NEXT: s_mov_b32 s10, 0x9761f7c8 ; GFX9-NEXT: s_mov_b32 s10, 0x9761f7c8
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4
; GFX9-NEXT: v_mul_hi_u32 v6, v0, s5
; GFX9-NEXT: v_mul_lo_u32 v7, v2, s5
; GFX9-NEXT: v_mul_lo_u32 v9, v0, s5
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_add_u32_e32 v4, v6, v4
; GFX9-NEXT: v_add_u32_e32 v4, v4, v7
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v9
; GFX9-NEXT: v_mul_hi_u32 v10, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v11, v2, v4
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v8, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v2, v9
; GFX9-NEXT: v_mul_hi_u32 v9, v2, v9
; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v10
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v11, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3
; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3
; GFX9-NEXT: v_mul_lo_u32 v6, v0, s3
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v4, v0, v6
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v6
; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; ;
; GFX90A-LABEL: urem_i64_oddk_denom: ; GFX90A-LABEL: urem_i64_oddk_denom:
; GFX90A: ; %bb.0: ; GFX90A: ; %bb.0:
; GFX90A-NEXT: v_mov_b32_e32 v0, 0x4f1761f8 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0x4f1761f8
; GFX90A-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GFX90A-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0 ; GFX90A-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0
; GFX90A-NEXT: v_rcp_f32_e32 v0, v0 ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0
; GFX90A-NEXT: s_movk_i32 s2, 0xfee0 ; GFX90A-NEXT: s_movk_i32 s2, 0xfee0
; GFX90A-NEXT: s_mov_b32 s3, 0x689e0837 ; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX90A-NEXT: v_mov_b32_e32 v8, 0 ; GFX90A-NEXT: s_mov_b32 s0, 0x689e0837
; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX90A-NEXT: v_trunc_f32_e32 v1, v1 ; GFX90A-NEXT: v_trunc_f32_e32 v1, v1
; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX90A-NEXT: v_mul_lo_u32 v3, v0, s2 ; GFX90A-NEXT: v_mul_lo_u32 v3, v0, s2
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s3 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s0
; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3
; GFX90A-NEXT: v_mul_lo_u32 v4, v1, s3 ; GFX90A-NEXT: v_mul_lo_u32 v4, v1, s0
; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4 ; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4
; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s3 ; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s0
; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 ; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e64 v0, s[0:1], v0, v3
; GFX90A-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[0:1]
; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s2
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, s3
; GFX90A-NEXT: v_mul_lo_u32 v5, v3, s3
; GFX90A-NEXT: v_add_u32_e32 v6, v7, v6
; GFX90A-NEXT: v_add_u32_e32 v5, v6, v5
; GFX90A-NEXT: v_mul_lo_u32 v9, v0, s3
; GFX90A-NEXT: v_mul_lo_u32 v7, v0, v5
; GFX90A-NEXT: v_mul_hi_u32 v10, v0, v9
; GFX90A-NEXT: v_mul_hi_u32 v6, v0, v5
; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v10, v7
; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, v8, v6, vcc
; GFX90A-NEXT: v_mul_hi_u32 v11, v3, v9
; GFX90A-NEXT: v_mul_lo_u32 v9, v3, v9
; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9
; GFX90A-NEXT: v_mul_hi_u32 v10, v3, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v11, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v3, v5
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v6, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v7, vcc
; GFX90A-NEXT: v_add_u32_e32 v1, v1, v4
; GFX90A-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[0:1]
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v4, v0, s2
; GFX90A-NEXT: v_mul_hi_u32 v5, v0, s0
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s0
; GFX90A-NEXT: v_add_u32_e32 v4, v5, v4
; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3
; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s0
; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_mul_lo_u32 v4, s6, v1 ; GFX90A-NEXT: v_mul_lo_u32 v4, s6, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0
; GFX90A-NEXT: v_mul_hi_u32 v3, s6, v1 ; GFX90A-NEXT: v_mul_hi_u32 v3, s6, v1
; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
; GFX90A-NEXT: v_mul_hi_u32 v6, s7, v0 ; GFX90A-NEXT: v_mul_hi_u32 v6, s7, v0
; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0
▲ Show 20 Lines • Show All 313 Lines • ▼ Show 20 Lines
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4 ; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: sdiv_i64_oddk_denom: ; GFX6-LABEL: sdiv_i64_oddk_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_mov_b32 s2, 0xffed2705 ; GFX6-NEXT: s_mov_b32 s5, 0xffed2705
; GFX6-NEXT: v_mov_b32_e32 v8, 0 ; GFX6-NEXT: v_mov_b32_e32 v8, 0
; GFX6-NEXT: v_mov_b32_e32 v7, 0 ; GFX6-NEXT: v_mov_b32_e32 v7, 0
; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s5
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s2 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s5
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s5
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, s8 ; GFX6-NEXT: s_ashr_i32 s8, s3, 31
; GFX6-NEXT: s_add_u32 s2, s2, s8
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX6-NEXT: v_mul_lo_u32 v4, v2, s2
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s2
; GFX6-NEXT: s_mov_b32 s5, s9
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_mul_lo_u32 v5, v0, s2
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4
; GFX6-NEXT: v_mul_lo_u32 v10, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v11, v0, v5
; GFX6-NEXT: v_mul_hi_u32 v12, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v9, v2, v5
; GFX6-NEXT: v_mul_lo_u32 v5, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v6, v2, v4
; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GFX6-NEXT: v_addc_u32_e32 v11, vcc, v8, v12, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v10, v5
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v11, v9, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: s_ashr_i32 s2, s11, 31
; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
; GFX6-NEXT: s_add_u32 s0, s10, s2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: s_mov_b32 s3, s2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: s_addc_u32 s1, s11, s2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s5
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s5
; GFX6-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3] ; GFX6-NEXT: s_mov_b32 s9, s8
; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1 ; GFX6-NEXT: s_addc_u32 s3, s3, s8
; GFX6-NEXT: v_mul_hi_u32 v3, s0, v0 ; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9]
; GFX6-NEXT: v_mul_hi_u32 v4, s0, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_hi_u32 v5, s1, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s5
; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GFX6-NEXT: v_mul_lo_u32 v6, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v0, v3
; GFX6-NEXT: v_mul_hi_u32 v10, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v2
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v9, v5, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: s_mov_b32 s3, 0x12d8fb ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX6-NEXT: v_mul_hi_u32 v4, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v5, s3, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: s_mov_b32 s0, 0x12d8fb
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s0
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s3 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, s0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v0
; GFX6-NEXT: v_mul_lo_u32 v8, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v8, v0, s0
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v0
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_mov_b32_e32 v5, s1 ; GFX6-NEXT: v_mov_b32_e32 v5, s3
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s0, v8 ; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s2, v8
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc ; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s3, v8 ; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s0, v8
; GFX6-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc ; GFX6-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
; GFX6-NEXT: s_mov_b32 s0, 0x12d8fa ; GFX6-NEXT: s_mov_b32 s0, 0x12d8fa
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v5 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GFX6-NEXT: s_mov_b32 s5, s1
; GFX6-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v8 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v8
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_cndmask_b32_e64 v4, -1, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, -1, v5, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0
; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s8, v1
; GFX6-NEXT: v_mov_b32_e32 v2, s2 ; GFX6-NEXT: v_mov_b32_e32 v2, s8
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_i64_oddk_denom: ; GFX9-LABEL: sdiv_i64_oddk_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_mov_b32 s8, 0xffed2705 ; GFX9-NEXT: s_mov_b32 s4, 0xffed2705
; GFX9-NEXT: v_mov_b32_e32 v7, 0 ; GFX9-NEXT: v_mov_b32_e32 v7, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s4
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s4
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s0, s7, 31
; GFX9-NEXT: s_mov_b32 s1, s0
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v4, v2, s8
; GFX9-NEXT: v_mul_hi_u32 v6, v0, s8
; GFX9-NEXT: v_mul_lo_u32 v8, v0, s8
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_add_u32_e32 v4, v6, v4
; GFX9-NEXT: v_sub_u32_e32 v4, v4, v0
; GFX9-NEXT: v_mul_lo_u32 v10, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v11, v0, v8
; GFX9-NEXT: v_mul_hi_u32 v12, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v9, v2, v8
; GFX9-NEXT: v_mul_lo_u32 v8, v2, v8
; GFX9-NEXT: v_mul_hi_u32 v6, v2, v4
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v7, v12, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
; GFX9-NEXT: s_add_u32 s2, s6, s0
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: s_addc_u32 s3, s7, s0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s4
; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1] ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s4
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s4, s3, 31
; GFX9-NEXT: s_add_u32 s2, s2, s4
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
; GFX9-NEXT: v_mul_lo_u32 v8, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v10, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v6, v1, v4
; GFX9-NEXT: v_mul_lo_u32 v4, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v7, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: s_mov_b32 s5, s4
; GFX9-NEXT: s_addc_u32 s3, s3, s4
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s2, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s2, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s2, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s3, v1 ; GFX9-NEXT: v_mul_hi_u32 v6, s3, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s3, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s3, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s3, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s3, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s3, v0
; GFX9-NEXT: s_mov_b32 s1, 0x12d8fb ; GFX9-NEXT: s_mov_b32 s5, 0x12d8fb
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s1 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s5
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s1 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s5
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s1 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s5
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s2, v4 ; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s2, v4
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s1, v4 ; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s5, v4
; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
; GFX9-NEXT: s_mov_b32 s1, 0x12d8fa ; GFX9-NEXT: s_mov_b32 s2, 0x12d8fa
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s1, v3 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s2, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX9-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 1, 2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 1, 2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s1, v4 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s2, v4
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, -1, v4, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s4, v0
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX90A-LABEL: sdiv_i64_oddk_denom: ; GFX90A-LABEL: sdiv_i64_oddk_denom:
; GFX90A: ; %bb.0: ; GFX90A: ; %bb.0:
; GFX90A-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GFX90A-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX90A-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
; GFX90A-NEXT: v_rcp_f32_e32 v0, v0 ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0
; GFX90A-NEXT: s_mov_b32 s2, 0xffed2705 ; GFX90A-NEXT: s_mov_b32 s4, 0xffed2705
; GFX90A-NEXT: v_mov_b32_e32 v8, 0 ; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX90A-NEXT: v_trunc_f32_e32 v1, v1 ; GFX90A-NEXT: v_trunc_f32_e32 v1, v1
; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s2 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s4
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s2 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s4
; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3
; GFX90A-NEXT: v_sub_u32_e32 v3, v3, v0 ; GFX90A-NEXT: v_sub_u32_e32 v3, v3, v0
; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s2 ; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s4
; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 ; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e64 v0, s[0:1], v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX90A-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[0:1] ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v5, v3, s2 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s4
; GFX90A-NEXT: v_mul_hi_u32 v6, v0, s2 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s4
; GFX90A-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3
; GFX90A-NEXT: v_sub_u32_e32 v5, v5, v0 ; GFX90A-NEXT: v_sub_u32_e32 v3, v3, v0
; GFX90A-NEXT: v_mul_lo_u32 v7, v0, s2 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, s4
; GFX90A-NEXT: v_mul_hi_u32 v9, v3, v7 ; GFX90A-NEXT: v_mul_hi_u32 v6, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v10, v3, v7 ; GFX90A-NEXT: v_mul_lo_u32 v7, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v12, v0, v5 ; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v3
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v7 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5
; GFX90A-NEXT: v_mul_hi_u32 v11, v0, v5 ; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v3
; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v12 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10
; GFX90A-NEXT: v_addc_co_u32_e32 v11, vcc, v8, v11, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, v8, v9, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v10 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7
; GFX90A-NEXT: v_mul_hi_u32 v6, v3, v5 ; GFX90A-NEXT: v_mul_hi_u32 v4, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v11, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v6, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v3, v5 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v6, vcc
; GFX90A-NEXT: v_add_u32_e32 v1, v1, v4
; GFX90A-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[0:1]
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_ashr_i32 s0, s7, 31 ; GFX90A-NEXT: s_ashr_i32 s4, s3, 31
; GFX90A-NEXT: s_add_u32 s2, s6, s0 ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX90A-NEXT: s_add_u32 s2, s2, s4
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX90A-NEXT: s_mov_b32 s1, s0 ; GFX90A-NEXT: s_mov_b32 s5, s4
; GFX90A-NEXT: s_addc_u32 s3, s7, s0 ; GFX90A-NEXT: s_addc_u32 s3, s3, s4
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX90A-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1] ; GFX90A-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
; GFX90A-NEXT: v_mul_lo_u32 v4, s2, v1 ; GFX90A-NEXT: v_mul_lo_u32 v4, s2, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s2, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s2, v0
; GFX90A-NEXT: v_mul_hi_u32 v3, s2, v1 ; GFX90A-NEXT: v_mul_hi_u32 v3, s2, v1
; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
; GFX90A-NEXT: v_mul_hi_u32 v6, s3, v0 ; GFX90A-NEXT: v_mul_hi_u32 v6, s3, v0
; GFX90A-NEXT: v_mul_lo_u32 v0, s3, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s3, v0
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0
; GFX90A-NEXT: v_mul_hi_u32 v5, s3, v1 ; GFX90A-NEXT: v_mul_hi_u32 v5, s3, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v6, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX90A-NEXT: v_mul_lo_u32 v1, s3, v1
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v3, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v3, vcc
; GFX90A-NEXT: s_mov_b32 s1, 0x12d8fb ; GFX90A-NEXT: s_mov_b32 s5, 0x12d8fb
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s1 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s5
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s1 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s5
; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3
; GFX90A-NEXT: v_mul_lo_u32 v4, v0, s1 ; GFX90A-NEXT: v_mul_lo_u32 v4, v0, s5
; GFX90A-NEXT: v_mov_b32_e32 v5, s3 ; GFX90A-NEXT: v_mov_b32_e32 v5, s3
; GFX90A-NEXT: v_sub_co_u32_e32 v4, vcc, s2, v4 ; GFX90A-NEXT: v_sub_co_u32_e32 v4, vcc, s2, v4
; GFX90A-NEXT: v_subb_co_u32_e32 v3, vcc, v5, v3, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v3, vcc, v5, v3, vcc
; GFX90A-NEXT: v_subrev_co_u32_e32 v5, vcc, s1, v4 ; GFX90A-NEXT: v_subrev_co_u32_e32 v5, vcc, s5, v4
; GFX90A-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc ; GFX90A-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc
; GFX90A-NEXT: s_mov_b32 s1, 0x12d8fa ; GFX90A-NEXT: s_mov_b32 s2, 0x12d8fa
; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s1, v5 ; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s2, v5
; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX90A-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX90A-NEXT: v_cndmask_b32_e64 v5, 1, 2, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v5, 1, 2, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v0, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v0, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc
; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s1, v4 ; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s2, v4
; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v3, -1, v4, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v3, -1, v4, vcc
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; GFX90A-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX90A-NEXT: v_xor_b32_e32 v0, s4, v0
; GFX90A-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX90A-NEXT: v_xor_b32_e32 v1, s4, v1
; GFX90A-NEXT: v_mov_b32_e32 v3, s0 ; GFX90A-NEXT: v_mov_b32_e32 v3, s4
; GFX90A-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0 ; GFX90A-NEXT: v_subrev_co_u32_e32 v0, vcc, s4, v0
; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
%r = sdiv i64 %x, 1235195 %r = sdiv i64 %x, 1235195
store i64 %r, i64 addrspace(1)* %out store i64 %r, i64 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @sdiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @sdiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
; CHECK-LABEL: @sdiv_i64_pow2k_denom( ; CHECK-LABEL: @sdiv_i64_pow2k_denom(
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]] ; CHECK-NEXT: [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = sdiv i64 [[X:%.*]], [[SHL_Y]] ; CHECK-NEXT: [[R:%.*]] = sdiv i64 [[X:%.*]], [[SHL_Y]]
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4 ; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: sdiv_i64_pow2_shl_denom: ; GFX6-LABEL: sdiv_i64_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s4, s[0:1], 0xd ; GFX6-NEXT: s_load_dword s4, s[0:1], 0xd
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
; GFX6-NEXT: s_mov_b64 s[2:3], 0x1000 ; GFX6-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b64 s[4:5], s[2:3], s4 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
; GFX6-NEXT: s_ashr_i32 s2, s5, 31 ; GFX6-NEXT: s_ashr_i32 s8, s3, 31
; GFX6-NEXT: s_add_u32 s4, s4, s2 ; GFX6-NEXT: s_add_u32 s2, s2, s8
; GFX6-NEXT: s_mov_b32 s3, s2 ; GFX6-NEXT: s_mov_b32 s9, s8
; GFX6-NEXT: s_addc_u32 s5, s5, s2 ; GFX6-NEXT: s_addc_u32 s3, s3, s8
; GFX6-NEXT: s_xor_b64 s[12:13], s[4:5], s[2:3] ; GFX6-NEXT: s_xor_b64 s[10:11], s[2:3], s[8:9]
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s10
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s13 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s11
; GFX6-NEXT: s_sub_u32 s4, 0, s12 ; GFX6-NEXT: s_sub_u32 s4, 0, s10
; GFX6-NEXT: s_subb_u32 s5, 0, s13 ; GFX6-NEXT: s_subb_u32 s5, 0, s11
; GFX6-NEXT: s_ashr_i32 s14, s11, 31 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_mov_b32 s15, s14 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_ashr_i32 s12, s3, 31
; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_add_u32 s2, s2, s12
; GFX6-NEXT: s_mov_b32 s13, s12
; GFX6-NEXT: v_mul_lo_u32 v2, s4, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, s4, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s4, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s4, v0
; GFX6-NEXT: v_mul_lo_u32 v5, s5, v0 ; GFX6-NEXT: v_mul_lo_u32 v5, s5, v0
; GFX6-NEXT: v_mul_lo_u32 v4, s4, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s4, v0
; GFX6-NEXT: s_addc_u32 s3, s3, s12
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13]
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
; GFX6-NEXT: v_mov_b32_e32 v4, 0 ; GFX6-NEXT: v_mov_b32_e32 v4, 0
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
; GFX6-NEXT: v_mov_b32_e32 v6, 0 ; GFX6-NEXT: v_mov_b32_e32 v6, 0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX6-NEXT: v_mul_lo_u32 v5, s4, v2
; GFX6-NEXT: v_mul_hi_u32 v7, s4, v0
; GFX6-NEXT: v_mul_lo_u32 v8, s5, v0
; GFX6-NEXT: s_mov_b32 s5, s9
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GFX6-NEXT: v_mul_lo_u32 v7, s4, v0
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GFX6-NEXT: v_mul_lo_u32 v10, v0, v5
; GFX6-NEXT: v_mul_hi_u32 v11, v0, v7
; GFX6-NEXT: v_mul_hi_u32 v12, v0, v5
; GFX6-NEXT: v_mul_hi_u32 v9, v2, v7
; GFX6-NEXT: v_mul_lo_u32 v7, v2, v7
; GFX6-NEXT: v_mul_hi_u32 v8, v2, v5
; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v5
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
; GFX6-NEXT: s_add_u32 s0, s10, s14
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: s_addc_u32 s1, s11, s14 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s4, v1
; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15] ; GFX6-NEXT: v_mul_hi_u32 v3, s4, v0
; GFX6-NEXT: v_mul_lo_u32 v2, s10, v1 ; GFX6-NEXT: v_mul_lo_u32 v5, s5, v0
; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0 ; GFX6-NEXT: s_mov_b32 s5, s1
; GFX6-NEXT: v_mul_hi_u32 v5, s10, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_hi_u32 v7, s11, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, s4, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GFX6-NEXT: v_mul_lo_u32 v8, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v0, v3
; GFX6-NEXT: v_mul_hi_u32 v10, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v5, v1, v2
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v8, v3
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v9, v7, vcc
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX6-NEXT: v_mul_hi_u32 v5, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v7, s3, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0 ; GFX6-NEXT: v_mul_lo_u32 v5, s3, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
; GFX6-NEXT: s_mov_b32 s4, s8 ; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s12, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, s10, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s12, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0
; GFX6-NEXT: v_mul_lo_u32 v4, s13, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s11, v0
; GFX6-NEXT: v_mov_b32_e32 v5, s13 ; GFX6-NEXT: v_mov_b32_e32 v5, s11
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_lo_u32 v3, s12, v0 ; GFX6-NEXT: v_mul_lo_u32 v3, s10, v0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s11, v2 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s3, v2
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s10, v3 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s2, v3
; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc ; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s12, v3 ; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s10, v3
; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v4 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v4
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v5 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v4 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v4
; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 ; GFX6-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0
; GFX6-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 ; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0
; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v6, s11 ; GFX6-NEXT: v_mov_b32_e32 v6, s3
; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s11, v2
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v3 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s13, v2 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s11, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: s_xor_b64 s[0:1], s[14:15], s[2:3] ; GFX6-NEXT: s_xor_b64 s[0:1], s[12:13], s[8:9]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX6-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX6-NEXT: v_mov_b32_e32 v2, s1 ; GFX6-NEXT: v_mov_b32_e32 v2, s1
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: sdiv_i64_pow2_shl_denom: ; GFX9-LABEL: sdiv_i64_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x34 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x34
; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000 ; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 ; GFX9-NEXT: s_lshl_b64 s[4:5], s[2:3], s4
; GFX9-NEXT: s_ashr_i32 s8, s3, 31 ; GFX9-NEXT: s_ashr_i32 s2, s5, 31
; GFX9-NEXT: s_add_u32 s2, s2, s8 ; GFX9-NEXT: s_add_u32 s4, s4, s2
; GFX9-NEXT: s_mov_b32 s9, s8 ; GFX9-NEXT: s_mov_b32 s3, s2
; GFX9-NEXT: s_addc_u32 s3, s3, s8 ; GFX9-NEXT: s_addc_u32 s5, s5, s2
; GFX9-NEXT: s_xor_b64 s[10:11], s[2:3], s[8:9] ; GFX9-NEXT: s_xor_b64 s[8:9], s[4:5], s[2:3]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s10 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s11 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX9-NEXT: s_sub_u32 s12, 0, s10 ; GFX9-NEXT: s_sub_u32 s10, 0, s8
; GFX9-NEXT: s_subb_u32 s4, 0, s11 ; GFX9-NEXT: s_subb_u32 s4, 0, s9
; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s12, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s12, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s10, v0
; GFX9-NEXT: v_mul_lo_u32 v6, s4, v0 ; GFX9-NEXT: v_mul_lo_u32 v6, s4, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s12, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s10, v0
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_add_u32_e32 v3, v3, v6 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v6
; GFX9-NEXT: v_mul_hi_u32 v4, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v5
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v3 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v3 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v7, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v7, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, s12, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s12, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s10, v0
; GFX9-NEXT: v_mul_lo_u32 v8, s4, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s4, v0
; GFX9-NEXT: v_mul_lo_u32 v9, s12, v0 ; GFX9-NEXT: v_mul_lo_u32 v7, s10, v0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_add_u32_e32 v5, v7, v5 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_add_u32_e32 v5, v5, v8 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
; GFX9-NEXT: v_mul_lo_u32 v10, v0, v5 ; GFX9-NEXT: v_mul_lo_u32 v8, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v11, v0, v9 ; GFX9-NEXT: v_mul_hi_u32 v9, v0, v7
; GFX9-NEXT: v_mul_hi_u32 v12, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v10, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v8, v3, v9 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v7
; GFX9-NEXT: v_mul_lo_u32 v9, v3, v9 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v7
; GFX9-NEXT: v_mul_hi_u32 v7, v3, v5 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v3, v5 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s2, s7, 31 ; GFX9-NEXT: s_ashr_i32 s10, s7, 31
; GFX9-NEXT: s_add_u32 s0, s6, s2 ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc
; GFX9-NEXT: s_add_u32 s0, s6, s10
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: s_mov_b32 s3, s2 ; GFX9-NEXT: s_mov_b32 s11, s10
; GFX9-NEXT: s_addc_u32 s1, s7, s2 ; GFX9-NEXT: s_addc_u32 s1, s7, s10
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[2:3] ; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11]
; GFX9-NEXT: v_mul_lo_u32 v3, s6, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v4, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s10, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s8, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s11, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s9, v0
; GFX9-NEXT: v_mov_b32_e32 v6, s11 ; GFX9-NEXT: v_mov_b32_e32 v6, s9
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_mul_lo_u32 v4, s10, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s8, v0
; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
; GFX9-NEXT: v_sub_u32_e32 v5, s7, v3 ; GFX9-NEXT: v_sub_u32_e32 v5, s7, v3
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s6, v4 ; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s6, v4
; GFX9-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc ; GFX9-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s10, v4 ; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s8, v4
; GFX9-NEXT: v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1] ; GFX9-NEXT: v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v5 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v5
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v6 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v6
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v5 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v5
; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1]
; GFX9-NEXT: v_mov_b32_e32 v7, s7 ; GFX9-NEXT: v_mov_b32_e32 v7, s7
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v7, v3, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v7, v3, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v4
; GFX9-NEXT: v_cndmask_b32_e64 v5, 1, 2, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v5, 1, 2, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v3 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v0, v5 ; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v0, v5
; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], 0, v1, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], 0, v1, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX9-NEXT: s_xor_b64 s[0:1], s[2:3], s[8:9] ; GFX9-NEXT: s_xor_b64 s[0:1], s[10:11], s[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX90A-LABEL: sdiv_i64_pow2_shl_denom: ; GFX90A-LABEL: sdiv_i64_pow2_shl_denom:
; GFX90A: ; %bb.0: ; GFX90A: ; %bb.0:
; GFX90A-NEXT: s_load_dword s4, s[0:1], 0x34 ; GFX90A-NEXT: s_load_dword s4, s[0:1], 0x34
; GFX90A-NEXT: s_mov_b64 s[2:3], 0x1000 ; GFX90A-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_lshl_b64 s[4:5], s[2:3], s4 ; GFX90A-NEXT: s_lshl_b64 s[4:5], s[2:3], s4
; GFX90A-NEXT: s_ashr_i32 s2, s5, 31 ; GFX90A-NEXT: s_ashr_i32 s2, s5, 31
; GFX90A-NEXT: s_add_u32 s4, s4, s2 ; GFX90A-NEXT: s_add_u32 s4, s4, s2
; GFX90A-NEXT: s_mov_b32 s3, s2 ; GFX90A-NEXT: s_mov_b32 s3, s2
; GFX90A-NEXT: s_addc_u32 s5, s5, s2 ; GFX90A-NEXT: s_addc_u32 s5, s5, s2
; GFX90A-NEXT: s_xor_b64 s[8:9], s[4:5], s[2:3] ; GFX90A-NEXT: s_xor_b64 s[8:9], s[4:5], s[2:3]
; GFX90A-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX90A-NEXT: s_sub_u32 s10, 0, s8
; GFX90A-NEXT: s_subb_u32 s11, 0, s9
; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX90A-NEXT: s_sub_u32 s0, 0, s8
; GFX90A-NEXT: s_subb_u32 s1, 0, s9
; GFX90A-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GFX90A-NEXT: v_rcp_f32_e32 v0, v0 ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_ashr_i32 s10, s7, 31
; GFX90A-NEXT: s_mov_b32 s11, s10
; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX90A-NEXT: v_trunc_f32_e32 v1, v1 ; GFX90A-NEXT: v_trunc_f32_e32 v1, v1
; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX90A-NEXT: v_mul_lo_u32 v3, s10, v1 ; GFX90A-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s10, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s0, v0
; GFX90A-NEXT: v_mul_lo_u32 v4, s11, v0 ; GFX90A-NEXT: v_mul_lo_u32 v4, s1, v0
; GFX90A-NEXT: v_add_u32_e32 v3, v5, v3 ; GFX90A-NEXT: v_add_u32_e32 v3, v5, v3
; GFX90A-NEXT: v_mul_lo_u32 v6, s10, v0 ; GFX90A-NEXT: v_mul_lo_u32 v6, s0, v0
; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4 ; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4
; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6 ; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX90A-NEXT: v_mov_b32_e32 v6, 0 ; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e64 v0, s[0:1], v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX90A-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[0:1] ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v5, s10, v3 ; GFX90A-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX90A-NEXT: v_mul_hi_u32 v7, s10, v0 ; GFX90A-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3
; GFX90A-NEXT: v_mul_lo_u32 v7, s11, v0 ; GFX90A-NEXT: v_mul_lo_u32 v4, s1, v0
; GFX90A-NEXT: v_add_u32_e32 v5, v5, v7 ; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4
; GFX90A-NEXT: v_mul_lo_u32 v8, s10, v0 ; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX90A-NEXT: v_mul_hi_u32 v9, v3, v8 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v10, v3, v8 ; GFX90A-NEXT: v_mul_lo_u32 v8, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v12, v0, v5 ; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v3
; GFX90A-NEXT: v_mul_hi_u32 v8, v0, v8 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5
; GFX90A-NEXT: v_mul_hi_u32 v11, v0, v5 ; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v3
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10
; GFX90A-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8
; GFX90A-NEXT: v_mul_hi_u32 v7, v3, v5 ; GFX90A-NEXT: v_mul_hi_u32 v4, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v7, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v3, v5 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v7, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc
; GFX90A-NEXT: v_add_u32_e32 v1, v1, v4
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_ashr_i32 s10, s7, 31
; GFX90A-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[0:1]
; GFX90A-NEXT: s_add_u32 s0, s6, s10 ; GFX90A-NEXT: s_add_u32 s0, s6, s10
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX90A-NEXT: s_mov_b32 s11, s10
; GFX90A-NEXT: s_addc_u32 s1, s7, s10 ; GFX90A-NEXT: s_addc_u32 s1, s7, s10
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX90A-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11] ; GFX90A-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11]
; GFX90A-NEXT: v_mul_lo_u32 v4, s6, v1 ; GFX90A-NEXT: v_mul_lo_u32 v4, s6, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0
; GFX90A-NEXT: v_mul_hi_u32 v3, s6, v1 ; GFX90A-NEXT: v_mul_hi_u32 v3, s6, v1
; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX90A-NEXT: v_mul_hi_u32 v7, s7, v0 ; GFX90A-NEXT: v_mul_hi_u32 v7, s7, v0
; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
; GFX6-LABEL: ssdiv_v2i64_mixed_pow2k_denom: ; GFX6-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v0, 0x457ff000 ; GFX6-NEXT: v_mov_b32_e32 v0, 0x457ff000
; GFX6-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX6-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GFX6-NEXT: v_mac_f32_e32 v0, 0, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0, v1
; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_movk_i32 s6, 0xf001 ; GFX6-NEXT: s_movk_i32 s6, 0xf001
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_ashr_i32 s0, s9, 31 ; GFX6-NEXT: s_ashr_i32 s8, s1, 31
; GFX6-NEXT: s_lshr_b32 s0, s0, 20 ; GFX6-NEXT: s_lshr_b32 s8, s8, 20
; GFX6-NEXT: v_mul_hi_u32 v2, v0, s6 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, s6
; GFX6-NEXT: v_mul_lo_u32 v3, v1, s6 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, s6
; GFX6-NEXT: s_add_u32 s2, s8, s0 ; GFX6-NEXT: s_add_u32 s0, s0, s8
; GFX6-NEXT: s_addc_u32 s3, s9, 0 ; GFX6-NEXT: s_addc_u32 s1, s1, 0
; GFX6-NEXT: s_ashr_i64 s[2:3], s[2:3], 12 ; GFX6-NEXT: s_ashr_i64 s[8:9], s[0:1], 12
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v0, s6 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s6
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: s_ashr_i32 s8, s11, 31 ; GFX6-NEXT: s_ashr_i32 s10, s3, 31
; GFX6-NEXT: s_mov_b32 s9, s8 ; GFX6-NEXT: s_add_u32 s0, s2, s10
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; GFX6-NEXT: v_mov_b32_e32 v4, 0 ; GFX6-NEXT: v_mov_b32_e32 v4, 0
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
; GFX6-NEXT: v_mov_b32_e32 v6, 0 ; GFX6-NEXT: v_mov_b32_e32 v6, 0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX6-NEXT: v_mul_lo_u32 v5, v2, s6
; GFX6-NEXT: v_mul_hi_u32 v7, v0, s6
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GFX6-NEXT: v_mul_lo_u32 v7, v0, s6
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5
; GFX6-NEXT: v_mul_lo_u32 v10, v0, v5
; GFX6-NEXT: v_mul_hi_u32 v11, v0, v7
; GFX6-NEXT: v_mul_hi_u32 v12, v0, v5
; GFX6-NEXT: v_mul_hi_u32 v9, v2, v7
; GFX6-NEXT: v_mul_lo_u32 v7, v2, v7
; GFX6-NEXT: v_mul_hi_u32 v8, v2, v5
; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v5
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
; GFX6-NEXT: s_add_u32 s0, s10, s8
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: s_addc_u32 s1, s11, s8 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s6
; GFX6-NEXT: s_xor_b64 s[0:1], s[0:1], s[8:9] ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s6
; GFX6-NEXT: s_mov_b32 s11, s10
; GFX6-NEXT: s_addc_u32 s1, s3, s10
; GFX6-NEXT: s_xor_b64 s[0:1], s[0:1], s[10:11]
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_lo_u32 v3, v0, s6
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GFX6-NEXT: v_mul_lo_u32 v8, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v0, v3
; GFX6-NEXT: v_mul_hi_u32 v10, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v5, v1, v2
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v8, v3
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v9, v7, vcc
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s0, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s0, v0
; GFX6-NEXT: v_mul_hi_u32 v5, s0, v1 ; GFX6-NEXT: v_mul_hi_u32 v5, s0, v1
; GFX6-NEXT: v_mul_hi_u32 v7, s1, v1 ; GFX6-NEXT: v_mul_hi_u32 v7, s1, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s1, v0 ; GFX6-NEXT: v_mul_lo_u32 v5, s1, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0
; GFX6-NEXT: s_movk_i32 s9, 0xfff ; GFX6-NEXT: s_movk_i32 s2, 0xfff
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v1, s9 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s2
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s9 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, s2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v0
; GFX6-NEXT: v_mul_lo_u32 v8, v0, s9 ; GFX6-NEXT: v_mul_lo_u32 v8, v0, s2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v0 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, 1, v0
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_mov_b32_e32 v5, s1 ; GFX6-NEXT: v_mov_b32_e32 v5, s1
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s0, v8 ; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s0, v8
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc ; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s9, v8 ; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s2, v8
; GFX6-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc ; GFX6-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
; GFX6-NEXT: s_movk_i32 s0, 0xffe ; GFX6-NEXT: s_movk_i32 s0, 0xffe
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v5 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GFX6-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v8 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v8
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_cndmask_b32_e64 v4, -1, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, -1, v5, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s10, v0
; GFX6-NEXT: v_xor_b32_e32 v1, s8, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s10, v1
; GFX6-NEXT: v_mov_b32_e32 v3, s8 ; GFX6-NEXT: v_mov_b32_e32 v3, s10
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s10, v0
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc ; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
; GFX6-NEXT: v_mov_b32_e32 v0, s2 ; GFX6-NEXT: v_mov_b32_e32 v0, s8
; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v1, s9
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: ssdiv_v2i64_mixed_pow2k_denom: ; GFX9-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0x457ff000 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x457ff000
; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GFX9-NEXT: v_mac_f32_e32 v0, 0, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0, v1
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_movk_i32 s8, 0xf001 ; GFX9-NEXT: s_movk_i32 s8, 0xf001
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s2, s5, 31 ; GFX9-NEXT: s_ashr_i32 s2, s5, 31
; GFX9-NEXT: s_lshr_b32 s2, s2, 20 ; GFX9-NEXT: s_lshr_b32 s2, s2, 20
; GFX9-NEXT: v_mul_hi_u32 v2, v0, s8 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, s8
; GFX9-NEXT: v_mul_lo_u32 v3, v1, s8 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, s8
; GFX9-NEXT: v_mul_lo_u32 v5, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v5, v0, s8
; GFX9-NEXT: s_add_u32 s4, s4, s2 ; GFX9-NEXT: s_add_u32 s2, s4, s2
; GFX9-NEXT: s_addc_u32 s5, s5, 0 ; GFX9-NEXT: s_addc_u32 s3, s5, 0
; GFX9-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v6, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v6, v3
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v7, v1, v5
; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5
; GFX9-NEXT: s_ashr_i64 s[4:5], s[4:5], 12 ; GFX9-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_ashr_i32 s4, s7, 31
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v5, v2, s8
; GFX9-NEXT: v_mul_hi_u32 v7, v0, s8
; GFX9-NEXT: v_mul_lo_u32 v8, v0, s8
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_add_u32_e32 v5, v7, v5
; GFX9-NEXT: v_sub_u32_e32 v5, v5, v0
; GFX9-NEXT: v_mul_lo_u32 v10, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v11, v0, v8
; GFX9-NEXT: v_mul_hi_u32 v12, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v9, v2, v8
; GFX9-NEXT: v_mul_lo_u32 v8, v2, v8
; GFX9-NEXT: v_mul_hi_u32 v7, v2, v5
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v2, v5
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
; GFX9-NEXT: s_ashr_i32 s2, s7, 31
; GFX9-NEXT: s_add_u32 s6, s6, s2
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: s_mov_b32 s3, s2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: s_addc_u32 s7, s7, s2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3] ; GFX9-NEXT: v_mul_lo_u32 v5, v0, s8
; GFX9-NEXT: s_add_u32 s6, s6, s4
; GFX9-NEXT: s_mov_b32 s5, s4
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
; GFX9-NEXT: v_mul_lo_u32 v8, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v10, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v7, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v8, v5
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v7, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: s_addc_u32 s7, s7, s4
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0
; GFX9-NEXT: s_movk_i32 s3, 0xfff ; GFX9-NEXT: s_movk_i32 s5, 0xfff
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s3 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s5
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s5
; GFX9-NEXT: v_mul_lo_u32 v5, v0, s3 ; GFX9-NEXT: v_mul_lo_u32 v5, v0, s5
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s7 ; GFX9-NEXT: v_mov_b32_e32 v3, s7
; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, s6, v5 ; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, s6, v5
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s3, v5 ; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s5, v5
; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
; GFX9-NEXT: s_movk_i32 s3, 0xffe ; GFX9-NEXT: s_movk_i32 s5, 0xffe
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v3 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s5, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX9-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_cndmask_b32_e64 v3, 1, 2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v3, 1, 2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v5 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s5, v5
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, -1, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, -1, v5, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s2, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s2 ; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s2, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s4, v0
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] ; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX90A-LABEL: ssdiv_v2i64_mixed_pow2k_denom: ; GFX90A-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
; GFX90A: ; %bb.0: ; GFX90A: ; %bb.0:
; GFX90A-NEXT: v_mov_b32_e32 v0, 0x457ff000 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0x457ff000
; GFX90A-NEXT: v_mov_b32_e32 v1, 0x4f800000 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x4f800000
; GFX90A-NEXT: v_mac_f32_e32 v0, 0, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0, v1
; GFX90A-NEXT: v_rcp_f32_e32 v0, v0 ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0
; GFX90A-NEXT: s_movk_i32 s8, 0xf001
; GFX90A-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX90A-NEXT: v_mov_b32_e32 v4, 0 ; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX90A-NEXT: v_trunc_f32_e32 v1, v1 ; GFX90A-NEXT: v_trunc_f32_e32 v1, v1
; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_ashr_i32 s0, s5, 31 ; GFX90A-NEXT: s_ashr_i32 s0, s5, 31
; GFX90A-NEXT: s_lshr_b32 s0, s0, 20 ; GFX90A-NEXT: s_lshr_b32 s0, s0, 20
; GFX90A-NEXT: v_mul_hi_u32 v2, v0, s8 ; GFX90A-NEXT: s_add_u32 s0, s4, s0
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s8 ; GFX90A-NEXT: s_movk_i32 s4, 0xf001
; GFX90A-NEXT: v_mul_hi_u32 v2, v0, s4
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s4
; GFX90A-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX90A-NEXT: v_add_u32_e32 v2, v2, v3
; GFX90A-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX90A-NEXT: v_sub_u32_e32 v2, v2, v0
; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s8 ; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s4
; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v3, v0, v2 ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, v2
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6 ; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v2 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc
; GFX90A-NEXT: s_add_u32 s0, s4, s0
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX90A-NEXT: s_addc_u32 s1, s5, 0
; GFX90A-NEXT: v_mov_b32_e32 v6, 0 ; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX90A-NEXT: s_ashr_i64 s[4:5], s[0:1], 12
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e64 v0, s[0:1], v0, v2
; GFX90A-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX90A-NEXT: v_mul_lo_u32 v5, v2, s8
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, s8
; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5
; GFX90A-NEXT: v_sub_u32_e32 v5, v5, v0
; GFX90A-NEXT: v_mul_lo_u32 v8, v0, s8
; GFX90A-NEXT: v_mul_hi_u32 v9, v2, v8
; GFX90A-NEXT: v_mul_lo_u32 v10, v2, v8
; GFX90A-NEXT: v_mul_lo_u32 v12, v0, v5
; GFX90A-NEXT: v_mul_hi_u32 v8, v0, v8
; GFX90A-NEXT: v_mul_hi_u32 v11, v0, v5
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12
; GFX90A-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10
; GFX90A-NEXT: v_mul_hi_u32 v7, v2, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v2, v2, v5
; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v7, vcc
; GFX90A-NEXT: v_add_u32_e32 v1, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[0:1]
; GFX90A-NEXT: s_ashr_i32 s0, s7, 31
; GFX90A-NEXT: s_add_u32 s6, s6, s0
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX90A-NEXT: s_mov_b32 s1, s0 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX90A-NEXT: s_addc_u32 s7, s7, s0 ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, s4
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, s4
; GFX90A-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1] ; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2
; GFX90A-NEXT: v_sub_u32_e32 v2, v2, v0
; GFX90A-NEXT: v_mul_lo_u32 v5, v0, s4
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v8, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v2
; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5
; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v2
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10
; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8
; GFX90A-NEXT: v_mul_hi_u32 v3, v1, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v7, vcc
; GFX90A-NEXT: s_addc_u32 s1, s5, 0
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX90A-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v5, v2
; GFX90A-NEXT: s_ashr_i32 s4, s7, 31
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
; GFX90A-NEXT: s_add_u32 s6, s6, s4
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX90A-NEXT: s_mov_b32 s5, s4
; GFX90A-NEXT: s_addc_u32 s7, s7, s4
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX90A-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5]
; GFX90A-NEXT: v_mul_lo_u32 v3, s6, v1 ; GFX90A-NEXT: v_mul_lo_u32 v3, s6, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0
; GFX90A-NEXT: v_mul_hi_u32 v2, s6, v1 ; GFX90A-NEXT: v_mul_hi_u32 v2, s6, v1
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX90A-NEXT: v_mul_hi_u32 v7, s7, v0 ; GFX90A-NEXT: v_mul_hi_u32 v7, s7, v0
; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0
; GFX90A-NEXT: v_mul_hi_u32 v5, s7, v1 ; GFX90A-NEXT: v_mul_hi_u32 v5, s7, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v2, v7, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v2, v7, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX90A-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
; GFX90A-NEXT: s_movk_i32 s1, 0xfff ; GFX90A-NEXT: s_movk_i32 s5, 0xfff
; GFX90A-NEXT: v_mul_lo_u32 v2, v1, s1 ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, s5
; GFX90A-NEXT: v_mul_hi_u32 v3, v0, s1 ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, s5
; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2
; GFX90A-NEXT: v_mul_lo_u32 v3, v0, s1 ; GFX90A-NEXT: v_mul_lo_u32 v3, v0, s5
; GFX90A-NEXT: v_mov_b32_e32 v5, s7 ; GFX90A-NEXT: v_mov_b32_e32 v5, s7
; GFX90A-NEXT: v_sub_co_u32_e32 v3, vcc, s6, v3 ; GFX90A-NEXT: v_sub_co_u32_e32 v3, vcc, s6, v3
; GFX90A-NEXT: v_subb_co_u32_e32 v2, vcc, v5, v2, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v2, vcc, v5, v2, vcc
; GFX90A-NEXT: v_subrev_co_u32_e32 v5, vcc, s1, v3 ; GFX90A-NEXT: v_subrev_co_u32_e32 v5, vcc, s5, v3
; GFX90A-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc ; GFX90A-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
; GFX90A-NEXT: s_movk_i32 s1, 0xffe ; GFX90A-NEXT: s_movk_i32 s5, 0xffe
; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s1, v5 ; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s5, v5
; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
; GFX90A-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX90A-NEXT: v_cndmask_b32_e64 v5, 1, 2, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v5, 1, 2, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v0, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v0, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v1, vcc
; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s1, v3 ; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s5, v3
; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX90A-NEXT: v_cndmask_b32_e32 v2, -1, v3, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v2, -1, v3, vcc
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; GFX90A-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX90A-NEXT: v_xor_b32_e32 v0, s4, v0
; GFX90A-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX90A-NEXT: v_xor_b32_e32 v1, s4, v1
; GFX90A-NEXT: v_mov_b32_e32 v3, s0 ; GFX90A-NEXT: v_mov_b32_e32 v3, s4
; GFX90A-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v0 ; GFX90A-NEXT: v_subrev_co_u32_e32 v2, vcc, s4, v0
; GFX90A-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
; GFX90A-NEXT: v_mov_b32_e32 v0, s4 ; GFX90A-NEXT: v_mov_b32_e32 v0, s0
; GFX90A-NEXT: v_mov_b32_e32 v1, s5 ; GFX90A-NEXT: v_mov_b32_e32 v1, s1
; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
%r = sdiv <2 x i64> %x, <i64 4096, i64 4095> %r = sdiv <2 x i64> %x, <i64 4096, i64 4095>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
Show All 13 Lines
; GFX6-LABEL: sdiv_v2i64_pow2_shl_denom: ; GFX6-LABEL: sdiv_v2i64_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11
; GFX6-NEXT: s_mov_b64 s[2:3], 0x1000 ; GFX6-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX6-NEXT: s_mov_b32 s18, 0x4f800000 ; GFX6-NEXT: s_mov_b32 s18, 0x4f800000
; GFX6-NEXT: s_mov_b32 s19, 0x5f7ffffc ; GFX6-NEXT: s_mov_b32 s19, 0x5f7ffffc
; GFX6-NEXT: s_mov_b32 s20, 0x2f800000 ; GFX6-NEXT: s_mov_b32 s20, 0x2f800000
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b64 s[12:13], s[2:3], s6 ; GFX6-NEXT: s_lshl_b64 s[8:9], s[2:3], s6
; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
; GFX6-NEXT: s_ashr_i32 s16, s3, 31 ; GFX6-NEXT: s_ashr_i32 s12, s3, 31
; GFX6-NEXT: s_add_u32 s2, s2, s16 ; GFX6-NEXT: s_add_u32 s2, s2, s12
; GFX6-NEXT: s_mov_b32 s17, s16 ; GFX6-NEXT: s_mov_b32 s13, s12
; GFX6-NEXT: s_addc_u32 s3, s3, s16 ; GFX6-NEXT: s_addc_u32 s3, s3, s12
; GFX6-NEXT: s_xor_b64 s[14:15], s[2:3], s[16:17] ; GFX6-NEXT: s_xor_b64 s[10:11], s[2:3], s[12:13]
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s14 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s10
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s15 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s11
; GFX6-NEXT: s_mov_b32 s21, 0xcf800000 ; GFX6-NEXT: s_mov_b32 s21, 0xcf800000
; GFX6-NEXT: s_sub_u32 s6, 0, s14 ; GFX6-NEXT: s_sub_u32 s6, 0, s10
; GFX6-NEXT: s_subb_u32 s7, 0, s15 ; GFX6-NEXT: s_subb_u32 s7, 0, s11
; GFX6-NEXT: v_mac_f32_e32 v0, s18, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, s18, v1
; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
; GFX6-NEXT: v_mul_f32_e32 v0, s19, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, s19, v0
; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_ashr_i32 s14, s1, 31
; GFX6-NEXT: s_add_u32 s0, s0, s14
; GFX6-NEXT: v_mul_lo_u32 v0, s6, v2 ; GFX6-NEXT: v_mul_lo_u32 v0, s6, v2
; GFX6-NEXT: v_mul_hi_u32 v1, s6, v3 ; GFX6-NEXT: v_mul_hi_u32 v1, s6, v3
; GFX6-NEXT: v_mul_lo_u32 v4, s7, v3 ; GFX6-NEXT: v_mul_lo_u32 v4, s7, v3
; GFX6-NEXT: v_mul_lo_u32 v5, s6, v3 ; GFX6-NEXT: v_mul_lo_u32 v5, s6, v3
; GFX6-NEXT: s_mov_b32 s15, s14
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v4 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v4
; GFX6-NEXT: v_mul_lo_u32 v0, v3, v1 ; GFX6-NEXT: v_mul_lo_u32 v0, v3, v1
; GFX6-NEXT: v_mul_hi_u32 v4, v3, v5 ; GFX6-NEXT: v_mul_hi_u32 v4, v3, v5
; GFX6-NEXT: v_mul_hi_u32 v6, v3, v1 ; GFX6-NEXT: v_mul_hi_u32 v6, v3, v1
; GFX6-NEXT: v_mul_hi_u32 v7, v2, v1 ; GFX6-NEXT: v_mul_hi_u32 v7, v2, v1
; GFX6-NEXT: s_addc_u32 s1, s1, s14
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v0
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v2, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5 ; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5
; GFX6-NEXT: s_xor_b64 s[16:17], s[0:1], s[14:15]
; GFX6-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13]
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, v2, v1 ; GFX6-NEXT: v_mul_lo_u32 v5, v2, v1
; GFX6-NEXT: v_mov_b32_e32 v0, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, 0
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v7, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v7, v0, vcc
; GFX6-NEXT: v_mov_b32_e32 v1, 0 ; GFX6-NEXT: v_mov_b32_e32 v1, 0
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v6, vcc
; GFX6-NEXT: v_add_i32_e64 v3, s[2:3], v3, v4
; GFX6-NEXT: v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
; GFX6-NEXT: v_mul_lo_u32 v6, s6, v4
; GFX6-NEXT: v_mul_hi_u32 v7, s6, v3
; GFX6-NEXT: v_mul_lo_u32 v8, s7, v3
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GFX6-NEXT: v_mul_lo_u32 v7, s6, v3
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GFX6-NEXT: v_mul_lo_u32 v10, v3, v6
; GFX6-NEXT: v_mul_hi_u32 v11, v3, v7
; GFX6-NEXT: v_mul_hi_u32 v12, v3, v6
; GFX6-NEXT: v_mul_hi_u32 v9, v4, v7
; GFX6-NEXT: v_mul_lo_u32 v7, v4, v7
; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6
; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v4, v6
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v8, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v1, v6, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_ashr_i32 s2, s9, 31
; GFX6-NEXT: s_add_u32 s0, s8, s2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: s_mov_b32 s3, s2 ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc
; GFX6-NEXT: s_addc_u32 s1, s9, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, s6, v2
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX6-NEXT: v_mul_hi_u32 v5, s6, v3
; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[2:3] ; GFX6-NEXT: v_mul_lo_u32 v6, s7, v3
; GFX6-NEXT: v_mul_lo_u32 v4, s8, v2 ; GFX6-NEXT: s_ashr_i32 s12, s9, 31
; GFX6-NEXT: v_mul_hi_u32 v5, s8, v3 ; GFX6-NEXT: s_add_u32 s8, s8, s12
; GFX6-NEXT: v_mul_hi_u32 v6, s8, v2 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_mul_hi_u32 v7, s9, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, s6, v3
; GFX6-NEXT: v_mul_lo_u32 v2, s9, v2 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GFX6-NEXT: v_mul_lo_u32 v8, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v9, v3, v5
; GFX6-NEXT: v_mul_hi_u32 v10, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v7, v2, v5
; GFX6-NEXT: v_mul_lo_u32 v5, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v6, v2, v4
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v2, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v6, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v6, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s16, v2
; GFX6-NEXT: v_mul_hi_u32 v5, s16, v3
; GFX6-NEXT: v_mul_hi_u32 v6, s16, v2
; GFX6-NEXT: v_mul_hi_u32 v7, s17, v2
; GFX6-NEXT: v_mul_lo_u32 v2, s17, v2
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, s9, v3 ; GFX6-NEXT: v_mul_lo_u32 v6, s17, v3
; GFX6-NEXT: v_mul_hi_u32 v3, s9, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, s17, v3
; GFX6-NEXT: s_xor_b64 s[16:17], s[2:3], s[16:17] ; GFX6-NEXT: s_mov_b32 s13, s12
; GFX6-NEXT: s_ashr_i32 s2, s13, 31 ; GFX6-NEXT: s_addc_u32 s9, s9, s12
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v1, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v1, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s14, v3 ; GFX6-NEXT: v_mul_lo_u32 v4, s10, v3
; GFX6-NEXT: v_mul_hi_u32 v5, s14, v2 ; GFX6-NEXT: v_mul_hi_u32 v5, s10, v2
; GFX6-NEXT: v_mul_lo_u32 v6, s15, v2 ; GFX6-NEXT: v_mul_lo_u32 v6, s11, v2
; GFX6-NEXT: v_mov_b32_e32 v7, s15 ; GFX6-NEXT: v_mov_b32_e32 v7, s11
; GFX6-NEXT: s_mov_b32 s3, s2 ; GFX6-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13]
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_mul_lo_u32 v5, s14, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, s10, v2
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s9, v4 ; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s17, v4
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s8, v5 ; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s16, v5
; GFX6-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc ; GFX6-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
; GFX6-NEXT: v_subrev_i32_e64 v7, s[0:1], s14, v5 ; GFX6-NEXT: v_subrev_i32_e64 v7, s[0:1], s10, v5
; GFX6-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v6 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v6
; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v7 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v7
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s15, v6 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v6
; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v2 ; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v2
; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v9, s[0:1], 1, v2 ; GFX6-NEXT: v_add_i32_e64 v9, s[0:1], 1, v2
; GFX6-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
; GFX6-NEXT: s_add_u32 s8, s12, s2
; GFX6-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v8, s9 ; GFX6-NEXT: v_mov_b32_e32 v8, s17
; GFX6-NEXT: s_addc_u32 s9, s13, s2
; GFX6-NEXT: s_xor_b64 s[8:9], s[8:9], s[2:3]
; GFX6-NEXT: v_cvt_f32_u32_e32 v10, s8 ; GFX6-NEXT: v_cvt_f32_u32_e32 v10, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v11, s9 ; GFX6-NEXT: v_cvt_f32_u32_e32 v11, s9
; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v8, v4, vcc ; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s15, v4 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s11, v4
; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s14, v5 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v5
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s15, v4 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s11, v4
; GFX6-NEXT: v_mac_f32_e32 v10, s18, v11 ; GFX6-NEXT: v_mac_f32_e32 v10, s18, v11
; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v5, vcc
; GFX6-NEXT: v_rcp_f32_e32 v5, v10 ; GFX6-NEXT: v_rcp_f32_e32 v5, v10
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[0:1]
; GFX6-NEXT: v_mul_f32_e32 v5, s19, v5 ; GFX6-NEXT: v_mul_f32_e32 v5, s19, v5
; GFX6-NEXT: v_mul_f32_e32 v6, s20, v5 ; GFX6-NEXT: v_mul_f32_e32 v6, s20, v5
; GFX6-NEXT: v_trunc_f32_e32 v6, v6 ; GFX6-NEXT: v_trunc_f32_e32 v6, v6
; GFX6-NEXT: v_mac_f32_e32 v5, s21, v6 ; GFX6-NEXT: v_mac_f32_e32 v5, s21, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX6-NEXT: s_sub_u32 s12, 0, s8 ; GFX6-NEXT: s_sub_u32 s0, 0, s8
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_mul_hi_u32 v4, s12, v5 ; GFX6-NEXT: v_mul_hi_u32 v4, s0, v5
; GFX6-NEXT: v_mul_lo_u32 v7, s12, v6 ; GFX6-NEXT: v_mul_lo_u32 v7, s0, v6
; GFX6-NEXT: s_subb_u32 s13, 0, s9 ; GFX6-NEXT: s_subb_u32 s1, 0, s9
; GFX6-NEXT: v_mul_lo_u32 v8, s13, v5 ; GFX6-NEXT: v_mul_lo_u32 v8, s1, v5
; GFX6-NEXT: v_xor_b32_e32 v2, s16, v2 ; GFX6-NEXT: s_ashr_i32 s10, s3, 31
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GFX6-NEXT: v_mul_lo_u32 v7, s12, v5 ; GFX6-NEXT: v_mul_lo_u32 v7, s0, v5
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GFX6-NEXT: v_mul_lo_u32 v8, v5, v4 ; GFX6-NEXT: v_mul_lo_u32 v8, v5, v4
; GFX6-NEXT: v_mul_hi_u32 v9, v5, v7 ; GFX6-NEXT: v_mul_hi_u32 v9, v5, v7
; GFX6-NEXT: v_mul_hi_u32 v10, v5, v4 ; GFX6-NEXT: v_mul_hi_u32 v10, v5, v4
; GFX6-NEXT: v_mul_hi_u32 v11, v6, v4 ; GFX6-NEXT: v_mul_hi_u32 v11, v6, v4
; GFX6-NEXT: v_mul_lo_u32 v4, v6, v4 ; GFX6-NEXT: v_mul_lo_u32 v4, v6, v4
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v10, v6, v7 ; GFX6-NEXT: v_mul_lo_u32 v10, v6, v7
; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7 ; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7
; GFX6-NEXT: v_xor_b32_e32 v3, s17, v3 ; GFX6-NEXT: s_mov_b32 s11, s10
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: v_xor_b32_e32 v2, s14, v2
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v11, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v11, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc
; GFX6-NEXT: v_add_i32_e64 v4, s[0:1], v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_addc_u32_e64 v5, vcc, v6, v7, s[0:1] ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v6, v7, vcc
; GFX6-NEXT: v_mul_lo_u32 v8, s12, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, s0, v5
; GFX6-NEXT: v_mul_hi_u32 v9, s12, v4 ; GFX6-NEXT: v_mul_hi_u32 v7, s0, v4
; GFX6-NEXT: v_mul_lo_u32 v10, s13, v4 ; GFX6-NEXT: v_mul_lo_u32 v8, s1, v4
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GFX6-NEXT: v_xor_b32_e32 v3, s15, v3
; GFX6-NEXT: v_mul_lo_u32 v9, s12, v4 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v10, v8 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GFX6-NEXT: v_mul_lo_u32 v12, v4, v8 ; GFX6-NEXT: v_mul_lo_u32 v7, s0, v4
; GFX6-NEXT: v_mul_hi_u32 v13, v4, v9 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GFX6-NEXT: v_mul_hi_u32 v14, v4, v8 ; GFX6-NEXT: v_mul_lo_u32 v10, v4, v6
; GFX6-NEXT: v_mul_hi_u32 v11, v5, v9 ; GFX6-NEXT: v_mul_hi_u32 v11, v4, v7
; GFX6-NEXT: v_mul_lo_u32 v9, v5, v9 ; GFX6-NEXT: v_mul_hi_u32 v12, v4, v6
; GFX6-NEXT: v_mul_hi_u32 v10, v5, v8 ; GFX6-NEXT: v_mul_hi_u32 v9, v5, v7
; GFX6-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; GFX6-NEXT: v_mul_lo_u32 v7, v5, v7
; GFX6-NEXT: v_addc_u32_e32 v13, vcc, 0, v14, vcc ; GFX6-NEXT: v_mul_hi_u32 v8, v5, v6
; GFX6-NEXT: v_mul_lo_u32 v5, v5, v8 ; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GFX6-NEXT: v_add_i32_e32 v9, vcc, v12, v9 ; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v13, v11, vcc ; GFX6-NEXT: v_mul_lo_u32 v6, v5, v6
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v10, v0, vcc ; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v9, v5 ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v8, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GFX6-NEXT: s_ashr_i32 s12, s11, 31 ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc
; GFX6-NEXT: v_addc_u32_e64 v6, vcc, v6, v8, s[0:1] ; GFX6-NEXT: s_add_u32 s0, s2, s10
; GFX6-NEXT: s_add_u32 s0, s10, s12 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; GFX6-NEXT: s_addc_u32 s1, s3, s10
; GFX6-NEXT: s_mov_b32 s13, s12 ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
; GFX6-NEXT: s_addc_u32 s1, s11, s12 ; GFX6-NEXT: s_xor_b64 s[2:3], s[0:1], s[10:11]
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_mul_lo_u32 v6, s2, v5
; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[12:13] ; GFX6-NEXT: v_mul_hi_u32 v7, s2, v4
; GFX6-NEXT: v_mul_lo_u32 v6, s10, v5 ; GFX6-NEXT: v_mul_hi_u32 v9, s2, v5
; GFX6-NEXT: v_mul_hi_u32 v7, s10, v4 ; GFX6-NEXT: v_mul_hi_u32 v10, s3, v5
; GFX6-NEXT: v_mul_hi_u32 v9, s10, v5 ; GFX6-NEXT: v_mul_lo_u32 v5, s3, v5
; GFX6-NEXT: v_mul_hi_u32 v10, s11, v5
; GFX6-NEXT: v_mul_lo_u32 v5, s11, v5
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
; GFX6-NEXT: v_mul_lo_u32 v9, s11, v4 ; GFX6-NEXT: v_mul_lo_u32 v9, s3, v4
; GFX6-NEXT: v_mul_hi_u32 v4, s11, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, s3, v4
; GFX6-NEXT: v_mov_b32_e32 v8, s17 ; GFX6-NEXT: v_mov_b32_e32 v8, s15
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v9 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v9
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v0, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, s8, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, s8, v5
; GFX6-NEXT: v_mul_hi_u32 v7, s8, v4 ; GFX6-NEXT: v_mul_hi_u32 v7, s8, v4
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s16, v2 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s14, v2
; GFX6-NEXT: v_mul_lo_u32 v2, s9, v4 ; GFX6-NEXT: v_mul_lo_u32 v2, s9, v4
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v3, v8, vcc ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v3, v8, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v7, v6 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v7, v6
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_lo_u32 v3, s8, v4 ; GFX6-NEXT: v_mul_lo_u32 v3, s8, v4
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s11, v2 ; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s3, v2
; GFX6-NEXT: v_mov_b32_e32 v7, s9 ; GFX6-NEXT: v_mov_b32_e32 v7, s9
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s10, v3 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s2, v3
; GFX6-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc ; GFX6-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
; GFX6-NEXT: v_subrev_i32_e64 v7, s[0:1], s8, v3 ; GFX6-NEXT: v_subrev_i32_e64 v7, s[0:1], s8, v3
; GFX6-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v6 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v6
; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v7 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v7
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v6 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v6
; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v4 ; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v4
; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v5, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v5, s[0:1]
; GFX6-NEXT: v_add_i32_e64 v9, s[0:1], 1, v4 ; GFX6-NEXT: v_add_i32_e64 v9, s[0:1], 1, v4
; GFX6-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v5, s[0:1] ; GFX6-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v5, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
; GFX6-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v8, s11 ; GFX6-NEXT: v_mov_b32_e32 v8, s3
; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v8, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v8, v2, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v2 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v2
; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s9, v2 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s9, v2
; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX6-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX6-NEXT: s_xor_b64 s[0:1], s[12:13], s[2:3] ; GFX6-NEXT: s_xor_b64 s[0:1], s[10:11], s[12:13]
; GFX6-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
; GFX6-NEXT: v_xor_b32_e32 v3, s0, v3 ; GFX6-NEXT: v_xor_b32_e32 v3, s0, v3
; GFX6-NEXT: v_xor_b32_e32 v4, s1, v2 ; GFX6-NEXT: v_xor_b32_e32 v4, s1, v2
; GFX6-NEXT: v_mov_b32_e32 v5, s1 ; GFX6-NEXT: v_mov_b32_e32 v5, s1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v3 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v3
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v4, v5, vcc ; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v4, v5, vcc
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
Show All 11 Lines
; GFX9-NEXT: s_ashr_i32 s12, s3, 31 ; GFX9-NEXT: s_ashr_i32 s12, s3, 31
; GFX9-NEXT: s_add_u32 s2, s2, s12 ; GFX9-NEXT: s_add_u32 s2, s2, s12
; GFX9-NEXT: s_mov_b32 s13, s12 ; GFX9-NEXT: s_mov_b32 s13, s12
; GFX9-NEXT: s_addc_u32 s3, s3, s12 ; GFX9-NEXT: s_addc_u32 s3, s3, s12
; GFX9-NEXT: s_xor_b64 s[10:11], s[2:3], s[12:13] ; GFX9-NEXT: s_xor_b64 s[10:11], s[2:3], s[12:13]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s10 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s10
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s11 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s11
; GFX9-NEXT: s_mov_b32 s19, 0xcf800000 ; GFX9-NEXT: s_mov_b32 s19, 0xcf800000
; GFX9-NEXT: s_sub_u32 s14, 0, s10 ; GFX9-NEXT: s_sub_u32 s2, 0, s10
; GFX9-NEXT: s_subb_u32 s4, 0, s11 ; GFX9-NEXT: s_subb_u32 s3, 0, s11
; GFX9-NEXT: v_mac_f32_e32 v0, s16, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, s16, v1
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX9-NEXT: v_mul_f32_e32 v0, s17, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s17, v0
; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v0
; GFX9-NEXT: v_mul_lo_u32 v0, s14, v2 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_hi_u32 v1, s14, v3 ; GFX9-NEXT: s_ashr_i32 s14, s5, 31
; GFX9-NEXT: v_mul_lo_u32 v5, s4, v3 ; GFX9-NEXT: s_mov_b32 s15, s14
; GFX9-NEXT: v_mul_lo_u32 v4, s14, v3 ; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2
; GFX9-NEXT: v_mul_hi_u32 v1, s2, v3
; GFX9-NEXT: v_mul_lo_u32 v5, s3, v3
; GFX9-NEXT: v_mul_lo_u32 v4, s2, v3
; GFX9-NEXT: v_add_u32_e32 v0, v1, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v1, v0
; GFX9-NEXT: v_add_u32_e32 v5, v0, v5 ; GFX9-NEXT: v_add_u32_e32 v5, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v1, v3, v4 ; GFX9-NEXT: v_mul_hi_u32 v1, v3, v4
; GFX9-NEXT: v_mul_lo_u32 v6, v3, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, v3, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v3, v5 ; GFX9-NEXT: v_mul_hi_u32 v7, v3, v5
; GFX9-NEXT: v_mul_hi_u32 v8, v2, v5 ; GFX9-NEXT: v_mul_hi_u32 v8, v2, v5
; GFX9-NEXT: v_mul_lo_u32 v5, v2, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v2, v5
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v6 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v6
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v2, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v2, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v2, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v2, v4
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v7 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v7
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v8, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v8, v0, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v6, vcc
; GFX9-NEXT: v_add_co_u32_e64 v3, s[2:3], v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_addc_co_u32_e64 v4, vcc, v2, v5, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, s14, v4 ; GFX9-NEXT: v_mul_lo_u32 v4, s2, v2
; GFX9-NEXT: v_mul_hi_u32 v7, s14, v3 ; GFX9-NEXT: v_mul_hi_u32 v5, s2, v3
; GFX9-NEXT: v_mul_lo_u32 v8, s4, v3 ; GFX9-NEXT: v_mul_lo_u32 v6, s3, v3
; GFX9-NEXT: v_mul_lo_u32 v9, s14, v3 ; GFX9-NEXT: v_mul_lo_u32 v7, s2, v3
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX9-NEXT: v_add_u32_e32 v6, v7, v6
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: v_mul_lo_u32 v10, v3, v6
; GFX9-NEXT: v_mul_hi_u32 v11, v3, v9
; GFX9-NEXT: v_mul_hi_u32 v12, v3, v6
; GFX9-NEXT: v_mul_hi_u32 v8, v4, v9
; GFX9-NEXT: v_mul_lo_u32 v9, v4, v9
; GFX9-NEXT: v_mul_hi_u32 v7, v4, v6
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, v4, v6
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v1, v6, vcc
; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s14, s5, 31
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v2, v6, s[2:3]
; GFX9-NEXT: s_add_u32 s2, s4, s14 ; GFX9-NEXT: s_add_u32 s2, s4, s14
; GFX9-NEXT: v_add_u32_e32 v4, v5, v4
; GFX9-NEXT: v_add_u32_e32 v4, v4, v6
; GFX9-NEXT: v_mul_lo_u32 v8, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v9, v3, v7
; GFX9-NEXT: v_mul_hi_u32 v10, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v6, v2, v7
; GFX9-NEXT: v_mul_lo_u32 v7, v2, v7
; GFX9-NEXT: v_mul_hi_u32 v5, v2, v4
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, v2, v4
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: s_mov_b32 s15, s14
; GFX9-NEXT: s_addc_u32 s3, s5, s14 ; GFX9-NEXT: s_addc_u32 s3, s5, s14
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: s_xor_b64 s[4:5], s[2:3], s[14:15] ; GFX9-NEXT: s_xor_b64 s[4:5], s[2:3], s[14:15]
; GFX9-NEXT: v_mul_lo_u32 v4, s4, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, s4, v2
; GFX9-NEXT: v_mul_hi_u32 v5, s4, v3 ; GFX9-NEXT: v_mul_hi_u32 v5, s4, v3
; GFX9-NEXT: v_mul_hi_u32 v6, s4, v2 ; GFX9-NEXT: v_mul_hi_u32 v6, s4, v2
; GFX9-NEXT: v_mul_hi_u32 v7, s5, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, s5, v2
; GFX9-NEXT: v_mul_lo_u32 v2, s5, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, s5, v2
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, s5, v3 ; GFX9-NEXT: v_mul_lo_u32 v6, s5, v3
; GFX9-NEXT: v_mul_hi_u32 v3, s5, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, s5, v3
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX9-NEXT: s_xor_b64 s[12:13], s[14:15], s[12:13]
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v3, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s10, v3 ; GFX9-NEXT: v_mul_lo_u32 v4, s10, v3
; GFX9-NEXT: v_mul_hi_u32 v5, s10, v2 ; GFX9-NEXT: v_mul_hi_u32 v5, s10, v2
; GFX9-NEXT: v_mul_lo_u32 v6, s11, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, s11, v2
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; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v7 ; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v7
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v6 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v6
; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1]
; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
; GFX9-NEXT: v_cndmask_b32_e64 v6, 1, 2, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, 1, 2, s[0:1]
; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], v2, v6 ; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], v2, v6
; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v3, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v3, s[0:1]
; GFX9-NEXT: s_xor_b64 s[0:1], s[14:15], s[12:13]
; GFX9-NEXT: s_ashr_i32 s4, s9, 31 ; GFX9-NEXT: s_ashr_i32 s4, s9, 31
; GFX9-NEXT: s_add_u32 s0, s8, s4 ; GFX9-NEXT: s_add_u32 s8, s8, s4
; GFX9-NEXT: v_mov_b32_e32 v8, s5 ; GFX9-NEXT: v_mov_b32_e32 v8, s5
; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_mov_b32 s5, s4
; GFX9-NEXT: s_addc_u32 s1, s9, s4 ; GFX9-NEXT: s_addc_u32 s9, s9, s4
; GFX9-NEXT: s_xor_b64 s[8:9], s[0:1], s[4:5] ; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[4:5]
; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v8, v4, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX9-NEXT: v_cvt_f32_u32_e32 v8, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v8, s8
; GFX9-NEXT: v_cvt_f32_u32_e32 v9, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v9, s9
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v4 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v4
; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v5 ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v5
; GFX9-NEXT: v_mac_f32_e32 v8, s16, v9 ; GFX9-NEXT: v_mac_f32_e32 v8, s16, v9
; GFX9-NEXT: v_rcp_f32_e32 v8, v8 ; GFX9-NEXT: v_rcp_f32_e32 v8, v8
Show All 21 Lines
; GFX9-NEXT: v_mul_hi_u32 v9, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v9, v4, v7
; GFX9-NEXT: v_mul_hi_u32 v10, v4, v6 ; GFX9-NEXT: v_mul_hi_u32 v10, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v11, v5, v6 ; GFX9-NEXT: v_mul_hi_u32 v11, v5, v6
; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6 ; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v5, v7 ; GFX9-NEXT: v_mul_lo_u32 v10, v5, v7
; GFX9-NEXT: v_mul_hi_u32 v7, v5, v7 ; GFX9-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX9-NEXT: v_xor_b32_e32 v2, s12, v2 ; GFX9-NEXT: v_xor_b32_e32 v2, s0, v2
; GFX9-NEXT: v_xor_b32_e32 v3, s13, v3 ; GFX9-NEXT: v_xor_b32_e32 v3, s1, v3
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v9, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v9, v7, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v8, vcc
; GFX9-NEXT: v_add_co_u32_e64 v4, s[0:1], v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v5, v7, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, s10, v6 ; GFX9-NEXT: v_mul_lo_u32 v6, s10, v5
; GFX9-NEXT: v_mul_hi_u32 v9, s10, v4 ; GFX9-NEXT: v_mul_hi_u32 v7, s10, v4
; GFX9-NEXT: v_mul_lo_u32 v10, s11, v4 ; GFX9-NEXT: v_mul_lo_u32 v8, s11, v4
; GFX9-NEXT: v_mul_lo_u32 v11, s10, v4 ; GFX9-NEXT: v_mul_lo_u32 v9, s10, v4
; GFX9-NEXT: v_add_u32_e32 v5, v5, v7
; GFX9-NEXT: v_add_u32_e32 v8, v9, v8
; GFX9-NEXT: v_add_u32_e32 v8, v8, v10
; GFX9-NEXT: v_mul_lo_u32 v12, v4, v8
; GFX9-NEXT: v_mul_hi_u32 v13, v4, v11
; GFX9-NEXT: v_mul_hi_u32 v14, v4, v8
; GFX9-NEXT: v_mul_hi_u32 v10, v6, v11
; GFX9-NEXT: v_mul_lo_u32 v11, v6, v11
; GFX9-NEXT: v_mul_hi_u32 v9, v6, v8
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v13, v12
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v14, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v6, v8
; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v10, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v9, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v1, v8, vcc
; GFX9-NEXT: s_ashr_i32 s10, s7, 31 ; GFX9-NEXT: s_ashr_i32 s10, s7, 31
; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v8, s[0:1] ; GFX9-NEXT: v_add_u32_e32 v6, v7, v6
; GFX9-NEXT: s_add_u32 s0, s6, s10 ; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: v_mul_lo_u32 v10, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v11, v4, v9
; GFX9-NEXT: v_mul_hi_u32 v12, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v8, v5, v9
; GFX9-NEXT: v_mul_lo_u32 v9, v5, v9
; GFX9-NEXT: v_mul_hi_u32 v7, v5, v6
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v8, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v7, vcc
; GFX9-NEXT: s_add_u32 s6, s6, s10
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
; GFX9-NEXT: s_mov_b32 s11, s10 ; GFX9-NEXT: s_mov_b32 s11, s10
; GFX9-NEXT: s_addc_u32 s1, s7, s10 ; GFX9-NEXT: s_addc_u32 s7, s7, s10
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc
; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11] ; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11]
; GFX9-NEXT: v_mul_lo_u32 v6, s6, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, s6, v5
; GFX9-NEXT: v_mul_hi_u32 v7, s6, v4 ; GFX9-NEXT: v_mul_hi_u32 v7, s6, v4
; GFX9-NEXT: v_mul_hi_u32 v9, s6, v5 ; GFX9-NEXT: v_mul_hi_u32 v9, s6, v5
; GFX9-NEXT: v_mul_hi_u32 v10, s7, v5 ; GFX9-NEXT: v_mul_hi_u32 v10, s7, v5
; GFX9-NEXT: v_mul_lo_u32 v5, s7, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, s7, v5
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
; GFX9-NEXT: v_mul_lo_u32 v9, s7, v4 ; GFX9-NEXT: v_mul_lo_u32 v9, s7, v4
; GFX9-NEXT: v_mul_hi_u32 v4, s7, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, s7, v4
; GFX9-NEXT: v_mov_b32_e32 v8, s13 ; GFX9-NEXT: v_mov_b32_e32 v8, s1
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v9 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v9
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v10, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v10, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v6, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, s8, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, s8, v5
; GFX9-NEXT: v_mul_hi_u32 v7, s8, v4 ; GFX9-NEXT: v_mul_hi_u32 v7, s8, v4
; GFX9-NEXT: v_mul_lo_u32 v9, s9, v4 ; GFX9-NEXT: v_mul_lo_u32 v9, s9, v4
; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s12, v2 ; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v8, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v8, vcc
; GFX9-NEXT: v_add_u32_e32 v3, v7, v6 ; GFX9-NEXT: v_add_u32_e32 v3, v7, v6
; GFX9-NEXT: v_mul_lo_u32 v6, s8, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, s8, v4
; GFX9-NEXT: v_add_u32_e32 v3, v3, v9 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v9
; GFX9-NEXT: v_sub_u32_e32 v7, s7, v3 ; GFX9-NEXT: v_sub_u32_e32 v7, s7, v3
; GFX9-NEXT: v_mov_b32_e32 v8, s9 ; GFX9-NEXT: v_mov_b32_e32 v8, s9
; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, s6, v6 ; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, s6, v6
; GFX9-NEXT: v_subb_co_u32_e64 v7, s[0:1], v7, v8, vcc ; GFX9-NEXT: v_subb_co_u32_e64 v7, s[0:1], v7, v8, vcc
Show All 40 Lines
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_lshl_b64 s[8:9], s[2:3], s6 ; GFX90A-NEXT: s_lshl_b64 s[8:9], s[2:3], s6
; GFX90A-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 ; GFX90A-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
; GFX90A-NEXT: s_ashr_i32 s10, s3, 31 ; GFX90A-NEXT: s_ashr_i32 s10, s3, 31
; GFX90A-NEXT: s_add_u32 s2, s2, s10 ; GFX90A-NEXT: s_add_u32 s2, s2, s10
; GFX90A-NEXT: s_mov_b32 s11, s10 ; GFX90A-NEXT: s_mov_b32 s11, s10
; GFX90A-NEXT: s_addc_u32 s3, s3, s10 ; GFX90A-NEXT: s_addc_u32 s3, s3, s10
; GFX90A-NEXT: s_xor_b64 s[12:13], s[2:3], s[10:11] ; GFX90A-NEXT: s_xor_b64 s[12:13], s[2:3], s[10:11]
; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s12 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX90A-NEXT: v_cvt_f32_u32_e32 v2, s13 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX90A-NEXT: s_mov_b32 s19, 0xcf800000 ; GFX90A-NEXT: s_mov_b32 s19, 0xcf800000
; GFX90A-NEXT: s_sub_u32 s14, 0, s12
; GFX90A-NEXT: s_subb_u32 s15, 0, s13
; GFX90A-NEXT: v_mac_f32_e32 v1, s16, v2
; GFX90A-NEXT: v_rcp_f32_e32 v1, v1
; GFX90A-NEXT: v_mov_b32_e32 v0, 0
; GFX90A-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX90A-NEXT: v_mul_f32_e32 v1, s17, v1 ; GFX90A-NEXT: s_sub_u32 s0, 0, s12
; GFX90A-NEXT: v_mul_f32_e32 v2, s18, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, s16, v1
; GFX90A-NEXT: v_trunc_f32_e32 v2, v2 ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0
; GFX90A-NEXT: v_mac_f32_e32 v1, s19, v2 ; GFX90A-NEXT: s_subb_u32 s1, 0, s13
; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_ashr_i32 s14, s5, 31
; GFX90A-NEXT: v_mul_f32_e32 v0, s17, v0
; GFX90A-NEXT: v_mul_f32_e32 v1, s18, v0
; GFX90A-NEXT: v_trunc_f32_e32 v1, v1
; GFX90A-NEXT: v_mac_f32_e32 v0, s19, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX90A-NEXT: s_mov_b32 s15, s14
; GFX90A-NEXT: v_mul_hi_u32 v4, s14, v1 ; GFX90A-NEXT: v_mul_hi_u32 v3, s0, v0
; GFX90A-NEXT: v_mul_lo_u32 v5, s14, v2 ; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v1
; GFX90A-NEXT: v_mul_lo_u32 v3, s15, v1 ; GFX90A-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX90A-NEXT: v_add_u32_e32 v4, v4, v5 ; GFX90A-NEXT: v_add_u32_e32 v3, v3, v5
; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2
; GFX90A-NEXT: v_mul_lo_u32 v6, s14, v1 ; GFX90A-NEXT: v_mul_lo_u32 v6, s0, v0
; GFX90A-NEXT: v_mul_lo_u32 v5, v1, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v4, v1, v3 ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, v2
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX90A-NEXT: v_mul_hi_u32 v8, v2, v6 ; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v2, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v2, v3 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v0, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v2, v3 ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX90A-NEXT: v_mov_b32_e32 v6, 0 ; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e64 v1, s[0:1], v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX90A-NEXT: v_addc_co_u32_e64 v3, vcc, v2, v4, s[0:1] ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX90A-NEXT: v_mul_lo_u32 v5, s14, v3 ; GFX90A-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX90A-NEXT: v_mul_hi_u32 v7, s14, v1 ; GFX90A-NEXT: v_mul_hi_u32 v3, s0, v0
; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5 ; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2
; GFX90A-NEXT: v_mul_lo_u32 v7, s15, v1 ; GFX90A-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX90A-NEXT: v_add_u32_e32 v5, v5, v7 ; GFX90A-NEXT: v_add_u32_e32 v2, v2, v3
; GFX90A-NEXT: v_mul_lo_u32 v8, s14, v1 ; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX90A-NEXT: v_mul_hi_u32 v9, v3, v8 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v10, v3, v8 ; GFX90A-NEXT: v_mul_lo_u32 v8, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v12, v1, v5 ; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v2
; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v8 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5
; GFX90A-NEXT: v_mul_hi_u32 v11, v1, v5 ; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v2
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10
; GFX90A-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8
; GFX90A-NEXT: v_mul_hi_u32 v7, v3, v5 ; GFX90A-NEXT: v_mul_hi_u32 v3, v1, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v7, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v0, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v3, v5 ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v5, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v7, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
; GFX90A-NEXT: v_add_u32_e32 v2, v2, v4
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_ashr_i32 s14, s5, 31
; GFX90A-NEXT: v_addc_co_u32_e64 v2, vcc, v2, v5, s[0:1]
; GFX90A-NEXT: s_add_u32 s0, s4, s14 ; GFX90A-NEXT: s_add_u32 s0, s4, s14
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX90A-NEXT: s_mov_b32 s15, s14
; GFX90A-NEXT: s_addc_u32 s1, s5, s14 ; GFX90A-NEXT: s_addc_u32 s1, s5, s14
; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], s[0:1], s[14:15] ; GFX90A-NEXT: s_xor_b64 s[4:5], s[0:1], s[14:15]
; GFX90A-NEXT: v_mul_lo_u32 v4, s4, v2 ; GFX90A-NEXT: v_mul_lo_u32 v3, s4, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s4, v1 ; GFX90A-NEXT: v_mul_hi_u32 v5, s4, v0
; GFX90A-NEXT: v_mul_hi_u32 v3, s4, v2 ; GFX90A-NEXT: v_mul_hi_u32 v2, s4, v1
; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX90A-NEXT: v_mul_hi_u32 v7, s5, v1 ; GFX90A-NEXT: v_mul_hi_u32 v7, s5, v0
; GFX90A-NEXT: v_mul_lo_u32 v0, s5, v0
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0
; GFX90A-NEXT: v_mul_hi_u32 v5, s5, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v2, v7, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v1, s5, v1 ; GFX90A-NEXT: v_mul_lo_u32 v1, s5, v1
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v4, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s5, v2 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v7, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, s12, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v0, vcc ; GFX90A-NEXT: v_mul_hi_u32 v3, s12, v0
; GFX90A-NEXT: v_mul_lo_u32 v2, s5, v2 ; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v1, v2 ; GFX90A-NEXT: v_mul_lo_u32 v3, s13, v0
; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v3, vcc ; GFX90A-NEXT: v_add_u32_e32 v2, v2, v3
; GFX90A-NEXT: v_mul_lo_u32 v3, s12, v2 ; GFX90A-NEXT: v_mul_lo_u32 v5, s12, v0
; GFX90A-NEXT: v_mul_hi_u32 v4, s12, v1 ; GFX90A-NEXT: v_sub_u32_e32 v3, s5, v2
; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3
; GFX90A-NEXT: v_mul_lo_u32 v4, s13, v1
; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4
; GFX90A-NEXT: v_mul_lo_u32 v5, s12, v1
; GFX90A-NEXT: v_sub_u32_e32 v4, s5, v3
; GFX90A-NEXT: v_mov_b32_e32 v7, s13 ; GFX90A-NEXT: v_mov_b32_e32 v7, s13
; GFX90A-NEXT: v_sub_co_u32_e32 v5, vcc, s4, v5 ; GFX90A-NEXT: v_sub_co_u32_e32 v5, vcc, s4, v5
; GFX90A-NEXT: v_subb_co_u32_e64 v4, s[0:1], v4, v7, vcc ; GFX90A-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v7, vcc
; GFX90A-NEXT: v_subrev_co_u32_e64 v7, s[0:1], s12, v5 ; GFX90A-NEXT: v_subrev_co_u32_e64 v7, s[0:1], s12, v5
; GFX90A-NEXT: v_subbrev_co_u32_e64 v4, s[0:1], 0, v4, s[0:1] ; GFX90A-NEXT: v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1]
; GFX90A-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v4 ; GFX90A-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v3
; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
; GFX90A-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v7 ; GFX90A-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v7
; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GFX90A-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v4 ; GFX90A-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v3
; GFX90A-NEXT: v_cndmask_b32_e64 v4, v8, v7, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v3, v8, v7, s[0:1]
; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 ; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
; GFX90A-NEXT: v_cndmask_b32_e64 v4, 1, 2, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v3, 1, 2, s[0:1]
; GFX90A-NEXT: v_mov_b32_e32 v8, s5 ; GFX90A-NEXT: v_mov_b32_e32 v8, s5
; GFX90A-NEXT: v_add_co_u32_e64 v4, s[0:1], v1, v4 ; GFX90A-NEXT: v_add_co_u32_e64 v3, s[0:1], v0, v3
; GFX90A-NEXT: v_subb_co_u32_e32 v3, vcc, v8, v3, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v2, vcc, v8, v2, vcc
; GFX90A-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v2, s[0:1] ; GFX90A-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v1, s[0:1]
; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s13, v3 ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s13, v2
; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s12, v5 ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s12, v5
; GFX90A-NEXT: s_xor_b64 s[0:1], s[14:15], s[10:11] ; GFX90A-NEXT: s_xor_b64 s[0:1], s[14:15], s[10:11]
; GFX90A-NEXT: s_ashr_i32 s4, s9, 31 ; GFX90A-NEXT: s_ashr_i32 s4, s9, 31
; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, s13, v3 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, s13, v2
; GFX90A-NEXT: s_add_u32 s8, s8, s4 ; GFX90A-NEXT: s_add_u32 s8, s8, s4
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v8, v5, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v2, v8, v5, vcc
; GFX90A-NEXT: s_mov_b32 s5, s4 ; GFX90A-NEXT: s_mov_b32 s5, s4
; GFX90A-NEXT: s_addc_u32 s9, s9, s4 ; GFX90A-NEXT: s_addc_u32 s9, s9, s4
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GFX90A-NEXT: s_xor_b64 s[8:9], s[8:9], s[4:5] ; GFX90A-NEXT: s_xor_b64 s[8:9], s[8:9], s[4:5]
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX90A-NEXT: v_cvt_f32_u32_e32 v3, s8 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v2, s8
; GFX90A-NEXT: v_cvt_f32_u32_e32 v4, s9 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v3, s9
; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc ; GFX90A-NEXT: v_xor_b32_e32 v0, s0, v0
; GFX90A-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX90A-NEXT: v_xor_b32_e32 v5, s1, v2 ; GFX90A-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0
; GFX90A-NEXT: v_mac_f32_e32 v3, s16, v4 ; GFX90A-NEXT: v_mac_f32_e32 v2, s16, v3
; GFX90A-NEXT: v_rcp_f32_e32 v4, v3 ; GFX90A-NEXT: v_rcp_f32_e32 v2, v2
; GFX90A-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v1 ; GFX90A-NEXT: s_sub_u32 s0, 0, s8
; GFX90A-NEXT: v_mov_b32_e32 v7, s1 ; GFX90A-NEXT: v_xor_b32_e32 v1, s1, v1
; GFX90A-NEXT: v_mul_f32_e32 v1, s17, v4 ; GFX90A-NEXT: v_mov_b32_e32 v5, s1
; GFX90A-NEXT: v_mul_f32_e32 v4, s18, v1 ; GFX90A-NEXT: v_mul_f32_e32 v2, s17, v2
; GFX90A-NEXT: v_trunc_f32_e32 v4, v4 ; GFX90A-NEXT: v_mul_f32_e32 v3, s18, v2
; GFX90A-NEXT: v_mac_f32_e32 v1, s19, v4 ; GFX90A-NEXT: v_trunc_f32_e32 v3, v3
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_mac_f32_e32 v2, s19, v3
; GFX90A-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX90A-NEXT: s_sub_u32 s10, 0, s8 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX90A-NEXT: v_subb_co_u32_e32 v3, vcc, v5, v7, vcc ; GFX90A-NEXT: s_subb_u32 s1, 0, s9
; GFX90A-NEXT: s_subb_u32 s11, 0, s9 ; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
; GFX90A-NEXT: v_mul_hi_u32 v7, s10, v1 ; GFX90A-NEXT: v_mul_hi_u32 v7, s0, v2
; GFX90A-NEXT: v_mul_lo_u32 v8, s10, v4 ; GFX90A-NEXT: v_mul_lo_u32 v8, s0, v3
; GFX90A-NEXT: v_mul_lo_u32 v5, s11, v1 ; GFX90A-NEXT: v_mul_lo_u32 v5, s1, v2
; GFX90A-NEXT: v_add_u32_e32 v7, v7, v8 ; GFX90A-NEXT: v_add_u32_e32 v7, v7, v8
; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5 ; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5
; GFX90A-NEXT: v_mul_lo_u32 v9, s10, v1 ; GFX90A-NEXT: v_mul_lo_u32 v9, s0, v2
; GFX90A-NEXT: v_mul_lo_u32 v8, v1, v5 ; GFX90A-NEXT: v_mul_lo_u32 v8, v2, v5
; GFX90A-NEXT: v_mul_hi_u32 v10, v1, v9 ; GFX90A-NEXT: v_mul_hi_u32 v10, v2, v9
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v5 ; GFX90A-NEXT: v_mul_hi_u32 v7, v2, v5
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8 ; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX90A-NEXT: v_mul_hi_u32 v11, v4, v9 ; GFX90A-NEXT: v_mul_hi_u32 v11, v3, v9
; GFX90A-NEXT: v_mul_lo_u32 v9, v4, v9 ; GFX90A-NEXT: v_mul_lo_u32 v9, v3, v9
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v9 ; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v9
; GFX90A-NEXT: v_mul_hi_u32 v10, v4, v5 ; GFX90A-NEXT: v_mul_hi_u32 v10, v3, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v11, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v11, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v10, v0, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v10, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v5, v4, v5 ; GFX90A-NEXT: v_mul_lo_u32 v5, v3, v5
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v6, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v6, v8, vcc
; GFX90A-NEXT: v_add_co_u32_e64 v1, s[0:1], v1, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5
; GFX90A-NEXT: v_addc_co_u32_e64 v5, vcc, v4, v7, s[0:1] ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v7, vcc
; GFX90A-NEXT: v_mul_lo_u32 v8, s10, v5 ; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v3
; GFX90A-NEXT: v_mul_hi_u32 v9, s10, v1 ; GFX90A-NEXT: v_mul_hi_u32 v7, s0, v2
; GFX90A-NEXT: v_add_u32_e32 v8, v9, v8 ; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5
; GFX90A-NEXT: v_mul_lo_u32 v9, s11, v1 ; GFX90A-NEXT: v_mul_lo_u32 v7, s1, v2
; GFX90A-NEXT: v_add_u32_e32 v8, v8, v9 ; GFX90A-NEXT: v_add_u32_e32 v5, v5, v7
; GFX90A-NEXT: v_mul_lo_u32 v10, s10, v1 ; GFX90A-NEXT: v_mul_lo_u32 v8, s0, v2
; GFX90A-NEXT: v_mul_hi_u32 v11, v5, v10 ; GFX90A-NEXT: v_mul_hi_u32 v9, v3, v8
; GFX90A-NEXT: v_mul_lo_u32 v12, v5, v10 ; GFX90A-NEXT: v_mul_lo_u32 v10, v3, v8
; GFX90A-NEXT: v_mul_lo_u32 v14, v1, v8 ; GFX90A-NEXT: v_mul_lo_u32 v12, v2, v5
; GFX90A-NEXT: v_mul_hi_u32 v10, v1, v10 ; GFX90A-NEXT: v_mul_hi_u32 v8, v2, v8
; GFX90A-NEXT: v_mul_hi_u32 v13, v1, v8 ; GFX90A-NEXT: v_mul_hi_u32 v11, v2, v5
; GFX90A-NEXT: v_add_co_u32_e32 v10, vcc, v10, v14 ; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12
; GFX90A-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v10, vcc, v10, v12 ; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10
; GFX90A-NEXT: v_mul_hi_u32 v9, v5, v8 ; GFX90A-NEXT: v_mul_hi_u32 v7, v3, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v11, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, v9, v0, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v5, v5, v8 ; GFX90A-NEXT: v_mul_lo_u32 v5, v3, v5
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v10, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v8, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v6, v9, vcc
; GFX90A-NEXT: v_add_u32_e32 v4, v4, v7
; GFX90A-NEXT: s_ashr_i32 s10, s7, 31 ; GFX90A-NEXT: s_ashr_i32 s10, s7, 31
; GFX90A-NEXT: v_addc_co_u32_e64 v4, vcc, v4, v8, s[0:1] ; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v6, v7, vcc
; GFX90A-NEXT: s_add_u32 s0, s6, s10 ; GFX90A-NEXT: s_add_u32 s0, s6, s10
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v1, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5
; GFX90A-NEXT: s_mov_b32 s11, s10 ; GFX90A-NEXT: s_mov_b32 s11, s10
; GFX90A-NEXT: s_addc_u32 s1, s7, s10 ; GFX90A-NEXT: s_addc_u32 s1, s7, s10
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v7, vcc
; GFX90A-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11] ; GFX90A-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11]
; GFX90A-NEXT: v_mul_lo_u32 v7, s6, v4 ; GFX90A-NEXT: v_mul_lo_u32 v7, s6, v3
; GFX90A-NEXT: v_mul_hi_u32 v8, s6, v1 ; GFX90A-NEXT: v_mul_hi_u32 v8, s6, v2
; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v4 ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v3
; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 ; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX90A-NEXT: v_mul_hi_u32 v9, s7, v1 ; GFX90A-NEXT: v_mul_hi_u32 v9, s7, v2
; GFX90A-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX90A-NEXT: v_mul_lo_u32 v2, s7, v2
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v7, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v7, v2
; GFX90A-NEXT: v_mul_hi_u32 v8, s7, v4 ; GFX90A-NEXT: v_mul_hi_u32 v8, s7, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v0, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v4, s7, v4 ; GFX90A-NEXT: v_mul_lo_u32 v3, s7, v3
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v1, v4 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
; GFX90A-NEXT: v_mul_lo_u32 v5, s8, v4 ; GFX90A-NEXT: v_mul_lo_u32 v5, s8, v3
; GFX90A-NEXT: v_mul_hi_u32 v6, s8, v1 ; GFX90A-NEXT: v_mul_hi_u32 v6, s8, v2
; GFX90A-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX90A-NEXT: v_add_u32_e32 v5, v6, v5
; GFX90A-NEXT: v_mul_lo_u32 v6, s9, v1 ; GFX90A-NEXT: v_mul_lo_u32 v6, s9, v2
; GFX90A-NEXT: v_add_u32_e32 v5, v5, v6 ; GFX90A-NEXT: v_add_u32_e32 v5, v5, v6
; GFX90A-NEXT: v_mul_lo_u32 v7, s8, v1 ; GFX90A-NEXT: v_mul_lo_u32 v7, s8, v2
; GFX90A-NEXT: v_sub_u32_e32 v6, s7, v5 ; GFX90A-NEXT: v_sub_u32_e32 v6, s7, v5
; GFX90A-NEXT: v_mov_b32_e32 v8, s9 ; GFX90A-NEXT: v_mov_b32_e32 v8, s9
; GFX90A-NEXT: v_sub_co_u32_e32 v7, vcc, s6, v7 ; GFX90A-NEXT: v_sub_co_u32_e32 v7, vcc, s6, v7
; GFX90A-NEXT: v_subb_co_u32_e64 v6, s[0:1], v6, v8, vcc ; GFX90A-NEXT: v_subb_co_u32_e64 v6, s[0:1], v6, v8, vcc
; GFX90A-NEXT: v_subrev_co_u32_e64 v8, s[0:1], s8, v7 ; GFX90A-NEXT: v_subrev_co_u32_e64 v8, s[0:1], s8, v7
; GFX90A-NEXT: v_subbrev_co_u32_e64 v6, s[0:1], 0, v6, s[0:1] ; GFX90A-NEXT: v_subbrev_co_u32_e64 v6, s[0:1], 0, v6, s[0:1]
; GFX90A-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v6 ; GFX90A-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v6
; GFX90A-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1]
; GFX90A-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v8 ; GFX90A-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v8
; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
; GFX90A-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v6 ; GFX90A-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v6
; GFX90A-NEXT: v_cndmask_b32_e64 v6, v9, v8, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v6, v9, v8, s[0:1]
; GFX90A-NEXT: v_mov_b32_e32 v9, s7 ; GFX90A-NEXT: v_mov_b32_e32 v9, s7
; GFX90A-NEXT: v_subb_co_u32_e32 v5, vcc, v9, v5, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v5, vcc, v9, v5, vcc
; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s9, v5 ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s9, v5
; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 ; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
; GFX90A-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s8, v7 ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s8, v7
; GFX90A-NEXT: v_cndmask_b32_e64 v6, 1, 2, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v6, 1, 2, s[0:1]
; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, s9, v5 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, s9, v5
; GFX90A-NEXT: v_add_co_u32_e64 v6, s[0:1], v1, v6 ; GFX90A-NEXT: v_add_co_u32_e64 v6, s[0:1], v2, v6
; GFX90A-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc
; GFX90A-NEXT: v_addc_co_u32_e64 v8, s[0:1], 0, v4, s[0:1] ; GFX90A-NEXT: v_addc_co_u32_e64 v8, s[0:1], 0, v3, s[0:1]
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX90A-NEXT: s_xor_b64 s[0:1], s[10:11], s[4:5] ; GFX90A-NEXT: s_xor_b64 s[0:1], s[10:11], s[4:5]
; GFX90A-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX90A-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX90A-NEXT: v_xor_b32_e32 v2, s0, v2
; GFX90A-NEXT: v_xor_b32_e32 v5, s1, v4 ; GFX90A-NEXT: v_xor_b32_e32 v3, s1, v3
; GFX90A-NEXT: v_mov_b32_e32 v6, s1 ; GFX90A-NEXT: v_mov_b32_e32 v5, s1
; GFX90A-NEXT: v_subrev_co_u32_e32 v4, vcc, s0, v1 ; GFX90A-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v2
; GFX90A-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v6, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v5, vcc
; GFX90A-NEXT: global_store_dwordx4 v0, v[2:5], s[2:3] ; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = sdiv <2 x i64> %x, %shl.y %r = sdiv <2 x i64> %x, %shl.y
store <2 x i64> %r, <2 x i64> addrspace(1)* %out store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
; CHECK-LABEL: @srem_i64_oddk_denom( ; CHECK-LABEL: @srem_i64_oddk_denom(
; CHECK-NEXT: [[R:%.*]] = srem i64 [[X:%.*]], 1235195 ; CHECK-NEXT: [[R:%.*]] = srem i64 [[X:%.*]], 1235195
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4 ; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: srem_i64_oddk_denom: ; GFX6-LABEL: srem_i64_oddk_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX6-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_mov_b32 s2, 0xffed2705 ; GFX6-NEXT: s_mov_b32 s4, 0xffed2705
; GFX6-NEXT: v_mov_b32_e32 v8, 0 ; GFX6-NEXT: v_mov_b32_e32 v8, 0
; GFX6-NEXT: v_mov_b32_e32 v7, 0 ; GFX6-NEXT: v_mov_b32_e32 v7, 0
; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s4
; GFX6-NEXT: v_mul_hi_u32 v3, v0, s2 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s4
; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s4
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, s8 ; GFX6-NEXT: s_ashr_i32 s8, s3, 31
; GFX6-NEXT: s_add_u32 s2, s2, s8
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX6-NEXT: v_mul_lo_u32 v4, v2, s2
; GFX6-NEXT: v_mul_hi_u32 v5, v0, s2
; GFX6-NEXT: s_mov_b32 s5, s9
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_mul_lo_u32 v5, v0, s2
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4
; GFX6-NEXT: v_mul_lo_u32 v10, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v11, v0, v5
; GFX6-NEXT: v_mul_hi_u32 v12, v0, v4
; GFX6-NEXT: v_mul_hi_u32 v9, v2, v5
; GFX6-NEXT: v_mul_lo_u32 v5, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v6, v2, v4
; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GFX6-NEXT: v_addc_u32_e32 v11, vcc, v8, v12, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v10, v5
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v11, v9, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: s_ashr_i32 s2, s11, 31
; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
; GFX6-NEXT: s_add_u32 s0, s10, s2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: s_mov_b32 s3, s2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: s_addc_u32 s1, s11, s2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s4
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s4
; GFX6-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3] ; GFX6-NEXT: s_mov_b32 s9, s8
; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1 ; GFX6-NEXT: s_addc_u32 s3, s3, s8
; GFX6-NEXT: v_mul_hi_u32 v3, s0, v0 ; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9]
; GFX6-NEXT: v_mul_hi_u32 v4, s0, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_hi_u32 v5, s1, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s4
; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GFX6-NEXT: v_mul_lo_u32 v6, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v0, v3
; GFX6-NEXT: v_mul_hi_u32 v10, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v2
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v9, v5, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: s_mov_b32 s3, 0x12d8fb ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX6-NEXT: v_mul_hi_u32 v4, s2, v1
; GFX6-NEXT: v_mul_hi_u32 v5, s3, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0
; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: s_mov_b32 s0, 0x12d8fb
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s0
; GFX6-NEXT: v_mul_hi_u32 v2, v0, s3 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, s0
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s0
; GFX6-NEXT: s_mov_b32 s5, s1
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_mov_b32_e32 v2, s1 ; GFX6-NEXT: v_mov_b32_e32 v2, s3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v0 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v0
; GFX6-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc ; GFX6-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s3, v2 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s0, v2
; GFX6-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v3, vcc ; GFX6-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
; GFX6-NEXT: s_mov_b32 s0, 0x12d8fa ; GFX6-NEXT: s_mov_b32 s0, 0x12d8fa
; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v2 ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v2
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX6-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v0 ; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
; GFX6-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GFX6-NEXT: v_xor_b32_e32 v0, s2, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s8, v0
; GFX6-NEXT: v_xor_b32_e32 v1, s2, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s8, v1
; GFX6-NEXT: v_mov_b32_e32 v2, s2 ; GFX6-NEXT: v_mov_b32_e32 v2, s8
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: srem_i64_oddk_denom: ; GFX9-LABEL: srem_i64_oddk_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_mov_b32 s8, 0xffed2705 ; GFX9-NEXT: s_mov_b32 s4, 0xffed2705
; GFX9-NEXT: v_mov_b32_e32 v7, 0 ; GFX9-NEXT: v_mov_b32_e32 v7, 0
; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s4
; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s4
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s0, s7, 31
; GFX9-NEXT: s_mov_b32 s1, s0
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v2
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v4, v2, s8
; GFX9-NEXT: v_mul_hi_u32 v6, v0, s8
; GFX9-NEXT: v_mul_lo_u32 v8, v0, s8
; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
; GFX9-NEXT: v_add_u32_e32 v4, v6, v4
; GFX9-NEXT: v_sub_u32_e32 v4, v4, v0
; GFX9-NEXT: v_mul_lo_u32 v10, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v11, v0, v8
; GFX9-NEXT: v_mul_hi_u32 v12, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v9, v2, v8
; GFX9-NEXT: v_mul_lo_u32 v8, v2, v8
; GFX9-NEXT: v_mul_hi_u32 v6, v2, v4
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v7, v12, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v2, v4
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
; GFX9-NEXT: s_add_u32 s2, s6, s0
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: s_addc_u32 s3, s7, s0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s4
; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1] ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s4
; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s4, s3, 31
; GFX9-NEXT: s_add_u32 s2, s2, s4
; GFX9-NEXT: v_add_u32_e32 v2, v3, v2
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0
; GFX9-NEXT: v_mul_lo_u32 v8, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v9, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v10, v0, v2
; GFX9-NEXT: v_mul_hi_u32 v6, v1, v4
; GFX9-NEXT: v_mul_lo_u32 v4, v1, v4
; GFX9-NEXT: v_mul_hi_u32 v3, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v7, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX9-NEXT: s_mov_b32 s5, s4
; GFX9-NEXT: s_addc_u32 s3, s3, s4
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
; GFX9-NEXT: v_mul_lo_u32 v2, s2, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, s2, v1
; GFX9-NEXT: v_mul_hi_u32 v3, s2, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, s2, v0
; GFX9-NEXT: v_mul_hi_u32 v4, s2, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s2, v1
; GFX9-NEXT: v_mul_hi_u32 v6, s3, v1 ; GFX9-NEXT: v_mul_hi_u32 v6, s3, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s3, v1
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s3, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s3, v0
; GFX9-NEXT: v_mul_hi_u32 v0, s3, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s3, v0
; GFX9-NEXT: s_mov_b32 s1, 0x12d8fb ; GFX9-NEXT: s_mov_b32 s5, 0x12d8fb
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s1 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s5
; GFX9-NEXT: v_mul_hi_u32 v2, v0, s1 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, s5
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s1 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s5
; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s3 ; GFX9-NEXT: v_mov_b32_e32 v2, s3
; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s2, v0 ; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s2, v0
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s1, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s5, v0
; GFX9-NEXT: v_subbrev_co_u32_e32 v3, vcc, 0, v1, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s1, v2 ; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s5, v2
; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc ; GFX9-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v3, vcc
; GFX9-NEXT: s_mov_b32 s1, 0x12d8fa ; GFX9-NEXT: s_mov_b32 s2, 0x12d8fa
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s1, v2 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s2, v2
; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GFX9-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s1, v0 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s2, v0
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX9-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX9-NEXT: v_xor_b32_e32 v0, s4, v0
; GFX9-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s4, v0
; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5] ; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX90A-LABEL: srem_i64_oddk_denom: ; GFX90A-LABEL: srem_i64_oddk_denom:
; GFX90A: ; %bb.0: ; GFX90A: ; %bb.0:
; GFX90A-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GFX90A-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX90A-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8
; GFX90A-NEXT: v_rcp_f32_e32 v0, v0 ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0
; GFX90A-NEXT: s_mov_b32 s2, 0xffed2705 ; GFX90A-NEXT: s_mov_b32 s4, 0xffed2705
; GFX90A-NEXT: v_mov_b32_e32 v8, 0 ; GFX90A-NEXT: v_mov_b32_e32 v8, 0
; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v2, 0
; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX90A-NEXT: v_trunc_f32_e32 v1, v1 ; GFX90A-NEXT: v_trunc_f32_e32 v1, v1
; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s2 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s4
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s2 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s4
; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3
; GFX90A-NEXT: v_sub_u32_e32 v3, v3, v0 ; GFX90A-NEXT: v_sub_u32_e32 v3, v3, v0
; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s2 ; GFX90A-NEXT: v_mul_lo_u32 v6, v0, s4
; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 ; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e64 v0, s[0:1], v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX90A-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[0:1] ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v5, v3, s2 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s4
; GFX90A-NEXT: v_mul_hi_u32 v6, v0, s2 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s4
; GFX90A-NEXT: v_add_u32_e32 v5, v6, v5 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3
; GFX90A-NEXT: v_sub_u32_e32 v5, v5, v0 ; GFX90A-NEXT: v_sub_u32_e32 v3, v3, v0
; GFX90A-NEXT: v_mul_lo_u32 v7, v0, s2 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, s4
; GFX90A-NEXT: v_mul_hi_u32 v9, v3, v7 ; GFX90A-NEXT: v_mul_hi_u32 v6, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v10, v3, v7 ; GFX90A-NEXT: v_mul_lo_u32 v7, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v12, v0, v5 ; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v3
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v7 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5
; GFX90A-NEXT: v_mul_hi_u32 v11, v0, v5 ; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v3
; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v12 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10
; GFX90A-NEXT: v_addc_co_u32_e32 v11, vcc, v8, v11, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, v8, v9, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v10 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7
; GFX90A-NEXT: v_mul_hi_u32 v6, v3, v5 ; GFX90A-NEXT: v_mul_hi_u32 v4, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v11, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v6, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v3, v5 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v6, vcc
; GFX90A-NEXT: v_add_u32_e32 v1, v1, v4
; GFX90A-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[0:1]
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_ashr_i32 s0, s7, 31 ; GFX90A-NEXT: s_ashr_i32 s4, s3, 31
; GFX90A-NEXT: s_add_u32 s2, s6, s0 ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
; GFX90A-NEXT: s_add_u32 s2, s2, s4
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX90A-NEXT: s_mov_b32 s1, s0 ; GFX90A-NEXT: s_mov_b32 s5, s4
; GFX90A-NEXT: s_addc_u32 s3, s7, s0 ; GFX90A-NEXT: s_addc_u32 s3, s3, s4
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX90A-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1] ; GFX90A-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
; GFX90A-NEXT: v_mul_lo_u32 v4, s2, v1 ; GFX90A-NEXT: v_mul_lo_u32 v4, s2, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s2, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s2, v0
; GFX90A-NEXT: v_mul_hi_u32 v3, s2, v1 ; GFX90A-NEXT: v_mul_hi_u32 v3, s2, v1
; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
; GFX90A-NEXT: v_mul_hi_u32 v6, s3, v0 ; GFX90A-NEXT: v_mul_hi_u32 v6, s3, v0
; GFX90A-NEXT: v_mul_lo_u32 v0, s3, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s3, v0
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0
; GFX90A-NEXT: v_mul_hi_u32 v5, s3, v1 ; GFX90A-NEXT: v_mul_hi_u32 v5, s3, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v6, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX90A-NEXT: v_mul_lo_u32 v1, s3, v1
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v3, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v3, vcc
; GFX90A-NEXT: s_mov_b32 s1, 0x12d8fb ; GFX90A-NEXT: s_mov_b32 s5, 0x12d8fb
; GFX90A-NEXT: v_mul_lo_u32 v1, v1, s1 ; GFX90A-NEXT: v_mul_lo_u32 v1, v1, s5
; GFX90A-NEXT: v_mul_hi_u32 v3, v0, s1 ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, s5
; GFX90A-NEXT: v_mul_lo_u32 v0, v0, s1 ; GFX90A-NEXT: v_mul_lo_u32 v0, v0, s5
; GFX90A-NEXT: v_add_u32_e32 v1, v3, v1 ; GFX90A-NEXT: v_add_u32_e32 v1, v3, v1
; GFX90A-NEXT: v_mov_b32_e32 v3, s3 ; GFX90A-NEXT: v_mov_b32_e32 v3, s3
; GFX90A-NEXT: v_sub_co_u32_e32 v0, vcc, s2, v0 ; GFX90A-NEXT: v_sub_co_u32_e32 v0, vcc, s2, v0
; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v3, v1, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v3, v1, vcc
; GFX90A-NEXT: v_subrev_co_u32_e32 v3, vcc, s1, v0 ; GFX90A-NEXT: v_subrev_co_u32_e32 v3, vcc, s5, v0
; GFX90A-NEXT: v_subbrev_co_u32_e32 v4, vcc, 0, v1, vcc ; GFX90A-NEXT: v_subbrev_co_u32_e32 v4, vcc, 0, v1, vcc
; GFX90A-NEXT: v_subrev_co_u32_e32 v5, vcc, s1, v3 ; GFX90A-NEXT: v_subrev_co_u32_e32 v5, vcc, s5, v3
; GFX90A-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v4, vcc ; GFX90A-NEXT: v_subbrev_co_u32_e32 v6, vcc, 0, v4, vcc
; GFX90A-NEXT: s_mov_b32 s1, 0x12d8fa ; GFX90A-NEXT: s_mov_b32 s2, 0x12d8fa
; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s1, v3 ; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s2, v3
; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
; GFX90A-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s1, v0 ; GFX90A-NEXT: v_cmp_lt_u32_e32 vcc, s2, v0
; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GFX90A-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX90A-NEXT: v_xor_b32_e32 v0, s0, v0 ; GFX90A-NEXT: v_xor_b32_e32 v0, s4, v0
; GFX90A-NEXT: v_xor_b32_e32 v1, s0, v1 ; GFX90A-NEXT: v_xor_b32_e32 v1, s4, v1
; GFX90A-NEXT: v_mov_b32_e32 v3, s0 ; GFX90A-NEXT: v_mov_b32_e32 v3, s4
; GFX90A-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0 ; GFX90A-NEXT: v_subrev_co_u32_e32 v0, vcc, s4, v0
; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; GFX90A-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
%r = srem i64 %x, 1235195 %r = srem i64 %x, 1235195
store i64 %r, i64 addrspace(1)* %out store i64 %r, i64 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @srem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @srem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
; CHECK-LABEL: @srem_i64_pow2k_denom( ; CHECK-LABEL: @srem_i64_pow2k_denom(
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]] ; CHECK-NEXT: [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = srem i64 [[X:%.*]], [[SHL_Y]] ; CHECK-NEXT: [[R:%.*]] = srem i64 [[X:%.*]], [[SHL_Y]]
; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4 ; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; GFX6-LABEL: srem_i64_pow2_shl_denom: ; GFX6-LABEL: srem_i64_pow2_shl_denom:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s4, s[0:1], 0xd ; GFX6-NEXT: s_load_dword s4, s[0:1], 0xd
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
; GFX6-NEXT: s_mov_b64 s[2:3], 0x1000 ; GFX6-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
; GFX6-NEXT: s_ashr_i32 s4, s3, 31 ; GFX6-NEXT: s_ashr_i32 s4, s3, 31
; GFX6-NEXT: s_add_u32 s2, s2, s4 ; GFX6-NEXT: s_add_u32 s2, s2, s4
; GFX6-NEXT: s_mov_b32 s5, s4 ; GFX6-NEXT: s_mov_b32 s5, s4
; GFX6-NEXT: s_addc_u32 s3, s3, s4 ; GFX6-NEXT: s_addc_u32 s3, s3, s4
; GFX6-NEXT: s_xor_b64 s[12:13], s[2:3], s[4:5] ; GFX6-NEXT: s_xor_b64 s[8:9], s[2:3], s[4:5]
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s13 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX6-NEXT: s_sub_u32 s2, 0, s12 ; GFX6-NEXT: s_sub_u32 s4, 0, s8
; GFX6-NEXT: s_subb_u32 s3, 0, s13 ; GFX6-NEXT: s_subb_u32 s5, 0, s9
; GFX6-NEXT: s_ashr_i32 s14, s11, 31 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_mov_b32 s15, s14 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, s8 ; GFX6-NEXT: s_ashr_i32 s10, s3, 31
; GFX6-NEXT: s_mov_b32 s5, s9
; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1 ; GFX6-NEXT: s_add_u32 s2, s2, s10
; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0 ; GFX6-NEXT: s_mov_b32 s11, s10
; GFX6-NEXT: v_mul_lo_u32 v5, s3, v0 ; GFX6-NEXT: v_mul_lo_u32 v2, s4, v1
; GFX6-NEXT: v_mul_lo_u32 v4, s2, v0 ; GFX6-NEXT: v_mul_hi_u32 v3, s4, v0
; GFX6-NEXT: v_mul_lo_u32 v5, s5, v0
; GFX6-NEXT: v_mul_lo_u32 v4, s4, v0
; GFX6-NEXT: s_addc_u32 s3, s3, s10
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4
; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2 ; GFX6-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4
; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
; GFX6-NEXT: s_xor_b64 s[12:13], s[2:3], s[10:11]
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
; GFX6-NEXT: v_mov_b32_e32 v4, 0 ; GFX6-NEXT: v_mov_b32_e32 v4, 0
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
; GFX6-NEXT: v_mov_b32_e32 v6, 0 ; GFX6-NEXT: v_mov_b32_e32 v6, 0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
; GFX6-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GFX6-NEXT: v_mul_lo_u32 v5, s2, v2
; GFX6-NEXT: v_mul_hi_u32 v7, s2, v0
; GFX6-NEXT: v_mul_lo_u32 v8, s3, v0
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GFX6-NEXT: v_mul_lo_u32 v7, s2, v0
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GFX6-NEXT: v_mul_lo_u32 v10, v0, v5
; GFX6-NEXT: v_mul_hi_u32 v11, v0, v7
; GFX6-NEXT: v_mul_hi_u32 v12, v0, v5
; GFX6-NEXT: v_mul_hi_u32 v9, v2, v7
; GFX6-NEXT: v_mul_lo_u32 v7, v2, v7
; GFX6-NEXT: v_mul_hi_u32 v8, v2, v5
; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v2, v5
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
; GFX6-NEXT: s_add_u32 s0, s10, s14
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: s_addc_u32 s1, s11, s14 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s4, v1
; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15] ; GFX6-NEXT: v_mul_hi_u32 v3, s4, v0
; GFX6-NEXT: v_mul_lo_u32 v2, s10, v1 ; GFX6-NEXT: v_mul_lo_u32 v5, s5, v0
; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0 ; GFX6-NEXT: s_mov_b32 s5, s1
; GFX6-NEXT: v_mul_hi_u32 v5, s10, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_mul_hi_u32 v7, s11, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, s4, v0
; GFX6-NEXT: v_mul_lo_u32 v1, s11, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GFX6-NEXT: v_mul_lo_u32 v8, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v9, v0, v3
; GFX6-NEXT: v_mul_hi_u32 v10, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX6-NEXT: v_mul_hi_u32 v5, v1, v2
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v8, v3
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v9, v7, vcc
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_mul_lo_u32 v2, s12, v1
; GFX6-NEXT: v_mul_hi_u32 v3, s12, v0
; GFX6-NEXT: v_mul_hi_u32 v5, s12, v1
; GFX6-NEXT: v_mul_hi_u32 v7, s13, v1
; GFX6-NEXT: v_mul_lo_u32 v1, s13, v1
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, s11, v0 ; GFX6-NEXT: v_mul_lo_u32 v5, s13, v0
; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s13, v0
; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
; GFX6-NEXT: v_mul_lo_u32 v1, s12, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s8, v1
; GFX6-NEXT: v_mul_hi_u32 v2, s12, v0 ; GFX6-NEXT: v_mul_hi_u32 v2, s8, v0
; GFX6-NEXT: v_mul_lo_u32 v3, s13, v0 ; GFX6-NEXT: v_mul_lo_u32 v3, s9, v0
; GFX6-NEXT: v_mul_lo_u32 v0, s12, v0 ; GFX6-NEXT: v_mul_lo_u32 v0, s8, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s11, v1 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s13, v1
; GFX6-NEXT: v_mov_b32_e32 v3, s13 ; GFX6-NEXT: v_mov_b32_e32 v3, s9
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s10, v0 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s12, v0
; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc ; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0 ; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s8, v0
; GFX6-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v5 ; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s9, v5
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3] ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3]
; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v4 ; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s8, v4
; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1] ; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] ; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v5 ; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s9, v5
; GFX6-NEXT: v_subrev_i32_e64 v3, s[0:1], s12, v4 ; GFX6-NEXT: v_subrev_i32_e64 v3, s[0:1], s8, v4
; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3] ; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3]
; GFX6-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] ; GFX6-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
; GFX6-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
; GFX6-NEXT: v_mov_b32_e32 v5, s11 ; GFX6-NEXT: v_mov_b32_e32 v5, s13
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v5, v1, vcc ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v5, v1, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v1 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1
; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v2, v4, v3, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, s14, v0 ; GFX6-NEXT: v_xor_b32_e32 v0, s10, v0
; GFX6-NEXT: v_xor_b32_e32 v1, s14, v1 ; GFX6-NEXT: v_xor_b32_e32 v1, s10, v1
; GFX6-NEXT: v_mov_b32_e32 v2, s14 ; GFX6-NEXT: v_mov_b32_e32 v2, s10
; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s14, v0 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s10, v0
; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX9-LABEL: srem_i64_pow2_shl_denom: ; GFX9-LABEL: srem_i64_pow2_shl_denom:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s4, s[0:1], 0x34 ; GFX9-NEXT: s_load_dword s4, s[0:1], 0x34
; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000 ; GFX9-NEXT: s_mov_b64 s[2:3], 0x1000
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
; GFX9-NEXT: s_ashr_i32 s4, s3, 31 ; GFX9-NEXT: s_ashr_i32 s4, s3, 31
; GFX9-NEXT: s_add_u32 s2, s2, s4 ; GFX9-NEXT: s_add_u32 s2, s2, s4
; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_mov_b32 s5, s4
; GFX9-NEXT: s_addc_u32 s3, s3, s4 ; GFX9-NEXT: s_addc_u32 s3, s3, s4
; GFX9-NEXT: s_xor_b64 s[8:9], s[2:3], s[4:5] ; GFX9-NEXT: s_xor_b64 s[8:9], s[2:3], s[4:5]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX9-NEXT: s_sub_u32 s10, 0, s8 ; GFX9-NEXT: s_sub_u32 s2, 0, s8
; GFX9-NEXT: s_subb_u32 s4, 0, s9 ; GFX9-NEXT: s_subb_u32 s3, 0, s9
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s10, s7, 31
; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1 ; GFX9-NEXT: s_add_u32 s0, s6, s10
; GFX9-NEXT: v_mul_hi_u32 v4, s10, v0 ; GFX9-NEXT: s_mov_b32 s11, s10
; GFX9-NEXT: v_mul_lo_u32 v6, s4, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, s2, v1
; GFX9-NEXT: v_mul_lo_u32 v5, s10, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s2, v0
; GFX9-NEXT: v_mul_lo_u32 v6, s3, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s2, v0
; GFX9-NEXT: s_addc_u32 s1, s7, s10
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_add_u32_e32 v3, v3, v6 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v6
; GFX9-NEXT: v_mul_hi_u32 v4, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v4, v0, v5
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v3 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v3 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v7, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v7, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mov_b32_e32 v6, 0
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_co_u32_e64 v0, s[2:3], v0, v3
; GFX9-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3]
; GFX9-NEXT: v_mul_lo_u32 v5, s10, v3
; GFX9-NEXT: v_mul_hi_u32 v7, s10, v0
; GFX9-NEXT: v_mul_lo_u32 v8, s4, v0
; GFX9-NEXT: v_mul_lo_u32 v9, s10, v0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_add_u32_e32 v5, v7, v5
; GFX9-NEXT: v_add_u32_e32 v5, v5, v8
; GFX9-NEXT: v_mul_lo_u32 v10, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v11, v0, v9
; GFX9-NEXT: v_mul_hi_u32 v12, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v8, v3, v9
; GFX9-NEXT: v_mul_lo_u32 v9, v3, v9
; GFX9-NEXT: v_mul_hi_u32 v7, v3, v5
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v3, v5
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s10, s7, 31
; GFX9-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
; GFX9-NEXT: s_add_u32 s0, s6, s10
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: s_mov_b32 s11, s10 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX9-NEXT: s_addc_u32 s1, s7, s10 ; GFX9-NEXT: v_mul_lo_u32 v3, s2, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_mul_hi_u32 v4, s2, v0
; GFX9-NEXT: v_mul_lo_u32 v5, s3, v0
; GFX9-NEXT: v_mul_lo_u32 v7, s2, v0
; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11] ; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11]
; GFX9-NEXT: v_add_u32_e32 v3, v4, v3
; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
; GFX9-NEXT: v_mul_lo_u32 v8, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v9, v0, v7
; GFX9-NEXT: v_mul_hi_u32 v10, v0, v3
; GFX9-NEXT: v_mul_hi_u32 v5, v1, v7
; GFX9-NEXT: v_mul_lo_u32 v7, v1, v7
; GFX9-NEXT: v_mul_hi_u32 v4, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, s6, v1 ; GFX9-NEXT: v_mul_lo_u32 v3, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0
; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1
; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 ; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1
; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s7, v0
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; GFX90A-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 ; GFX90A-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
; GFX90A-NEXT: s_ashr_i32 s4, s3, 31 ; GFX90A-NEXT: s_ashr_i32 s4, s3, 31
; GFX90A-NEXT: s_add_u32 s2, s2, s4 ; GFX90A-NEXT: s_add_u32 s2, s2, s4
; GFX90A-NEXT: s_mov_b32 s5, s4 ; GFX90A-NEXT: s_mov_b32 s5, s4
; GFX90A-NEXT: s_addc_u32 s3, s3, s4 ; GFX90A-NEXT: s_addc_u32 s3, s3, s4
; GFX90A-NEXT: s_xor_b64 s[8:9], s[2:3], s[4:5] ; GFX90A-NEXT: s_xor_b64 s[8:9], s[2:3], s[4:5]
; GFX90A-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v0, s8
; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s9
; GFX90A-NEXT: s_sub_u32 s2, 0, s8
; GFX90A-NEXT: s_subb_u32 s3, 0, s9
; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX90A-NEXT: s_sub_u32 s0, 0, s8
; GFX90A-NEXT: s_subb_u32 s1, 0, s9
; GFX90A-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GFX90A-NEXT: v_rcp_f32_e32 v0, v0 ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_ashr_i32 s10, s7, 31 ; GFX90A-NEXT: s_ashr_i32 s10, s7, 31
; GFX90A-NEXT: s_mov_b32 s11, s10
; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GFX90A-NEXT: v_trunc_f32_e32 v1, v1 ; GFX90A-NEXT: v_trunc_f32_e32 v1, v1
; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX90A-NEXT: s_mov_b32 s11, s10 ; GFX90A-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX90A-NEXT: v_mul_lo_u32 v3, s2, v1 ; GFX90A-NEXT: v_mul_hi_u32 v5, s0, v0
; GFX90A-NEXT: v_mul_hi_u32 v5, s2, v0 ; GFX90A-NEXT: v_mul_lo_u32 v4, s1, v0
; GFX90A-NEXT: v_mul_lo_u32 v4, s3, v0
; GFX90A-NEXT: v_add_u32_e32 v3, v5, v3 ; GFX90A-NEXT: v_add_u32_e32 v3, v5, v3
; GFX90A-NEXT: v_mul_lo_u32 v6, s2, v0 ; GFX90A-NEXT: v_mul_lo_u32 v6, s0, v0
; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4 ; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4
; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v3
; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6 ; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX90A-NEXT: v_mov_b32_e32 v6, 0 ; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e64 v0, s[0:1], v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX90A-NEXT: v_addc_co_u32_e64 v3, vcc, v1, v4, s[0:1] ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v5, s2, v3 ; GFX90A-NEXT: v_mul_lo_u32 v3, s0, v1
; GFX90A-NEXT: v_mul_hi_u32 v7, s2, v0 ; GFX90A-NEXT: v_mul_hi_u32 v4, s0, v0
; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3
; GFX90A-NEXT: v_mul_lo_u32 v7, s3, v0 ; GFX90A-NEXT: v_mul_lo_u32 v4, s1, v0
; GFX90A-NEXT: v_add_u32_e32 v5, v5, v7 ; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4
; GFX90A-NEXT: v_mul_lo_u32 v8, s2, v0 ; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX90A-NEXT: v_mul_hi_u32 v9, v3, v8 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v10, v3, v8 ; GFX90A-NEXT: v_mul_lo_u32 v8, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v12, v0, v5 ; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v3
; GFX90A-NEXT: v_mul_hi_u32 v8, v0, v8 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5
; GFX90A-NEXT: v_mul_hi_u32 v11, v0, v5 ; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v3
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10
; GFX90A-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8
; GFX90A-NEXT: v_mul_hi_u32 v7, v3, v5 ; GFX90A-NEXT: v_mul_hi_u32 v4, v1, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v7, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v3, v5 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v7, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc
; GFX90A-NEXT: v_add_u32_e32 v1, v1, v4
; GFX90A-NEXT: v_addc_co_u32_e64 v1, vcc, v1, v5, s[0:1]
; GFX90A-NEXT: s_add_u32 s0, s6, s10 ; GFX90A-NEXT: s_add_u32 s0, s6, s10
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3
; GFX90A-NEXT: s_addc_u32 s1, s7, s10 ; GFX90A-NEXT: s_addc_u32 s1, s7, s10
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; GFX90A-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11] ; GFX90A-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11]
; GFX90A-NEXT: v_mul_lo_u32 v4, s6, v1 ; GFX90A-NEXT: v_mul_lo_u32 v4, s6, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0
; GFX90A-NEXT: v_mul_hi_u32 v3, s6, v1 ; GFX90A-NEXT: v_mul_hi_u32 v3, s6, v1
; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX90A-NEXT: v_mul_hi_u32 v7, s7, v0 ; GFX90A-NEXT: v_mul_hi_u32 v7, s7, v0
; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Lines
; GFX6-NEXT: s_ashr_i32 s4, s3, 31 ; GFX6-NEXT: s_ashr_i32 s4, s3, 31
; GFX6-NEXT: s_add_u32 s2, s2, s4 ; GFX6-NEXT: s_add_u32 s2, s2, s4
; GFX6-NEXT: s_mov_b32 s5, s4 ; GFX6-NEXT: s_mov_b32 s5, s4
; GFX6-NEXT: s_addc_u32 s3, s3, s4 ; GFX6-NEXT: s_addc_u32 s3, s3, s4
; GFX6-NEXT: s_xor_b64 s[16:17], s[2:3], s[4:5] ; GFX6-NEXT: s_xor_b64 s[16:17], s[2:3], s[4:5]
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s16 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s16
; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s17 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s17
; GFX6-NEXT: s_mov_b32 s21, 0xcf800000 ; GFX6-NEXT: s_mov_b32 s21, 0xcf800000
; GFX6-NEXT: s_sub_u32 s6, 0, s16 ; GFX6-NEXT: s_sub_u32 s2, 0, s16
; GFX6-NEXT: s_subb_u32 s7, 0, s17 ; GFX6-NEXT: s_subb_u32 s3, 0, s17
; GFX6-NEXT: v_mac_f32_e32 v0, s18, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, s18, v1
; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0
; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd ; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_mul_f32_e32 v0, s19, v0 ; GFX6-NEXT: v_mul_f32_e32 v0, s19, v0
; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0
; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1
; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_ashr_i32 s12, s9, 31 ; GFX6-NEXT: s_ashr_i32 s12, s9, 31
; GFX6-NEXT: s_add_u32 s0, s8, s12 ; GFX6-NEXT: s_add_u32 s0, s8, s12
; GFX6-NEXT: v_mul_lo_u32 v0, s6, v2 ; GFX6-NEXT: v_mul_lo_u32 v0, s2, v2
; GFX6-NEXT: v_mul_hi_u32 v1, s6, v3 ; GFX6-NEXT: v_mul_hi_u32 v1, s2, v3
; GFX6-NEXT: v_mul_lo_u32 v4, s7, v3 ; GFX6-NEXT: v_mul_lo_u32 v4, s3, v3
; GFX6-NEXT: v_mul_lo_u32 v5, s6, v3 ; GFX6-NEXT: v_mul_lo_u32 v5, s2, v3
; GFX6-NEXT: s_mov_b32 s13, s12 ; GFX6-NEXT: s_mov_b32 s13, s12
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v4 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v4
; GFX6-NEXT: v_mul_lo_u32 v0, v3, v1 ; GFX6-NEXT: v_mul_lo_u32 v0, v3, v1
; GFX6-NEXT: v_mul_hi_u32 v4, v3, v5 ; GFX6-NEXT: v_mul_hi_u32 v4, v3, v5
; GFX6-NEXT: v_mul_hi_u32 v6, v3, v1 ; GFX6-NEXT: v_mul_hi_u32 v6, v3, v1
; GFX6-NEXT: v_mul_hi_u32 v7, v2, v1 ; GFX6-NEXT: v_mul_hi_u32 v7, v2, v1
; GFX6-NEXT: s_addc_u32 s1, s9, s12 ; GFX6-NEXT: s_addc_u32 s1, s9, s12
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v0
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, v2, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5 ; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5
; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13] ; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13]
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, v2, v1 ; GFX6-NEXT: v_mul_lo_u32 v5, v2, v1
; GFX6-NEXT: v_mov_b32_e32 v0, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, 0
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v7, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v7, v0, vcc
; GFX6-NEXT: v_mov_b32_e32 v1, 0 ; GFX6-NEXT: v_mov_b32_e32 v1, 0
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v6, vcc
; GFX6-NEXT: v_add_i32_e64 v3, s[2:3], v3, v4
; GFX6-NEXT: v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
; GFX6-NEXT: v_mul_lo_u32 v6, s6, v4
; GFX6-NEXT: v_mul_hi_u32 v7, s6, v3
; GFX6-NEXT: v_mul_lo_u32 v8, s7, v3
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GFX6-NEXT: v_mul_lo_u32 v7, s6, v3
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GFX6-NEXT: v_mul_lo_u32 v10, v3, v6
; GFX6-NEXT: v_mul_hi_u32 v11, v3, v7
; GFX6-NEXT: v_mul_hi_u32 v12, v3, v6
; GFX6-NEXT: v_mul_hi_u32 v9, v4, v7
; GFX6-NEXT: v_mul_lo_u32 v7, v4, v7
; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6
; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v4, v6
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v8, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v1, v6, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s2, v2
; GFX6-NEXT: v_mul_hi_u32 v5, s2, v3
; GFX6-NEXT: v_mul_lo_u32 v6, s3, v3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_mul_lo_u32 v5, s2, v3
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GFX6-NEXT: v_mul_lo_u32 v8, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v9, v3, v5
; GFX6-NEXT: v_mul_hi_u32 v10, v3, v4
; GFX6-NEXT: v_mul_hi_u32 v7, v2, v5
; GFX6-NEXT: v_mul_lo_u32 v5, v2, v5
; GFX6-NEXT: v_mul_hi_u32 v6, v2, v4
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, v2, v4
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v6, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v6, vcc
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc
; GFX6-NEXT: v_mul_lo_u32 v4, s8, v2 ; GFX6-NEXT: v_mul_lo_u32 v4, s8, v2
; GFX6-NEXT: v_mul_hi_u32 v5, s8, v3 ; GFX6-NEXT: v_mul_hi_u32 v5, s8, v3
; GFX6-NEXT: v_mul_hi_u32 v6, s8, v2 ; GFX6-NEXT: v_mul_hi_u32 v6, s8, v2
; GFX6-NEXT: v_mul_hi_u32 v7, s9, v2 ; GFX6-NEXT: v_mul_hi_u32 v7, s9, v2
; GFX6-NEXT: v_mul_lo_u32 v2, s9, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, s9, v2
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
; GFX6-NEXT: v_mul_lo_u32 v6, s9, v3 ; GFX6-NEXT: v_mul_lo_u32 v6, s9, v3
; GFX6-NEXT: v_mul_hi_u32 v3, s9, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, s9, v3
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v1, v4, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v1, v4, vcc
; GFX6-NEXT: v_mul_lo_u32 v3, s16, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, s16, v3
; GFX6-NEXT: v_mul_hi_u32 v4, s16, v2 ; GFX6-NEXT: v_mul_hi_u32 v4, s16, v2
; GFX6-NEXT: v_mul_lo_u32 v5, s17, v2 ; GFX6-NEXT: v_mul_lo_u32 v5, s17, v2
Show All 38 Lines
; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
; GFX6-NEXT: v_mul_f32_e32 v5, s19, v8 ; GFX6-NEXT: v_mul_f32_e32 v5, s19, v8
; GFX6-NEXT: v_mul_f32_e32 v6, s20, v5 ; GFX6-NEXT: v_mul_f32_e32 v6, s20, v5
; GFX6-NEXT: v_trunc_f32_e32 v6, v6 ; GFX6-NEXT: v_trunc_f32_e32 v6, v6
; GFX6-NEXT: v_mac_f32_e32 v5, s21, v6 ; GFX6-NEXT: v_mac_f32_e32 v5, s21, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX6-NEXT: s_sub_u32 s2, 0, s8 ; GFX6-NEXT: s_sub_u32 s0, 0, s8
; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX6-NEXT: v_mul_hi_u32 v4, s2, v5 ; GFX6-NEXT: v_mul_hi_u32 v4, s0, v5
; GFX6-NEXT: v_mul_lo_u32 v7, s2, v6 ; GFX6-NEXT: v_mul_lo_u32 v7, s0, v6
; GFX6-NEXT: s_subb_u32 s3, 0, s9 ; GFX6-NEXT: s_subb_u32 s1, 0, s9
; GFX6-NEXT: v_mul_lo_u32 v8, s3, v5 ; GFX6-NEXT: v_mul_lo_u32 v8, s1, v5
; GFX6-NEXT: s_ashr_i32 s14, s11, 31 ; GFX6-NEXT: s_ashr_i32 s14, s11, 31
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GFX6-NEXT: v_mul_lo_u32 v7, s2, v5 ; GFX6-NEXT: v_mul_lo_u32 v7, s0, v5
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GFX6-NEXT: v_mul_lo_u32 v8, v5, v4 ; GFX6-NEXT: v_mul_lo_u32 v8, v5, v4
; GFX6-NEXT: v_mul_hi_u32 v9, v5, v7 ; GFX6-NEXT: v_mul_hi_u32 v9, v5, v7
; GFX6-NEXT: v_mul_hi_u32 v10, v5, v4 ; GFX6-NEXT: v_mul_hi_u32 v10, v5, v4
; GFX6-NEXT: v_mul_hi_u32 v11, v6, v4 ; GFX6-NEXT: v_mul_hi_u32 v11, v6, v4
; GFX6-NEXT: v_mul_lo_u32 v4, v6, v4 ; GFX6-NEXT: v_mul_lo_u32 v4, v6, v4
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
; GFX6-NEXT: v_mul_lo_u32 v10, v6, v7 ; GFX6-NEXT: v_mul_lo_u32 v10, v6, v7
; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7 ; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7
; GFX6-NEXT: s_mov_b32 s15, s14 ; GFX6-NEXT: s_mov_b32 s15, s14
; GFX6-NEXT: v_xor_b32_e32 v2, s12, v2 ; GFX6-NEXT: v_xor_b32_e32 v2, s12, v2
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v11, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v11, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc
; GFX6-NEXT: v_add_i32_e64 v4, s[0:1], v5, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GFX6-NEXT: v_addc_u32_e64 v5, vcc, v6, v7, s[0:1] ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v6, v7, vcc
; GFX6-NEXT: v_mul_lo_u32 v8, s2, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, s0, v5
; GFX6-NEXT: v_mul_hi_u32 v9, s2, v4 ; GFX6-NEXT: v_mul_hi_u32 v7, s0, v4
; GFX6-NEXT: v_mul_lo_u32 v10, s3, v4 ; GFX6-NEXT: v_mul_lo_u32 v8, s1, v4
; GFX6-NEXT: v_xor_b32_e32 v3, s12, v3 ; GFX6-NEXT: v_xor_b32_e32 v3, s12, v3
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GFX6-NEXT: v_mul_lo_u32 v9, s2, v4 ; GFX6-NEXT: v_mul_lo_u32 v7, s0, v4
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v10, v8 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GFX6-NEXT: v_mul_lo_u32 v12, v4, v8 ; GFX6-NEXT: v_mul_lo_u32 v10, v4, v6
; GFX6-NEXT: v_mul_hi_u32 v13, v4, v9 ; GFX6-NEXT: v_mul_hi_u32 v11, v4, v7
; GFX6-NEXT: v_mul_hi_u32 v14, v4, v8 ; GFX6-NEXT: v_mul_hi_u32 v12, v4, v6
; GFX6-NEXT: v_mul_hi_u32 v11, v5, v9 ; GFX6-NEXT: v_mul_hi_u32 v9, v5, v7
; GFX6-NEXT: v_mul_lo_u32 v9, v5, v9 ; GFX6-NEXT: v_mul_lo_u32 v7, v5, v7
; GFX6-NEXT: v_mul_hi_u32 v10, v5, v8 ; GFX6-NEXT: v_mul_hi_u32 v8, v5, v6
; GFX6-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GFX6-NEXT: v_addc_u32_e32 v13, vcc, 0, v14, vcc ; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
; GFX6-NEXT: v_mul_lo_u32 v5, v5, v8 ; GFX6-NEXT: v_mul_lo_u32 v6, v5, v6
; GFX6-NEXT: v_add_i32_e32 v9, vcc, v12, v9 ; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v13, v11, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v10, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v8, v0, vcc
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v9, v5 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GFX6-NEXT: v_addc_u32_e64 v6, vcc, v6, v8, s[0:1]
; GFX6-NEXT: s_add_u32 s0, s10, s14 ; GFX6-NEXT: s_add_u32 s0, s10, s14
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: s_addc_u32 s1, s11, s14 ; GFX6-NEXT: s_addc_u32 s1, s11, s14
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15] ; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
; GFX6-NEXT: v_mul_lo_u32 v6, s10, v5 ; GFX6-NEXT: v_mul_lo_u32 v6, s10, v5
; GFX6-NEXT: v_mul_hi_u32 v7, s10, v4 ; GFX6-NEXT: v_mul_hi_u32 v7, s10, v4
; GFX6-NEXT: v_mul_hi_u32 v9, s10, v5 ; GFX6-NEXT: v_mul_hi_u32 v9, s10, v5
; GFX6-NEXT: v_mul_hi_u32 v10, s11, v5 ; GFX6-NEXT: v_mul_hi_u32 v10, s11, v5
; GFX6-NEXT: v_mul_lo_u32 v5, s11, v5 ; GFX6-NEXT: v_mul_lo_u32 v5, s11, v5
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_ashr_i32 s4, s3, 31 ; GFX9-NEXT: s_ashr_i32 s4, s3, 31
; GFX9-NEXT: s_add_u32 s2, s2, s4 ; GFX9-NEXT: s_add_u32 s2, s2, s4
; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_mov_b32 s5, s4
; GFX9-NEXT: s_addc_u32 s3, s3, s4 ; GFX9-NEXT: s_addc_u32 s3, s3, s4
; GFX9-NEXT: s_xor_b64 s[12:13], s[2:3], s[4:5] ; GFX9-NEXT: s_xor_b64 s[12:13], s[2:3], s[4:5]
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s12 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s13 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX9-NEXT: s_mov_b32 s19, 0xcf800000 ; GFX9-NEXT: s_mov_b32 s19, 0xcf800000
; GFX9-NEXT: s_sub_u32 s8, 0, s12 ; GFX9-NEXT: s_sub_u32 s2, 0, s12
; GFX9-NEXT: s_subb_u32 s4, 0, s13 ; GFX9-NEXT: s_subb_u32 s3, 0, s13
; GFX9-NEXT: v_mac_f32_e32 v0, s16, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, s16, v1
; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX9-NEXT: v_mul_f32_e32 v0, s17, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, s17, v0
; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0
; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v0
; GFX9-NEXT: v_mul_lo_u32 v0, s8, v2 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mul_hi_u32 v1, s8, v3 ; GFX9-NEXT: s_ashr_i32 s8, s5, 31
; GFX9-NEXT: v_mul_lo_u32 v5, s4, v3 ; GFX9-NEXT: s_mov_b32 s9, s8
; GFX9-NEXT: v_mul_lo_u32 v4, s8, v3 ; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2
; GFX9-NEXT: v_mul_hi_u32 v1, s2, v3
; GFX9-NEXT: v_mul_lo_u32 v5, s3, v3
; GFX9-NEXT: v_mul_lo_u32 v4, s2, v3
; GFX9-NEXT: v_add_u32_e32 v0, v1, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v1, v0
; GFX9-NEXT: v_add_u32_e32 v5, v0, v5 ; GFX9-NEXT: v_add_u32_e32 v5, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v1, v3, v4 ; GFX9-NEXT: v_mul_hi_u32 v1, v3, v4
; GFX9-NEXT: v_mul_lo_u32 v6, v3, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, v3, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v3, v5 ; GFX9-NEXT: v_mul_hi_u32 v7, v3, v5
; GFX9-NEXT: v_mul_hi_u32 v8, v2, v5 ; GFX9-NEXT: v_mul_hi_u32 v8, v2, v5
; GFX9-NEXT: v_mul_lo_u32 v5, v2, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v2, v5
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v6 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v6
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v7, v2, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v2, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v2, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v2, v4
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v7 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v7
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v8, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v8, v0, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v6, vcc
; GFX9-NEXT: v_add_co_u32_e64 v3, s[2:3], v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: v_addc_co_u32_e64 v4, vcc, v2, v5, s[2:3] ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, s8, v4 ; GFX9-NEXT: v_mul_lo_u32 v4, s2, v2
; GFX9-NEXT: v_mul_hi_u32 v7, s8, v3 ; GFX9-NEXT: v_mul_hi_u32 v5, s2, v3
; GFX9-NEXT: v_mul_lo_u32 v8, s4, v3 ; GFX9-NEXT: v_mul_lo_u32 v6, s3, v3
; GFX9-NEXT: v_mul_lo_u32 v9, s8, v3 ; GFX9-NEXT: v_mul_lo_u32 v7, s2, v3
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX9-NEXT: v_add_u32_e32 v6, v7, v6
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: v_mul_lo_u32 v10, v3, v6
; GFX9-NEXT: v_mul_hi_u32 v11, v3, v9
; GFX9-NEXT: v_mul_hi_u32 v12, v3, v6
; GFX9-NEXT: v_mul_hi_u32 v8, v4, v9
; GFX9-NEXT: v_mul_lo_u32 v9, v4, v9
; GFX9-NEXT: v_mul_hi_u32 v7, v4, v6
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, v4, v6
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v1, v6, vcc
; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s8, s5, 31
; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v2, v6, s[2:3]
; GFX9-NEXT: s_add_u32 s2, s4, s8 ; GFX9-NEXT: s_add_u32 s2, s4, s8
; GFX9-NEXT: v_add_u32_e32 v4, v5, v4
; GFX9-NEXT: v_add_u32_e32 v4, v4, v6
; GFX9-NEXT: v_mul_lo_u32 v8, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v9, v3, v7
; GFX9-NEXT: v_mul_hi_u32 v10, v3, v4
; GFX9-NEXT: v_mul_hi_u32 v6, v2, v7
; GFX9-NEXT: v_mul_lo_u32 v7, v2, v7
; GFX9-NEXT: v_mul_hi_u32 v5, v2, v4
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, v2, v4
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v5, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
; GFX9-NEXT: s_mov_b32 s9, s8
; GFX9-NEXT: s_addc_u32 s3, s5, s8 ; GFX9-NEXT: s_addc_u32 s3, s5, s8
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v5, vcc
; GFX9-NEXT: s_xor_b64 s[14:15], s[2:3], s[8:9] ; GFX9-NEXT: s_xor_b64 s[14:15], s[2:3], s[8:9]
; GFX9-NEXT: v_mul_lo_u32 v4, s14, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, s14, v2
; GFX9-NEXT: v_mul_hi_u32 v5, s14, v3 ; GFX9-NEXT: v_mul_hi_u32 v5, s14, v3
; GFX9-NEXT: v_mul_hi_u32 v6, s14, v2 ; GFX9-NEXT: v_mul_hi_u32 v6, s14, v2
; GFX9-NEXT: v_mul_hi_u32 v7, s15, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, s15, v2
; GFX9-NEXT: v_mul_lo_u32 v2, s15, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, s15, v2
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX9-NEXT: v_mul_f32_e32 v5, s17, v6 ; GFX9-NEXT: v_mul_f32_e32 v5, s17, v6
; GFX9-NEXT: v_mul_f32_e32 v6, s18, v5 ; GFX9-NEXT: v_mul_f32_e32 v6, s18, v5
; GFX9-NEXT: v_trunc_f32_e32 v6, v6 ; GFX9-NEXT: v_trunc_f32_e32 v6, v6
; GFX9-NEXT: v_mac_f32_e32 v5, s19, v6 ; GFX9-NEXT: v_mac_f32_e32 v5, s19, v6
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX9-NEXT: s_sub_u32 s2, 0, s10 ; GFX9-NEXT: s_sub_u32 s0, 0, s10
; GFX9-NEXT: s_subb_u32 s3, 0, s11 ; GFX9-NEXT: s_subb_u32 s1, 0, s11
; GFX9-NEXT: v_mul_hi_u32 v7, s2, v5 ; GFX9-NEXT: v_mul_hi_u32 v7, s0, v5
; GFX9-NEXT: v_mul_lo_u32 v8, s2, v6 ; GFX9-NEXT: v_mul_lo_u32 v8, s0, v6
; GFX9-NEXT: v_mul_lo_u32 v9, s3, v5 ; GFX9-NEXT: v_mul_lo_u32 v9, s1, v5
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT: v_mul_lo_u32 v4, s2, v5 ; GFX9-NEXT: v_mul_lo_u32 v4, s0, v5
; GFX9-NEXT: v_add_u32_e32 v7, v7, v8 ; GFX9-NEXT: v_add_u32_e32 v7, v7, v8
; GFX9-NEXT: v_add_u32_e32 v7, v7, v9 ; GFX9-NEXT: v_add_u32_e32 v7, v7, v9
; GFX9-NEXT: v_mul_lo_u32 v8, v5, v7 ; GFX9-NEXT: v_mul_lo_u32 v8, v5, v7
; GFX9-NEXT: v_mul_hi_u32 v9, v5, v4 ; GFX9-NEXT: v_mul_hi_u32 v9, v5, v4
; GFX9-NEXT: v_mul_hi_u32 v10, v5, v7 ; GFX9-NEXT: v_mul_hi_u32 v10, v5, v7
; GFX9-NEXT: v_mul_hi_u32 v11, v6, v7 ; GFX9-NEXT: v_mul_hi_u32 v11, v6, v7
; GFX9-NEXT: v_mul_lo_u32 v7, v6, v7 ; GFX9-NEXT: v_mul_lo_u32 v7, v6, v7
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v6, v4 ; GFX9-NEXT: v_mul_lo_u32 v10, v6, v4
; GFX9-NEXT: v_mul_hi_u32 v4, v6, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v6, v4
; GFX9-NEXT: s_ashr_i32 s12, s7, 31 ; GFX9-NEXT: s_ashr_i32 s12, s7, 31
; GFX9-NEXT: s_mov_b32 s13, s12 ; GFX9-NEXT: s_mov_b32 s13, s12
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v4, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v7 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v7
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v8, vcc
; GFX9-NEXT: v_add_co_u32_e64 v4, s[0:1], v5, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4
; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v6, v7, s[0:1] ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, s2, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, s0, v5
; GFX9-NEXT: v_mul_hi_u32 v9, s2, v4 ; GFX9-NEXT: v_mul_hi_u32 v7, s0, v4
; GFX9-NEXT: v_mul_lo_u32 v10, s3, v4 ; GFX9-NEXT: v_mul_lo_u32 v8, s1, v4
; GFX9-NEXT: v_mul_lo_u32 v11, s2, v4 ; GFX9-NEXT: v_mul_lo_u32 v9, s0, v4
; GFX9-NEXT: v_add_u32_e32 v6, v6, v7
; GFX9-NEXT: v_add_u32_e32 v8, v9, v8
; GFX9-NEXT: v_add_u32_e32 v8, v8, v10
; GFX9-NEXT: v_mul_lo_u32 v12, v4, v8
; GFX9-NEXT: v_mul_hi_u32 v13, v4, v11
; GFX9-NEXT: v_mul_hi_u32 v14, v4, v8
; GFX9-NEXT: v_mul_hi_u32 v10, v5, v11
; GFX9-NEXT: v_mul_lo_u32 v11, v5, v11
; GFX9-NEXT: v_mul_hi_u32 v9, v5, v8
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v13, v12
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v14, vcc
; GFX9-NEXT: v_mul_lo_u32 v5, v5, v8
; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v10, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v9, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v10, v5
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v1, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[0:1]
; GFX9-NEXT: s_add_u32 s0, s6, s12 ; GFX9-NEXT: s_add_u32 s0, s6, s12
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 ; GFX9-NEXT: v_add_u32_e32 v6, v7, v6
; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
; GFX9-NEXT: v_mul_lo_u32 v10, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v11, v4, v9
; GFX9-NEXT: v_mul_hi_u32 v12, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v8, v5, v9
; GFX9-NEXT: v_mul_lo_u32 v9, v5, v9
; GFX9-NEXT: v_mul_hi_u32 v7, v5, v6
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v0, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v8, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v7, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
; GFX9-NEXT: s_addc_u32 s1, s7, s12 ; GFX9-NEXT: s_addc_u32 s1, s7, s12
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc
; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[12:13] ; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[12:13]
; GFX9-NEXT: v_mul_lo_u32 v6, s6, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, s6, v5
; GFX9-NEXT: v_mul_hi_u32 v7, s6, v4 ; GFX9-NEXT: v_mul_hi_u32 v7, s6, v4
; GFX9-NEXT: v_mul_hi_u32 v9, s6, v5 ; GFX9-NEXT: v_mul_hi_u32 v9, s6, v5
; GFX9-NEXT: v_mul_hi_u32 v10, s7, v5 ; GFX9-NEXT: v_mul_hi_u32 v10, s7, v5
; GFX9-NEXT: v_mul_lo_u32 v5, s7, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, s7, v5
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_lshl_b64 s[10:11], s[2:3], s6 ; GFX90A-NEXT: s_lshl_b64 s[10:11], s[2:3], s6
; GFX90A-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 ; GFX90A-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
; GFX90A-NEXT: s_ashr_i32 s4, s3, 31 ; GFX90A-NEXT: s_ashr_i32 s4, s3, 31
; GFX90A-NEXT: s_add_u32 s2, s2, s4 ; GFX90A-NEXT: s_add_u32 s2, s2, s4
; GFX90A-NEXT: s_mov_b32 s5, s4 ; GFX90A-NEXT: s_mov_b32 s5, s4
; GFX90A-NEXT: s_addc_u32 s3, s3, s4 ; GFX90A-NEXT: s_addc_u32 s3, s3, s4
; GFX90A-NEXT: s_xor_b64 s[12:13], s[2:3], s[4:5] ; GFX90A-NEXT: s_xor_b64 s[12:13], s[2:3], s[4:5]
; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s12 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v0, s12
; GFX90A-NEXT: v_cvt_f32_u32_e32 v2, s13 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s13
; GFX90A-NEXT: s_mov_b32 s19, 0xcf800000 ; GFX90A-NEXT: s_mov_b32 s19, 0xcf800000
; GFX90A-NEXT: s_sub_u32 s2, 0, s12
; GFX90A-NEXT: s_subb_u32 s3, 0, s13
; GFX90A-NEXT: v_mac_f32_e32 v1, s16, v2
; GFX90A-NEXT: v_rcp_f32_e32 v1, v1
; GFX90A-NEXT: v_mov_b32_e32 v0, 0
; GFX90A-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24
; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
; GFX90A-NEXT: v_mul_f32_e32 v1, s17, v1 ; GFX90A-NEXT: s_sub_u32 s0, 0, s12
; GFX90A-NEXT: v_mul_f32_e32 v2, s18, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, s16, v1
; GFX90A-NEXT: v_trunc_f32_e32 v2, v2 ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0
; GFX90A-NEXT: v_mac_f32_e32 v1, s19, v2 ; GFX90A-NEXT: s_subb_u32 s1, 0, s13
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_mov_b32_e32 v4, 0
; GFX90A-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_ashr_i32 s14, s5, 31 ; GFX90A-NEXT: s_ashr_i32 s14, s5, 31
; GFX90A-NEXT: v_mul_f32_e32 v0, s17, v0
; GFX90A-NEXT: v_mul_f32_e32 v1, s18, v0
; GFX90A-NEXT: v_trunc_f32_e32 v1, v1
; GFX90A-NEXT: v_mac_f32_e32 v0, s19, v1
; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX90A-NEXT: s_mov_b32 s15, s14 ; GFX90A-NEXT: s_mov_b32 s15, s14
; GFX90A-NEXT: v_mul_hi_u32 v4, s2, v1 ; GFX90A-NEXT: v_mul_hi_u32 v3, s0, v0
; GFX90A-NEXT: v_mul_lo_u32 v5, s2, v2 ; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v1
; GFX90A-NEXT: v_mul_lo_u32 v3, s3, v1 ; GFX90A-NEXT: v_mul_lo_u32 v2, s1, v0
; GFX90A-NEXT: v_add_u32_e32 v4, v4, v5 ; GFX90A-NEXT: v_add_u32_e32 v3, v3, v5
; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2
; GFX90A-NEXT: v_mul_lo_u32 v6, s2, v1 ; GFX90A-NEXT: v_mul_lo_u32 v6, s0, v0
; GFX90A-NEXT: v_mul_lo_u32 v5, v1, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, v2
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6
; GFX90A-NEXT: v_mul_hi_u32 v4, v1, v3 ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, v2
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX90A-NEXT: v_mul_hi_u32 v8, v2, v6 ; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6
; GFX90A-NEXT: v_mul_lo_u32 v6, v2, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6
; GFX90A-NEXT: v_mul_hi_u32 v7, v2, v3 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v0, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v2, v3 ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX90A-NEXT: v_mov_b32_e32 v6, 0 ; GFX90A-NEXT: v_mov_b32_e32 v6, 0
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
; GFX90A-NEXT: v_add_co_u32_e64 v1, s[0:1], v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX90A-NEXT: v_addc_co_u32_e64 v3, vcc, v2, v4, s[0:1] ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX90A-NEXT: v_mul_lo_u32 v5, s2, v3 ; GFX90A-NEXT: v_mul_lo_u32 v2, s0, v1
; GFX90A-NEXT: v_mul_hi_u32 v7, s2, v1 ; GFX90A-NEXT: v_mul_hi_u32 v3, s0, v0
; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5 ; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2
; GFX90A-NEXT: v_mul_lo_u32 v7, s3, v1 ; GFX90A-NEXT: v_mul_lo_u32 v3, s1, v0
; GFX90A-NEXT: v_add_u32_e32 v5, v5, v7 ; GFX90A-NEXT: v_add_u32_e32 v2, v2, v3
; GFX90A-NEXT: v_mul_lo_u32 v8, s2, v1 ; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v0
; GFX90A-NEXT: v_mul_hi_u32 v9, v3, v8 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v10, v3, v8 ; GFX90A-NEXT: v_mul_lo_u32 v8, v1, v5
; GFX90A-NEXT: v_mul_lo_u32 v12, v1, v5 ; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v2
; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v8 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5
; GFX90A-NEXT: v_mul_hi_u32 v11, v1, v5 ; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v2
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10
; GFX90A-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8
; GFX90A-NEXT: v_mul_hi_u32 v7, v3, v5 ; GFX90A-NEXT: v_mul_hi_u32 v3, v1, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v7, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v0, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v3, v3, v5 ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2
; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v8, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v5, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v7, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
; GFX90A-NEXT: v_add_u32_e32 v2, v2, v4
; GFX90A-NEXT: v_addc_co_u32_e64 v2, vcc, v2, v5, s[0:1]
; GFX90A-NEXT: s_add_u32 s0, s4, s14 ; GFX90A-NEXT: s_add_u32 s0, s4, s14
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; GFX90A-NEXT: s_addc_u32 s1, s5, s14 ; GFX90A-NEXT: s_addc_u32 s1, s5, s14
; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX90A-NEXT: s_xor_b64 s[4:5], s[0:1], s[14:15] ; GFX90A-NEXT: s_xor_b64 s[4:5], s[0:1], s[14:15]
; GFX90A-NEXT: v_mul_lo_u32 v4, s4, v2 ; GFX90A-NEXT: v_mul_lo_u32 v3, s4, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s4, v1 ; GFX90A-NEXT: v_mul_hi_u32 v5, s4, v0
; GFX90A-NEXT: v_mul_hi_u32 v3, s4, v2 ; GFX90A-NEXT: v_mul_hi_u32 v2, s4, v1
; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX90A-NEXT: v_mul_hi_u32 v7, s5, v1 ; GFX90A-NEXT: v_mul_hi_u32 v7, s5, v0
; GFX90A-NEXT: v_mul_lo_u32 v0, s5, v0
; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0
; GFX90A-NEXT: v_mul_hi_u32 v5, s5, v1
; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v2, v7, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v1, s5, v1 ; GFX90A-NEXT: v_mul_lo_u32 v1, s5, v1
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v4, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1
; GFX90A-NEXT: v_mul_hi_u32 v5, s5, v2 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v7, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v0, vcc
; GFX90A-NEXT: v_mul_lo_u32 v2, s5, v2
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v1, v2
; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v3, vcc
; GFX90A-NEXT: v_mul_lo_u32 v2, s12, v2
; GFX90A-NEXT: v_mul_hi_u32 v3, s12, v1
; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2
; GFX90A-NEXT: v_mul_lo_u32 v3, s13, v1
; GFX90A-NEXT: v_add_u32_e32 v2, v2, v3
; GFX90A-NEXT: v_mul_lo_u32 v1, s12, v1 ; GFX90A-NEXT: v_mul_lo_u32 v1, s12, v1
; GFX90A-NEXT: v_sub_u32_e32 v3, s5, v2 ; GFX90A-NEXT: v_mul_hi_u32 v2, s12, v0
; GFX90A-NEXT: v_mov_b32_e32 v4, s13 ; GFX90A-NEXT: v_add_u32_e32 v1, v2, v1
; GFX90A-NEXT: v_sub_co_u32_e32 v1, vcc, s4, v1 ; GFX90A-NEXT: v_mul_lo_u32 v2, s13, v0
; GFX90A-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v4, vcc ; GFX90A-NEXT: v_add_u32_e32 v1, v1, v2
; GFX90A-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s12, v1 ; GFX90A-NEXT: v_mul_lo_u32 v0, s12, v0
; GFX90A-NEXT: v_subbrev_co_u32_e64 v7, s[2:3], 0, v3, s[0:1] ; GFX90A-NEXT: v_sub_u32_e32 v2, s5, v1
; GFX90A-NEXT: v_mov_b32_e32 v3, s13
; GFX90A-NEXT: v_sub_co_u32_e32 v0, vcc, s4, v0
; GFX90A-NEXT: v_subb_co_u32_e64 v2, s[0:1], v2, v3, vcc
; GFX90A-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s12, v0
; GFX90A-NEXT: v_subbrev_co_u32_e64 v7, s[2:3], 0, v2, s[0:1]
; GFX90A-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v7 ; GFX90A-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v7
; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3] ; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3]
; GFX90A-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v5 ; GFX90A-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v5
; GFX90A-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v4, s[0:1] ; GFX90A-NEXT: v_subb_co_u32_e64 v2, s[0:1], v2, v3, s[0:1]
; GFX90A-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3] ; GFX90A-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3]
; GFX90A-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v7 ; GFX90A-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v7
; GFX90A-NEXT: v_subrev_co_u32_e64 v4, s[0:1], s12, v5 ; GFX90A-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s12, v5
; GFX90A-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3] ; GFX90A-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3]
; GFX90A-NEXT: v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1] ; GFX90A-NEXT: v_subbrev_co_u32_e64 v2, s[0:1], 0, v2, s[0:1]
; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8 ; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8
; GFX90A-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[0:1]
; GFX90A-NEXT: v_mov_b32_e32 v5, s5 ; GFX90A-NEXT: v_mov_b32_e32 v5, s5
; GFX90A-NEXT: v_subb_co_u32_e32 v2, vcc, v5, v2, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v5, v1, vcc
; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s13, v2 ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
; GFX90A-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v2, v7, v2, s[0:1]
; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s12, v1 ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
; GFX90A-NEXT: s_ashr_i32 s0, s11, 31 ; GFX90A-NEXT: s_ashr_i32 s0, s11, 31
; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, s13, v2 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1
; GFX90A-NEXT: s_add_u32 s2, s10, s0 ; GFX90A-NEXT: s_add_u32 s2, s10, s0
; GFX90A-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX90A-NEXT: s_mov_b32 s1, s0 ; GFX90A-NEXT: s_mov_b32 s1, s0
; GFX90A-NEXT: s_addc_u32 s3, s11, s0 ; GFX90A-NEXT: s_addc_u32 s3, s11, s0
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GFX90A-NEXT: s_xor_b64 s[4:5], s[2:3], s[0:1] ; GFX90A-NEXT: s_xor_b64 s[4:5], s[2:3], s[0:1]
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX90A-NEXT: v_cvt_f32_u32_e32 v3, s4 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v2, s4
; GFX90A-NEXT: v_cvt_f32_u32_e32 v4, s5 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v3, s5
; GFX90A-NEXT: v_xor_b32_e32 v0, s14, v0
; GFX90A-NEXT: s_sub_u32 s0, 0, s4
; GFX90A-NEXT: v_xor_b32_e32 v1, s14, v1 ; GFX90A-NEXT: v_xor_b32_e32 v1, s14, v1
; GFX90A-NEXT: v_xor_b32_e32 v5, s14, v2 ; GFX90A-NEXT: v_mac_f32_e32 v2, s16, v3
; GFX90A-NEXT: v_subrev_co_u32_e32 v2, vcc, s14, v1 ; GFX90A-NEXT: v_rcp_f32_e32 v2, v2
; GFX90A-NEXT: v_mac_f32_e32 v3, s16, v4 ; GFX90A-NEXT: v_mov_b32_e32 v5, s14
; GFX90A-NEXT: v_rcp_f32_e32 v4, v3 ; GFX90A-NEXT: v_subrev_co_u32_e32 v0, vcc, s14, v0
; GFX90A-NEXT: v_mov_b32_e32 v7, s14 ; GFX90A-NEXT: v_mul_f32_e32 v2, s17, v2
; GFX90A-NEXT: s_sub_u32 s2, 0, s4 ; GFX90A-NEXT: v_mul_f32_e32 v3, s18, v2
; GFX90A-NEXT: v_subb_co_u32_e32 v3, vcc, v5, v7, vcc ; GFX90A-NEXT: v_trunc_f32_e32 v3, v3
; GFX90A-NEXT: v_mul_f32_e32 v1, s17, v4 ; GFX90A-NEXT: v_mac_f32_e32 v2, s19, v3
; GFX90A-NEXT: v_mul_f32_e32 v4, s18, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX90A-NEXT: v_trunc_f32_e32 v4, v4 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v3, v3
; GFX90A-NEXT: v_mac_f32_e32 v1, s19, v4 ; GFX90A-NEXT: s_subb_u32 s1, 0, s5
; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc
; GFX90A-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX90A-NEXT: v_mul_hi_u32 v7, s0, v2
; GFX90A-NEXT: s_subb_u32 s3, 0, s5 ; GFX90A-NEXT: v_mul_lo_u32 v8, s0, v3
; GFX90A-NEXT: s_ashr_i32 s10, s7, 31 ; GFX90A-NEXT: v_mul_lo_u32 v5, s1, v2
; GFX90A-NEXT: v_mul_hi_u32 v7, s2, v1
; GFX90A-NEXT: v_mul_lo_u32 v8, s2, v4
; GFX90A-NEXT: v_mul_lo_u32 v5, s3, v1
; GFX90A-NEXT: v_add_u32_e32 v7, v7, v8 ; GFX90A-NEXT: v_add_u32_e32 v7, v7, v8
; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5 ; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5
; GFX90A-NEXT: v_mul_lo_u32 v9, s2, v1 ; GFX90A-NEXT: v_mul_lo_u32 v9, s0, v2
; GFX90A-NEXT: v_mul_lo_u32 v8, v1, v5 ; GFX90A-NEXT: v_mul_lo_u32 v8, v2, v5
; GFX90A-NEXT: v_mul_hi_u32 v10, v1, v9 ; GFX90A-NEXT: v_mul_hi_u32 v10, v2, v9
; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v5 ; GFX90A-NEXT: v_mul_hi_u32 v7, v2, v5
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8 ; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
; GFX90A-NEXT: v_mul_hi_u32 v11, v4, v9 ; GFX90A-NEXT: v_mul_hi_u32 v11, v3, v9
; GFX90A-NEXT: v_mul_lo_u32 v9, v4, v9 ; GFX90A-NEXT: v_mul_lo_u32 v9, v3, v9
; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v9 ; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v9
; GFX90A-NEXT: v_mul_hi_u32 v10, v4, v5 ; GFX90A-NEXT: v_mul_hi_u32 v10, v3, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v11, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v11, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v10, v0, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v10, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v5, v4, v5 ; GFX90A-NEXT: v_mul_lo_u32 v5, v3, v5
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v6, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v6, v8, vcc
; GFX90A-NEXT: v_add_co_u32_e64 v1, s[0:1], v1, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5
; GFX90A-NEXT: v_addc_co_u32_e64 v5, vcc, v4, v7, s[0:1] ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v7, vcc
; GFX90A-NEXT: v_mul_lo_u32 v8, s2, v5 ; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v3
; GFX90A-NEXT: v_mul_hi_u32 v9, s2, v1 ; GFX90A-NEXT: v_mul_hi_u32 v7, s0, v2
; GFX90A-NEXT: v_add_u32_e32 v8, v9, v8 ; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5
; GFX90A-NEXT: v_mul_lo_u32 v9, s3, v1 ; GFX90A-NEXT: v_mul_lo_u32 v7, s1, v2
; GFX90A-NEXT: v_add_u32_e32 v8, v8, v9 ; GFX90A-NEXT: v_add_u32_e32 v5, v5, v7
; GFX90A-NEXT: v_mul_lo_u32 v10, s2, v1 ; GFX90A-NEXT: v_mul_lo_u32 v8, s0, v2
; GFX90A-NEXT: v_mul_hi_u32 v11, v5, v10 ; GFX90A-NEXT: v_mul_hi_u32 v9, v3, v8
; GFX90A-NEXT: v_mul_lo_u32 v12, v5, v10 ; GFX90A-NEXT: v_mul_lo_u32 v10, v3, v8
; GFX90A-NEXT: v_mul_lo_u32 v14, v1, v8 ; GFX90A-NEXT: v_mul_lo_u32 v12, v2, v5
; GFX90A-NEXT: v_mul_hi_u32 v10, v1, v10 ; GFX90A-NEXT: v_mul_hi_u32 v8, v2, v8
; GFX90A-NEXT: v_mul_hi_u32 v13, v1, v8 ; GFX90A-NEXT: v_mul_hi_u32 v11, v2, v5
; GFX90A-NEXT: v_add_co_u32_e32 v10, vcc, v10, v14 ; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12
; GFX90A-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
; GFX90A-NEXT: v_add_co_u32_e32 v10, vcc, v10, v12 ; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10
; GFX90A-NEXT: v_mul_hi_u32 v9, v5, v8 ; GFX90A-NEXT: v_mul_hi_u32 v7, v3, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v11, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, v9, v0, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v5, v5, v8 ; GFX90A-NEXT: v_mul_lo_u32 v5, v3, v5
; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v10, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v8, v5
; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v6, v9, vcc ; GFX90A-NEXT: s_ashr_i32 s10, s7, 31
; GFX90A-NEXT: v_add_u32_e32 v4, v4, v7 ; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v6, v7, vcc
; GFX90A-NEXT: v_addc_co_u32_e64 v4, vcc, v4, v8, s[0:1]
; GFX90A-NEXT: s_add_u32 s0, s6, s10 ; GFX90A-NEXT: s_add_u32 s0, s6, s10
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v1, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5
; GFX90A-NEXT: s_mov_b32 s11, s10 ; GFX90A-NEXT: s_mov_b32 s11, s10
; GFX90A-NEXT: s_addc_u32 s1, s7, s10 ; GFX90A-NEXT: s_addc_u32 s1, s7, s10
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v7, vcc
; GFX90A-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11] ; GFX90A-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11]
; GFX90A-NEXT: v_mul_lo_u32 v7, s6, v4 ; GFX90A-NEXT: v_mul_lo_u32 v7, s6, v3
; GFX90A-NEXT: v_mul_hi_u32 v8, s6, v1 ; GFX90A-NEXT: v_mul_hi_u32 v8, s6, v2
; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v4 ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v3
; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 ; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX90A-NEXT: v_mul_hi_u32 v9, s7, v1 ; GFX90A-NEXT: v_mul_hi_u32 v9, s7, v2
; GFX90A-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX90A-NEXT: v_mul_lo_u32 v2, s7, v2
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v7, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v7, v2
; GFX90A-NEXT: v_mul_hi_u32 v8, s7, v4 ; GFX90A-NEXT: v_mul_hi_u32 v8, s7, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v9, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v9, vcc
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v0, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
; GFX90A-NEXT: v_mul_lo_u32 v4, s7, v4 ; GFX90A-NEXT: v_mul_lo_u32 v3, s7, v3
; GFX90A-NEXT: v_add_co_u32_e32 v1, vcc, v1, v4 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3
; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
; GFX90A-NEXT: v_mul_lo_u32 v4, s4, v4 ; GFX90A-NEXT: v_mul_lo_u32 v3, s4, v3
; GFX90A-NEXT: v_mul_hi_u32 v5, s4, v1 ; GFX90A-NEXT: v_mul_hi_u32 v5, s4, v2
; GFX90A-NEXT: v_add_u32_e32 v4, v5, v4 ; GFX90A-NEXT: v_add_u32_e32 v3, v5, v3
; GFX90A-NEXT: v_mul_lo_u32 v5, s5, v1 ; GFX90A-NEXT: v_mul_lo_u32 v5, s5, v2
; GFX90A-NEXT: v_add_u32_e32 v4, v4, v5 ; GFX90A-NEXT: v_add_u32_e32 v3, v3, v5
; GFX90A-NEXT: v_mul_lo_u32 v1, s4, v1 ; GFX90A-NEXT: v_mul_lo_u32 v2, s4, v2
; GFX90A-NEXT: v_sub_u32_e32 v5, s7, v4 ; GFX90A-NEXT: v_sub_u32_e32 v5, s7, v3
; GFX90A-NEXT: v_mov_b32_e32 v6, s5 ; GFX90A-NEXT: v_mov_b32_e32 v6, s5
; GFX90A-NEXT: v_sub_co_u32_e32 v1, vcc, s6, v1 ; GFX90A-NEXT: v_sub_co_u32_e32 v2, vcc, s6, v2
; GFX90A-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc ; GFX90A-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc
; GFX90A-NEXT: v_subrev_co_u32_e64 v7, s[0:1], s4, v1 ; GFX90A-NEXT: v_subrev_co_u32_e64 v7, s[0:1], s4, v2
; GFX90A-NEXT: v_subbrev_co_u32_e64 v8, s[2:3], 0, v5, s[0:1] ; GFX90A-NEXT: v_subbrev_co_u32_e64 v8, s[2:3], 0, v5, s[0:1]
; GFX90A-NEXT: v_cmp_le_u32_e64 s[2:3], s5, v8 ; GFX90A-NEXT: v_cmp_le_u32_e64 s[2:3], s5, v8
; GFX90A-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3] ; GFX90A-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3]
; GFX90A-NEXT: v_cmp_le_u32_e64 s[2:3], s4, v7 ; GFX90A-NEXT: v_cmp_le_u32_e64 s[2:3], s4, v7
; GFX90A-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, s[0:1] ; GFX90A-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, s[0:1]
; GFX90A-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[2:3] ; GFX90A-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[2:3]
; GFX90A-NEXT: v_cmp_eq_u32_e64 s[2:3], s5, v8 ; GFX90A-NEXT: v_cmp_eq_u32_e64 s[2:3], s5, v8
; GFX90A-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s4, v7 ; GFX90A-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s4, v7
; GFX90A-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[2:3] ; GFX90A-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[2:3]
; GFX90A-NEXT: v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1] ; GFX90A-NEXT: v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1]
; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9 ; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9
; GFX90A-NEXT: v_cndmask_b32_e64 v6, v7, v6, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v6, v7, v6, s[0:1]
; GFX90A-NEXT: v_mov_b32_e32 v7, s7 ; GFX90A-NEXT: v_mov_b32_e32 v7, s7
; GFX90A-NEXT: v_subb_co_u32_e32 v4, vcc, v7, v4, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v3, vcc, v7, v3, vcc
; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s5, v4 ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s5, v3
; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s4, v1 ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s4, v2
; GFX90A-NEXT: v_cndmask_b32_e64 v5, v8, v5, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v5, v8, v5, s[0:1]
; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, s5, v4 ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, s5, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX90A-NEXT: v_xor_b32_e32 v1, s10, v1 ; GFX90A-NEXT: v_xor_b32_e32 v2, s10, v2
; GFX90A-NEXT: v_xor_b32_e32 v5, s10, v4 ; GFX90A-NEXT: v_xor_b32_e32 v3, s10, v3
; GFX90A-NEXT: v_mov_b32_e32 v6, s10 ; GFX90A-NEXT: v_mov_b32_e32 v5, s10
; GFX90A-NEXT: v_subrev_co_u32_e32 v4, vcc, s10, v1 ; GFX90A-NEXT: v_subrev_co_u32_e32 v2, vcc, s10, v2
; GFX90A-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v6, vcc ; GFX90A-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v5, vcc
; GFX90A-NEXT: global_store_dwordx4 v0, v[2:5], s[8:9] ; GFX90A-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
; GFX90A-NEXT: s_endpgm ; GFX90A-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = srem <2 x i64> %x, %shl.y %r = srem <2 x i64> %x, %shl.y
store <2 x i64> %r, <2 x i64> addrspace(1)* %out store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/bypass-div.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v13, v6, v12 ; GFX9-NEXT: v_mul_lo_u32 v13, v6, v12
; GFX9-NEXT: v_mul_hi_u32 v12, v6, v12 ; GFX9-NEXT: v_mul_hi_u32 v12, v6, v12
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v10, vcc
; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v11, v13 ; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v11, v13
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v10, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v14, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v14, vcc
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v11, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
; GFX9-NEXT: v_add_co_u32_e64 v5, s[4:5], v5, v9 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9
; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5] ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v11, v7, v9 ; GFX9-NEXT: v_mul_lo_u32 v9, v7, v6
; GFX9-NEXT: v_mul_lo_u32 v8, v8, v5 ; GFX9-NEXT: v_mul_lo_u32 v8, v8, v5
; GFX9-NEXT: v_mul_hi_u32 v12, v7, v5 ; GFX9-NEXT: v_mul_hi_u32 v10, v7, v5
; GFX9-NEXT: v_mul_lo_u32 v7, v7, v5 ; GFX9-NEXT: v_mul_lo_u32 v7, v7, v5
; GFX9-NEXT: v_add_u32_e32 v6, v6, v10 ; GFX9-NEXT: v_add3_u32 v8, v10, v9, v8
; GFX9-NEXT: v_add3_u32 v8, v12, v11, v8 ; GFX9-NEXT: v_mul_lo_u32 v11, v5, v8
; GFX9-NEXT: v_mul_lo_u32 v13, v5, v8 ; GFX9-NEXT: v_mul_hi_u32 v12, v5, v7
; GFX9-NEXT: v_mul_hi_u32 v16, v5, v7 ; GFX9-NEXT: v_mul_hi_u32 v13, v5, v8
; GFX9-NEXT: v_mul_hi_u32 v17, v5, v8 ; GFX9-NEXT: v_mul_hi_u32 v10, v6, v7
; GFX9-NEXT: v_mul_hi_u32 v12, v9, v7 ; GFX9-NEXT: v_mul_lo_u32 v7, v6, v7
; GFX9-NEXT: v_mul_lo_u32 v7, v9, v7 ; GFX9-NEXT: v_mul_hi_u32 v9, v6, v8
; GFX9-NEXT: v_mul_hi_u32 v11, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11
; GFX9-NEXT: v_add_co_u32_e32 v13, vcc, v16, v13 ; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, v15, v13, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v16, vcc, v15, v17, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v6, v8
; GFX9-NEXT: v_mul_lo_u32 v8, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v11, v7
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v13, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v12, v10, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v16, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v9, v14, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v11, v14, vcc
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v15, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v15, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v8, vcc
; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v1 ; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v7 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v7
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v7 ; GFX9-NEXT: v_xor_b32_e32 v0, v0, v7
; GFX9-NEXT: v_mul_lo_u32 v8, v0, v6 ; GFX9-NEXT: v_mul_lo_u32 v8, v0, v6
; GFX9-NEXT: v_mul_hi_u32 v9, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v9, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v10, v0, v6 ; GFX9-NEXT: v_mul_hi_u32 v10, v0, v6
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v7, vcc
; GFX9-NEXT: v_xor_b32_e32 v1, v1, v7 ; GFX9-NEXT: v_xor_b32_e32 v1, v1, v7
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v14, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
; GFX9-NEXT: v_mul_lo_u32 v14, v5, v11 ; GFX9-NEXT: v_mul_lo_u32 v14, v5, v11
; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11 ; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v14 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v14
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v8 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8
; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v9, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v6, v8 ; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5
; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4
; GFX9-NEXT: v_mul_hi_u32 v11, v6, v4 ; GFX9-NEXT: v_mul_hi_u32 v9, v6, v4
; GFX9-NEXT: v_mul_lo_u32 v6, v6, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, v6, v4
; GFX9-NEXT: v_add_u32_e32 v5, v5, v9 ; GFX9-NEXT: v_add3_u32 v7, v9, v8, v7
; GFX9-NEXT: v_add3_u32 v7, v11, v10, v7
; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7
; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6 ; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v15, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v14, v4, v7
; GFX9-NEXT: v_mul_hi_u32 v14, v8, v7 ; GFX9-NEXT: v_mul_hi_u32 v9, v5, v6
; GFX9-NEXT: v_mul_lo_u32 v7, v8, v7 ; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6
; GFX9-NEXT: v_mul_hi_u32 v8, v5, v7
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_mul_hi_u32 v11, v8, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v13, v14, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v8, v6 ; GFX9-NEXT: v_mul_lo_u32 v7, v5, v7
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v15, v11, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v11, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v14, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v8, v12, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v12, v5, v11 ; GFX9-NEXT: v_mul_lo_u32 v12, v5, v11
; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11 ; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v14, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v14, v9, vcc
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v10, v12 ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v10, v12
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v9, v11, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v9, v11, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v13, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v13, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v14, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v14, v10, vcc
; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v8 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8
; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v9, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v6, v8 ; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5
; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4
; GFX9-NEXT: v_mul_hi_u32 v11, v6, v4 ; GFX9-NEXT: v_mul_hi_u32 v9, v6, v4
; GFX9-NEXT: v_mul_lo_u32 v6, v6, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, v6, v4
; GFX9-NEXT: v_add_u32_e32 v5, v5, v9 ; GFX9-NEXT: v_add3_u32 v7, v9, v8, v7
; GFX9-NEXT: v_add3_u32 v7, v11, v10, v7 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7
; GFX9-NEXT: v_mul_lo_u32 v12, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v15, v4, v6 ; GFX9-NEXT: v_mul_hi_u32 v12, v4, v7
; GFX9-NEXT: v_mul_hi_u32 v16, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v9, v5, v6
; GFX9-NEXT: v_mul_hi_u32 v11, v8, v6 ; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6
; GFX9-NEXT: v_mul_lo_u32 v6, v8, v6 ; GFX9-NEXT: v_mul_hi_u32 v8, v5, v7
; GFX9-NEXT: v_mul_hi_u32 v10, v8, v7 ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, v15, v12 ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v14, v12, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, v14, v16, vcc ; GFX9-NEXT: v_mul_lo_u32 v7, v5, v7
; GFX9-NEXT: v_mul_lo_u32 v7, v8, v7 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v12, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v11, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v15, v11, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v8, v13, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v10, v13, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v14, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v14, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc
; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v1 ; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v6 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v6
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v6 ; GFX9-NEXT: v_xor_b32_e32 v0, v0, v6
; GFX9-NEXT: v_mul_lo_u32 v7, v0, v5 ; GFX9-NEXT: v_mul_lo_u32 v7, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v9, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v9, v0, v5
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v6, vcc
; GFX9-NEXT: v_xor_b32_e32 v1, v1, v6 ; GFX9-NEXT: v_xor_b32_e32 v1, v1, v6
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v14, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
; GFX9-NEXT: v_mul_lo_u32 v14, v5, v11 ; GFX9-NEXT: v_mul_lo_u32 v14, v5, v11
; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11 ; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v14 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v14
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v8 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8
; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v9, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v6, v8 ; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5
; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4
; GFX9-NEXT: v_mul_hi_u32 v11, v6, v4 ; GFX9-NEXT: v_mul_hi_u32 v9, v6, v4
; GFX9-NEXT: v_mul_lo_u32 v6, v6, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, v6, v4
; GFX9-NEXT: v_add_u32_e32 v5, v5, v9 ; GFX9-NEXT: v_add3_u32 v7, v9, v8, v7
; GFX9-NEXT: v_add3_u32 v7, v11, v10, v7
; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7
; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6 ; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v15, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v14, v4, v7
; GFX9-NEXT: v_mul_hi_u32 v14, v8, v7 ; GFX9-NEXT: v_mul_hi_u32 v9, v5, v6
; GFX9-NEXT: v_mul_lo_u32 v7, v8, v7 ; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6
; GFX9-NEXT: v_mul_hi_u32 v8, v5, v7
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_mul_hi_u32 v11, v8, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v13, v14, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v8, v6 ; GFX9-NEXT: v_mul_lo_u32 v7, v5, v7
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v15, v11, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v11, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v14, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v8, v12, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
▲ Show 20 Lines • Show All 240 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mul_lo_u32 v13, v6, v12 ; GFX9-NEXT: v_mul_lo_u32 v13, v6, v12
; GFX9-NEXT: v_mul_hi_u32 v12, v6, v12 ; GFX9-NEXT: v_mul_hi_u32 v12, v6, v12
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v10, vcc
; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v11, v13 ; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v11, v13
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v10, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v14, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v14, vcc
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v11, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
; GFX9-NEXT: v_add_co_u32_e64 v5, s[4:5], v5, v9 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9
; GFX9-NEXT: v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5] ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v10, vcc
; GFX9-NEXT: v_mul_lo_u32 v11, v7, v9 ; GFX9-NEXT: v_mul_lo_u32 v9, v7, v6
; GFX9-NEXT: v_mul_lo_u32 v8, v8, v5 ; GFX9-NEXT: v_mul_lo_u32 v8, v8, v5
; GFX9-NEXT: v_mul_hi_u32 v12, v7, v5 ; GFX9-NEXT: v_mul_hi_u32 v10, v7, v5
; GFX9-NEXT: v_mul_lo_u32 v7, v7, v5 ; GFX9-NEXT: v_mul_lo_u32 v7, v7, v5
; GFX9-NEXT: v_add_u32_e32 v6, v6, v10 ; GFX9-NEXT: v_add3_u32 v8, v10, v9, v8
; GFX9-NEXT: v_add3_u32 v8, v12, v11, v8 ; GFX9-NEXT: v_mul_lo_u32 v11, v5, v8
; GFX9-NEXT: v_mul_lo_u32 v13, v5, v8 ; GFX9-NEXT: v_mul_hi_u32 v12, v5, v7
; GFX9-NEXT: v_mul_hi_u32 v16, v5, v7 ; GFX9-NEXT: v_mul_hi_u32 v13, v5, v8
; GFX9-NEXT: v_mul_hi_u32 v17, v5, v8 ; GFX9-NEXT: v_mul_hi_u32 v10, v6, v7
; GFX9-NEXT: v_mul_hi_u32 v12, v9, v7 ; GFX9-NEXT: v_mul_lo_u32 v7, v6, v7
; GFX9-NEXT: v_mul_lo_u32 v7, v9, v7 ; GFX9-NEXT: v_mul_hi_u32 v9, v6, v8
; GFX9-NEXT: v_mul_hi_u32 v11, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11
; GFX9-NEXT: v_add_co_u32_e32 v13, vcc, v16, v13 ; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, v15, v13, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v16, vcc, v15, v17, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v6, v8
; GFX9-NEXT: v_mul_lo_u32 v8, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v11, v7
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v13, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v12, v10, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v16, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v9, v14, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v11, v14, vcc
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v15, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v15, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7 ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v8, vcc
; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v1 ; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v7 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v7
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v7 ; GFX9-NEXT: v_xor_b32_e32 v0, v0, v7
; GFX9-NEXT: v_mul_lo_u32 v8, v0, v6 ; GFX9-NEXT: v_mul_lo_u32 v8, v0, v6
; GFX9-NEXT: v_mul_hi_u32 v9, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v9, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v10, v0, v6 ; GFX9-NEXT: v_mul_hi_u32 v10, v0, v6
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v7, vcc
; GFX9-NEXT: v_xor_b32_e32 v1, v1, v7 ; GFX9-NEXT: v_xor_b32_e32 v1, v1, v7
▲ Show 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v14, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
; GFX9-NEXT: v_mul_lo_u32 v14, v5, v11 ; GFX9-NEXT: v_mul_lo_u32 v14, v5, v11
; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11 ; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v14 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v14
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
; GFX9-NEXT: v_add_co_u32_e64 v4, s[4:5], v4, v8 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8
; GFX9-NEXT: v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5] ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v9, vcc
; GFX9-NEXT: v_mul_lo_u32 v10, v6, v8 ; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5
; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v7, v4
; GFX9-NEXT: v_mul_hi_u32 v11, v6, v4 ; GFX9-NEXT: v_mul_hi_u32 v9, v6, v4
; GFX9-NEXT: v_mul_lo_u32 v6, v6, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, v6, v4
; GFX9-NEXT: v_add_u32_e32 v5, v5, v9 ; GFX9-NEXT: v_add3_u32 v7, v9, v8, v7
; GFX9-NEXT: v_add3_u32 v7, v11, v10, v7
; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7
; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6 ; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6
; GFX9-NEXT: v_mul_hi_u32 v15, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v14, v4, v7
; GFX9-NEXT: v_mul_hi_u32 v14, v8, v7 ; GFX9-NEXT: v_mul_hi_u32 v9, v5, v6
; GFX9-NEXT: v_mul_lo_u32 v7, v8, v7 ; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6
; GFX9-NEXT: v_mul_hi_u32 v8, v5, v7
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10
; GFX9-NEXT: v_mul_hi_u32 v11, v8, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v13, v14, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v8, v6 ; GFX9-NEXT: v_mul_lo_u32 v7, v5, v7
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v15, v11, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v11, v9, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v14, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v8, v12, vcc
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
; GFX9-NEXT: v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc
; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v7, v0, v4 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v4
; GFX9-NEXT: v_mul_hi_u32 v8, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v5
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5
; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4
▲ Show 20 Lines • Show All 132 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/carryout-selection.ll

Show First 20 Lines • Show All 366 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @vusubo64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a) #0 {
store i1 %carry, i1 addrspace(1)* %carryout store i1 %carry, i1 addrspace(1)* %carryout
ret void ret void
} }
; GCN-ISEL-LABEL: name: sudiv64 ; GCN-ISEL-LABEL: name: sudiv64
; GCN-ISEL-LABEL: body: ; GCN-ISEL-LABEL: body:
; GCN-ISEL-LABEL: bb.3 ; GCN-ISEL-LABEL: bb.3
; GCN-ISEL: %[[CARRY:[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 ; GCN-ISEL: %[[CARRY:[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64
; GCN-ISEL: S_ADD_CO_PSEUDO %{{[0-9]+}}, %{{[0-9]+}}, %[[CARRY]] ; GCN-ISEL: S_ADD_CO_PSEUDO %{{[0-9]+}}, killed %{{[0-9]+}}, killed %[[CARRY]]
; GCN-ISEL: %[[CARRY:[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64 ; GCN-ISEL: %[[CARRY:[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64
; GCN-ISEL: S_SUB_CO_PSEUDO %{{[0-9]+}}, %{{[0-9]+}}, %[[CARRY]] ; GCN-ISEL: S_SUB_CO_PSEUDO killed %{{[0-9]+}}, %{{[0-9]+}}, %[[CARRY]]
define amdgpu_kernel void @sudiv64(i64 addrspace(1)* %out, i64 %x, i64 %y) { define amdgpu_kernel void @sudiv64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
%result = udiv i64 %x, %y %result = udiv i64 %x, %y
store i64 %result, i64 addrspace(1)* %out store i64 %result, i64 addrspace(1)* %out
ret void ret void
} }
Show All 13 Lines

llvm/test/CodeGen/AMDGPU/sdiv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_sdiv: ; GCN-LABEL: s_test_sdiv:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
; GCN-NEXT: v_mov_b32_e32 v7, 0 ; GCN-NEXT: v_mov_b32_e32 v7, 0
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s2, s5, 31 ; GCN-NEXT: s_ashr_i32 s8, s3, 31
; GCN-NEXT: s_add_u32 s4, s4, s2 ; GCN-NEXT: s_add_u32 s2, s2, s8
; GCN-NEXT: s_mov_b32 s3, s2 ; GCN-NEXT: s_mov_b32 s9, s8
; GCN-NEXT: s_addc_u32 s5, s5, s2 ; GCN-NEXT: s_addc_u32 s3, s3, s8
; GCN-NEXT: s_xor_b64 s[12:13], s[4:5], s[2:3] ; GCN-NEXT: s_xor_b64 s[10:11], s[2:3], s[8:9]
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s10
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s11
; GCN-NEXT: s_sub_u32 s4, 0, s12 ; GCN-NEXT: s_sub_u32 s4, 0, s10
; GCN-NEXT: s_subb_u32 s5, 0, s13 ; GCN-NEXT: s_subb_u32 s5, 0, s11
; GCN-NEXT: s_ashr_i32 s14, s11, 31 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s15, s14 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s12, s3, 31
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 ; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: s_add_u32 s2, s2, s12
; GCN-NEXT: s_mov_b32 s13, s12
; GCN-NEXT: v_mul_lo_u32 v3, s4, v2 ; GCN-NEXT: v_mul_lo_u32 v3, s4, v2
; GCN-NEXT: v_mul_hi_u32 v4, s4, v0 ; GCN-NEXT: v_mul_hi_u32 v4, s4, v0
; GCN-NEXT: v_mul_lo_u32 v6, s5, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s5, v0
; GCN-NEXT: v_mul_lo_u32 v5, s4, v0 ; GCN-NEXT: v_mul_lo_u32 v5, s4, v0
; GCN-NEXT: s_addc_u32 s3, s3, s12
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v5
; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v3
; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v3
; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 ; GCN-NEXT: v_mul_hi_u32 v9, v2, v3
; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 ; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v2, v5 ; GCN-NEXT: v_mul_lo_u32 v8, v2, v5
; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 ; GCN-NEXT: v_mul_hi_u32 v5, v2, v5
; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13]
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v3
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v5, s4, v3
; GCN-NEXT: v_mul_hi_u32 v6, s4, v0
; GCN-NEXT: v_mul_lo_u32 v8, s5, v0
; GCN-NEXT: s_mov_b32 s5, s9
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-NEXT: v_mul_lo_u32 v6, s4, v0
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GCN-NEXT: v_mul_lo_u32 v10, v0, v5
; GCN-NEXT: v_mul_hi_u32 v11, v0, v6
; GCN-NEXT: v_mul_hi_u32 v12, v0, v5
; GCN-NEXT: v_mul_hi_u32 v9, v3, v6
; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
; GCN-NEXT: v_mul_hi_u32 v8, v3, v5
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v7, v12, vcc
; GCN-NEXT: v_mul_lo_u32 v3, v3, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v1, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
; GCN-NEXT: s_add_u32 s0, s10, s14
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: s_addc_u32 s1, s11, s14 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GCN-NEXT: v_mul_lo_u32 v3, s4, v2
; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15] ; GCN-NEXT: v_mul_hi_u32 v4, s4, v0
; GCN-NEXT: v_mul_lo_u32 v3, s10, v2 ; GCN-NEXT: v_mul_lo_u32 v5, s5, v0
; GCN-NEXT: v_mul_hi_u32 v4, s10, v0 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: v_mul_hi_u32 v5, s10, v2 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_mul_hi_u32 v6, s11, v2 ; GCN-NEXT: v_mul_lo_u32 v4, s4, v0
; GCN-NEXT: v_mul_lo_u32 v2, s11, v2 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; GCN-NEXT: v_mul_lo_u32 v8, v0, v3
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_hi_u32 v10, v0, v3
; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
; GCN-NEXT: v_mul_lo_u32 v4, v2, v4
; GCN-NEXT: v_mul_hi_u32 v5, v2, v3
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v1, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v3, s2, v2
; GCN-NEXT: v_mul_hi_u32 v4, s2, v0
; GCN-NEXT: v_mul_hi_u32 v5, s2, v2
; GCN-NEXT: v_mul_hi_u32 v6, s3, v2
; GCN-NEXT: v_mul_lo_u32 v2, s3, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v5, s11, v0 ; GCN-NEXT: v_mul_lo_u32 v5, s3, v0
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
; GCN-NEXT: s_mov_b32 s4, s8 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s12, v1 ; GCN-NEXT: v_mul_lo_u32 v2, s10, v1
; GCN-NEXT: v_mul_hi_u32 v3, s12, v0 ; GCN-NEXT: v_mul_hi_u32 v3, s10, v0
; GCN-NEXT: v_mul_lo_u32 v4, s13, v0 ; GCN-NEXT: v_mul_lo_u32 v4, s11, v0
; GCN-NEXT: v_mov_b32_e32 v5, s13 ; GCN-NEXT: v_mov_b32_e32 v5, s11
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_mul_lo_u32 v3, s12, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s10, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s11, v2 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, s3, v2
; GCN-NEXT: v_sub_i32_e32 v3, vcc, s10, v3 ; GCN-NEXT: v_sub_i32_e32 v3, vcc, s2, v3
; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc ; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s12, v3 ; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s10, v3
; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] ; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v4 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v4
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v5 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v5
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v4 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v4
; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 ; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0
; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 ; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0
; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v6, s11 ; GCN-NEXT: v_mov_b32_e32 v6, s3
; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc ; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v2 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s11, v2
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v3 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v2 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s11, v2
; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: s_xor_b64 s[0:1], s[14:15], s[2:3] ; GCN-NEXT: s_xor_b64 s[0:1], s[12:13], s[8:9]
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GCN-NEXT: v_xor_b32_e32 v0, s0, v0 ; GCN-NEXT: v_xor_b32_e32 v0, s0, v0
; GCN-NEXT: v_xor_b32_e32 v1, s1, v1 ; GCN-NEXT: v_xor_b32_e32 v1, s1, v1
; GCN-NEXT: v_mov_b32_e32 v2, s1 ; GCN-NEXT: v_mov_b32_e32 v2, s1
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_lo_u32 v13, v6, v10 ; GCN-NEXT: v_mul_lo_u32 v13, v6, v10
; GCN-NEXT: v_mul_hi_u32 v10, v6, v10 ; GCN-NEXT: v_mul_hi_u32 v10, v6, v10
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v15, v11, vcc ; GCN-NEXT: v_addc_u32_e32 v11, vcc, v15, v11, vcc
; GCN-NEXT: v_add_i32_e32 v12, vcc, v12, v13 ; GCN-NEXT: v_add_i32_e32 v12, vcc, v12, v13
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v11, v10, vcc ; GCN-NEXT: v_addc_u32_e32 v10, vcc, v11, v10, vcc
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v16, v14, vcc ; GCN-NEXT: v_addc_u32_e32 v11, vcc, v16, v14, vcc
; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v11, vcc ; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v11, vcc
; GCN-NEXT: v_add_i32_e64 v5, s[4:5], v5, v9 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; GCN-NEXT: v_addc_u32_e64 v9, vcc, v6, v10, s[4:5] ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v11, v7, v9 ; GCN-NEXT: v_mul_lo_u32 v9, v7, v6
; GCN-NEXT: v_mul_hi_u32 v12, v7, v5 ; GCN-NEXT: v_mul_hi_u32 v10, v7, v5
; GCN-NEXT: v_mul_lo_u32 v8, v8, v5 ; GCN-NEXT: v_mul_lo_u32 v8, v8, v5
; GCN-NEXT: v_mul_lo_u32 v7, v7, v5 ; GCN-NEXT: v_mul_lo_u32 v7, v7, v5
; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_mul_lo_u32 v11, v5, v8
; GCN-NEXT: v_mul_hi_u32 v12, v5, v7
; GCN-NEXT: v_mul_hi_u32 v13, v5, v8
; GCN-NEXT: v_mul_hi_u32 v10, v6, v7
; GCN-NEXT: v_mul_lo_u32 v7, v6, v7
; GCN-NEXT: v_mul_hi_u32 v9, v6, v8
; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v8 ; GCN-NEXT: v_addc_u32_e32 v12, vcc, v15, v13, vcc
; GCN-NEXT: v_mul_lo_u32 v13, v5, v8 ; GCN-NEXT: v_mul_lo_u32 v8, v6, v8
; GCN-NEXT: v_mul_hi_u32 v16, v5, v7 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; GCN-NEXT: v_mul_hi_u32 v17, v5, v8 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v10, vcc
; GCN-NEXT: v_mul_hi_u32 v12, v9, v7 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v14, vcc
; GCN-NEXT: v_mul_lo_u32 v7, v9, v7
; GCN-NEXT: v_mul_hi_u32 v11, v9, v8
; GCN-NEXT: v_add_i32_e32 v13, vcc, v16, v13
; GCN-NEXT: v_addc_u32_e32 v16, vcc, v15, v17, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v9, v8
; GCN-NEXT: v_add_i32_e32 v7, vcc, v13, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v16, v12, vcc
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v14, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v15, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v15, v9, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; GCN-NEXT: v_addc_u32_e64 v6, vcc, v6, v8, s[4:5]
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc
; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v1 ; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v1
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v7 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v7
; GCN-NEXT: v_xor_b32_e32 v0, v0, v7 ; GCN-NEXT: v_xor_b32_e32 v0, v0, v7
; GCN-NEXT: v_mul_lo_u32 v8, v0, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v0, v6
; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v5
; GCN-NEXT: v_mul_hi_u32 v10, v0, v6 ; GCN-NEXT: v_mul_hi_u32 v10, v0, v6
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc
; GCN-NEXT: v_xor_b32_e32 v1, v1, v7 ; GCN-NEXT: v_xor_b32_e32 v1, v1, v7
▲ Show 20 Lines • Show All 782 Lines • ▼ Show 20 Lines; GCN-IR-NEXT: s_endpgm
%result = sdiv i48 %1, %2 %result = sdiv i48 %1, %2
store i48 %result, i48 addrspace(1)* %out store i48 %result, i48 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
; GCN-LABEL: s_test_sdiv_k_num_i64: ; GCN-LABEL: s_test_sdiv_k_num_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s2, s7, 31
; GCN-NEXT: s_add_u32 s0, s6, s2
; GCN-NEXT: s_mov_b32 s3, s2
; GCN-NEXT: s_addc_u32 s1, s7, s2
; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[2:3]
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9
; GCN-NEXT: s_sub_u32 s3, 0, s8
; GCN-NEXT: s_subb_u32 s6, 0, s9
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s8, s3, 31
; GCN-NEXT: s_add_u32 s2, s2, s8
; GCN-NEXT: s_mov_b32 s9, s8
; GCN-NEXT: s_addc_u32 s3, s3, s8
; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9]
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3
; GCN-NEXT: s_sub_u32 s4, 0, s2
; GCN-NEXT: s_subb_u32 s5, 0, s3
; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v3, v3 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_lo_u32 v4, s3, v3 ; GCN-NEXT: v_mul_lo_u32 v4, s4, v3
; GCN-NEXT: v_mul_hi_u32 v5, s3, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s4, v0
; GCN-NEXT: v_mul_lo_u32 v7, s6, v0 ; GCN-NEXT: v_mul_lo_u32 v7, s5, v0
; GCN-NEXT: v_mul_lo_u32 v6, s3, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s4, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v6
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v10, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v6, s3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, s4, v3
; GCN-NEXT: v_mul_hi_u32 v7, s3, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s4, v0
; GCN-NEXT: v_mul_lo_u32 v8, s6, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s5, v0
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 ; GCN-NEXT: v_mul_lo_u32 v5, s4, v0
; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v0, v4
; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v5
; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 ; GCN-NEXT: v_mul_hi_u32 v10, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 ; GCN-NEXT: v_mul_hi_u32 v7, v3, v5
; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v4
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v3, v1, 24 ; GCN-NEXT: v_mul_lo_u32 v3, v1, 24
; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v0, v0, 24
; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 ; GCN-NEXT: v_mul_hi_u32 v1, v1, 24
; GCN-NEXT: v_mov_b32_e32 v5, s9 ; GCN-NEXT: v_mov_b32_e32 v5, s3
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v1, s9, v0 ; GCN-NEXT: v_mul_lo_u32 v1, s3, v0
; GCN-NEXT: v_mul_hi_u32 v3, s8, v0 ; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1
; GCN-NEXT: v_mul_lo_u32 v3, s8, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s2, v0
; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v1 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v1
; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v3 ; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v3
; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc ; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s8, v3 ; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3
; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] ; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v5 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4
; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 ; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0
; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v2, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v2, s[0:1]
; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 ; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0
; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: v_addc_u32_e64 v2, s[0:1], 0, v2, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v2, s[0:1], 0, v2, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_xor_b32_e32 v0, s2, v0 ; GCN-NEXT: v_xor_b32_e32 v0, s8, v0
; GCN-NEXT: v_xor_b32_e32 v1, s2, v1 ; GCN-NEXT: v_xor_b32_e32 v1, s8, v1
; GCN-NEXT: v_mov_b32_e32 v2, s2 ; GCN-NEXT: v_mov_b32_e32 v2, s8
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_sdiv_k_num_i64: ; GCN-IR-LABEL: s_test_sdiv_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 ; GCN-NEXT: v_mul_lo_u32 v11, v4, v8
; GCN-NEXT: v_mul_hi_u32 v8, v4, v8 ; GCN-NEXT: v_mul_hi_u32 v8, v4, v8
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v9, vcc
; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v9, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v9, v8, vcc
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v12, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v12, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v9, vcc
; GCN-NEXT: v_add_i32_e64 v3, s[4:5], v3, v7 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; GCN-NEXT: v_addc_u32_e64 v7, vcc, v4, v8, s[4:5] ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc
; GCN-NEXT: v_mul_lo_u32 v9, v5, v7 ; GCN-NEXT: v_mul_lo_u32 v7, v5, v4
; GCN-NEXT: v_mul_hi_u32 v10, v5, v3 ; GCN-NEXT: v_mul_hi_u32 v8, v5, v3
; GCN-NEXT: v_mul_lo_u32 v6, v6, v3 ; GCN-NEXT: v_mul_lo_u32 v6, v6, v3
; GCN-NEXT: v_mul_lo_u32 v5, v5, v3 ; GCN-NEXT: v_mul_lo_u32 v5, v5, v3
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_mul_lo_u32 v9, v3, v6
; GCN-NEXT: v_mul_hi_u32 v10, v3, v5
; GCN-NEXT: v_mul_hi_u32 v11, v3, v6
; GCN-NEXT: v_mul_hi_u32 v8, v4, v5
; GCN-NEXT: v_mul_lo_u32 v5, v4, v5
; GCN-NEXT: v_mul_hi_u32 v7, v4, v6
; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 ; GCN-NEXT: v_addc_u32_e32 v10, vcc, v13, v11, vcc
; GCN-NEXT: v_mul_lo_u32 v11, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v6
; GCN-NEXT: v_mul_hi_u32 v14, v3, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
; GCN-NEXT: v_mul_hi_u32 v15, v3, v6 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc
; GCN-NEXT: v_mul_hi_u32 v10, v7, v5 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v12, vcc
; GCN-NEXT: v_mul_lo_u32 v5, v7, v5
; GCN-NEXT: v_mul_hi_u32 v9, v7, v6
; GCN-NEXT: v_add_i32_e32 v11, vcc, v14, v11
; GCN-NEXT: v_addc_u32_e32 v14, vcc, v13, v15, vcc
; GCN-NEXT: v_mul_lo_u32 v6, v7, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v11, v5
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v10, vcc
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v12, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v7, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v4, v6, s[4:5]
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc
; GCN-NEXT: v_mul_lo_u32 v5, v4, 24 ; GCN-NEXT: v_mul_lo_u32 v5, v4, 24
; GCN-NEXT: v_mul_hi_u32 v3, v3, 24 ; GCN-NEXT: v_mul_hi_u32 v3, v3, 24
; GCN-NEXT: v_mul_hi_u32 v4, v4, 24 ; GCN-NEXT: v_mul_hi_u32 v4, v4, 24
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v13, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v13, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v1, v3 ; GCN-NEXT: v_mul_lo_u32 v4, v1, v3
; GCN-NEXT: v_mul_hi_u32 v5, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
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; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0 ; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0
; GCN-NEXT: v_cvt_f32_u32_e32 v4, v1 ; GCN-NEXT: v_cvt_f32_u32_e32 v4, v1
; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v0 ; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v0
; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v1, vcc ; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v1, vcc
; GCN-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4 ; GCN-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4
; GCN-NEXT: v_rcp_f32_e32 v3, v3 ; GCN-NEXT: v_rcp_f32_e32 v3, v3
; GCN-NEXT: v_mov_b32_e32 v13, 0 ; GCN-NEXT: v_mov_b32_e32 v13, 0
; GCN-NEXT: v_mov_b32_e32 v12, 0 ; GCN-NEXT: v_mov_b32_e32 v12, 0
; GCN-NEXT: s_mov_b32 s4, 0x8000
; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 ; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 ; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
; GCN-NEXT: v_trunc_f32_e32 v4, v4 ; GCN-NEXT: v_trunc_f32_e32 v4, v4
; GCN-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4 ; GCN-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
; GCN-NEXT: v_mul_hi_u32 v7, v5, v3 ; GCN-NEXT: v_mul_hi_u32 v7, v5, v3
; GCN-NEXT: v_mul_lo_u32 v8, v5, v4 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v4
Show All 10 Lines
; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 ; GCN-NEXT: v_mul_lo_u32 v11, v4, v8
; GCN-NEXT: v_mul_hi_u32 v8, v4, v8 ; GCN-NEXT: v_mul_hi_u32 v8, v4, v8
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v9, vcc
; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v11
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v9, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v9, v8, vcc
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v12, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v12, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v9, vcc
; GCN-NEXT: v_add_i32_e64 v3, s[4:5], v3, v7 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; GCN-NEXT: v_addc_u32_e64 v7, vcc, v4, v8, s[4:5] ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc
; GCN-NEXT: v_mul_lo_u32 v9, v5, v7 ; GCN-NEXT: v_mul_lo_u32 v7, v5, v4
; GCN-NEXT: v_mul_hi_u32 v10, v5, v3 ; GCN-NEXT: v_mul_hi_u32 v8, v5, v3
; GCN-NEXT: v_mul_lo_u32 v6, v6, v3 ; GCN-NEXT: v_mul_lo_u32 v6, v6, v3
; GCN-NEXT: v_mul_lo_u32 v5, v5, v3 ; GCN-NEXT: v_mul_lo_u32 v5, v5, v3
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_mul_lo_u32 v9, v3, v6
; GCN-NEXT: v_mul_hi_u32 v10, v3, v5
; GCN-NEXT: v_mul_hi_u32 v11, v3, v6
; GCN-NEXT: v_mul_hi_u32 v8, v4, v5
; GCN-NEXT: v_mul_lo_u32 v5, v4, v5
; GCN-NEXT: v_mul_hi_u32 v7, v4, v6
; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 ; GCN-NEXT: v_addc_u32_e32 v10, vcc, v13, v11, vcc
; GCN-NEXT: v_mul_lo_u32 v11, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v6
; GCN-NEXT: v_mul_hi_u32 v14, v3, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
; GCN-NEXT: v_mul_hi_u32 v15, v3, v6 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc
; GCN-NEXT: v_mul_hi_u32 v10, v7, v5 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v12, vcc
; GCN-NEXT: v_mul_lo_u32 v5, v7, v5
; GCN-NEXT: v_mul_hi_u32 v9, v7, v6
; GCN-NEXT: v_add_i32_e32 v11, vcc, v14, v11
; GCN-NEXT: v_addc_u32_e32 v14, vcc, v13, v15, vcc
; GCN-NEXT: v_mul_lo_u32 v6, v7, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v11, v5
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v10, vcc
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v12, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v7, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v4, v6, s[4:5]
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc
; GCN-NEXT: v_lshrrev_b32_e32 v5, 17, v4 ; GCN-NEXT: v_lshrrev_b32_e32 v5, 17, v4
; GCN-NEXT: v_lshlrev_b32_e32 v4, 15, v4 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 15, v4
; GCN-NEXT: v_lshrrev_b32_e32 v3, 17, v3 ; GCN-NEXT: v_lshrrev_b32_e32 v3, 17, v3
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v13, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v13, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v1, v3 ; GCN-NEXT: v_mul_lo_u32 v4, v1, v3
; GCN-NEXT: v_mul_hi_u32 v5, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v3
; GCN-NEXT: s_mov_b32 s4, 0x8000
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_mul_lo_u32 v5, v0, v3 ; GCN-NEXT: v_mul_lo_u32 v5, v0, v3
; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v4 ; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v4
; GCN-NEXT: v_sub_i32_e32 v5, vcc, s4, v5 ; GCN-NEXT: v_sub_i32_e32 v5, vcc, s4, v5
; GCN-NEXT: v_subb_u32_e64 v6, s[4:5], v6, v1, vcc ; GCN-NEXT: v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
; GCN-NEXT: v_sub_i32_e64 v7, s[4:5], v5, v0 ; GCN-NEXT: v_sub_i32_e64 v7, s[4:5], v5, v0
; GCN-NEXT: v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5] ; GCN-NEXT: v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v1 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v1
▲ Show 20 Lines • Show All 464 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/srem64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) { define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_srem: ; GCN-LABEL: s_test_srem:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13
; GCN-NEXT: s_sub_u32 s2, 0, s12 ; GCN-NEXT: s_sub_u32 s0, 0, s12
; GCN-NEXT: s_subb_u32 s3, 0, s13 ; GCN-NEXT: s_subb_u32 s1, 0, s13
; GCN-NEXT: s_mov_b32 s4, s8 ; GCN-NEXT: s_mov_b32 s4, s8
; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s5, s9 ; GCN-NEXT: s_mov_b32 s5, s9
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v3, v3 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v3
; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s0, v0
; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 ; GCN-NEXT: v_mul_lo_u32 v7, s1, v0
; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s0, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v6
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v6, s2, v4
; GCN-NEXT: v_mul_hi_u32 v7, s2, v0
; GCN-NEXT: v_mul_lo_u32 v8, s3, v0
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_mul_lo_u32 v7, s2, v0
; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GCN-NEXT: v_mul_lo_u32 v10, v0, v6
; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
; GCN-NEXT: v_mul_hi_u32 v12, v0, v6
; GCN-NEXT: v_mul_hi_u32 v9, v4, v7
; GCN-NEXT: v_mul_lo_u32 v7, v4, v7
; GCN-NEXT: v_mul_hi_u32 v8, v4, v6
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v4, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s0, v3
; GCN-NEXT: v_mul_hi_u32 v5, s0, v0
; GCN-NEXT: v_mul_lo_u32 v6, s1, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_mul_lo_u32 v5, s0, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GCN-NEXT: v_mul_lo_u32 v8, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v5
; GCN-NEXT: v_mul_hi_u32 v10, v0, v4
; GCN-NEXT: v_mul_hi_u32 v7, v3, v5
; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
; GCN-NEXT: v_mul_hi_u32 v6, v3, v4
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s10, v3 ; GCN-NEXT: v_mul_lo_u32 v4, s10, v3
; GCN-NEXT: v_mul_hi_u32 v5, s10, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s10, v0
; GCN-NEXT: v_mul_hi_u32 v6, s10, v3 ; GCN-NEXT: v_mul_hi_u32 v6, s10, v3
; GCN-NEXT: v_mul_hi_u32 v7, s11, v3 ; GCN-NEXT: v_mul_hi_u32 v7, s11, v3
; GCN-NEXT: v_mul_lo_u32 v3, s11, v3 ; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_mul_lo_u32 v6, s11, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s11, v0
▲ Show 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 ; GCN-NEXT: v_mul_lo_u32 v12, v5, v9
; GCN-NEXT: v_mul_hi_u32 v9, v5, v9 ; GCN-NEXT: v_mul_hi_u32 v9, v5, v9
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc ; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc
; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc ; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc
; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v8 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GCN-NEXT: v_addc_u32_e64 v8, vcc, v5, v9, s[4:5] ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc
; GCN-NEXT: v_mul_lo_u32 v10, v6, v8 ; GCN-NEXT: v_mul_lo_u32 v8, v6, v5
; GCN-NEXT: v_mul_hi_u32 v11, v6, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v6, v4
; GCN-NEXT: v_mul_lo_u32 v7, v7, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v7, v4
; GCN-NEXT: v_mul_lo_u32 v6, v6, v4 ; GCN-NEXT: v_mul_lo_u32 v6, v6, v4
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GCN-NEXT: v_mul_lo_u32 v10, v4, v7
; GCN-NEXT: v_mul_hi_u32 v11, v4, v6
; GCN-NEXT: v_mul_hi_u32 v12, v4, v7
; GCN-NEXT: v_mul_hi_u32 v9, v5, v6
; GCN-NEXT: v_mul_lo_u32 v6, v5, v6
; GCN-NEXT: v_mul_hi_u32 v8, v5, v7
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 ; GCN-NEXT: v_addc_u32_e32 v11, vcc, v14, v12, vcc
; GCN-NEXT: v_mul_lo_u32 v12, v4, v7 ; GCN-NEXT: v_mul_lo_u32 v7, v5, v7
; GCN-NEXT: v_mul_hi_u32 v15, v4, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
; GCN-NEXT: v_mul_hi_u32 v16, v4, v7 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc
; GCN-NEXT: v_mul_hi_u32 v11, v8, v6 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc
; GCN-NEXT: v_mul_lo_u32 v6, v8, v6
; GCN-NEXT: v_mul_hi_u32 v10, v8, v7
; GCN-NEXT: v_add_i32_e32 v12, vcc, v15, v12
; GCN-NEXT: v_addc_u32_e32 v15, vcc, v14, v16, vcc
; GCN-NEXT: v_mul_lo_u32 v7, v8, v7
; GCN-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v15, v11, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v13, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
; GCN-NEXT: v_ashrrev_i32_e32 v6, 31, v1 ; GCN-NEXT: v_ashrrev_i32_e32 v6, 31, v1
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v6
; GCN-NEXT: v_xor_b32_e32 v0, v0, v6 ; GCN-NEXT: v_xor_b32_e32 v0, v0, v6
; GCN-NEXT: v_mul_lo_u32 v7, v0, v5 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v5
; GCN-NEXT: v_mul_hi_u32 v8, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v5
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v6, vcc
; GCN-NEXT: v_xor_b32_e32 v1, v1, v6 ; GCN-NEXT: v_xor_b32_e32 v1, v1, v6
▲ Show 20 Lines • Show All 578 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_ashr_i64 s[4:5], s[0:1], 31 ; GCN-NEXT: s_ashr_i64 s[4:5], s[0:1], 31
; GCN-NEXT: s_ashr_i32 s0, s1, 31 ; GCN-NEXT: s_ashr_i32 s0, s1, 31
; GCN-NEXT: s_add_u32 s4, s4, s0 ; GCN-NEXT: s_add_u32 s4, s4, s0
; GCN-NEXT: s_mov_b32 s1, s0 ; GCN-NEXT: s_mov_b32 s1, s0
; GCN-NEXT: s_addc_u32 s5, s5, s0 ; GCN-NEXT: s_addc_u32 s5, s5, s0
; GCN-NEXT: s_xor_b64 s[12:13], s[4:5], s[0:1] ; GCN-NEXT: s_xor_b64 s[12:13], s[4:5], s[0:1]
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13
; GCN-NEXT: s_sub_u32 s4, 0, s12 ; GCN-NEXT: s_sub_u32 s0, 0, s12
; GCN-NEXT: s_subb_u32 s5, 0, s13 ; GCN-NEXT: s_subb_u32 s1, 0, s13
; GCN-NEXT: s_ashr_i32 s10, s11, 31 ; GCN-NEXT: s_ashr_i32 s10, s11, 31
; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s11, s10 ; GCN-NEXT: s_mov_b32 s11, s10
; GCN-NEXT: s_mov_b32 s4, s8
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 ; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_lo_u32 v3, s4, v2 ; GCN-NEXT: s_mov_b32 s5, s9
; GCN-NEXT: v_mul_hi_u32 v4, s4, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s0, v2
; GCN-NEXT: v_mul_lo_u32 v6, s5, v0 ; GCN-NEXT: v_mul_hi_u32 v4, s0, v0
; GCN-NEXT: v_mul_lo_u32 v5, s4, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s1, v0
; GCN-NEXT: v_mul_lo_u32 v5, s0, v0
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v5
; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v3
; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v3
; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 ; GCN-NEXT: v_mul_hi_u32 v9, v2, v3
; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 ; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v2, v5 ; GCN-NEXT: v_mul_lo_u32 v8, v2, v5
; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 ; GCN-NEXT: v_mul_hi_u32 v5, v2, v5
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v3 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[0:1] ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v5, s4, v3 ; GCN-NEXT: v_mul_lo_u32 v3, s0, v2
; GCN-NEXT: v_mul_hi_u32 v6, s4, v0 ; GCN-NEXT: v_mul_hi_u32 v4, s0, v0
; GCN-NEXT: v_mul_lo_u32 v8, s5, v0 ; GCN-NEXT: v_mul_lo_u32 v5, s1, v0
; GCN-NEXT: s_mov_b32 s5, s9 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v0
; GCN-NEXT: v_mul_lo_u32 v6, s4, v0 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; GCN-NEXT: v_mul_lo_u32 v8, v0, v3
; GCN-NEXT: v_mul_lo_u32 v10, v0, v5 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_hi_u32 v11, v0, v6 ; GCN-NEXT: v_mul_hi_u32 v10, v0, v3
; GCN-NEXT: v_mul_hi_u32 v12, v0, v5 ; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
; GCN-NEXT: v_mul_hi_u32 v9, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v4, v2, v4
; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v5, v2, v3
; GCN-NEXT: v_mul_hi_u32 v8, v3, v5 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v7, v12, vcc ; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
; GCN-NEXT: v_mul_lo_u32 v3, v3, v5 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v1, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v1, vcc ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
; GCN-NEXT: s_add_u32 s0, s2, s10 ; GCN-NEXT: s_add_u32 s0, s2, s10
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: s_addc_u32 s1, s3, s10 ; GCN-NEXT: s_addc_u32 s1, s3, s10
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GCN-NEXT: s_xor_b64 s[14:15], s[0:1], s[10:11] ; GCN-NEXT: s_xor_b64 s[14:15], s[0:1], s[10:11]
; GCN-NEXT: v_mul_lo_u32 v3, s14, v2 ; GCN-NEXT: v_mul_lo_u32 v3, s14, v2
; GCN-NEXT: v_mul_hi_u32 v4, s14, v0 ; GCN-NEXT: v_mul_hi_u32 v4, s14, v0
; GCN-NEXT: v_mul_hi_u32 v5, s14, v2 ; GCN-NEXT: v_mul_hi_u32 v5, s14, v2
; GCN-NEXT: v_mul_hi_u32 v6, s15, v2 ; GCN-NEXT: v_mul_hi_u32 v6, s15, v2
; GCN-NEXT: v_mul_lo_u32 v2, s15, v2 ; GCN-NEXT: v_mul_lo_u32 v2, s15, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v5, s15, v0 ; GCN-NEXT: v_mul_lo_u32 v5, s15, v0
; GCN-NEXT: v_mul_hi_u32 v0, s15, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s15, v0
; GCN-NEXT: s_mov_b32 s4, s8
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 ; GCN-NEXT: v_mul_lo_u32 v1, s12, v1
; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 ; GCN-NEXT: v_mul_hi_u32 v2, s12, v0
; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s13, v0
▲ Show 20 Lines • Show All 317 Lines • ▼ Show 20 Lines; GCN-IR-NEXT: s_endpgm
%result = srem i48 %1, %2 %result = srem i48 %1, %2
store i48 %result, i48 addrspace(1)* %out store i48 %result, i48 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
; GCN-LABEL: s_test_srem_k_num_i64: ; GCN-LABEL: s_test_srem_k_num_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s0, s7, 31 ; GCN-NEXT: s_ashr_i32 s4, s3, 31
; GCN-NEXT: s_add_u32 s2, s6, s0 ; GCN-NEXT: s_add_u32 s2, s2, s4
; GCN-NEXT: s_mov_b32 s1, s0 ; GCN-NEXT: s_mov_b32 s5, s4
; GCN-NEXT: s_addc_u32 s3, s7, s0 ; GCN-NEXT: s_addc_u32 s3, s3, s4
; GCN-NEXT: s_xor_b64 s[8:9], s[2:3], s[0:1] ; GCN-NEXT: s_xor_b64 s[8:9], s[2:3], s[4:5]
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9
; GCN-NEXT: s_sub_u32 s2, 0, s8 ; GCN-NEXT: s_sub_u32 s2, 0, s8
; GCN-NEXT: s_subb_u32 s3, 0, s9 ; GCN-NEXT: s_subb_u32 s3, 0, s9
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v3, v3 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 ; GCN-NEXT: v_mul_lo_u32 v4, s2, v3
; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s2, v0
Show All 10 Lines
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 ; GCN-NEXT: v_mul_lo_u32 v4, s2, v3
; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s2, v0
; GCN-NEXT: v_mul_lo_u32 v8, s3, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s3, v0
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 ; GCN-NEXT: v_mul_lo_u32 v5, s2, v0
; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v0, v4
; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v5
; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 ; GCN-NEXT: v_mul_hi_u32 v10, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 ; GCN-NEXT: v_mul_hi_u32 v7, v3, v5
; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v4
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v3, v1, 24 ; GCN-NEXT: v_mul_lo_u32 v3, v1, 24
; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v0, v0, 24
; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 ; GCN-NEXT: v_mul_hi_u32 v1, v1, 24
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v1, s9, v0 ; GCN-NEXT: v_mul_lo_u32 v1, s9, v0
; GCN-NEXT: v_mul_hi_u32 v2, s8, v0 ; GCN-NEXT: v_mul_hi_u32 v2, s8, v0
; GCN-NEXT: v_mul_lo_u32 v0, s8, v0 ; GCN-NEXT: v_mul_lo_u32 v0, s8, v0
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_lo_u32 v10, v3, v7 ; GCN-NEXT: v_mul_lo_u32 v10, v3, v7
; GCN-NEXT: v_mul_hi_u32 v7, v3, v7 ; GCN-NEXT: v_mul_hi_u32 v7, v3, v7
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v8, vcc
; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v7, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc
; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v6 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[4:5] ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v4, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v3
; GCN-NEXT: v_mul_hi_u32 v9, v4, v2 ; GCN-NEXT: v_mul_hi_u32 v7, v4, v2
; GCN-NEXT: v_mul_lo_u32 v5, v5, v2 ; GCN-NEXT: v_mul_lo_u32 v5, v5, v2
; GCN-NEXT: v_mul_lo_u32 v4, v4, v2 ; GCN-NEXT: v_mul_lo_u32 v4, v4, v2
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-NEXT: v_mul_lo_u32 v8, v2, v5
; GCN-NEXT: v_mul_hi_u32 v9, v2, v4
; GCN-NEXT: v_mul_hi_u32 v10, v2, v5
; GCN-NEXT: v_mul_hi_u32 v7, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_mul_hi_u32 v6, v3, v5
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v12, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
; GCN-NEXT: v_mul_hi_u32 v13, v2, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
; GCN-NEXT: v_mul_hi_u32 v14, v2, v5 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v6, v4 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v11, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v6, v4
; GCN-NEXT: v_mul_hi_u32 v8, v6, v5
; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v10
; GCN-NEXT: v_addc_u32_e32 v13, vcc, v12, v14, vcc
; GCN-NEXT: v_mul_lo_u32 v5, v6, v5
; GCN-NEXT: v_add_i32_e32 v4, vcc, v10, v4
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v13, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v11, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 ; GCN-NEXT: v_mul_lo_u32 v4, v3, 24
; GCN-NEXT: v_mul_hi_u32 v2, v2, 24 ; GCN-NEXT: v_mul_hi_u32 v2, v2, 24
; GCN-NEXT: v_mul_hi_u32 v3, v3, 24 ; GCN-NEXT: v_mul_hi_u32 v3, v3, 24
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v12, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v12, v3, vcc
; GCN-NEXT: v_mul_lo_u32 v3, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v2
; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
; GCN-NEXT: v_mul_lo_u32 v2, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v0, v2
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0 ; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0
; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1 ; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1
; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0
; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc ; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc
; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; GCN-NEXT: v_rcp_f32_e32 v2, v2 ; GCN-NEXT: v_rcp_f32_e32 v2, v2
; GCN-NEXT: v_mov_b32_e32 v12, 0 ; GCN-NEXT: v_mov_b32_e32 v12, 0
; GCN-NEXT: v_mov_b32_e32 v11, 0 ; GCN-NEXT: v_mov_b32_e32 v11, 0
; GCN-NEXT: s_mov_b32 s4, 0x8000
; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
; GCN-NEXT: v_trunc_f32_e32 v3, v3 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 ; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_mul_hi_u32 v6, v4, v2 ; GCN-NEXT: v_mul_hi_u32 v6, v4, v2
; GCN-NEXT: v_mul_lo_u32 v7, v4, v3 ; GCN-NEXT: v_mul_lo_u32 v7, v4, v3
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; GCN-NEXT: v_mul_lo_u32 v10, v3, v7 ; GCN-NEXT: v_mul_lo_u32 v10, v3, v7
; GCN-NEXT: v_mul_hi_u32 v7, v3, v7 ; GCN-NEXT: v_mul_hi_u32 v7, v3, v7
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v8, vcc
; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v7, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc
; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v6 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[4:5] ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v4, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v3
; GCN-NEXT: v_mul_hi_u32 v9, v4, v2 ; GCN-NEXT: v_mul_hi_u32 v7, v4, v2
; GCN-NEXT: v_mul_lo_u32 v5, v5, v2 ; GCN-NEXT: v_mul_lo_u32 v5, v5, v2
; GCN-NEXT: v_mul_lo_u32 v4, v4, v2 ; GCN-NEXT: v_mul_lo_u32 v4, v4, v2
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-NEXT: v_mul_lo_u32 v8, v2, v5
; GCN-NEXT: v_mul_hi_u32 v9, v2, v4
; GCN-NEXT: v_mul_hi_u32 v10, v2, v5
; GCN-NEXT: v_mul_hi_u32 v7, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_mul_hi_u32 v6, v3, v5
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v12, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
; GCN-NEXT: v_mul_hi_u32 v13, v2, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
; GCN-NEXT: v_mul_hi_u32 v14, v2, v5 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v6, v4 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v11, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v6, v4
; GCN-NEXT: v_mul_hi_u32 v8, v6, v5
; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v10
; GCN-NEXT: v_addc_u32_e32 v13, vcc, v12, v14, vcc
; GCN-NEXT: v_mul_lo_u32 v5, v6, v5
; GCN-NEXT: v_add_i32_e32 v4, vcc, v10, v4
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v13, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v11, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_lshrrev_b32_e32 v4, 17, v3 ; GCN-NEXT: v_lshrrev_b32_e32 v4, 17, v3
; GCN-NEXT: v_lshlrev_b32_e32 v3, 15, v3 ; GCN-NEXT: v_lshlrev_b32_e32 v3, 15, v3
; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v12, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v12, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v3, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v2
; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
; GCN-NEXT: v_mul_lo_u32 v2, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v0, v2
; GCN-NEXT: s_mov_b32 s4, 0x8000
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
; GCN-NEXT: v_sub_i32_e32 v2, vcc, s4, v2 ; GCN-NEXT: v_sub_i32_e32 v2, vcc, s4, v2
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc ; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
; GCN-NEXT: v_sub_i32_e64 v5, s[4:5], v2, v0 ; GCN-NEXT: v_sub_i32_e64 v5, s[4:5], v2, v0
; GCN-NEXT: v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5] ; GCN-NEXT: v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v6, v1 ; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v6, v1
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7] ; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]
▲ Show 20 Lines • Show All 484 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/udiv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) { define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_udiv_i64: ; GCN-LABEL: s_test_udiv_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9
; GCN-NEXT: s_sub_u32 s4, 0, s2 ; GCN-NEXT: s_sub_u32 s4, 0, s8
; GCN-NEXT: s_subb_u32 s5, 0, s3 ; GCN-NEXT: s_subb_u32 s5, 0, s9
; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v3, v3 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
Show All 13 Lines
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v6, s4, v4
; GCN-NEXT: v_mul_hi_u32 v7, s4, v0
; GCN-NEXT: v_mul_lo_u32 v8, s5, v0
; GCN-NEXT: s_mov_b32 s5, s9
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_mul_lo_u32 v7, s4, v0
; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GCN-NEXT: v_mul_lo_u32 v10, v0, v6
; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
; GCN-NEXT: v_mul_hi_u32 v12, v0, v6
; GCN-NEXT: v_mul_hi_u32 v9, v4, v7
; GCN-NEXT: v_mul_lo_u32 v7, v4, v7
; GCN-NEXT: v_mul_hi_u32 v8, v4, v6
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v4, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s10, v3 ; GCN-NEXT: v_mul_lo_u32 v4, s4, v3
; GCN-NEXT: v_mul_hi_u32 v5, s10, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s4, v0
; GCN-NEXT: v_mul_hi_u32 v6, s10, v3 ; GCN-NEXT: v_mul_lo_u32 v6, s5, v0
; GCN-NEXT: v_mul_hi_u32 v7, s11, v3 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: v_mul_lo_u32 v3, s11, v3 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_mul_lo_u32 v5, s4, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GCN-NEXT: v_mul_lo_u32 v8, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v5
; GCN-NEXT: v_mul_hi_u32 v10, v0, v4
; GCN-NEXT: v_mul_hi_u32 v7, v3, v5
; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
; GCN-NEXT: v_mul_hi_u32 v6, v3, v4
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s2, v3
; GCN-NEXT: v_mul_hi_u32 v5, s2, v0
; GCN-NEXT: v_mul_hi_u32 v6, s2, v3
; GCN-NEXT: v_mul_hi_u32 v7, s3, v3
; GCN-NEXT: v_mul_lo_u32 v3, s3, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_mul_lo_u32 v6, s11, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s3, v0
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
; GCN-NEXT: s_mov_b32 s4, s8 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 ; GCN-NEXT: v_mul_lo_u32 v2, s8, v1
; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v3, s8, v0
; GCN-NEXT: v_mul_lo_u32 v4, s3, v0 ; GCN-NEXT: v_mul_lo_u32 v4, s9, v0
; GCN-NEXT: v_mov_b32_e32 v5, s3 ; GCN-NEXT: v_mov_b32_e32 v5, s9
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_mul_lo_u32 v3, s2, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s8, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s11, v2 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, s3, v2
; GCN-NEXT: v_sub_i32_e32 v3, vcc, s10, v3 ; GCN-NEXT: v_sub_i32_e32 v3, vcc, s2, v3
; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc ; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3 ; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s8, v3
; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] ; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v5
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4
; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 ; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0
; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 ; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0
; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v6, s11 ; GCN-NEXT: v_mov_b32_e32 v6, s3
; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc ; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v2 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v2
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v2
; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 ; GCN-NEXT: v_mul_lo_u32 v12, v5, v9
; GCN-NEXT: v_mul_hi_u32 v9, v5, v9 ; GCN-NEXT: v_mul_hi_u32 v9, v5, v9
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc ; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc
; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc ; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc
; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v8 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GCN-NEXT: v_addc_u32_e64 v8, vcc, v5, v9, s[4:5] ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc
foadAuthorUnsubmitted
Done
ReplyInline Actions

This is probably the clearest place to see the effect of the patch. Here, in the old code, we save the carry-out from one add into s[4:5] in order to use it again 20-odd instructions later...

foad: This is probably the clearest place to see the effect of the patch. Here, in the old code, we…
; GCN-NEXT: v_mul_lo_u32 v10, v6, v8 ; GCN-NEXT: v_mul_lo_u32 v8, v6, v5
; GCN-NEXT: v_mul_hi_u32 v11, v6, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v6, v4
; GCN-NEXT: v_mul_lo_u32 v7, v7, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v7, v4
; GCN-NEXT: v_mul_lo_u32 v6, v6, v4 ; GCN-NEXT: v_mul_lo_u32 v6, v6, v4
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GCN-NEXT: v_mul_lo_u32 v10, v4, v7
; GCN-NEXT: v_mul_hi_u32 v11, v4, v6
; GCN-NEXT: v_mul_hi_u32 v12, v4, v7
; GCN-NEXT: v_mul_hi_u32 v9, v5, v6
; GCN-NEXT: v_mul_lo_u32 v6, v5, v6
; GCN-NEXT: v_mul_hi_u32 v8, v5, v7
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 ; GCN-NEXT: v_addc_u32_e32 v11, vcc, v14, v12, vcc
; GCN-NEXT: v_mul_lo_u32 v12, v4, v7 ; GCN-NEXT: v_mul_lo_u32 v7, v5, v7
; GCN-NEXT: v_mul_hi_u32 v15, v4, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
; GCN-NEXT: v_mul_hi_u32 v16, v4, v7 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc
; GCN-NEXT: v_mul_hi_u32 v11, v8, v6 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc
; GCN-NEXT: v_mul_lo_u32 v6, v8, v6
; GCN-NEXT: v_mul_hi_u32 v10, v8, v7
; GCN-NEXT: v_add_i32_e32 v12, vcc, v15, v12
; GCN-NEXT: v_addc_u32_e32 v15, vcc, v14, v16, vcc
; GCN-NEXT: v_mul_lo_u32 v7, v8, v7
; GCN-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v15, v11, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v13, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
foadAuthorUnsubmitted
Done
ReplyInline Actions

.. and here we recompute v5+v9 but without carry-in from the corresponding low part addition v4+v8, but in the very next instruction we add back in the missing carry!

foad: .. and here we recompute v5+v9 but //without// carry-in from the corresponding low part…
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
; GCN-NEXT: v_mul_lo_u32 v6, v0, v5 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v5
; GCN-NEXT: v_mul_hi_u32 v7, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v8, v0, v5 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v5
; GCN-NEXT: v_mul_hi_u32 v9, v1, v5 ; GCN-NEXT: v_mul_hi_u32 v9, v1, v5
; GCN-NEXT: v_mul_lo_u32 v5, v1, v5 ; GCN-NEXT: v_mul_lo_u32 v5, v1, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v1, v4 ; GCN-NEXT: v_mul_lo_u32 v8, v1, v4
▲ Show 20 Lines • Show All 423 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_and_b32 s8, s8, s7 ; GCN-NEXT: s_and_b32 s8, s8, s7
; GCN-NEXT: s_lshr_b64 s[0:1], s[2:3], 24 ; GCN-NEXT: s_lshr_b64 s[0:1], s[2:3], 24
; GCN-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 ; GCN-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1 ; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
; GCN-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mac_f32_e32 v1, 0xcf800000, v2 ; GCN-NEXT: v_mac_f32_e32 v1, 0xcf800000, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
; GCN-NEXT: s_sub_u32 s2, 0, s0 ; GCN-NEXT: s_sub_u32 s0, 0, s0
; GCN-NEXT: s_subb_u32 s3, 0, s1 ; GCN-NEXT: s_subb_u32 s1, 0, s1
; GCN-NEXT: v_mul_hi_u32 v3, s2, v1 ; GCN-NEXT: v_mul_hi_u32 v3, s0, v1
; GCN-NEXT: v_mul_lo_u32 v4, s2, v2 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v2
; GCN-NEXT: v_mul_lo_u32 v5, s3, v1 ; GCN-NEXT: v_mul_lo_u32 v5, s1, v1
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, s2, v1 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v1
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_mul_lo_u32 v6, v1, v3 ; GCN-NEXT: v_mul_lo_u32 v6, v1, v3
; GCN-NEXT: v_mul_hi_u32 v7, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v7, v1, v4
; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 ; GCN-NEXT: v_mul_hi_u32 v5, v1, v3
; GCN-NEXT: v_mul_hi_u32 v10, v2, v3 ; GCN-NEXT: v_mul_hi_u32 v10, v2, v3
; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 ; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v2, v4
; GCN-NEXT: v_mul_hi_u32 v4, v2, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v2, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc
; GCN-NEXT: v_add_i32_e64 v1, s[0:1], v1, v3 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[0:1] ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v5, s2, v3 ; GCN-NEXT: v_mul_lo_u32 v3, s0, v2
; GCN-NEXT: v_mul_hi_u32 v6, s2, v1 ; GCN-NEXT: v_mul_hi_u32 v4, s0, v1
; GCN-NEXT: v_mul_lo_u32 v7, s3, v1 ; GCN-NEXT: v_mul_lo_u32 v5, s1, v1
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_mul_lo_u32 v6, s2, v1 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v1
; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; GCN-NEXT: v_mul_lo_u32 v11, v1, v5 ; GCN-NEXT: v_mul_lo_u32 v7, v1, v3
; GCN-NEXT: v_mul_hi_u32 v12, v1, v6 ; GCN-NEXT: v_mul_hi_u32 v10, v1, v4
; GCN-NEXT: v_mul_hi_u32 v13, v1, v5 ; GCN-NEXT: v_mul_hi_u32 v11, v1, v3
; GCN-NEXT: v_mul_hi_u32 v10, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v4, v2, v4
; GCN-NEXT: v_mul_hi_u32 v7, v3, v5 ; GCN-NEXT: v_mul_hi_u32 v5, v2, v3
; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GCN-NEXT: v_addc_u32_e32 v12, vcc, v9, v13, vcc ; GCN-NEXT: v_addc_u32_e32 v10, vcc, v9, v11, vcc
; GCN-NEXT: v_mul_lo_u32 v3, v3, v5 ; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
; GCN-NEXT: v_add_i32_e32 v6, vcc, v11, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v12, v10, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v8, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-NEXT: v_mov_b32_e32 v3, s8 ; GCN-NEXT: v_mov_b32_e32 v3, s8
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
; GCN-NEXT: v_alignbit_b32 v3, s6, v3, 24 ; GCN-NEXT: v_alignbit_b32 v3, s6, v3, 24
; GCN-NEXT: v_mul_lo_u32 v4, v3, v2 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v2
; GCN-NEXT: v_mul_hi_u32 v1, v3, v1 ; GCN-NEXT: v_mul_hi_u32 v1, v3, v1
; GCN-NEXT: v_mul_hi_u32 v2, v3, v2 ; GCN-NEXT: v_mul_hi_u32 v2, v3, v2
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v2, vcc
; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1 ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines; GCN-IR-NEXT: s_endpgm
%result = udiv i48 %1, %2 %result = udiv i48 %1, %2
store i48 %result, i48 addrspace(1)* %out store i48 %result, i48 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
; GCN-LABEL: s_test_udiv_k_num_i64: ; GCN-LABEL: s_test_udiv_k_num_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: s_mov_b32 s11, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s10, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3
; GCN-NEXT: s_sub_u32 s2, 0, s6 ; GCN-NEXT: s_sub_u32 s4, 0, s2
; GCN-NEXT: s_subb_u32 s3, 0, s7 ; GCN-NEXT: s_subb_u32 s5, 0, s3
; GCN-NEXT: s_mov_b32 s8, s4
; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s9, s5
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v3, v3 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 ; GCN-NEXT: v_mul_lo_u32 v4, s4, v3
; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s4, v0
; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 ; GCN-NEXT: v_mul_lo_u32 v7, s5, v0
; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s4, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v6
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_hi_u32 v8, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v8, v3, v6
; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v10, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 ; GCN-NEXT: v_mul_lo_u32 v4, s4, v3
; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s4, v0
; GCN-NEXT: v_mul_lo_u32 v8, s3, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s5, v0
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 ; GCN-NEXT: v_mul_lo_u32 v5, s4, v0
; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 ; GCN-NEXT: v_mul_lo_u32 v8, v0, v4
; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v5
; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 ; GCN-NEXT: v_mul_hi_u32 v10, v0, v4
; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 ; GCN-NEXT: v_mul_hi_u32 v7, v3, v5
; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v4
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc ; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v3, v1, 24 ; GCN-NEXT: v_mul_lo_u32 v3, v1, 24
; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v0, v0, 24
; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 ; GCN-NEXT: v_mul_hi_u32 v1, v1, 24
; GCN-NEXT: v_mov_b32_e32 v5, s7 ; GCN-NEXT: v_mov_b32_e32 v5, s3
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v1, s7, v0 ; GCN-NEXT: v_mul_lo_u32 v1, s3, v0
; GCN-NEXT: v_mul_hi_u32 v3, s6, v0 ; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1
; GCN-NEXT: v_mul_lo_u32 v3, s6, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s2, v0
; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v1 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v1
; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v3 ; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v3
; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc ; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s6, v3 ; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3
; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] ; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v4 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v5 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s7, v4 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4
; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 ; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0
; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v2, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v2, s[0:1]
; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 ; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0
; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: v_addc_u32_e64 v2, s[0:1], 0, v2, s[0:1] ; GCN-NEXT: v_addc_u32_e64 v2, s[0:1], 0, v2, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s7, v1 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v3 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3
; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s7, v1 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_udiv_k_num_i64: ; GCN-IR-LABEL: s_test_udiv_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3
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; GCN-NEXT: v_mul_lo_u32 v10, v3, v9 ; GCN-NEXT: v_mul_lo_u32 v10, v3, v9
; GCN-NEXT: v_mul_hi_u32 v9, v3, v9 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v9
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v7, vcc
; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc
; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v6 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[4:5] ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v4, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v3
; GCN-NEXT: v_mul_hi_u32 v9, v4, v2 ; GCN-NEXT: v_mul_hi_u32 v7, v4, v2
; GCN-NEXT: v_mul_lo_u32 v5, v5, v2 ; GCN-NEXT: v_mul_lo_u32 v5, v5, v2
; GCN-NEXT: v_mul_lo_u32 v4, v4, v2 ; GCN-NEXT: v_mul_lo_u32 v4, v4, v2
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-NEXT: v_mul_lo_u32 v8, v2, v5
; GCN-NEXT: v_mul_hi_u32 v9, v2, v4
; GCN-NEXT: v_mul_hi_u32 v10, v2, v5
; GCN-NEXT: v_mul_hi_u32 v7, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_mul_hi_u32 v6, v3, v5
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v12, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
; GCN-NEXT: v_mul_hi_u32 v13, v2, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
; GCN-NEXT: v_mul_hi_u32 v14, v2, v5 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v6, v4 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v11, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v6, v4
; GCN-NEXT: v_mul_hi_u32 v8, v6, v5
; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v10
; GCN-NEXT: v_addc_u32_e32 v13, vcc, v12, v14, vcc
; GCN-NEXT: v_mul_lo_u32 v5, v6, v5
; GCN-NEXT: v_add_i32_e32 v4, vcc, v10, v4
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v13, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v11, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v3, v5, vcc
; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
; GCN-NEXT: v_mul_lo_u32 v3, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v2
; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_mul_lo_u32 v4, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v4, v0, v2
; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v3 ; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v3
; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0x8000, v4 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0x8000, v4
; GCN-NEXT: v_subb_u32_e64 v5, s[4:5], v5, v1, vcc ; GCN-NEXT: v_subb_u32_e64 v5, s[4:5], v5, v1, vcc
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} }
define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
; GCN-LABEL: s_test_udiv_k_den_i64: ; GCN-LABEL: s_test_udiv_k_den_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000 ; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000
; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: s_movk_i32 s2, 0xffe8 ; GCN-NEXT: s_movk_i32 s4, 0xffe8
; GCN-NEXT: v_mov_b32_e32 v8, 0 ; GCN-NEXT: v_mov_b32_e32 v8, 0
; GCN-NEXT: v_mov_b32_e32 v7, 0 ; GCN-NEXT: v_mov_b32_e32 v7, 0
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: v_mul_hi_u32 v2, v0, s2 ; GCN-NEXT: v_mul_hi_u32 v2, v0, s4
; GCN-NEXT: v_mul_lo_u32 v3, v1, s2 ; GCN-NEXT: v_mul_lo_u32 v3, v1, s4
; GCN-NEXT: v_mul_lo_u32 v4, v0, s2 ; GCN-NEXT: v_mul_lo_u32 v4, v0, s4
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 ; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v6, v0, v4
; GCN-NEXT: v_mul_hi_u32 v3, v0, v2 ; GCN-NEXT: v_mul_hi_u32 v3, v0, v2
; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 ; GCN-NEXT: v_mul_hi_u32 v9, v1, v2
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 ; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v4, v0, s2
; GCN-NEXT: v_mul_lo_u32 v5, v2, s2
; GCN-NEXT: v_mul_lo_u32 v6, v0, s2
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, s8
; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GCN-NEXT: v_mul_lo_u32 v5, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v6
; GCN-NEXT: v_mul_hi_u32 v10, v0, v4
; GCN-NEXT: v_mul_hi_u32 v11, v2, v4
; GCN-NEXT: s_mov_b32 s5, s9
; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v10, v2, v6
; GCN-NEXT: v_mul_hi_u32 v6, v2, v6
; GCN-NEXT: v_mul_lo_u32 v2, v2, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v10
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 ; GCN-NEXT: v_mul_hi_u32 v2, v0, s4
; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 ; GCN-NEXT: v_mul_lo_u32 v3, v1, s4
; GCN-NEXT: v_mul_hi_u32 v4, s10, v1 ; GCN-NEXT: v_mul_lo_u32 v4, v0, s4
; GCN-NEXT: v_mul_hi_u32 v5, s11, v1 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: v_mul_lo_u32 v1, s11, v1 ; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GCN-NEXT: v_mul_lo_u32 v3, v0, v2
; GCN-NEXT: v_mul_hi_u32 v5, v0, v4
; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
; GCN-NEXT: v_mul_hi_u32 v9, v1, v2
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc
; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s2, v1
; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
; GCN-NEXT: v_mul_hi_u32 v4, s2, v1
; GCN-NEXT: v_mul_hi_u32 v5, s3, v1
; GCN-NEXT: v_mul_lo_u32 v1, s3, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s11, v0 ; GCN-NEXT: v_mul_lo_u32 v4, s3, v0
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v1, 24 ; GCN-NEXT: v_mul_lo_u32 v4, v1, 24
; GCN-NEXT: v_mul_hi_u32 v5, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v5, v0, 24
; GCN-NEXT: v_add_i32_e32 v2, vcc, 2, v0 ; GCN-NEXT: v_add_i32_e32 v2, vcc, 2, v0
; GCN-NEXT: v_mul_lo_u32 v8, v0, 24 ; GCN-NEXT: v_mul_lo_u32 v8, v0, 24
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, 1, v0 ; GCN-NEXT: v_add_i32_e32 v6, vcc, 1, v0
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_mov_b32_e32 v5, s11 ; GCN-NEXT: v_mov_b32_e32 v5, s3
; GCN-NEXT: v_sub_i32_e32 v8, vcc, s10, v8 ; GCN-NEXT: v_sub_i32_e32 v8, vcc, s2, v8
; GCN-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc ; GCN-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc
; GCN-NEXT: v_subrev_i32_e32 v5, vcc, 24, v8 ; GCN-NEXT: v_subrev_i32_e32 v5, vcc, 24, v8
; GCN-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc ; GCN-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v5 ; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v5
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GCN-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc ; GCN-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v8 ; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v8
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
define i64 @v_test_udiv_k_den_i64(i64 %x) { define i64 @v_test_udiv_k_den_i64(i64 %x) {
; GCN-LABEL: v_test_udiv_k_den_i64: ; GCN-LABEL: v_test_udiv_k_den_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000 ; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000
; GCN-NEXT: v_madak_f32 v2, 0, v2, 0x41c00000 ; GCN-NEXT: v_madak_f32 v2, 0, v2, 0x41c00000
; GCN-NEXT: v_rcp_f32_e32 v2, v2 ; GCN-NEXT: v_rcp_f32_e32 v2, v2
; GCN-NEXT: s_movk_i32 s6, 0xffe8 ; GCN-NEXT: s_movk_i32 s4, 0xffe8
; GCN-NEXT: v_mov_b32_e32 v10, 0 ; GCN-NEXT: v_mov_b32_e32 v10, 0
; GCN-NEXT: v_mov_b32_e32 v9, 0 ; GCN-NEXT: v_mov_b32_e32 v9, 0
; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
; GCN-NEXT: v_trunc_f32_e32 v3, v3 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 ; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_mul_hi_u32 v4, v2, s6 ; GCN-NEXT: v_mul_hi_u32 v4, v2, s4
; GCN-NEXT: v_mul_lo_u32 v5, v3, s6 ; GCN-NEXT: v_mul_lo_u32 v5, v3, s4
; GCN-NEXT: v_mul_lo_u32 v6, v2, s6 ; GCN-NEXT: v_mul_lo_u32 v6, v2, s4
; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v2, v4 ; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v2, v4
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v2, v4
; GCN-NEXT: v_mul_hi_u32 v8, v2, v6 ; GCN-NEXT: v_mul_hi_u32 v8, v2, v6
; GCN-NEXT: v_mul_hi_u32 v5, v2, v4 ; GCN-NEXT: v_mul_hi_u32 v5, v2, v4
; GCN-NEXT: v_mul_hi_u32 v11, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v11, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v5, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc
; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v4
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[4:5]
; GCN-NEXT: v_mul_hi_u32 v6, v2, s6
; GCN-NEXT: v_mul_lo_u32 v7, v4, s6
; GCN-NEXT: v_mul_lo_u32 v8, v2, s6
; GCN-NEXT: v_subrev_i32_e32 v6, vcc, v2, v6
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GCN-NEXT: v_mul_lo_u32 v7, v2, v6
; GCN-NEXT: v_mul_hi_u32 v11, v2, v8
; GCN-NEXT: v_mul_hi_u32 v12, v2, v6
; GCN-NEXT: v_mul_hi_u32 v13, v4, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v10, v12, vcc
; GCN-NEXT: v_mul_lo_u32 v12, v4, v8
; GCN-NEXT: v_mul_hi_u32 v8, v4, v8
; GCN-NEXT: v_mul_lo_u32 v4, v4, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v12
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v8, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v9, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v6, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[4:5]
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_hi_u32 v4, v2, s4
; GCN-NEXT: v_mul_lo_u32 v5, v3, s4
; GCN-NEXT: v_mul_lo_u32 v6, v2, s4
; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v2, v4
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GCN-NEXT: v_mul_lo_u32 v5, v2, v4
; GCN-NEXT: v_mul_hi_u32 v7, v2, v6
; GCN-NEXT: v_mul_hi_u32 v8, v2, v4
; GCN-NEXT: v_mul_hi_u32 v11, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v10, v8, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v0, v3 ; GCN-NEXT: v_mul_lo_u32 v4, v0, v3
; GCN-NEXT: v_mul_hi_u32 v5, v0, v2 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v2
; GCN-NEXT: v_mul_hi_u32 v6, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v6, v0, v3
; GCN-NEXT: v_mul_hi_u32 v7, v1, v3 ; GCN-NEXT: v_mul_hi_u32 v7, v1, v3
; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc
; GCN-NEXT: v_mul_lo_u32 v6, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v6, v1, v2
▲ Show 20 Lines • Show All 316 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/urem64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) { define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_urem_i64: ; GCN-LABEL: s_test_urem_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13
; GCN-NEXT: s_sub_u32 s2, 0, s12 ; GCN-NEXT: s_sub_u32 s0, 0, s12
; GCN-NEXT: s_subb_u32 s3, 0, s13 ; GCN-NEXT: s_subb_u32 s1, 0, s13
; GCN-NEXT: s_mov_b32 s4, s8 ; GCN-NEXT: s_mov_b32 s4, s8
; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s5, s9 ; GCN-NEXT: s_mov_b32 s5, s9
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v3, v3 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v3
; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s0, v0
; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 ; GCN-NEXT: v_mul_lo_u32 v7, s1, v0
; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s0, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v6
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
; GCN-NEXT: v_mul_lo_u32 v6, s2, v4
; GCN-NEXT: v_mul_hi_u32 v7, s2, v0
; GCN-NEXT: v_mul_lo_u32 v8, s3, v0
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_mul_lo_u32 v7, s2, v0
; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GCN-NEXT: v_mul_lo_u32 v10, v0, v6
; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
; GCN-NEXT: v_mul_hi_u32 v12, v0, v6
; GCN-NEXT: v_mul_hi_u32 v9, v4, v7
; GCN-NEXT: v_mul_lo_u32 v7, v4, v7
; GCN-NEXT: v_mul_hi_u32 v8, v4, v6
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v4, v6
; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s0, v3
; GCN-NEXT: v_mul_hi_u32 v5, s0, v0
; GCN-NEXT: v_mul_lo_u32 v6, s1, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_mul_lo_u32 v5, s0, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GCN-NEXT: v_mul_lo_u32 v8, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v5
; GCN-NEXT: v_mul_hi_u32 v10, v0, v4
; GCN-NEXT: v_mul_hi_u32 v7, v3, v5
; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
; GCN-NEXT: v_mul_hi_u32 v6, v3, v4
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s10, v3 ; GCN-NEXT: v_mul_lo_u32 v4, s10, v3
; GCN-NEXT: v_mul_hi_u32 v5, s10, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s10, v0
; GCN-NEXT: v_mul_hi_u32 v6, s10, v3 ; GCN-NEXT: v_mul_hi_u32 v6, s10, v3
; GCN-NEXT: v_mul_hi_u32 v7, s11, v3 ; GCN-NEXT: v_mul_hi_u32 v7, s11, v3
; GCN-NEXT: v_mul_lo_u32 v3, s11, v3 ; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_mul_lo_u32 v6, s11, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s11, v0
▲ Show 20 Lines • Show All 176 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 ; GCN-NEXT: v_mul_lo_u32 v12, v5, v9
; GCN-NEXT: v_mul_hi_u32 v9, v5, v9 ; GCN-NEXT: v_mul_hi_u32 v9, v5, v9
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc ; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc
; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc ; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc
; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v8 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GCN-NEXT: v_addc_u32_e64 v8, vcc, v5, v9, s[4:5] ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc
; GCN-NEXT: v_mul_lo_u32 v10, v6, v8 ; GCN-NEXT: v_mul_lo_u32 v8, v6, v5
; GCN-NEXT: v_mul_hi_u32 v11, v6, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v6, v4
; GCN-NEXT: v_mul_lo_u32 v7, v7, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v7, v4
; GCN-NEXT: v_mul_lo_u32 v6, v6, v4 ; GCN-NEXT: v_mul_lo_u32 v6, v6, v4
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; GCN-NEXT: v_mul_lo_u32 v10, v4, v7
; GCN-NEXT: v_mul_hi_u32 v11, v4, v6
; GCN-NEXT: v_mul_hi_u32 v12, v4, v7
; GCN-NEXT: v_mul_hi_u32 v9, v5, v6
; GCN-NEXT: v_mul_lo_u32 v6, v5, v6
; GCN-NEXT: v_mul_hi_u32 v8, v5, v7
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 ; GCN-NEXT: v_addc_u32_e32 v11, vcc, v14, v12, vcc
; GCN-NEXT: v_mul_lo_u32 v12, v4, v7 ; GCN-NEXT: v_mul_lo_u32 v7, v5, v7
; GCN-NEXT: v_mul_hi_u32 v15, v4, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
; GCN-NEXT: v_mul_hi_u32 v16, v4, v7 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc
; GCN-NEXT: v_mul_hi_u32 v11, v8, v6 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc
; GCN-NEXT: v_mul_lo_u32 v6, v8, v6
; GCN-NEXT: v_mul_hi_u32 v10, v8, v7
; GCN-NEXT: v_add_i32_e32 v12, vcc, v15, v12
; GCN-NEXT: v_addc_u32_e32 v15, vcc, v14, v16, vcc
; GCN-NEXT: v_mul_lo_u32 v7, v8, v7
; GCN-NEXT: v_add_i32_e32 v6, vcc, v12, v6
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v15, v11, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v13, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
; GCN-NEXT: v_mul_lo_u32 v6, v0, v5 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v5
; GCN-NEXT: v_mul_hi_u32 v7, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v8, v0, v5 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v5
; GCN-NEXT: v_mul_hi_u32 v9, v1, v5 ; GCN-NEXT: v_mul_hi_u32 v9, v1, v5
; GCN-NEXT: v_mul_lo_u32 v5, v1, v5 ; GCN-NEXT: v_mul_lo_u32 v5, v1, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v1, v4 ; GCN-NEXT: v_mul_lo_u32 v8, v1, v4
▲ Show 20 Lines • Show All 441 Lines • ▼ Show 20 Lines
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: s_mov_b32 s11, 0xf000 ; GCN-NEXT: s_mov_b32 s11, 0xf000
; GCN-NEXT: s_mov_b32 s10, -1 ; GCN-NEXT: s_mov_b32 s10, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7
; GCN-NEXT: s_sub_u32 s2, 0, s6 ; GCN-NEXT: s_sub_u32 s0, 0, s6
; GCN-NEXT: s_subb_u32 s3, 0, s7 ; GCN-NEXT: s_subb_u32 s1, 0, s7
; GCN-NEXT: s_mov_b32 s8, s4 ; GCN-NEXT: s_mov_b32 s8, s4
; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s9, s5 ; GCN-NEXT: s_mov_b32 s9, s5
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v3, v3 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v3
; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s0, v0
; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 ; GCN-NEXT: v_mul_lo_u32 v7, s1, v0
; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s0, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v6
; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v4
; GCN-NEXT: v_mul_hi_u32 v8, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v8, v3, v6
; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v10, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v3
; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 ; GCN-NEXT: v_mul_hi_u32 v5, s0, v0
; GCN-NEXT: v_mul_lo_u32 v8, s3, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s1, v0
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 ; GCN-NEXT: v_mul_lo_u32 v5, s0, v0
; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 ; GCN-NEXT: v_mul_lo_u32 v8, v0, v4
; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v5
; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 ; GCN-NEXT: v_mul_hi_u32 v10, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 ; GCN-NEXT: v_mul_hi_u32 v7, v3, v5
; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v4
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v3, v1, 24 ; GCN-NEXT: v_mul_lo_u32 v3, v1, 24
; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v0, v0, 24
; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 ; GCN-NEXT: v_mul_hi_u32 v1, v1, 24
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v1, s7, v0 ; GCN-NEXT: v_mul_lo_u32 v1, s7, v0
; GCN-NEXT: v_mul_hi_u32 v2, s6, v0 ; GCN-NEXT: v_mul_hi_u32 v2, s6, v0
; GCN-NEXT: v_mul_lo_u32 v0, s6, v0 ; GCN-NEXT: v_mul_lo_u32 v0, s6, v0
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
} }
define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) { define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
; GCN-LABEL: s_test_urem_k_den_i64: ; GCN-LABEL: s_test_urem_k_den_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000 ; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000 ; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000
; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: s_movk_i32 s2, 0xffe8 ; GCN-NEXT: s_movk_i32 s4, 0xffe8
; GCN-NEXT: v_mov_b32_e32 v8, 0 ; GCN-NEXT: v_mov_b32_e32 v8, 0
; GCN-NEXT: v_mov_b32_e32 v7, 0 ; GCN-NEXT: v_mov_b32_e32 v7, 0
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s11, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: v_mul_hi_u32 v2, v0, s2 ; GCN-NEXT: v_mul_hi_u32 v2, v0, s4
; GCN-NEXT: v_mul_lo_u32 v3, v1, s2 ; GCN-NEXT: v_mul_lo_u32 v3, v1, s4
; GCN-NEXT: v_mul_lo_u32 v4, v0, s2 ; GCN-NEXT: v_mul_lo_u32 v4, v0, s4
; GCN-NEXT: s_mov_b32 s10, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 ; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v6, v0, v4
; GCN-NEXT: v_mul_hi_u32 v3, v0, v2 ; GCN-NEXT: v_mul_hi_u32 v3, v0, v2
; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 ; GCN-NEXT: v_mul_hi_u32 v9, v1, v2
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 ; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
; GCN-NEXT: v_mul_hi_u32 v4, v0, s2
; GCN-NEXT: v_mul_lo_u32 v5, v2, s2
; GCN-NEXT: v_mul_lo_u32 v6, v0, s2
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s4
; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GCN-NEXT: v_mul_lo_u32 v5, v0, v4
; GCN-NEXT: v_mul_hi_u32 v9, v0, v6
; GCN-NEXT: v_mul_hi_u32 v10, v0, v4
; GCN-NEXT: v_mul_hi_u32 v11, v2, v4
; GCN-NEXT: s_mov_b32 s9, s5
; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v10, v2, v6
; GCN-NEXT: v_mul_hi_u32 v6, v2, v6
; GCN-NEXT: v_mul_lo_u32 v2, v2, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v10
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s6, v1 ; GCN-NEXT: v_mul_hi_u32 v2, v0, s4
; GCN-NEXT: v_mul_hi_u32 v3, s6, v0 ; GCN-NEXT: v_mul_lo_u32 v3, v1, s4
; GCN-NEXT: v_mul_hi_u32 v4, s6, v1 ; GCN-NEXT: v_mul_lo_u32 v4, v0, s4
; GCN-NEXT: v_mul_hi_u32 v5, s7, v1 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: v_mul_lo_u32 v1, s7, v1 ; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GCN-NEXT: v_mul_lo_u32 v3, v0, v2
; GCN-NEXT: v_mul_hi_u32 v5, v0, v4
; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
; GCN-NEXT: v_mul_hi_u32 v9, v1, v2
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc
; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s2, v1
; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
; GCN-NEXT: v_mul_hi_u32 v4, s2, v1
; GCN-NEXT: v_mul_hi_u32 v5, s3, v1
; GCN-NEXT: v_mul_lo_u32 v1, s3, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s7, v0 ; GCN-NEXT: v_mul_lo_u32 v4, s3, v0
; GCN-NEXT: v_mul_hi_u32 v0, s7, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc
; GCN-NEXT: v_mul_lo_u32 v1, v1, 24 ; GCN-NEXT: v_mul_lo_u32 v1, v1, 24
; GCN-NEXT: v_mul_hi_u32 v2, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v2, v0, 24
; GCN-NEXT: v_mul_lo_u32 v0, v0, 24 ; GCN-NEXT: v_mul_lo_u32 v0, v0, 24
; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-NEXT: v_mov_b32_e32 v2, s7 ; GCN-NEXT: v_mov_b32_e32 v2, s3
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0 ; GCN-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
; GCN-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc ; GCN-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
; GCN-NEXT: v_subrev_i32_e32 v4, vcc, 24, v2 ; GCN-NEXT: v_subrev_i32_e32 v4, vcc, 24, v2
; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v3, vcc ; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v2 ; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v2
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; GCN-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc ; GCN-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v0 ; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v0
; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GCN-IR-LABEL: s_test_urem_k_den_i64: ; GCN-IR-LABEL: s_test_urem_k_den_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mul_lo_u32 v10, v3, v9 ; GCN-NEXT: v_mul_lo_u32 v10, v3, v9
; GCN-NEXT: v_mul_hi_u32 v9, v3, v9 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v9
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v7, vcc
; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc
; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v6 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[4:5] ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v4, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v3
; GCN-NEXT: v_mul_hi_u32 v9, v4, v2 ; GCN-NEXT: v_mul_hi_u32 v7, v4, v2
; GCN-NEXT: v_mul_lo_u32 v5, v5, v2 ; GCN-NEXT: v_mul_lo_u32 v5, v5, v2
; GCN-NEXT: v_mul_lo_u32 v4, v4, v2 ; GCN-NEXT: v_mul_lo_u32 v4, v4, v2
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-NEXT: v_mul_lo_u32 v8, v2, v5
; GCN-NEXT: v_mul_hi_u32 v9, v2, v4
; GCN-NEXT: v_mul_hi_u32 v10, v2, v5
; GCN-NEXT: v_mul_hi_u32 v7, v3, v4
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
; GCN-NEXT: v_mul_hi_u32 v6, v3, v5
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v12, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
; GCN-NEXT: v_mul_hi_u32 v13, v2, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
; GCN-NEXT: v_mul_hi_u32 v14, v2, v5 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
; GCN-NEXT: v_mul_hi_u32 v9, v6, v4 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v11, vcc
; GCN-NEXT: v_mul_lo_u32 v4, v6, v4
; GCN-NEXT: v_mul_hi_u32 v8, v6, v5
; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v10
; GCN-NEXT: v_addc_u32_e32 v13, vcc, v12, v14, vcc
; GCN-NEXT: v_mul_lo_u32 v5, v6, v5
; GCN-NEXT: v_add_i32_e32 v4, vcc, v10, v4
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v13, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v11, vcc
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v3, v5, vcc
; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
; GCN-NEXT: v_mul_lo_u32 v3, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v2
; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
; GCN-NEXT: v_mul_lo_u32 v2, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v0, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0x8000, v2 ; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0x8000, v2
; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc ; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
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llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll