[PowerPC] Allow scalars for asm constraint "v" with VSX

[nemanjai]

Summary

Similarly to what GCC does, we should allow scalars with the "v" constraint rather than introducing unnecessary new constraints for scalars in Altivec registers.

[saghir]

LGTM.

[amyk]

I just had a couple minor comments.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

17696

Is it possible to add a comment to detail what exactly is going on here for future reference?

llvm/test/CodeGen/PowerPC/scalars-in-altivec-regs.ll

2

I think -ppc-asm-full-reg-names works with the AIX triple now. It would be good to add this option prior to committing.

llvm/lib/Target/PowerPC/PPCISelLowering.h

PPC::AddrMode SelectOptimalAddrMode(const SDNode *Parent, SDValue N,
                                         SDValue &Disp, SDValue &Base,
                                         SelectionDAG &DAG,
                                         MaybeAlign Align) const;
     /// SelectForceXFormMode - Given the specified address, force it to be
     /// represented as an indexed [r+r] operation (an XForm instruction).
     PPC::AddrMode SelectForceXFormMode(SDValue N, SDValue &Disp, SDValue &Base,
                                        SelectionDAG &DAG) const;
 
+    bool
+    splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
+                                SDValue *Parts, unsigned NumParts, MVT PartVT,
+                                Optional<CallingConv::ID> CC) const override;
     /// Structure that collects some common arguments that get passed around
     /// between the functions for call lowering.
     struct CallFlags {
       const CallingConv::ID CallConv;
       const bool IsTailCall : 1;
       const bool IsVarArg : 1;
       const bool IsPatchPoint : 1;
       const bool IsIndirect : 1;

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

case 'f':
       } else {
         if (VT == MVT::f32 || VT == MVT::i32)
           return std::make_pair(0U, &PPC::F4RCRegClass);
         if (VT == MVT::f64 || VT == MVT::i64)
           return std::make_pair(0U, &PPC::F8RCRegClass);
       }
       break;
     case 'v':
-      if (Subtarget.hasAltivec())
+      if (Subtarget.hasAltivec() && VT.isVector())
         return std::make_pair(0U, &PPC::VRRCRegClass);
+      else if (Subtarget.hasVSX())
+        // Scalars in Altivec registers only make sense with VSX.
+        return std::make_pair(0U, &PPC::VFRCRegClass);
       break;
     case 'y':   // crrc
       return std::make_pair(0U, &PPC::CRRCRegClass);
     }
   } else if (Constraint == "wc" && Subtarget.useCRBits()) {
     // An individual CR bit.
     return std::make_pair(0U, &PPC::CRBITRCRegClass);
   } else if ((Constraint == "wa" || Constraint == "wd" ||
PPC::AddrMode PPCTargetLowering::SelectForceXFormMode(SDValue N, SDValue &Disp,
   // Otherwise, use R0 as the base register.
   Disp = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
                          N.getValueType());
   Base = N;
 
   return Mode;
 }
 
+bool PPCTargetLowering::splitValueIntoRegisterParts(
+    SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
+    unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
+  EVT ValVT = Val.getValueType();
+  if (PartVT == MVT::f64 &&
+      (ValVT == MVT::i32 || ValVT == MVT::i16 || ValVT == MVT::i8)) {
+    Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
+    Val = DAG.getNode(ISD::BITCAST, DL, MVT::f64, Val);
+    Parts[0] = Val;
+    return true;
+  }
+  return false;
+}
+
 // If we happen to match to an aligned D-Form, check if the Frame Index is
 // adequately aligned. If it is not, reset the mode to match to X-Form.
 static void setXFormForUnalignedFI(SDValue N, unsigned Flags,
                                    PPC::AddrMode &Mode) {
   if (!isa<FrameIndexSDNode>(N))
     return;
   if ((Mode == PPC::AM_DSForm && !(Flags & PPC::MOF_RPlusSImm16Mult4)) ||
       (Mode == PPC::AM_DQForm && !(Flags & PPC::MOF_RPlusSImm16Mult16)))

llvm/test/CodeGen/PowerPC/scalars-in-altivec-regs.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
+; RUN:   -mcpu=pwr8 < %s | FileCheck --check-prefix=AIX64 %s
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN:   -mcpu=pwr8 < %s | FileCheck --check-prefix=AIX32 %s
+; RUN: llc -mtriple=powerpc64le-- -verify-machineinstrs -mcpu=pwr8 | \
+; RUN:   FileCheck --check-prefix=LE %s
+
+define dso_local void @test1(<2 x double>* %v, i64 %a) local_unnamed_addr #0 {
+; AIX64-LABEL: test1:
+; AIX64:       # %bb.0: # %entry
+; AIX64-NEXT:    mtvsrd 34, 4
+; AIX64-NEXT:    #APP
+; AIX64-NEXT:    stvx 2, 0, 3
+; AIX64-NEXT:    #NO_APP
+; AIX64-NEXT:    blr
+;
+; AIX32-LABEL: test1:
+; AIX32:       # %bb.0: # %entry
+; AIX32-NEXT:    stw 5, -4(1)
+; AIX32-NEXT:    stw 4, -8(1)
+; AIX32-NEXT:    lfd 0, -8(1)
+; AIX32-NEXT:    xxlor 34, 0, 0
+; AIX32-NEXT:    #APP
+; AIX32-NEXT:    stvx 2, 0, 3
+; AIX32-NEXT:    #NO_APP
+; AIX32-NEXT:    blr
+;
+; LE-LABEL: test1:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    mtvsrd 34, 4
+; LE-NEXT:    #APP
+; LE-NEXT:    stvx 2, 0, 3
+; LE-NEXT:    #NO_APP
+; LE-NEXT:    blr
+entry:
+  tail call void asm sideeffect "stvx $0,0,$1", "v,r,~{memory}"(i64 %a, <2 x double>* %v)
+  ret void
+}
+
+define dso_local void @test2(<2 x double>* %v, i32 signext %a) local_unnamed_addr #0 {
+; AIX64-LABEL: test2:
+; AIX64:       # %bb.0: # %entry
+; AIX64-NEXT:    clrldi 4, 4, 32
+; AIX64-NEXT:    mtvsrd 34, 4
+; AIX64-NEXT:    #APP
+; AIX64-NEXT:    stvx 2, 0, 3
+; AIX64-NEXT:    #NO_APP
+; AIX64-NEXT:    blr
+;
+; AIX32-LABEL: test2:
+; AIX32:       # %bb.0: # %entry
+; AIX32-NEXT:    li 5, 0
+; AIX32-NEXT:    stw 4, -4(1)
+; AIX32-NEXT:    stw 5, -8(1)
+; AIX32-NEXT:    lfd 0, -8(1)
+; AIX32-NEXT:    xxlor 34, 0, 0
+; AIX32-NEXT:    #APP
+; AIX32-NEXT:    stvx 2, 0, 3
+; AIX32-NEXT:    #NO_APP
+; AIX32-NEXT:    blr
+;
+; LE-LABEL: test2:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    clrldi 4, 4, 32
+; LE-NEXT:    mtvsrd 34, 4
+; LE-NEXT:    #APP
+; LE-NEXT:    stvx 2, 0, 3
+; LE-NEXT:    #NO_APP
+; LE-NEXT:    blr
+entry:
+  tail call void asm sideeffect "stvx $0,0,$1", "v,r,~{memory}"(i32 %a, <2 x double>* %v)
+  ret void
+}
+
+define dso_local void @test3(<2 x double>* %v, i16 signext %a) local_unnamed_addr #0 {
+; AIX64-LABEL: test3:
+; AIX64:       # %bb.0: # %entry
+; AIX64-NEXT:    clrldi 4, 4, 48
+; AIX64-NEXT:    mtvsrd 34, 4
+; AIX64-NEXT:    #APP
+; AIX64-NEXT:    stvx 2, 0, 3
+; AIX64-NEXT:    #NO_APP
+; AIX64-NEXT:    blr
+;
+; AIX32-LABEL: test3:
+; AIX32:       # %bb.0: # %entry
+; AIX32-NEXT:    li 5, 0
+; AIX32-NEXT:    clrlwi 4, 4, 16
+; AIX32-NEXT:    stw 5, -8(1)
+; AIX32-NEXT:    stw 4, -4(1)
+; AIX32-NEXT:    lfd 0, -8(1)
+; AIX32-NEXT:    xxlor 34, 0, 0
+; AIX32-NEXT:    #APP
+; AIX32-NEXT:    stvx 2, 0, 3
+; AIX32-NEXT:    #NO_APP
+; AIX32-NEXT:    blr
+;
+; LE-LABEL: test3:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    clrldi 4, 4, 48
+; LE-NEXT:    mtvsrd 34, 4
+; LE-NEXT:    #APP
+; LE-NEXT:    stvx 2, 0, 3
+; LE-NEXT:    #NO_APP
+; LE-NEXT:    blr
+entry:
+  tail call void asm sideeffect "stvx $0,0,$1", "v,r,~{memory}"(i16 %a, <2 x double>* %v)
+  ret void
+}
+
+define dso_local void @test4(<2 x double>* %v, i8 signext %a) local_unnamed_addr #0 {
+; AIX64-LABEL: test4:
+; AIX64:       # %bb.0: # %entry
+; AIX64-NEXT:    clrldi 4, 4, 56
+; AIX64-NEXT:    mtvsrd 34, 4
+; AIX64-NEXT:    #APP
+; AIX64-NEXT:    stvx 2, 0, 3
+; AIX64-NEXT:    #NO_APP
+; AIX64-NEXT:    blr
+;
+; AIX32-LABEL: test4:
+; AIX32:       # %bb.0: # %entry
+; AIX32-NEXT:    li 5, 0
+; AIX32-NEXT:    clrlwi 4, 4, 24
+; AIX32-NEXT:    stw 5, -8(1)
+; AIX32-NEXT:    stw 4, -4(1)
+; AIX32-NEXT:    lfd 0, -8(1)
+; AIX32-NEXT:    xxlor 34, 0, 0
+; AIX32-NEXT:    #APP
+; AIX32-NEXT:    stvx 2, 0, 3
+; AIX32-NEXT:    #NO_APP
+; AIX32-NEXT:    blr
+;
+; LE-LABEL: test4:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    clrldi 4, 4, 56
+; LE-NEXT:    mtvsrd 34, 4
+; LE-NEXT:    #APP
+; LE-NEXT:    stvx 2, 0, 3
+; LE-NEXT:    #NO_APP
+; LE-NEXT:    blr
+entry:
+  tail call void asm sideeffect "stvx $0,0,$1", "v,r,~{memory}"(i8 %a, <2 x double>* %v)
+  ret void
+}
+
+define dso_local void @test6(<2 x double>* %v, i32 zeroext %a) local_unnamed_addr #0 {
+; AIX64-LABEL: test6:
+; AIX64:       # %bb.0: # %entry
+; AIX64-NEXT:    mtvsrd 34, 4
+; AIX64-NEXT:    #APP
+; AIX64-NEXT:    stvx 2, 0, 3
+; AIX64-NEXT:    #NO_APP
+; AIX64-NEXT:    blr
+;
+; AIX32-LABEL: test6:
+; AIX32:       # %bb.0: # %entry
+; AIX32-NEXT:    li 5, 0
+; AIX32-NEXT:    stw 4, -4(1)
+; AIX32-NEXT:    stw 5, -8(1)
+; AIX32-NEXT:    lfd 0, -8(1)
+; AIX32-NEXT:    xxlor 34, 0, 0
+; AIX32-NEXT:    #APP
+; AIX32-NEXT:    stvx 2, 0, 3
+; AIX32-NEXT:    #NO_APP
+; AIX32-NEXT:    blr
+;
+; LE-LABEL: test6:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    mtvsrd 34, 4
+; LE-NEXT:    #APP
+; LE-NEXT:    stvx 2, 0, 3
+; LE-NEXT:    #NO_APP
+; LE-NEXT:    blr
+entry:
+  tail call void asm sideeffect "stvx $0,0,$1", "v,r,~{memory}"(i32 %a, <2 x double>* %v)
+  ret void
+}
+
+define dso_local void @test7(<2 x double>* %v, i16 zeroext %a) local_unnamed_addr #0 {
+; AIX64-LABEL: test7:
+; AIX64:       # %bb.0: # %entry
+; AIX64-NEXT:    mtvsrd 34, 4
+; AIX64-NEXT:    #APP
+; AIX64-NEXT:    stvx 2, 0, 3
+; AIX64-NEXT:    #NO_APP
+; AIX64-NEXT:    blr
+;
+; AIX32-LABEL: test7:
+; AIX32:       # %bb.0: # %entry
+; AIX32-NEXT:    li 5, 0
+; AIX32-NEXT:    stw 4, -4(1)
+; AIX32-NEXT:    stw 5, -8(1)
+; AIX32-NEXT:    lfd 0, -8(1)
+; AIX32-NEXT:    xxlor 34, 0, 0
+; AIX32-NEXT:    #APP
+; AIX32-NEXT:    stvx 2, 0, 3
+; AIX32-NEXT:    #NO_APP
+; AIX32-NEXT:    blr
+;
+; LE-LABEL: test7:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    mtvsrd 34, 4
+; LE-NEXT:    #APP
+; LE-NEXT:    stvx 2, 0, 3
+; LE-NEXT:    #NO_APP
+; LE-NEXT:    blr
+entry:
+  tail call void asm sideeffect "stvx $0,0,$1", "v,r,~{memory}"(i16 %a, <2 x double>* %v)
+  ret void
+}
+
+define dso_local void @test8(<2 x double>* %v, i8 zeroext %a) local_unnamed_addr #0 {
+; AIX64-LABEL: test8:
+; AIX64:       # %bb.0: # %entry
+; AIX64-NEXT:    mtvsrd 34, 4
+; AIX64-NEXT:    #APP
+; AIX64-NEXT:    stvx 2, 0, 3
+; AIX64-NEXT:    #NO_APP
+; AIX64-NEXT:    blr
+;
+; AIX32-LABEL: test8:
+; AIX32:       # %bb.0: # %entry
+; AIX32-NEXT:    li 5, 0
+; AIX32-NEXT:    stw 4, -4(1)
+; AIX32-NEXT:    stw 5, -8(1)
+; AIX32-NEXT:    lfd 0, -8(1)
+; AIX32-NEXT:    xxlor 34, 0, 0
+; AIX32-NEXT:    #APP
+; AIX32-NEXT:    stvx 2, 0, 3
+; AIX32-NEXT:    #NO_APP
+; AIX32-NEXT:    blr
+;
+; LE-LABEL: test8:
+; LE:       # %bb.0: # %entry
+; LE-NEXT:    mtvsrd 34, 4
+; LE-NEXT:    #APP
+; LE-NEXT:    stvx 2, 0, 3
+; LE-NEXT:    #NO_APP
+; LE-NEXT:    blr
+entry:
+  tail call void asm sideeffect "stvx $0,0,$1", "v,r,~{memory}"(i8 %a, <2 x double>* %v)
+  ret void
+}
+
+attributes #0 = { nounwind }