[PowerPC] use right register class for input operand of XXPERMDIs

[shchenz]

Summary

This is from code review comments for D106555

In D106555, after we added:

def : Pat<(v2i64 (PPCzextldsplat ForceXForm:$A)),
          (v2i64 (XXPERMDIs (LFIWZX ForceXForm:$A), 0))>;
def : Pat<(v2i64 (PPCsextldsplat ForceXForm:$A)),
          (v2i64 (XXPERMDIs (LFIWAX ForceXForm:$A), 0))>;

some LIT cases change the input for vector splat instruction from vs0 to f0. But for vector splat instruction, like xxspltd, vs0 makes more sense than f0.

This patch changes register class for XXPERMDIs from vsfrc to vsrc. Now XXPERMDIs has same input type with XXPERMDI. So that it needs a vector register instead of a scalar float register.

Some other vector instructions have same issue, like XXSLDWI/XXSLDWIs, XXSPLTW/XXSPLTWs.

[jsji]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1069

I believe the intention was to use XXPERMDIs for single precision , for vsfrc, while XXPERMDI for vsrc.
Are we sure we are using XXPERMDIs correctly in D106555?

[shchenz]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1069

def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM),
                           "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;

XXPERMDIs should be an operation based on doubleword. I think the suffix s is for same, which means register operand are both the same?

Compared with XXPERMDI:

def XXPERMDI : XX3Form_2<60, 10,
                     (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM),
                     "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm,
                     [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB,
                       imm32SExt16:$DM))]>;

VSFRC is for f64, VSSRC is for f32, vsrc is for a vector type?

[qiucf]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

1069

Yes:

• F8RC contains first 64 double
• VFRC contains second 64 double
• VSLRC contains first 64 vector
• VRRC contains second 64 vector
• VSSRC contains all 128 float
• VSFRC contains all 128 double
• VSRC contains all 128 vector

[nemanjai]

I am not in favour of this patch. The reasons I added XXPERMDIs a long time ago are:

1. To allow a single input operand for single register splat/swap. This is useful when the input is a load (since due to chains, having a load as an input will end up with both loads emitted - i.e. no CSE).
2. Since this is primarily useful for loads that load a partial vector (LFIWZX, etc.) the input register class is vsfrc (i.e. all scalar floating point registers).

Switching the register class to vsrc does end up producing the name of a VSX register, but I consider that a positive thing. It clearly shows the reader that this is operating on a partial vector. Of course the distinction is purely aesthetic, but I think it helps readability.

[jsji]

Of course the distinction is purely aesthetic, but I think it helps readability.

Yes, this help readability when there are large number of instructions between lfiwax and xxspltd.
But this does introduce confusion about register classes -- it is suspicious that xxspltd operate on f0 instead of vs0.

I am OK with leaving it as it is, but I think we should at least add some comments in XXPERMDIs to clarify this register class change.

[shchenz]

In D113178#3111575, @jsji wrote:

Of course the distinction is purely aesthetic, but I think it helps readability.

Yes, this help readability when there are large number of instructions between lfiwax and xxspltd.
But this does introduce confusion about register classes -- it is suspicious that xxspltd operate on f0 instead of vs0.

I have the same feeling about the f0 instead of vs0. In Power ISA, instruction format for xxpermdi is like: xxpermdi XT,XA,XB,DM. I think XT, XA, XB are all for VSR register index even when XA == XB.

I am OK with leaving it as it is, but I think we should at least add some comments in XXPERMDIs to clarify this register class change.

OK, then I will abandon this patch, and commit an NFC patch to explain the different register classes for XXPERMDIs and XXPERMDI

Thanks for your review @nemanjai @jsji

[nemanjai]

In D113178#3111575, @jsji wrote:

...
But this does introduce confusion about register classes -- it is suspicious that xxspltd operate on f0 instead of vs0.

Ha ha, yup! Confusion about register classes is kind of a fact of life with PPC's complex overlaying of registers in a single register file. It certainly takes some time to get your mind around FP/VR/VSR/ACC registers.

But in any case, the neat feature of something like xxspltd vs34, f0, 0 is that you know that vs0 is only expected to be partially defined. So seeing something like xxspltd vs34, f0, 1 should set off some alarm bells because we are splatting what is expected to be undefined. No such determination can be made for xxspltd vs34, vs0, 1 (without tracking down how vs0 was defined).

[shchenz]

NFC patch 7c6f5950f08d41017536575152fb765ba85a09a1 is committed for the required comments.

Based on the discussion, we should abandon this patch.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def XXMRGLW : XX3Form<60, 50,
                        "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>;
 
   def XXPERMDI : XX3Form_2<60, 10,
                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM),
                        "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm,
                        [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB,
                          imm32SExt16:$DM))]>;
   let isCodeGenOnly = 1 in
-  def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM),
+  def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsrc:$XA, u2imm:$DM),
                              "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;
   def XXSEL : XX4Form<60, 3,
                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
                       "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
 
   def XXSLDWI : XX3Form_2<60, 2,
                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW),
                        "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm,
def : Pat<(v2f64 (PPCldsplat ForceXForm:$A)),
           (v2f64 (LXVDSX ForceXForm:$A))>;
 def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)),
           (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>;
 def : Pat<(v2i64 (PPCldsplat ForceXForm:$A)),
           (v2i64 (LXVDSX ForceXForm:$A))>;
 def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)),
           (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>;
 def : Pat<(v2i64 (PPCzextldsplat ForceXForm:$A)),
-          (v2i64 (XXPERMDIs (LFIWZX ForceXForm:$A), 0))>;
+          (v2i64 (XXPERMDIs (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 0))>;
 def : Pat<(v2i64 (PPCsextldsplat ForceXForm:$A)),
-          (v2i64 (XXPERMDIs (LFIWAX ForceXForm:$A), 0))>;
+          (v2i64 (XXPERMDIs (SUBREG_TO_REG (i64 1), (LFIWAX ForceXForm:$A), sub_64), 0))>;
 
 // Build vectors of floating point converted to i64.
-def : Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)),
-          (v2i64 (XXPERMDIs
-                   (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), 0))>;
-def : Pat<(v2i64 (build_vector FltToULong.A, FltToULong.A)),
-          (v2i64 (XXPERMDIs
-                   (COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), 0))>;
+def: Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)),
+      (v2i64 (XXPERMDIs 
+               (SUBREG_TO_REG (i64 1), (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), sub_64), 0))>;
+def: Pat<(v2i64 (build_vector FltToULong.A, FltToULong.A)),
+               (SUBREG_TO_REG (i64 1), (COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), sub_64), 0))>;
 defm : ScalToVecWPermute<
   v2i64, DblToLongLoad.A,
   (XVCVDPSXDS (LXVDSX ForceXForm:$A)), (XVCVDPSXDS (LXVDSX ForceXForm:$A))>;
 defm : ScalToVecWPermute<
   v2i64, DblToULongLoad.A,
   (XVCVDPUXDS (LXVDSX ForceXForm:$A)), (XVCVDPUXDS (LXVDSX ForceXForm:$A))>;
 
 // Doubleword vector predicate comparisons without Power8.
defm : ScalToVecWPermute<
   (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1),
   (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64)>;
 defm : ScalToVecWPermute<
   v4i32, DblToUIntLoad.A,
   (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1),
   (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, FltToLongLoad.A,
-  (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), sub_64), 0),
   (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A),
                                                         VSFRC)), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, FltToULongLoad.A,
-  (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), sub_64), 0),
   (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A),
                                                         VSFRC)), sub_64)>;
 } // HasVSX, NoP9Vector
 
 // Any little endian pre-Power9 VSX subtarget.
 let Predicates = [HasVSX, NoP9Vector, IsLittleEndian] in {
 // Load-and-splat using only X-Form VSX loads.
 defm : ScalToVecWPermute<
   v2i64, (i64 (load ForceXForm:$src)),
-  (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v2f64, (f64 (load ForceXForm:$src)),
-  (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>;
 } // HasVSX, NoP9Vector, IsLittleEndian
 
 let Predicates = [HasVSX, NoP9Vector, IsBigEndian] in {
   def : Pat<(v2f64 (int_ppc_vsx_lxvd2x ForceXForm:$src)),
             (LXVD2X ForceXForm:$src)>;
   def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, ForceXForm:$dst),
             (STXVD2X $rS, ForceXForm:$dst)>;

 def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))),
           (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>;
 
 // LIWAX - This instruction is used for sign extending i32 -> i64.
 // LIWZX - This instruction will be emitted for i32, f32, and when
 //         zero-extending i32 to i64 (zext i32 -> i64).
 defm : ScalToVecWPermute<
   v2i64, (i64 (sextloadi32 ForceXForm:$src)),
-  (XXPERMDIs (LIWAX ForceXForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64)>;
 
 defm : ScalToVecWPermute<
   v2i64, (i64 (zextloadi32 ForceXForm:$src)),
-  (XXPERMDIs (LIWZX ForceXForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
 
 defm : ScalToVecWPermute<
   v4i32, (i32 (load ForceXForm:$src)),
-  (XXPERMDIs (LIWZX ForceXForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
 
 defm : ScalToVecWPermute<
   v4f32, (f32 (load ForceXForm:$src)),
-  (XXPERMDIs (LIWZX ForceXForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>;
 
 def : Pat<DWToSPExtractConv.BVU,
           (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3),
                           (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3)))>;
 def : Pat<DWToSPExtractConv.BVS,
           (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3),
                           (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3)))>;

 // Build vectors from i8 loads
 defm : ScalToVecWPermute<v8i16, ScalarLoads.ZELi8,
                          (VSPLTHs 3, (LXSIBZX ForceXForm:$src)),
                          (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
 defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi8,
                          (XXSPLTWs (LXSIBZX ForceXForm:$src), 1),
                          (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
 defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi8i64,
-                         (XXPERMDIs (LXSIBZX ForceXForm:$src), 0),
+                         (XXPERMDIs (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64), 0),
                          (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v4i32, ScalarLoads.SELi8,
   (XXSPLTWs (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), 1),
   (SUBREG_TO_REG (i64 1), (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, ScalarLoads.SELi8i64,
-  (XXPERMDIs (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), sub_64), 0),
   (SUBREG_TO_REG (i64 1), (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), sub_64)>;
 
 // Build vectors from i16 loads
 defm : ScalToVecWPermute<
   v4i32, ScalarLoads.ZELi16,
   (XXSPLTWs (LXSIHZX ForceXForm:$src), 1),
   (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, ScalarLoads.ZELi16i64,
-  (XXPERMDIs (LXSIHZX ForceXForm:$src), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64), 0),
   (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v4i32, ScalarLoads.SELi16,
   (XXSPLTWs (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), 1),
   (SUBREG_TO_REG (i64 1), (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, ScalarLoads.SELi16i64,
-  (XXPERMDIs (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64), 0),
   (SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>;
 
 // Load/convert and convert/store patterns for f16.
 def : Pat<(f64 (extloadf16 ForceXForm:$src)),
           (f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>;
 def : Pat<(truncstoref16 f64:$src, ForceXForm:$dst),
           (STXSIHX (XSCVDPHP $src), ForceXForm:$dst)>;
 def : Pat<(f32 (extloadf16 ForceXForm:$src)),
defm : ScalToVecWPermute<
   (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64), 1),
   (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64)>;
 defm : ScalToVecWPermute<
   v4i32, DblToUIntLoadP9.A,
   (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64), 1),
   (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, FltToLongLoadP9.A,
-  (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64), 0),
   (SUBREG_TO_REG
      (i64 1),
      (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, FltToULongLoadP9.A,
-  (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64), 0),
   (SUBREG_TO_REG
      (i64 1),
      (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>;
 def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)),
           (v4f32 (LXVWSX ForceXForm:$A))>;
 def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)),
           (v4i32 (LXVWSX ForceXForm:$A))>;
 def : Pat<(v8i16 (PPCldsplat ForceXForm:$A)),
def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), ForceXForm:$dst),
           (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), ForceXForm:$dst)>;
 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), ForceXForm:$dst),
           (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), ForceXForm:$dst)>;
 def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst),
           (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>;
 
 defm : ScalToVecWPermute<
   v2i64, (i64 (load DSForm:$src)),
-  (XXPERMDIs (DFLOADf64 DSForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v2i64, (i64 (load XForm:$src)),
-  (XXPERMDIs (XFLOADf64 XForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v2f64, (f64 (load DSForm:$src)),
-  (XXPERMDIs (DFLOADf64 DSForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>;
 defm : ScalToVecWPermute<
   v2f64, (f64 (load XForm:$src)),
-  (XXPERMDIs (XFLOADf64 XForm:$src), 2),
+  (XXPERMDIs (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64), 2),
   (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>;
 
 def : Pat<(store (i64 (extractelt v2i64:$A, 0)), XForm:$src),
           (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
                        sub_64), XForm:$src)>;
 def : Pat<(store (f64 (extractelt v2f64:$A, 0)), XForm:$src),
           (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2),
                        sub_64), XForm:$src)>;

 
 // Certain versions of the AIX assembler may missassemble these mnemonics.
 let Predicates = [ModernAs] in {
   def : InstAlias<"xxspltd $XT, $XB, 0",
                   (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>;
   def : InstAlias<"xxspltd $XT, $XB, 1",
                   (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>;
   def : InstAlias<"xxspltd $XT, $XB, 0",
-                  (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0)>;
+                  (XXPERMDIs vsrc:$XT, vsrc:$XB, 0)>;
   def : InstAlias<"xxspltd $XT, $XB, 1",
-                  (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3)>;
+                  (XXPERMDIs vsrc:$XT, vsrc:$XB, 3)>;
 }
 
 def : InstAlias<"xxmrghd $XT, $XA, $XB",
                 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>;
 def : InstAlias<"xxmrgld $XT, $XA, $XB",
                 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>;
 def : InstAlias<"xxswapd $XT, $XB",
                 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;
 def : InstAlias<"xxswapd $XT, $XB",
-                (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2)>;
+                (XXPERMDIs vsrc:$XT, vsrc:$XB, 2)>;
 def : InstAlias<"mfvrd $rA, $XT",
                 (MFVRD g8rc:$rA, vrrc:$XT), 0>;
 def : InstAlias<"mffprd $rA, $src",
                 (MFVSRD g8rc:$rA, f8rc:$src)>;
 def : InstAlias<"mtvrd $XT, $rA",
                 (MTVRD vrrc:$XT, g8rc:$rA), 0>;
 def : InstAlias<"mtfprd $dst, $rA",
                 (MTVSRD f8rc:$dst, g8rc:$rA)>;

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

entry:
   %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
   ret <2 x i64> %vecinit4
 }
 
 define <2 x i64> @spltRegValConvftoll(float %val) {
 ; P9BE-LABEL: spltRegValConvftoll:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    xscvdpsxds f0, f1
-; P9BE-NEXT:    xxspltd v2, f0, 0
+; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltRegValConvftoll:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    xscvdpsxds f0, f1
-; P9LE-NEXT:    xxspltd v2, f0, 0
+; P9LE-NEXT:    xxspltd v2, vs0, 0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltRegValConvftoll:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    xscvdpsxds f0, f1
-; P8BE-NEXT:    xxspltd v2, f0, 0
+; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltRegValConvftoll:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    xscvdpsxds f0, f1
-; P8LE-NEXT:    xxspltd v2, f0, 0
+; P8LE-NEXT:    xxspltd v2, vs0, 0
 ; P8LE-NEXT:    blr
 entry:
   %conv = fptosi float %val to i64
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
 }
 
 define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) {
 ; P9BE-LABEL: spltMemValConvftoll:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfs f0, 0(r3)
 ; P9BE-NEXT:    xscvdpsxds f0, f0
-; P9BE-NEXT:    xxspltd v2, f0, 0
+; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltMemValConvftoll:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfs f0, 0(r3)
 ; P9LE-NEXT:    xscvdpsxds f0, f0
 ; P9LE-NEXT:    xxspltd v2, vs0, 0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltMemValConvftoll:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfsx f0, 0, r3
 ; P8BE-NEXT:    xscvdpsxds f0, f0
-; P8BE-NEXT:    xxspltd v2, f0, 0
+; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltMemValConvftoll:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfsx f0, 0, r3
 ; P8LE-NEXT:    xscvdpsxds f0, f0
 ; P8LE-NEXT:    xxspltd v2, vs0, 0
 ; P8LE-NEXT:    blr
entry:
   %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
   ret <2 x i64> %vecinit4
 }
 
 define <2 x i64> @spltRegValConvftoull(float %val) {
 ; P9BE-LABEL: spltRegValConvftoull:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    xscvdpuxds f0, f1
-; P9BE-NEXT:    xxspltd v2, f0, 0
+; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltRegValConvftoull:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    xscvdpuxds f0, f1
-; P9LE-NEXT:    xxspltd v2, f0, 0
+; P9LE-NEXT:    xxspltd v2, vs0, 0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltRegValConvftoull:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    xscvdpuxds f0, f1
-; P8BE-NEXT:    xxspltd v2, f0, 0
+; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltRegValConvftoull:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    xscvdpuxds f0, f1
-; P8LE-NEXT:    xxspltd v2, f0, 0
+; P8LE-NEXT:    xxspltd v2, vs0, 0
 ; P8LE-NEXT:    blr
 entry:
   %conv = fptoui float %val to i64
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
 }
 
 define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) {
 ; P9BE-LABEL: spltMemValConvftoull:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfs f0, 0(r3)
 ; P9BE-NEXT:    xscvdpuxds f0, f0
-; P9BE-NEXT:    xxspltd v2, f0, 0
+; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: spltMemValConvftoull:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfs f0, 0(r3)
 ; P9LE-NEXT:    xscvdpuxds f0, f0
 ; P9LE-NEXT:    xxspltd v2, vs0, 0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltMemValConvftoull:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfsx f0, 0, r3
 ; P8BE-NEXT:    xscvdpuxds f0, f0
-; P8BE-NEXT:    xxspltd v2, f0, 0
+; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltMemValConvftoull:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfsx f0, 0, r3
 ; P8LE-NEXT:    xscvdpuxds f0, f0
 ; P8LE-NEXT:    xxspltd v2, vs0, 0
 ; P8LE-NEXT:    blr

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

 }
 
 define dso_local <16 x i8> @no_RAUW_in_combine_during_legalize(i32* nocapture readonly %ptr, i32 signext %offset) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: no_RAUW_in_combine_during_legalize:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    sldi r4, r4, 2
 ; CHECK-P8-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P8-NEXT:    lfiwzx f0, r3, r4
-; CHECK-P8-NEXT:    xxspltd v2, f0, 0
+; CHECK-P8-NEXT:    xxspltd v2, vs0, 0
 ; CHECK-P8-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: no_RAUW_in_combine_during_legalize:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    sldi r4, r4, 2
 ; CHECK-P9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P9-NEXT:    lfiwzx f0, r3, r4
-; CHECK-P9-NEXT:    xxspltd v2, f0, 0
+; CHECK-P9-NEXT:    xxspltd v2, vs0, 0
 ; CHECK-P9-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: no_RAUW_in_combine_during_legalize:
 ; CHECK-P9-BE:       # %bb.0: # %entry
 ; CHECK-P9-BE-NEXT:    sldi r4, r4, 2
 ; CHECK-P9-BE-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P9-BE-NEXT:    lxsiwzx v2, r3, r4

 ; CHECK-NOVSX-NEXT:    vmrglb v2, v2, v3
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: no_RAUW_in_combine_during_legalize:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    sldi r4, r4, 2
 ; CHECK-P7-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P7-NEXT:    lfiwzx f0, r3, r4
-; CHECK-P7-NEXT:    xxspltd v2, f0, 0
+; CHECK-P7-NEXT:    xxspltd v2, vs0, 0
 ; CHECK-P7-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P7-NEXT:    blr
 entry:
   %idx.ext = sext i32 %offset to i64
   %add.ptr = getelementptr inbounds i32, i32* %ptr, i64 %idx.ext
   %0 = load i32, i32* %add.ptr, align 4
   %conv = zext i32 %0 to i64
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0

llvm/test/CodeGen/PowerPC/load-and-splat.ll

entry:
   ret void
 }
 
 ; sext v2i64
 define void @test5(<2 x i64>* %a, i32* %in) {
 ; P9-LABEL: test5:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lfiwax f0, 0, r4
-; P9-NEXT:    xxspltd vs0, f0, 0
+; P9-NEXT:    xxspltd vs0, vs0, 0
 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test5:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lfiwax f0, 0, r4
-; P8-NEXT:    xxspltd vs0, f0, 0
+; P8-NEXT:    xxspltd vs0, vs0, 0
 ; P8-NEXT:    stxvd2x vs0, 0, r3
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test5:
 ; P7:       # %bb.0: # %entry
 ; P7-NEXT:    lfiwax f0, 0, r4
-; P7-NEXT:    xxspltd vs0, f0, 0
+; P7-NEXT:    xxspltd vs0, vs0, 0
 ; P7-NEXT:    stxvd2x vs0, 0, r3
 ; P7-NEXT:    blr
 entry:
   %0 = load i32, i32* %in, align 4
   %conv = sext i32 %0 to i64
   %splat.splatinsert.i = insertelement <2 x i64> poison, i64 %conv, i32 0
   %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> poison, <2 x i32> zeroinitializer
   store <2 x i64> %splat.splat.i, <2 x i64>* %a, align 16
   ret void
 }
 
 ; zext v2i64
 define void @test6(<2 x i64>* %a, i32* %in) {
 ; P9-LABEL: test6:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lfiwzx f0, 0, r4
-; P9-NEXT:    xxspltd vs0, f0, 0
+; P9-NEXT:    xxspltd vs0, vs0, 0
 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test6:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lfiwzx f0, 0, r4
-; P8-NEXT:    xxspltd vs0, f0, 0
+; P8-NEXT:    xxspltd vs0, vs0, 0
 ; P8-NEXT:    stxvd2x vs0, 0, r3
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test6:
 ; P7:       # %bb.0: # %entry
 ; P7-NEXT:    lfiwzx f0, 0, r4
-; P7-NEXT:    xxspltd vs0, f0, 0
+; P7-NEXT:    xxspltd vs0, vs0, 0
 ; P7-NEXT:    stxvd2x vs0, 0, r3
 ; P7-NEXT:    blr
 entry:
   %0 = load i32, i32* %in, align 4
   %conv = zext i32 %0 to i64
   %splat.splatinsert.i = insertelement <2 x i64> poison, i64 %conv, i32 0
   %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> poison, <2 x i32> zeroinitializer
   store <2 x i64> %splat.splat.i, <2 x i64>* %a, align 16

llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll

entry:
   ret <2 x i64> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test6(i32* nocapture readonly %ptr)  {
 ; P9LE-LABEL: s2v_test6:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxspltd v2, f0, 0
+; P9LE-NEXT:    xxspltd v2, vs0, 0
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: s2v_test6:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfiwax f0, 0, r3
-; P9BE-NEXT:    xxspltd v2, f0, 0
+; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test6:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxspltd v2, f0, 0
+; P8LE-NEXT:    xxspltd v2, vs0, 0
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test6:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwax f0, 0, r3
-; P8BE-NEXT:    xxspltd v2, f0, 0
+; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 
 
 
 entry:
   %0 = load i32, i32* %ptr, align 4
   %conv = sext i32 %0 to i64
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x i64> @s2v_test7(i32* nocapture readonly %ptr)  {
 ; P9LE-LABEL: s2v_test7:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfiwax f0, 0, r3
-; P9LE-NEXT:    xxspltd v2, f0, 0
+; P9LE-NEXT:    xxspltd v2, vs0, 0
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: s2v_test7:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfiwax f0, 0, r3
-; P9BE-NEXT:    xxspltd v2, f0, 0
+; P9BE-NEXT:    xxspltd v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test7:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwax f0, 0, r3
-; P8LE-NEXT:    xxspltd v2, f0, 0
+; P8LE-NEXT:    xxspltd v2, vs0, 0
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test7:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwax f0, 0, r3
-; P8BE-NEXT:    xxspltd v2, f0, 0
+; P8BE-NEXT:    xxspltd v2, vs0, 0
 ; P8BE-NEXT:    blr
 
 
 
 entry:
   %0 = load i32, i32* %ptr, align 4
   %conv = sext i32 %0 to i64
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
 }