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AMDGPU: Assume all amdhsa kernarg passed implicit arguments by default
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Authored by arsenm on Oct 25 2021, 2:09 PM.

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Reviewers

rampitec
b-sumner
jdoerfert

Summary

Previously we would require adding an attribute to kernels to enable
the inputs passed in the kernarg segment, accessed by
llvm.amdgcn.implicitarg.ptr. This violates the principle of being
correct by default. Some OpenMP testcases were broken recently since
it wasn't correctly setting this attribute, and no known frontends are
setting this to anything other than the maximum.

Most of the test changes are from load widening of argument loads
since there now more implied dereferenceable bytes.

Diff Detail

Event Timeline

arsenm created this revision.Oct 25 2021, 2:09 PM

Herald added subscribers: foad, kerbowa, hiraditya and 7 others. · View Herald TranscriptOct 25 2021, 2:09 PM

arsenm requested review of this revision.Oct 25 2021, 2:09 PM

Herald added a reviewer: jdoerfert. · View Herald TranscriptOct 25 2021, 2:09 PM

Herald added a project: Restricted Project. · View Herald Transcript

Herald added subscribers: sstefan1, wdng. · View Herald Transcript

Harbormaster completed remote builds in B130552: Diff 382119.Oct 25 2021, 2:09 PM

rampitec added inline comments.Oct 25 2021, 2:17 PM

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
659	It is not immediately obvious we have a HSA kernel at this point.

arsenm added inline comments.Oct 25 2021, 2:23 PM

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
659	This is only meaningfully called with a kernel

rampitec added inline comments.Oct 25 2021, 2:25 PM

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
659	With MESA ruled out does that mean only a HSA kernel remains? Maybe add at least an assert?

Add assert

Harbormaster completed remote builds in B130582: Diff 382161.Oct 25 2021, 6:31 PM

rampitec added inline comments.Oct 26 2021, 11:06 AM

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
659	Is this also true for SPIR_KERNEL?

arsenm added inline comments.Oct 26 2021, 11:12 AM

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
659	We never distinguished them (although SPIR_KERNEL should never really be seen, but nobody ever implemented SPIR correctly)

rampitec accepted this revision.Oct 26 2021, 11:14 AM

This revision is now accepted and ready to land.Oct 26 2021, 11:14 AM

Correct by default the optimise to elide is much safer, thank you

arsenm mentioned this in D113538: OpenMP: Start calling setTargetAttributes for generated kernels.Nov 10 2021, 5:52 AM

Can we land this? Seems likely to step on many latent bugs all at once

In D112488#3121906, @JonChesterfield wrote:

Can we land this? Seems likely to step on many latent bugs all at once

The only holdup is surviving openmp precheckin, which is mostly complicated due to a reverted commit

In D112488#3122779, @arsenm wrote:

In D112488#3121906, @JonChesterfield wrote:

Can we land this? Seems likely to step on many latent bugs all at once

The only holdup is surviving openmp precheckin, which is mostly complicated due to a reverted commit

D113538 should help unblock the unrevert, which will unblock this patch

2959e082e1427647e107af0b82770682eaa58fe1

Revision Contents

Path

Size

llvm/

lib/

Target/

AMDGPU/

AMDGPUSubtarget.cpp

4 lines

test/

CodeGen/

AMDGPU/

GlobalISel/

irtranslator-call-abi-attribute-hints.ll

298 lines

irtranslator-call-return-values.ll

3011 lines

llvm.amdgcn.kernarg.segment.ptr.ll

2 lines

callee-special-input-sgprs-fixed-abi.ll

3 lines

callee-special-input-sgprs.ll

3 lines

cc-update.ll

96 lines

flat-scratch-init.ll

8 lines

indirect-call.ll

4 lines

llvm.amdgcn.implicitarg.ptr.ll

40 lines

llvm.amdgcn.kernarg.segment.ptr.ll

4 lines

lower-kernargs.ll

243 lines

Diff 382119

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

	Show First 20 Lines • Show All 649 Lines • ▼ Show 20 Lines
	unsigned AMDGPUSubtarget::getImplicitArgNumBytes(const Function &F) const {			unsigned AMDGPUSubtarget::getImplicitArgNumBytes(const Function &F) const {
	// We don't allocate the segment if we know the implicit arguments weren't			// We don't allocate the segment if we know the implicit arguments weren't
	// used, even if the ABI implies we need them.			// used, even if the ABI implies we need them.
	if (F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))			if (F.hasFnAttribute("amdgpu-no-implicitarg-ptr"))
	return 0;			return 0;

	if (isMesaKernel(F))			if (isMesaKernel(F))
	return 16;			return 16;
	return AMDGPU::getIntegerAttribute(F, "amdgpu-implicitarg-num-bytes", 0);
				// Assume all implicit inputs are used by default
				rampitecUnsubmitted Not Done Reply Inline Actions It is not immediately obvious we have a HSA kernel at this point. rampitec: It is not immediately obvious we have a HSA kernel at this point.
				arsenmAuthorUnsubmitted Done Reply Inline Actions This is only meaningfully called with a kernel arsenm: This is only meaningfully called with a kernel
				rampitecUnsubmitted Not Done Reply Inline Actions With MESA ruled out does that mean only a HSA kernel remains? Maybe add at least an assert? rampitec: With MESA ruled out does that mean only a HSA kernel remains? Maybe add at least an assert?
				rampitecUnsubmitted Not Done Reply Inline Actions Is this also true for SPIR_KERNEL? rampitec: Is this also true for SPIR_KERNEL?
				arsenmAuthorUnsubmitted Done Reply Inline Actions We never distinguished them (although SPIR_KERNEL should never really be seen, but nobody ever implemented SPIR correctly) arsenm: We never distinguished them (although SPIR_KERNEL should never really be seen, but nobody ever…
				return AMDGPU::getIntegerAttribute(F, "amdgpu-implicitarg-num-bytes", 56);
	}			}

	uint64_t AMDGPUSubtarget::getExplicitKernArgSize(const Function &F,			uint64_t AMDGPUSubtarget::getExplicitKernArgSize(const Function &F,
	Align &MaxAlign) const {			Align &MaxAlign) const {
	assert(F.getCallingConv() == CallingConv::AMDGPU_KERNEL \|\|			assert(F.getCallingConv() == CallingConv::AMDGPU_KERNEL \|\|
	F.getCallingConv() == CallingConv::SPIR_KERNEL);			F.getCallingConv() == CallingConv::SPIR_KERNEL);

	const DataLayout &DL = F.getParent()->getDataLayout();			const DataLayout &DL = F.getParent()->getDataLayout();
	▲ Show 20 Lines • Show All 463 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll

	; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	; RUN: llc -global-isel -amdgpu-fixed-function-abi -stop-after=irtranslator -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -o - %s \| FileCheck -enable-var-scope %s			; RUN: llc -global-isel -amdgpu-fixed-function-abi -stop-after=irtranslator -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -o - %s \| FileCheck -enable-var-scope %s

	; Test that we don't insert code to pass implicit arguments we know			; Test that we don't insert code to pass implicit arguments we know
	; the callee does not need.			; the callee does not need.

	declare hidden void @extern()			declare hidden void @extern()

	define amdgpu_kernel void @kernel_call_no_workitem_ids() {			define amdgpu_kernel void @kernel_call_no_workitem_ids() {
	; CHECK-LABEL: name: kernel_call_no_workitem_ids			; CHECK-LABEL: name: kernel_call_no_workitem_ids
	; CHECK: bb.1 (%ir-block.0):			; CHECK: bb.1 (%ir-block.0):
	; CHECK: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9			; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
	; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr14			; CHECK-NEXT: {{ $}}
	; CHECK: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr13			; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr16
	; CHECK: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr12			; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15
	; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9			; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14
	; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7			; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
	; CHECK: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5			; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
	; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc			; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
	; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @extern			; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
	; CHECK: [[COPY6:%[0-9]+]]:_(p4) = COPY [[COPY5]]			; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
	; CHECK: [[COPY7:%[0-9]+]]:_(p4) = COPY [[COPY4]]			; CHECK-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @extern
	; CHECK: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0			; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(p4) = COPY [[COPY5]]
	; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0			; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(p4) = COPY [[COPY4]]
	; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)			; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY6]](p4)
	; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY [[COPY3]]			; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
	; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY2]]			; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY9]], [[C]](s64)
	; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY1]]			; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY [[COPY3]]
	; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY]]			; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY2]]
	; CHECK: [[COPY12:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg			; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY1]]
	; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY12]](<4 x s32>)			; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY]]
	; CHECK: $sgpr4_sgpr5 = COPY [[COPY6]](p4)			; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
	; CHECK: $sgpr6_sgpr7 = COPY [[COPY7]](p4)			; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY14]](<4 x s32>)
	; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)			; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY7]](p4)
	; CHECK: $sgpr10_sgpr11 = COPY [[COPY8]](s64)			; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY8]](p4)
	; CHECK: $sgpr12 = COPY [[COPY9]](s32)			; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
	; CHECK: $sgpr13 = COPY [[COPY10]](s32)			; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY10]](s64)
	; CHECK: $sgpr14 = COPY [[COPY11]](s32)			; CHECK-NEXT: $sgpr12 = COPY [[COPY11]](s32)
	; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @extern, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14			; CHECK-NEXT: $sgpr13 = COPY [[COPY12]](s32)
	; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc			; CHECK-NEXT: $sgpr14 = COPY [[COPY13]](s32)
	; CHECK: S_ENDPGM 0			; CHECK-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @extern, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14
				; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
				; CHECK-NEXT: S_ENDPGM 0
	call void @extern() "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z"			call void @extern() "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z"
	ret void			ret void
	}			}

	define amdgpu_kernel void @kernel_call_no_workgroup_ids() {			define amdgpu_kernel void @kernel_call_no_workgroup_ids() {
	; CHECK-LABEL: name: kernel_call_no_workgroup_ids			; CHECK-LABEL: name: kernel_call_no_workgroup_ids
	; CHECK: bb.1 (%ir-block.0):			; CHECK: bb.1 (%ir-block.0):
	; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9			; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
	; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2			; CHECK-NEXT: {{ $}}
	; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1			; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
	; CHECK: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0			; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
	; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9			; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
	; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7			; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
	; CHECK: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5			; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
	; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc			; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
	; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @extern			; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
	; CHECK: [[COPY6:%[0-9]+]]:_(p4) = COPY [[COPY5]]			; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
	; CHECK: [[COPY7:%[0-9]+]]:_(p4) = COPY [[COPY4]]			; CHECK-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @extern
	; CHECK: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0			; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(p4) = COPY [[COPY5]]
	; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0			; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(p4) = COPY [[COPY4]]
	; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)			; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY6]](p4)
	; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY [[COPY3]]			; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
	; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)			; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY9]], [[C]](s64)
	; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY [[COPY3]]
	; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10			; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
	; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[C2]](s32)			; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
	; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY9]], [[SHL]]			; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
	; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)			; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[C1]](s32)
	; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20			; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY11]], [[SHL]]
	; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[C3]](s32)			; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
	; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]			; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
	; CHECK: [[COPY12:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg			; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[C2]](s32)
	; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY12]](<4 x s32>)			; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
	; CHECK: $sgpr4_sgpr5 = COPY [[COPY6]](p4)			; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
	; CHECK: $sgpr6_sgpr7 = COPY [[COPY7]](p4)			; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY14]](<4 x s32>)
	; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)			; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY7]](p4)
	; CHECK: $sgpr10_sgpr11 = COPY [[COPY8]](s64)			; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY8]](p4)
	; CHECK: $vgpr31 = COPY [[OR1]](s32)			; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
	; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @extern, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $vgpr31			; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY10]](s64)
	; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc			; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
	; CHECK: S_ENDPGM 0			; CHECK-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @extern, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $vgpr31
				; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
				; CHECK-NEXT: S_ENDPGM 0
	call void @extern() "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z"			call void @extern() "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z"
	ret void			ret void
	}			}

	define amdgpu_kernel void @kernel_call_no_other_sgprs() {			define amdgpu_kernel void @kernel_call_no_other_sgprs() {
	; CHECK-LABEL: name: kernel_call_no_other_sgprs			; CHECK-LABEL: name: kernel_call_no_other_sgprs
	; CHECK: bb.1 (%ir-block.0):			; CHECK: bb.1 (%ir-block.0):
	; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2			; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr8_sgpr9
	; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2			; CHECK-NEXT: {{ $}}
	; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1			; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
	; CHECK: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0			; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
	; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc			; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
	; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @extern			; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
	; CHECK: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0			; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
	; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0			; CHECK-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @extern
	; CHECK: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)			; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p4) = COPY [[COPY3]](p4)
	; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)			; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
	; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)			; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY4]], [[C]](s64)
	; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10			; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
	; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s32)			; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
	; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[SHL]]			; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
	; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)			; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C1]](s32)
	; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20			; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[SHL]]
	; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C3]](s32)			; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
	; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]			; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
	; CHECK: [[COPY6:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg			; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C2]](s32)
	; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY6]](<4 x s32>)			; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
	; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)			; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
	; CHECK: $vgpr31 = COPY [[OR1]](s32)			; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY8]](<4 x s32>)
	; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @extern, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr8_sgpr9, implicit $vgpr31			; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
	; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc			; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)
	; CHECK: S_ENDPGM 0			; CHECK-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @extern, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr8_sgpr9, implicit $vgpr31
				; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
				; CHECK-NEXT: S_ENDPGM 0
	call void @extern() "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z"			call void @extern() "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z"
	ret void			ret void
	}			}

	define void @func_call_no_workitem_ids() {			define void @func_call_no_workitem_ids() {
	; CHECK-LABEL: name: func_call_no_workitem_ids			; CHECK-LABEL: name: func_call_no_workitem_ids
	; CHECK: bb.1 (%ir-block.0):			; CHECK: bb.1 (%ir-block.0):
	; CHECK: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31			; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31
	; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr14			; CHECK-NEXT: {{ $}}
	; CHECK: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr13			; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr14
	; CHECK: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr12			; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr13
	; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11			; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr12
	; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9			; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
	; CHECK: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7			; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
	; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5			; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
	; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31			; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
	; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc			; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
	; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @extern			; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
	; CHECK: [[COPY8:%[0-9]+]]:_(p4) = COPY [[COPY6]]			; CHECK-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @extern
	; CHECK: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY5]]			; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(p4) = COPY [[COPY6]]
	; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY4]]			; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY5]]
	; CHECK: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY3]]			; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY4]]
	; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY2]]			; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY3]]
	; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY1]]			; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY2]]
	; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY]]			; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY1]]
	; CHECK: [[COPY15:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3			; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY]]
	; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY15]](<4 x s32>)			; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
	; CHECK: $sgpr4_sgpr5 = COPY [[COPY8]](p4)			; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY15]](<4 x s32>)
	; CHECK: $sgpr6_sgpr7 = COPY [[COPY9]](p4)			; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY8]](p4)
	; CHECK: $sgpr8_sgpr9 = COPY [[COPY10]](p4)			; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY9]](p4)
	; CHECK: $sgpr10_sgpr11 = COPY [[COPY11]](s64)			; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY10]](p4)
	; CHECK: $sgpr12 = COPY [[COPY12]](s32)			; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)
	; CHECK: $sgpr13 = COPY [[COPY13]](s32)			; CHECK-NEXT: $sgpr12 = COPY [[COPY12]](s32)
	; CHECK: $sgpr14 = COPY [[COPY14]](s32)			; CHECK-NEXT: $sgpr13 = COPY [[COPY13]](s32)
	; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @extern, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14			; CHECK-NEXT: $sgpr14 = COPY [[COPY14]](s32)
	; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc			; CHECK-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @extern, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14
	; CHECK: [[COPY16:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY7]]			; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
	; CHECK: S_SETPC_B64_return [[COPY16]]			; CHECK-NEXT: [[COPY16:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY7]]
				; CHECK-NEXT: S_SETPC_B64_return [[COPY16]]
	call void @extern() "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z"			call void @extern() "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z"
	ret void			ret void
	}			}

	define void @func_call_no_workgroup_ids() {			define void @func_call_no_workgroup_ids() {
	; CHECK-LABEL: name: func_call_no_workgroup_ids			; CHECK-LABEL: name: func_call_no_workgroup_ids
	; CHECK: bb.1 (%ir-block.0):			; CHECK: bb.1 (%ir-block.0):
	; CHECK: liveins: $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31			; CHECK-NEXT: liveins: $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31
	; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31			; CHECK-NEXT: {{ $}}
	; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11			; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
	; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9			; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
	; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7			; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
	; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5			; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
	; CHECK: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31			; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
	; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc			; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
	; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @extern			; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
	; CHECK: [[COPY6:%[0-9]+]]:_(p4) = COPY [[COPY4]]			; CHECK-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @extern
	; CHECK: [[COPY7:%[0-9]+]]:_(p4) = COPY [[COPY3]]			; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(p4) = COPY [[COPY4]]
	; CHECK: [[COPY8:%[0-9]+]]:_(p4) = COPY [[COPY2]]			; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(p4) = COPY [[COPY3]]
	; CHECK: [[COPY9:%[0-9]+]]:_(s64) = COPY [[COPY1]]			; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(p4) = COPY [[COPY2]]
	; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)			; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s64) = COPY [[COPY1]]
	; CHECK: [[COPY11:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3			; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
	; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY11]](<4 x s32>)			; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
	; CHECK: $sgpr4_sgpr5 = COPY [[COPY6]](p4)			; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY11]](<4 x s32>)
	; CHECK: $sgpr6_sgpr7 = COPY [[COPY7]](p4)			; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY6]](p4)
	; CHECK: $sgpr8_sgpr9 = COPY [[COPY8]](p4)			; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY7]](p4)
	; CHECK: $sgpr10_sgpr11 = COPY [[COPY9]](s64)			; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY8]](p4)
	; CHECK: $vgpr31 = COPY [[COPY10]](s32)			; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY9]](s64)
	; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @extern, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $vgpr31			; CHECK-NEXT: $vgpr31 = COPY [[COPY10]](s32)
	; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $scc			; CHECK-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @extern, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $vgpr31
	; CHECK: [[COPY12:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY5]]			; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
	; CHECK: S_SETPC_B64_return [[COPY12]]			; CHECK-NEXT: [[COPY12:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY5]]
				; CHECK-NEXT: S_SETPC_B64_return [[COPY12]]
	call void @extern() "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z"			call void @extern() "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z"
	ret void			ret void
	}			}

	define void @func_call_no_other_sgprs() {			define void @func_call_no_other_sgprs() {
	; CHECK-LABEL: name: func_call_no_other_sgprs			; CHECK-LABEL: name: func_call_no_other_sgprs
	; CHECK: bb.1 (%ir-block.0):			; CHECK: bb.1 (%ir-block.0):
	; CHECK: liveins: $vgpr31, $sgpr8_sgpr9, $sgpr30_sgpr31			; CHECK: liveins: $vgpr31, $sgpr8_sgpr9, $sgpr30_sgpr31
	Show All 18 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines	define amdgpu_gfx void @test_gfx_call_external_i32_func_i32_imm(i32 addrspace(1)* %out) #0 {
%val = call amdgpu_gfx i32 @external_gfx_i32_func_i32(i32 42)		%val = call amdgpu_gfx i32 @external_gfx_i32_func_i32(i32 42)
store volatile i32 %val, i32 addrspace(1)* %out		store volatile i32 %val, i32 addrspace(1)* %out
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i1_func_void() #0 {		define amdgpu_kernel void @test_call_external_i1_func_void() #0 {
; GCN-LABEL: name: test_call_external_i1_func_void		; GCN-LABEL: name: test_call_external_i1_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i1_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i1_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i1_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i1_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY19]](s32)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY21]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[TRUNC]](s1), [[DEF]](p1) :: (volatile store (s1) into `i1 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[TRUNC]](s1), [[DEF]](p1) :: (volatile store (s1) into `i1 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i1 @external_i1_func_void()		%val = call i1 @external_i1_func_void()
store volatile i1 %val, i1 addrspace(1)* undef		store volatile i1 %val, i1 addrspace(1)* undef
ret void		ret void
}		}

Show All 18 Lines	define amdgpu_gfx void @test_gfx_call_external_i1_func_void() #0 {
%val = call amdgpu_gfx i1 @external_gfx_i1_func_void()		%val = call amdgpu_gfx i1 @external_gfx_i1_func_void()
store volatile i1 %val, i1 addrspace(1)* undef		store volatile i1 %val, i1 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i1_zeroext_func_void() #0 {		define amdgpu_kernel void @test_call_external_i1_zeroext_func_void() #0 {
; GCN-LABEL: name: test_call_external_i1_zeroext_func_void		; GCN-LABEL: name: test_call_external_i1_zeroext_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i1_zeroext_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i1_zeroext_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i1_zeroext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i1_zeroext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY19]](s32)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY21]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)		; GCN-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)
; GCN-NEXT: G_STORE [[ZEXT]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[ZEXT]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i1 @external_i1_zeroext_func_void()		%val = call i1 @external_i1_zeroext_func_void()
%val.ext = zext i1 %val to i32		%val.ext = zext i1 %val to i32
store volatile i32 %val.ext, i32 addrspace(1)* undef		store volatile i32 %val.ext, i32 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i1_signext_func_void() #0 {		define amdgpu_kernel void @test_call_external_i1_signext_func_void() #0 {
; GCN-LABEL: name: test_call_external_i1_signext_func_void		; GCN-LABEL: name: test_call_external_i1_signext_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i1_signext_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i1_signext_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i1_signext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i1_signext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY19]](s32)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY21]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s1)		; GCN-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s1)
; GCN-NEXT: G_STORE [[SEXT]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[SEXT]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i1 @external_i1_signext_func_void()		%val = call i1 @external_i1_signext_func_void()
%val.ext = sext i1 %val to i32		%val.ext = sext i1 %val to i32
store volatile i32 %val.ext, i32 addrspace(1)* undef		store volatile i32 %val.ext, i32 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i8_func_void() #0 {		define amdgpu_kernel void @test_call_external_i8_func_void() #0 {
; GCN-LABEL: name: test_call_external_i8_func_void		; GCN-LABEL: name: test_call_external_i8_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i8_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i8_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i8_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i8_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY19]](s32)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY21]](s32)
; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC]](s16)		; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC]](s16)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[TRUNC1]](s8), [[DEF]](p1) :: (volatile store (s8) into `i8 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[TRUNC1]](s8), [[DEF]](p1) :: (volatile store (s8) into `i8 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i8 @external_i8_func_void()		%val = call i8 @external_i8_func_void()
store volatile i8 %val, i8 addrspace(1)* undef		store volatile i8 %val, i8 addrspace(1)* undef
ret void		ret void
}		}
Show All 20 Lines	define amdgpu_gfx void @test_gfx_call_external_i8_func_void() #0 {
%val = call amdgpu_gfx i8 @external_gfx_i8_func_void()		%val = call amdgpu_gfx i8 @external_gfx_i8_func_void()
store volatile i8 %val, i8 addrspace(1)* undef		store volatile i8 %val, i8 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i8_zeroext_func_void() #0 {		define amdgpu_kernel void @test_call_external_i8_zeroext_func_void() #0 {
; GCN-LABEL: name: test_call_external_i8_zeroext_func_void		; GCN-LABEL: name: test_call_external_i8_zeroext_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i8_zeroext_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i8_zeroext_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i8_zeroext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i8_zeroext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY19]](s32)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY21]](s32)
; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC]](s16)		; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC]](s16)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s8)		; GCN-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC1]](s8)
; GCN-NEXT: G_STORE [[ZEXT]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[ZEXT]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i8 @external_i8_zeroext_func_void()		%val = call i8 @external_i8_zeroext_func_void()
%val.ext = zext i8 %val to i32		%val.ext = zext i8 %val to i32
store volatile i32 %val.ext, i32 addrspace(1)* undef		store volatile i32 %val.ext, i32 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i8_signext_func_void() #0 {		define amdgpu_kernel void @test_call_external_i8_signext_func_void() #0 {
; GCN-LABEL: name: test_call_external_i8_signext_func_void		; GCN-LABEL: name: test_call_external_i8_signext_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i8_signext_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i8_signext_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i8_signext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i8_signext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY19]](s32)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY21]](s32)
; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC]](s16)		; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC]](s16)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC1]](s8)		; GCN-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC1]](s8)
; GCN-NEXT: G_STORE [[SEXT]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[SEXT]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i8 @external_i8_signext_func_void()		%val = call i8 @external_i8_signext_func_void()
%val.ext = sext i8 %val to i32		%val.ext = sext i8 %val to i32
store volatile i32 %val.ext, i32 addrspace(1)* undef		store volatile i32 %val.ext, i32 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i16_func_void() #0 {		define amdgpu_kernel void @test_call_external_i16_func_void() #0 {
; GCN-LABEL: name: test_call_external_i16_func_void		; GCN-LABEL: name: test_call_external_i16_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i16_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i16_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY19]](s32)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY21]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[TRUNC]](s16), [[DEF]](p1) :: (volatile store (s16) into `i16 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[TRUNC]](s16), [[DEF]](p1) :: (volatile store (s16) into `i16 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i16 @external_i16_func_void()		%val = call i16 @external_i16_func_void()
store volatile i16 %val, i16 addrspace(1)* undef		store volatile i16 %val, i16 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i16_zeroext_func_void() #0 {		define amdgpu_kernel void @test_call_external_i16_zeroext_func_void() #0 {
; GCN-LABEL: name: test_call_external_i16_zeroext_func_void		; GCN-LABEL: name: test_call_external_i16_zeroext_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i16_zeroext_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i16_zeroext_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i16_zeroext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i16_zeroext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY19]](s32)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY21]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)		; GCN-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
; GCN-NEXT: G_STORE [[ZEXT]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[ZEXT]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i16 @external_i16_zeroext_func_void()		%val = call i16 @external_i16_zeroext_func_void()
%val.ext = zext i16 %val to i32		%val.ext = zext i16 %val to i32
store volatile i32 %val.ext, i32 addrspace(1)* undef		store volatile i32 %val.ext, i32 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i16_signext_func_void() #0 {		define amdgpu_kernel void @test_call_external_i16_signext_func_void() #0 {
; GCN-LABEL: name: test_call_external_i16_signext_func_void		; GCN-LABEL: name: test_call_external_i16_signext_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i16_signext_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i16_signext_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i16_signext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i16_signext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY19]](s32)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY21]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)		; GCN-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
; GCN-NEXT: G_STORE [[SEXT]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[SEXT]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i16 @external_i16_signext_func_void()		%val = call i16 @external_i16_signext_func_void()
%val.ext = sext i16 %val to i32		%val.ext = sext i16 %val to i32
store volatile i32 %val.ext, i32 addrspace(1)* undef		store volatile i32 %val.ext, i32 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i32_func_void() #0 {		define amdgpu_kernel void @test_call_external_i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_i32_func_void		; GCN-LABEL: name: test_call_external_i32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[COPY19]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[COPY21]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i32 @external_i32_func_void()		%val = call i32 @external_i32_func_void()
store volatile i32 %val, i32 addrspace(1)* undef		store volatile i32 %val, i32 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_gfx void @test_gfx_call_external_i32_func_void() #0 {		define amdgpu_gfx void @test_gfx_call_external_i32_func_void() #0 {
; GCN-LABEL: name: test_gfx_call_external_i32_func_void		; GCN-LABEL: name: test_gfx_call_external_i32_func_void
Show All 15 Lines	define amdgpu_gfx void @test_gfx_call_external_i32_func_void() #0 {
%val = call amdgpu_gfx i32 @external_gfx_i32_func_void()		%val = call amdgpu_gfx i32 @external_gfx_i32_func_void()
store volatile i32 %val, i32 addrspace(1)* undef		store volatile i32 %val, i32 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i48_func_void() #0 {		define amdgpu_kernel void @test_call_external_i48_func_void() #0 {
; GCN-LABEL: name: test_call_external_i48_func_void		; GCN-LABEL: name: test_call_external_i48_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i48_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i48_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i48_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i48_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY19]](s32), [[COPY20]](s32)		; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[TRUNC]](s48), [[DEF]](p1) :: (volatile store (s48) into `i48 addrspace(1)* undef`, align 8, addrspace 1)		; GCN-NEXT: G_STORE [[TRUNC]](s48), [[DEF]](p1) :: (volatile store (s48) into `i48 addrspace(1)* undef`, align 8, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i48 @external_i48_func_void()		%val = call i48 @external_i48_func_void()
store volatile i48 %val, i48 addrspace(1)* undef		store volatile i48 %val, i48 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i48_zeroext_func_void() #0 {		define amdgpu_kernel void @test_call_external_i48_zeroext_func_void() #0 {
; GCN-LABEL: name: test_call_external_i48_zeroext_func_void		; GCN-LABEL: name: test_call_external_i48_zeroext_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i48_zeroext_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i48_zeroext_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i48_zeroext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i48_zeroext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY19]](s32), [[COPY20]](s32)		; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s48)		; GCN-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s48)
; GCN-NEXT: G_STORE [[ZEXT]](s64), [[DEF]](p1) :: (volatile store (s64) into `i64 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[ZEXT]](s64), [[DEF]](p1) :: (volatile store (s64) into `i64 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i48 @external_i48_zeroext_func_void()		%val = call i48 @external_i48_zeroext_func_void()
%ext = zext i48 %val to i64		%ext = zext i48 %val to i64
store volatile i64 %ext, i64 addrspace(1)* undef		store volatile i64 %ext, i64 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i48_signext_func_void() #0 {		define amdgpu_kernel void @test_call_external_i48_signext_func_void() #0 {
; GCN-LABEL: name: test_call_external_i48_signext_func_void		; GCN-LABEL: name: test_call_external_i48_signext_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i48_signext_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i48_signext_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i48_signext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i48_signext_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY19]](s32), [[COPY20]](s32)		; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[MV]](s64)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s48)		; GCN-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s48)
; GCN-NEXT: G_STORE [[SEXT]](s64), [[DEF]](p1) :: (volatile store (s64) into `i64 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[SEXT]](s64), [[DEF]](p1) :: (volatile store (s64) into `i64 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i48 @external_i48_signext_func_void()		%val = call i48 @external_i48_signext_func_void()
%ext = sext i48 %val to i64		%ext = sext i48 %val to i64
store volatile i64 %ext, i64 addrspace(1)* undef		store volatile i64 %ext, i64 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i64_func_void() #0 {		define amdgpu_kernel void @test_call_external_i64_func_void() #0 {
; GCN-LABEL: name: test_call_external_i64_func_void		; GCN-LABEL: name: test_call_external_i64_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i64_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i64_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY19]](s32), [[COPY20]](s32)		; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[MV]](s64), [[DEF]](p1) :: (volatile store (s64) into `i64 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[MV]](s64), [[DEF]](p1) :: (volatile store (s64) into `i64 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i64 @external_i64_func_void()		%val = call i64 @external_i64_func_void()
store volatile i64 %val, i64 addrspace(1)* undef		store volatile i64 %val, i64 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_p1_func_void() #0 {		define amdgpu_kernel void @test_call_external_p1_func_void() #0 {
; GCN-LABEL: name: test_call_external_p1_func_void		; GCN-LABEL: name: test_call_external_p1_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_p1_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_p1_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_p1_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_p1_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY19]](s32), [[COPY20]](s32)		; GCN-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[MV]](p1), [[DEF]](p1) :: (volatile store (p1) into `i8 addrspace(1)* addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[MV]](p1), [[DEF]](p1) :: (volatile store (p1) into `i8 addrspace(1)* addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i8 addrspace(1)* @external_p1_func_void()		%val = call i8 addrspace(1)* @external_p1_func_void()
store volatile i8 addrspace(1)* %val, i8 addrspace(1)* addrspace(1)* undef		store volatile i8 addrspace(1)* %val, i8 addrspace(1)* addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v2p1_func_void() #0 {		define amdgpu_kernel void @test_call_external_v2p1_func_void() #0 {
; GCN-LABEL: name: test_call_external_v2p1_func_void		; GCN-LABEL: name: test_call_external_v2p1_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v2p1_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v2p1_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2p1_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2p1_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr3		; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
; GCN-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY19]](s32), [[COPY20]](s32)		; GCN-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
; GCN-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)		; GCN-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY23]](s32), [[COPY24]](s32)
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)		; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x p1>), [[DEF]](p1) :: (volatile store (<2 x p1>) into `<2 x i8 addrspace(1)> addrspace(1) undef`, addrspace 1)		; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x p1>), [[DEF]](p1) :: (volatile store (<2 x p1>) into `<2 x i8 addrspace(1)> addrspace(1) undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <2 x i8 addrspace(1)*> @external_v2p1_func_void()		%val = call <2 x i8 addrspace(1)*> @external_v2p1_func_void()
store volatile <2 x i8 addrspace(1)> %val, <2 x i8 addrspace(1)> addrspace(1)* undef		store volatile <2 x i8 addrspace(1)> %val, <2 x i8 addrspace(1)> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_p3_func_void() #0 {		define amdgpu_kernel void @test_call_external_p3_func_void() #0 {
; GCN-LABEL: name: test_call_external_p3_func_void		; GCN-LABEL: name: test_call_external_p3_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p3) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p3) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_p3_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_p3_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_p3_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_p3_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(p3) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(p3) = COPY $vgpr0
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[COPY19]](p3), [[DEF]](p3) :: (volatile store (p3) into `i8 addrspace(3)* addrspace(3)* undef`, addrspace 3)		; GCN-NEXT: G_STORE [[COPY21]](p3), [[DEF]](p3) :: (volatile store (p3) into `i8 addrspace(3)* addrspace(3)* undef`, addrspace 3)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call i8 addrspace(3)* @external_p3_func_void()		%val = call i8 addrspace(3)* @external_p3_func_void()
store volatile i8 addrspace(3)* %val, i8 addrspace(3)* addrspace(3)* undef		store volatile i8 addrspace(3)* %val, i8 addrspace(3)* addrspace(3)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v2p3_func_void() #0 {		define amdgpu_kernel void @test_call_external_v2p3_func_void() #0 {
; GCN-LABEL: name: test_call_external_v2p3_func_void		; GCN-LABEL: name: test_call_external_v2p3_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p3) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p3) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v2p3_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v2p3_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2p3_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2p3_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(p3) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(p3) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(p3) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(p3) = COPY $vgpr1
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY19]](p3), [[COPY20]](p3)		; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY21]](p3), [[COPY22]](p3)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x p3>), [[DEF]](p3) :: (volatile store (<2 x p3>) into `<2 x i8 addrspace(3)> addrspace(3) undef`, addrspace 3)		; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x p3>), [[DEF]](p3) :: (volatile store (<2 x p3>) into `<2 x i8 addrspace(3)> addrspace(3) undef`, addrspace 3)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <2 x i8 addrspace(3)*> @external_v2p3_func_void()		%val = call <2 x i8 addrspace(3)*> @external_v2p3_func_void()
store volatile <2 x i8 addrspace(3)> %val, <2 x i8 addrspace(3)> addrspace(3)* undef		store volatile <2 x i8 addrspace(3)> %val, <2 x i8 addrspace(3)> addrspace(3)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_f16_func_void() #0 {		define amdgpu_kernel void @test_call_external_f16_func_void() #0 {
; GCN-LABEL: name: test_call_external_f16_func_void		; GCN-LABEL: name: test_call_external_f16_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_f16_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_f16_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_f16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_f16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY19]](s32)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY21]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[TRUNC]](s16), [[DEF]](p1) :: (volatile store (s16) into `half addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[TRUNC]](s16), [[DEF]](p1) :: (volatile store (s16) into `half addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call half @external_f16_func_void()		%val = call half @external_f16_func_void()
store volatile half %val, half addrspace(1)* undef		store volatile half %val, half addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_f32_func_void() #0 {		define amdgpu_kernel void @test_call_external_f32_func_void() #0 {
; GCN-LABEL: name: test_call_external_f32_func_void		; GCN-LABEL: name: test_call_external_f32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_f32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_f32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_f32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_f32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[COPY19]](s32), [[DEF]](p1) :: (volatile store (s32) into `float addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[COPY21]](s32), [[DEF]](p1) :: (volatile store (s32) into `float addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call float @external_f32_func_void()		%val = call float @external_f32_func_void()
store volatile float %val, float addrspace(1)* undef		store volatile float %val, float addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_f64_func_void() #0 {		define amdgpu_kernel void @test_call_external_f64_func_void() #0 {
; GCN-LABEL: name: test_call_external_f64_func_void		; GCN-LABEL: name: test_call_external_f64_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_f64_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_f64_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_f64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_f64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY19]](s32), [[COPY20]](s32)		; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[MV]](s64), [[DEF]](p1) :: (volatile store (s64) into `double addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[MV]](s64), [[DEF]](p1) :: (volatile store (s64) into `double addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call double @external_f64_func_void()		%val = call double @external_f64_func_void()
store volatile double %val, double addrspace(1)* undef		store volatile double %val, double addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v2f64_func_void() #0 {		define amdgpu_kernel void @test_call_external_v2f64_func_void() #0 {
; GCN-LABEL: name: test_call_external_v2f64_func_void		; GCN-LABEL: name: test_call_external_v2f64_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v2f64_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v2f64_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2f64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2f64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr3		; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY19]](s32), [[COPY20]](s32)		; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)
; GCN-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)		; GCN-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY23]](s32), [[COPY24]](s32)
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)		; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[DEF]](p1) :: (volatile store (<2 x s64>) into `<2 x double> addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[DEF]](p1) :: (volatile store (<2 x s64>) into `<2 x double> addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <2 x double> @external_v2f64_func_void()		%val = call <2 x double> @external_v2f64_func_void()
store volatile <2 x double> %val, <2 x double> addrspace(1)* undef		store volatile <2 x double> %val, <2 x double> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v2i32_func_void() #0 {		define amdgpu_kernel void @test_call_external_v2i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v2i32_func_void		; GCN-LABEL: name: test_call_external_v2i32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v2i32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v2i32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32)		; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s32>), [[DEF]](p1) :: (volatile store (<2 x s32>) into `<2 x i32> addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s32>), [[DEF]](p1) :: (volatile store (<2 x s32>) into `<2 x i32> addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <2 x i32> @external_v2i32_func_void()		%val = call <2 x i32> @external_v2i32_func_void()
store volatile <2 x i32> %val, <2 x i32> addrspace(1)* undef		store volatile <2 x i32> %val, <2 x i32> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v3i32_func_void() #0 {		define amdgpu_kernel void @test_call_external_v3i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v3i32_func_void		; GCN-LABEL: name: test_call_external_v3i32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v3i32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v3i32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32)		; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<3 x s32>), [[DEF]](p1) :: (volatile store (<3 x s32>) into `<3 x i32> addrspace(1)* undef`, align 8, addrspace 1)		; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<3 x s32>), [[DEF]](p1) :: (volatile store (<3 x s32>) into `<3 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <3 x i32> @external_v3i32_func_void()		%val = call <3 x i32> @external_v3i32_func_void()
store volatile <3 x i32> %val, <3 x i32> addrspace(1)* undef, align 8		store volatile <3 x i32> %val, <3 x i32> addrspace(1)* undef, align 8
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v4i32_func_void() #0 {		define amdgpu_kernel void @test_call_external_v4i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v4i32_func_void		; GCN-LABEL: name: test_call_external_v4i32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v4i32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v4i32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v4i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v4i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr3		; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32)		; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s32>), [[DEF]](p1) :: (volatile store (<4 x s32>) into `<4 x i32> addrspace(1)* undef`, align 8, addrspace 1)		; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s32>), [[DEF]](p1) :: (volatile store (<4 x s32>) into `<4 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <4 x i32> @external_v4i32_func_void()		%val = call <4 x i32> @external_v4i32_func_void()
store volatile <4 x i32> %val, <4 x i32> addrspace(1)* undef, align 8		store volatile <4 x i32> %val, <4 x i32> addrspace(1)* undef, align 8
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v5i32_func_void() #0 {		define amdgpu_kernel void @test_call_external_v5i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v5i32_func_void		; GCN-LABEL: name: test_call_external_v5i32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v5i32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v5i32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v5i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v5i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr3		; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr4		; GCN-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32)		; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<5 x s32>), [[DEF]](p1) :: (volatile store (<5 x s32>) into `<5 x i32> addrspace(1)* undef`, align 8, addrspace 1)		; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<5 x s32>), [[DEF]](p1) :: (volatile store (<5 x s32>) into `<5 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <5 x i32> @external_v5i32_func_void()		%val = call <5 x i32> @external_v5i32_func_void()
store volatile <5 x i32> %val, <5 x i32> addrspace(1)* undef, align 8		store volatile <5 x i32> %val, <5 x i32> addrspace(1)* undef, align 8
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v8i32_func_void() #0 {		define amdgpu_kernel void @test_call_external_v8i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v8i32_func_void		; GCN-LABEL: name: test_call_external_v8i32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v8i32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v8i32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v8i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v8i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr3		; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr4		; GCN-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4
; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr5		; GCN-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr5
; GCN-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr6		; GCN-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr6
; GCN-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr7		; GCN-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr7
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32)		; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<8 x s32>), [[DEF]](p1) :: (volatile store (<8 x s32>) into `<8 x i32> addrspace(1)* undef`, align 8, addrspace 1)		; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<8 x s32>), [[DEF]](p1) :: (volatile store (<8 x s32>) into `<8 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <8 x i32> @external_v8i32_func_void()		%val = call <8 x i32> @external_v8i32_func_void()
store volatile <8 x i32> %val, <8 x i32> addrspace(1)* undef, align 8		store volatile <8 x i32> %val, <8 x i32> addrspace(1)* undef, align 8
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v16i32_func_void() #0 {		define amdgpu_kernel void @test_call_external_v16i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v16i32_func_void		; GCN-LABEL: name: test_call_external_v16i32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v16i32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v16i32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v16i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7, implicit-def $vgpr8, implicit-def $vgpr9, implicit-def $vgpr10, implicit-def $vgpr11, implicit-def $vgpr12, implicit-def $vgpr13, implicit-def $vgpr14, implicit-def $vgpr15		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v16i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7, implicit-def $vgpr8, implicit-def $vgpr9, implicit-def $vgpr10, implicit-def $vgpr11, implicit-def $vgpr12, implicit-def $vgpr13, implicit-def $vgpr14, implicit-def $vgpr15
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr3		; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr4		; GCN-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4
; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr5		; GCN-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr5
; GCN-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr6		; GCN-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr6
; GCN-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr7		; GCN-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr7
; GCN-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr8		; GCN-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr8
; GCN-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr9		; GCN-NEXT: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr9
; GCN-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr10		; GCN-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr10
; GCN-NEXT: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr11		; GCN-NEXT: [[COPY32:%[0-9]+]]:_(s32) = COPY $vgpr11
; GCN-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr12		; GCN-NEXT: [[COPY33:%[0-9]+]]:_(s32) = COPY $vgpr12
; GCN-NEXT: [[COPY32:%[0-9]+]]:_(s32) = COPY $vgpr13		; GCN-NEXT: [[COPY34:%[0-9]+]]:_(s32) = COPY $vgpr13
; GCN-NEXT: [[COPY33:%[0-9]+]]:_(s32) = COPY $vgpr14		; GCN-NEXT: [[COPY35:%[0-9]+]]:_(s32) = COPY $vgpr14
; GCN-NEXT: [[COPY34:%[0-9]+]]:_(s32) = COPY $vgpr15		; GCN-NEXT: [[COPY36:%[0-9]+]]:_(s32) = COPY $vgpr15
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32), [[COPY33]](s32), [[COPY34]](s32)		; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32), [[COPY33]](s32), [[COPY34]](s32), [[COPY35]](s32), [[COPY36]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<16 x s32>), [[DEF]](p1) :: (volatile store (<16 x s32>) into `<16 x i32> addrspace(1)* undef`, align 8, addrspace 1)		; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<16 x s32>), [[DEF]](p1) :: (volatile store (<16 x s32>) into `<16 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <16 x i32> @external_v16i32_func_void()		%val = call <16 x i32> @external_v16i32_func_void()
store volatile <16 x i32> %val, <16 x i32> addrspace(1)* undef, align 8		store volatile <16 x i32> %val, <16 x i32> addrspace(1)* undef, align 8
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v32i32_func_void() #0 {		define amdgpu_kernel void @test_call_external_v32i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v32i32_func_void		; GCN-LABEL: name: test_call_external_v32i32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v32i32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v32i32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v32i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7, implicit-def $vgpr8, implicit-def $vgpr9, implicit-def $vgpr10, implicit-def $vgpr11, implicit-def $vgpr12, implicit-def $vgpr13, implicit-def $vgpr14, implicit-def $vgpr15, implicit-def $vgpr16, implicit-def $vgpr17, implicit-def $vgpr18, implicit-def $vgpr19, implicit-def $vgpr20, implicit-def $vgpr21, implicit-def $vgpr22, implicit-def $vgpr23, implicit-def $vgpr24, implicit-def $vgpr25, implicit-def $vgpr26, implicit-def $vgpr27, implicit-def $vgpr28, implicit-def $vgpr29, implicit-def $vgpr30, implicit-def $vgpr31		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v32i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7, implicit-def $vgpr8, implicit-def $vgpr9, implicit-def $vgpr10, implicit-def $vgpr11, implicit-def $vgpr12, implicit-def $vgpr13, implicit-def $vgpr14, implicit-def $vgpr15, implicit-def $vgpr16, implicit-def $vgpr17, implicit-def $vgpr18, implicit-def $vgpr19, implicit-def $vgpr20, implicit-def $vgpr21, implicit-def $vgpr22, implicit-def $vgpr23, implicit-def $vgpr24, implicit-def $vgpr25, implicit-def $vgpr26, implicit-def $vgpr27, implicit-def $vgpr28, implicit-def $vgpr29, implicit-def $vgpr30, implicit-def $vgpr31
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr3		; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr4		; GCN-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4
; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr5		; GCN-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr5
; GCN-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr6		; GCN-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr6
; GCN-NEXT: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr7		; GCN-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr7
; GCN-NEXT: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr8		; GCN-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr8
; GCN-NEXT: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr9		; GCN-NEXT: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr9
; GCN-NEXT: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr10		; GCN-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr10
; GCN-NEXT: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr11		; GCN-NEXT: [[COPY32:%[0-9]+]]:_(s32) = COPY $vgpr11
; GCN-NEXT: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr12		; GCN-NEXT: [[COPY33:%[0-9]+]]:_(s32) = COPY $vgpr12
; GCN-NEXT: [[COPY32:%[0-9]+]]:_(s32) = COPY $vgpr13		; GCN-NEXT: [[COPY34:%[0-9]+]]:_(s32) = COPY $vgpr13
; GCN-NEXT: [[COPY33:%[0-9]+]]:_(s32) = COPY $vgpr14		; GCN-NEXT: [[COPY35:%[0-9]+]]:_(s32) = COPY $vgpr14
; GCN-NEXT: [[COPY34:%[0-9]+]]:_(s32) = COPY $vgpr15		; GCN-NEXT: [[COPY36:%[0-9]+]]:_(s32) = COPY $vgpr15
; GCN-NEXT: [[COPY35:%[0-9]+]]:_(s32) = COPY $vgpr16		; GCN-NEXT: [[COPY37:%[0-9]+]]:_(s32) = COPY $vgpr16
; GCN-NEXT: [[COPY36:%[0-9]+]]:_(s32) = COPY $vgpr17		; GCN-NEXT: [[COPY38:%[0-9]+]]:_(s32) = COPY $vgpr17
; GCN-NEXT: [[COPY37:%[0-9]+]]:_(s32) = COPY $vgpr18		; GCN-NEXT: [[COPY39:%[0-9]+]]:_(s32) = COPY $vgpr18
; GCN-NEXT: [[COPY38:%[0-9]+]]:_(s32) = COPY $vgpr19		; GCN-NEXT: [[COPY40:%[0-9]+]]:_(s32) = COPY $vgpr19
; GCN-NEXT: [[COPY39:%[0-9]+]]:_(s32) = COPY $vgpr20		; GCN-NEXT: [[COPY41:%[0-9]+]]:_(s32) = COPY $vgpr20
; GCN-NEXT: [[COPY40:%[0-9]+]]:_(s32) = COPY $vgpr21		; GCN-NEXT: [[COPY42:%[0-9]+]]:_(s32) = COPY $vgpr21
; GCN-NEXT: [[COPY41:%[0-9]+]]:_(s32) = COPY $vgpr22		; GCN-NEXT: [[COPY43:%[0-9]+]]:_(s32) = COPY $vgpr22
; GCN-NEXT: [[COPY42:%[0-9]+]]:_(s32) = COPY $vgpr23		; GCN-NEXT: [[COPY44:%[0-9]+]]:_(s32) = COPY $vgpr23
; GCN-NEXT: [[COPY43:%[0-9]+]]:_(s32) = COPY $vgpr24		; GCN-NEXT: [[COPY45:%[0-9]+]]:_(s32) = COPY $vgpr24
; GCN-NEXT: [[COPY44:%[0-9]+]]:_(s32) = COPY $vgpr25		; GCN-NEXT: [[COPY46:%[0-9]+]]:_(s32) = COPY $vgpr25
; GCN-NEXT: [[COPY45:%[0-9]+]]:_(s32) = COPY $vgpr26		; GCN-NEXT: [[COPY47:%[0-9]+]]:_(s32) = COPY $vgpr26
; GCN-NEXT: [[COPY46:%[0-9]+]]:_(s32) = COPY $vgpr27		; GCN-NEXT: [[COPY48:%[0-9]+]]:_(s32) = COPY $vgpr27
; GCN-NEXT: [[COPY47:%[0-9]+]]:_(s32) = COPY $vgpr28		; GCN-NEXT: [[COPY49:%[0-9]+]]:_(s32) = COPY $vgpr28
; GCN-NEXT: [[COPY48:%[0-9]+]]:_(s32) = COPY $vgpr29		; GCN-NEXT: [[COPY50:%[0-9]+]]:_(s32) = COPY $vgpr29
; GCN-NEXT: [[COPY49:%[0-9]+]]:_(s32) = COPY $vgpr30		; GCN-NEXT: [[COPY51:%[0-9]+]]:_(s32) = COPY $vgpr30
; GCN-NEXT: [[COPY50:%[0-9]+]]:_(s32) = COPY $vgpr31		; GCN-NEXT: [[COPY52:%[0-9]+]]:_(s32) = COPY $vgpr31
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32), [[COPY33]](s32), [[COPY34]](s32), [[COPY35]](s32), [[COPY36]](s32), [[COPY37]](s32), [[COPY38]](s32), [[COPY39]](s32), [[COPY40]](s32), [[COPY41]](s32), [[COPY42]](s32), [[COPY43]](s32), [[COPY44]](s32), [[COPY45]](s32), [[COPY46]](s32), [[COPY47]](s32), [[COPY48]](s32), [[COPY49]](s32), [[COPY50]](s32)		; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32), [[COPY33]](s32), [[COPY34]](s32), [[COPY35]](s32), [[COPY36]](s32), [[COPY37]](s32), [[COPY38]](s32), [[COPY39]](s32), [[COPY40]](s32), [[COPY41]](s32), [[COPY42]](s32), [[COPY43]](s32), [[COPY44]](s32), [[COPY45]](s32), [[COPY46]](s32), [[COPY47]](s32), [[COPY48]](s32), [[COPY49]](s32), [[COPY50]](s32), [[COPY51]](s32), [[COPY52]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store (<32 x s32>) into `<32 x i32> addrspace(1)* undef`, align 8, addrspace 1)		; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store (<32 x s32>) into `<32 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <32 x i32> @external_v32i32_func_void()		%val = call <32 x i32> @external_v32i32_func_void()
store volatile <32 x i32> %val, <32 x i32> addrspace(1)* undef, align 8		store volatile <32 x i32> %val, <32 x i32> addrspace(1)* undef, align 8
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v2i16_func_void() #0 {		define amdgpu_kernel void @test_call_external_v2i16_func_void() #0 {
; GCN-LABEL: name: test_call_external_v2i16_func_void		; GCN-LABEL: name: test_call_external_v2i16_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v2i16_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v2i16_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2i16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2i16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[COPY19]](<2 x s16>), [[DEF]](p1) :: (volatile store (<2 x s16>) into `<2 x i16> addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[COPY21]](<2 x s16>), [[DEF]](p1) :: (volatile store (<2 x s16>) into `<2 x i16> addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <2 x i16> @external_v2i16_func_void()		%val = call <2 x i16> @external_v2i16_func_void()
store volatile <2 x i16> %val, <2 x i16> addrspace(1)* undef		store volatile <2 x i16> %val, <2 x i16> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v3i16_func_void() #0 {		define amdgpu_kernel void @test_call_external_v3i16_func_void() #0 {
; GCN-LABEL: name: test_call_external_v3i16_func_void		; GCN-LABEL: name: test_call_external_v3i16_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v3i16_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v3i16_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3i16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3i16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY19]](<2 x s16>), [[COPY20]](<2 x s16>), [[DEF1]](<2 x s16>)		; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>), [[DEF1]](<2 x s16>)
; GCN-NEXT: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)		; GCN-NEXT: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[UV]](<3 x s16>), [[DEF]](p1) :: (volatile store (<3 x s16>) into `<3 x i16> addrspace(1)* undef`, align 8, addrspace 1)		; GCN-NEXT: G_STORE [[UV]](<3 x s16>), [[DEF]](p1) :: (volatile store (<3 x s16>) into `<3 x i16> addrspace(1)* undef`, align 8, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <3 x i16> @external_v3i16_func_void()		%val = call <3 x i16> @external_v3i16_func_void()
store volatile <3 x i16> %val, <3 x i16> addrspace(1)* undef		store volatile <3 x i16> %val, <3 x i16> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v4i16_func_void() #0 {		define amdgpu_kernel void @test_call_external_v4i16_func_void() #0 {
; GCN-LABEL: name: test_call_external_v4i16_func_void		; GCN-LABEL: name: test_call_external_v4i16_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v4i16_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v4i16_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v4i16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v4i16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY19]](<2 x s16>), [[COPY20]](<2 x s16>)		; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[CONCAT_VECTORS]](<4 x s16>), [[DEF]](p1) :: (volatile store (<4 x s16>) into `<4 x i16> addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[CONCAT_VECTORS]](<4 x s16>), [[DEF]](p1) :: (volatile store (<4 x s16>) into `<4 x i16> addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <4 x i16> @external_v4i16_func_void()		%val = call <4 x i16> @external_v4i16_func_void()
store volatile <4 x i16> %val, <4 x i16> addrspace(1)* undef		store volatile <4 x i16> %val, <4 x i16> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v2f16_func_void() #0 {		define amdgpu_kernel void @test_call_external_v2f16_func_void() #0 {
; GCN-LABEL: name: test_call_external_v2f16_func_void		; GCN-LABEL: name: test_call_external_v2f16_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v2f16_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v2f16_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2f16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v2f16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[COPY19]](<2 x s16>), [[DEF]](p1) :: (volatile store (<2 x s16>) into `<2 x half> addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[COPY21]](<2 x s16>), [[DEF]](p1) :: (volatile store (<2 x s16>) into `<2 x half> addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <2 x half> @external_v2f16_func_void()		%val = call <2 x half> @external_v2f16_func_void()
store volatile <2 x half> %val, <2 x half> addrspace(1)* undef		store volatile <2 x half> %val, <2 x half> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v3f16_func_void() #0 {		define amdgpu_kernel void @test_call_external_v3f16_func_void() #0 {
; GCN-LABEL: name: test_call_external_v3f16_func_void		; GCN-LABEL: name: test_call_external_v3f16_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v3f16_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v3f16_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3f16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3f16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY19]](<2 x s16>), [[COPY20]](<2 x s16>), [[DEF1]](<2 x s16>)		; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>), [[DEF1]](<2 x s16>)
; GCN-NEXT: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)		; GCN-NEXT: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[UV]](<3 x s16>), [[DEF]](p1) :: (volatile store (<3 x s16>) into `<3 x half> addrspace(1)* undef`, align 8, addrspace 1)		; GCN-NEXT: G_STORE [[UV]](<3 x s16>), [[DEF]](p1) :: (volatile store (<3 x s16>) into `<3 x half> addrspace(1)* undef`, align 8, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <3 x half> @external_v3f16_func_void()		%val = call <3 x half> @external_v3f16_func_void()
store volatile <3 x half> %val, <3 x half> addrspace(1)* undef		store volatile <3 x half> %val, <3 x half> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v4f16_func_void() #0 {		define amdgpu_kernel void @test_call_external_v4f16_func_void() #0 {
; GCN-LABEL: name: test_call_external_v4f16_func_void		; GCN-LABEL: name: test_call_external_v4f16_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v4f16_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v4f16_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v4f16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v4f16_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY19]](<2 x s16>), [[COPY20]](<2 x s16>)		; GCN-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[CONCAT_VECTORS]](<4 x s16>), [[DEF]](p1) :: (volatile store (<4 x s16>) into `<4 x half> addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[CONCAT_VECTORS]](<4 x s16>), [[DEF]](p1) :: (volatile store (<4 x s16>) into `<4 x half> addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <4 x half> @external_v4f16_func_void()		%val = call <4 x half> @external_v4f16_func_void()
store volatile <4 x half> %val, <4 x half> addrspace(1)* undef		store volatile <4 x half> %val, <4 x half> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v3f32_func_void() #0 {		define amdgpu_kernel void @test_call_external_v3f32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v3f32_func_void		; GCN-LABEL: name: test_call_external_v3f32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v3f32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v3f32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3f32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v3f32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32)		; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<3 x s32>), [[DEF]](p1) :: (volatile store (<3 x s32>) into `<3 x float> addrspace(1)* undef`, align 16, addrspace 1)		; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<3 x s32>), [[DEF]](p1) :: (volatile store (<3 x s32>) into `<3 x float> addrspace(1)* undef`, align 16, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <3 x float> @external_v3f32_func_void()		%val = call <3 x float> @external_v3f32_func_void()
store volatile <3 x float> %val, <3 x float> addrspace(1)* undef		store volatile <3 x float> %val, <3 x float> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v5f32_func_void() #0 {		define amdgpu_kernel void @test_call_external_v5f32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v5f32_func_void		; GCN-LABEL: name: test_call_external_v5f32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v5f32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v5f32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v5f32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v5f32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr3		; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr4		; GCN-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4
; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32)		; GCN-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<5 x s32>), [[DEF]](p1) :: (volatile store (<5 x s32>) into `<5 x float> addrspace(1)* undef`, align 32, addrspace 1)		; GCN-NEXT: G_STORE [[BUILD_VECTOR]](<5 x s32>), [[DEF]](p1) :: (volatile store (<5 x s32>) into `<5 x float> addrspace(1)* undef`, align 32, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <5 x float> @external_v5f32_func_void()		%val = call <5 x float> @external_v5f32_func_void()
store volatile <5 x float> %val, <5 x float> addrspace(1)* undef		store volatile <5 x float> %val, <5 x float> addrspace(1)* undef
ret void		ret void
}		}


define amdgpu_kernel void @test_call_external_i32_i64_func_void() #0 {		define amdgpu_kernel void @test_call_external_i32_i64_func_void() #0 {
; GCN-LABEL: name: test_call_external_i32_i64_func_void		; GCN-LABEL: name: test_call_external_i32_i64_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i32_i64_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i32_i64_func_void
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C]](s64)
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY16]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY12]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY14]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY15]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i32_i64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i32_i64_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY21]](s32), [[COPY22]](s32)		; GCN-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY23]](s32), [[COPY24]](s32)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[COPY20]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[COPY22]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: G_STORE [[MV]](s64), [[COPY9]](p1) :: (volatile store (s64) into `i64 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[MV]](s64), [[COPY10]](p1) :: (volatile store (s64) into `i64 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call { i32, i64 } @external_i32_i64_func_void()		%val = call { i32, i64 } @external_i32_i64_func_void()
%val.0 = extractvalue { i32, i64 } %val, 0		%val.0 = extractvalue { i32, i64 } %val, 0
%val.1 = extractvalue { i32, i64 } %val, 1		%val.1 = extractvalue { i32, i64 } %val, 1
store volatile i32 %val.0, i32 addrspace(1)* undef		store volatile i32 %val.0, i32 addrspace(1)* undef
store volatile i64 %val.1, i64 addrspace(1)* undef		store volatile i64 %val.1, i64 addrspace(1)* undef
ret void		ret void
}		}
Show All 26 Lines	define amdgpu_gfx void @test_gfx_call_external_i32_i64_func_void() #0 {
store volatile i32 %val.0, i32 addrspace(1)* undef		store volatile i32 %val.0, i32 addrspace(1)* undef
store volatile i64 %val.1, i64 addrspace(1)* undef		store volatile i64 %val.1, i64 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_a2i32_func_void() #0 {		define amdgpu_kernel void @test_call_external_a2i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_a2i32_func_void		; GCN-LABEL: name: test_call_external_a2i32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_a2i32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_a2i32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_a2i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_a2i32_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[COPY19]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[COPY21]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: G_STORE [[COPY20]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[COPY22]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call [2 x i32] @external_a2i32_func_void()		%val = call [2 x i32] @external_a2i32_func_void()
%val.0 = extractvalue [2 x i32] %val, 0		%val.0 = extractvalue [2 x i32] %val, 0
%val.1 = extractvalue [2 x i32] %val, 1		%val.1 = extractvalue [2 x i32] %val, 1
store volatile i32 %val.0, i32 addrspace(1)* undef		store volatile i32 %val.0, i32 addrspace(1)* undef
store volatile i32 %val.1, i32 addrspace(1)* undef		store volatile i32 %val.1, i32 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_a5i8_func_void() #0 {		define amdgpu_kernel void @test_call_external_a5i8_func_void() #0 {
; GCN-LABEL: name: test_call_external_a5i8_func_void		; GCN-LABEL: name: test_call_external_a5i8_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_a5i8_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_a5i8_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_a5i8_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_a5i8_func_void, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY19]](s32)		; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY21]](s32)
; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC]](s16)		; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC]](s16)
; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY20]](s32)		; GCN-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY22]](s32)
; GCN-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC2]](s16)		; GCN-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC2]](s16)
; GCN-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY21]](s32)		; GCN-NEXT: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY23]](s32)
; GCN-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC4]](s16)		; GCN-NEXT: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC4]](s16)
; GCN-NEXT: [[COPY22:%[0-9]+]]:_(s32) = COPY $vgpr3		; GCN-NEXT: [[COPY24:%[0-9]+]]:_(s32) = COPY $vgpr3
; GCN-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY22]](s32)		; GCN-NEXT: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY24]](s32)
; GCN-NEXT: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC6]](s16)		; GCN-NEXT: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC6]](s16)
; GCN-NEXT: [[COPY23:%[0-9]+]]:_(s32) = COPY $vgpr4		; GCN-NEXT: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr4
; GCN-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[COPY23]](s32)		; GCN-NEXT: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[COPY25]](s32)
; GCN-NEXT: [[TRUNC9:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC8]](s16)		; GCN-NEXT: [[TRUNC9:%[0-9]+]]:_(s8) = G_TRUNC [[TRUNC8]](s16)
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: G_STORE [[TRUNC1]](s8), [[DEF]](p1) :: (volatile store (s8) into `i8 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[TRUNC1]](s8), [[DEF]](p1) :: (volatile store (s8) into `i8 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: G_STORE [[TRUNC3]](s8), [[DEF]](p1) :: (volatile store (s8) into `i8 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[TRUNC3]](s8), [[DEF]](p1) :: (volatile store (s8) into `i8 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: G_STORE [[TRUNC5]](s8), [[DEF]](p1) :: (volatile store (s8) into `i8 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[TRUNC5]](s8), [[DEF]](p1) :: (volatile store (s8) into `i8 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: G_STORE [[TRUNC7]](s8), [[DEF]](p1) :: (volatile store (s8) into `i8 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[TRUNC7]](s8), [[DEF]](p1) :: (volatile store (s8) into `i8 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: G_STORE [[TRUNC9]](s8), [[DEF]](p1) :: (volatile store (s8) into `i8 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[TRUNC9]](s8), [[DEF]](p1) :: (volatile store (s8) into `i8 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
Show All 9 Lines	define amdgpu_kernel void @test_call_external_a5i8_func_void() #0 {
store volatile i8 %val.3, i8 addrspace(1)* undef		store volatile i8 %val.3, i8 addrspace(1)* undef
store volatile i8 %val.4, i8 addrspace(1)* undef		store volatile i8 %val.4, i8 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v32i32_i32_func_void() #0 {		define amdgpu_kernel void @test_call_external_v32i32_i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v32i32_i32_func_void		; GCN-LABEL: name: test_call_external_v32i32_i32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; GCN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0		; GCN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v32i32_i32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v32i32_i32_func_void
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C]](s64)
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY16]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: $vgpr0 = COPY [[FRAME_INDEX]](p5)		; GCN-NEXT: $vgpr0 = COPY [[FRAME_INDEX]](p5)
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY12]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY14]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY15]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v32i32_i32_func_void, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v32i32_i32_func_void, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load (<32 x s32>) from %stack.0, addrspace 5)		; GCN-NEXT: [[LOAD:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load (<32 x s32>) from %stack.0, addrspace 5)
; GCN-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 128		; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; GCN-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C4]](s32)		; GCN-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C3]](s32)
; GCN-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s32) from %stack.0, align 128, addrspace 5)		; GCN-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s32) from %stack.0, align 128, addrspace 5)
; GCN-NEXT: G_STORE [[LOAD]](<32 x s32>), [[DEF]](p1) :: (volatile store (<32 x s32>) into `<32 x i32> addrspace(1)* undef`, align 8, addrspace 1)		; GCN-NEXT: G_STORE [[LOAD]](<32 x s32>), [[DEF]](p1) :: (volatile store (<32 x s32>) into `<32 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN-NEXT: G_STORE [[LOAD1]](s32), [[COPY9]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[LOAD1]](s32), [[COPY10]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call { <32 x i32>, i32 } @external_v32i32_i32_func_void()		%val = call { <32 x i32>, i32 } @external_v32i32_i32_func_void()
%val0 = extractvalue { <32 x i32>, i32 } %val, 0		%val0 = extractvalue { <32 x i32>, i32 } %val, 0
%val1 = extractvalue { <32 x i32>, i32 } %val, 1		%val1 = extractvalue { <32 x i32>, i32 } %val, 1
store volatile <32 x i32> %val0, <32 x i32> addrspace(1)* undef, align 8		store volatile <32 x i32> %val0, <32 x i32> addrspace(1)* undef, align 8
store volatile i32 %val1, i32 addrspace(1)* undef		store volatile i32 %val1, i32 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_i32_v32i32_func_void() #0 {		define amdgpu_kernel void @test_call_external_i32_v32i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_i32_v32i32_func_void		; GCN-LABEL: name: test_call_external_i32_v32i32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; GCN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0		; GCN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i32_v32i32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_i32_v32i32_func_void
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C]](s64)
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY16]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]]
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: $vgpr0 = COPY [[FRAME_INDEX]](p5)		; GCN-NEXT: $vgpr0 = COPY [[FRAME_INDEX]](p5)
; GCN-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY12]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY14]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY16]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY15]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY17]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i32_v32i32_func_void, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_i32_v32i32_func_void, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (load (s32) from %stack.0, align 128, addrspace 5)		; GCN-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (load (s32) from %stack.0, align 128, addrspace 5)
; GCN-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 128		; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; GCN-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C4]](s32)		; GCN-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C3]](s32)
; GCN-NEXT: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[PTR_ADD1]](p5) :: (load (<32 x s32>) from %stack.0, addrspace 5)		; GCN-NEXT: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[PTR_ADD1]](p5) :: (load (<32 x s32>) from %stack.0, addrspace 5)
; GCN-NEXT: G_STORE [[LOAD]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)		; GCN-NEXT: G_STORE [[LOAD]](s32), [[DEF]](p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; GCN-NEXT: G_STORE [[LOAD1]](<32 x s32>), [[COPY9]](p1) :: (volatile store (<32 x s32>) into `<32 x i32> addrspace(1)* undef`, align 8, addrspace 1)		; GCN-NEXT: G_STORE [[LOAD1]](<32 x s32>), [[COPY10]](p1) :: (volatile store (<32 x s32>) into `<32 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call { i32, <32 x i32> } @external_i32_v32i32_func_void()		%val = call { i32, <32 x i32> } @external_i32_v32i32_func_void()
%val0 = extractvalue { i32, <32 x i32> } %val, 0		%val0 = extractvalue { i32, <32 x i32> } %val, 0
%val1 = extractvalue { i32, <32 x i32> } %val, 1		%val1 = extractvalue { i32, <32 x i32> } %val, 1
store volatile i32 %val0, i32 addrspace(1)* undef		store volatile i32 %val0, i32 addrspace(1)* undef
store volatile <32 x i32> %val1, <32 x i32> addrspace(1)* undef, align 8		store volatile <32 x i32> %val1, <32 x i32> addrspace(1)* undef, align 8
ret void		ret void
}		}

define amdgpu_kernel void @test_call_external_v33i32_func_void() #0 {		define amdgpu_kernel void @test_call_external_v33i32_func_void() #0 {
; GCN-LABEL: name: test_call_external_v33i32_func_void		; GCN-LABEL: name: test_call_external_v33i32_func_void
; GCN: bb.1 (%ir-block.0):		; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9		; GCN-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN-NEXT: {{ $}}		; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2		; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1		; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0		; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14		; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13		; GCN-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12		; GCN-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9		; GCN-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7		; GCN-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5		; GCN-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
		; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF		; GCN-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0		; GCN-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0
; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v33i32_func_void		; GCN-NEXT: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_v33i32_func_void
; GCN-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]		; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]		; GCN-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN-NEXT: [[C:%[0-9]+]]:_(p4) = G_CONSTANT i64 0		; GCN-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0		; GCN-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[C]], [[C1]](s64)		; GCN-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY12]], [[C]](s64)
; GCN-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY [[COPY6]]		; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]]		; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]		; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]		; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)		; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10		; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C2]](s32)		; GCN-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)
; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL]]		; GCN-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GCN-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20		; GCN-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C3]](s32)		; GCN-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)
; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]		; GCN-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN-NEXT: $vgpr0 = COPY [[FRAME_INDEX]](p5)		; GCN-NEXT: $vgpr0 = COPY [[FRAME_INDEX]](p5)
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg		; GCN-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)		; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)		; GCN-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)		; GCN-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)		; GCN-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY11]](s64)		; GCN-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GCN-NEXT: $sgpr12 = COPY [[COPY12]](s32)		; GCN-NEXT: $sgpr12 = COPY [[COPY14]](s32)
; GCN-NEXT: $sgpr13 = COPY [[COPY13]](s32)		; GCN-NEXT: $sgpr13 = COPY [[COPY15]](s32)
; GCN-NEXT: $sgpr14 = COPY [[COPY14]](s32)		; GCN-NEXT: $sgpr14 = COPY [[COPY16]](s32)
; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)		; GCN-NEXT: $vgpr31 = COPY [[OR1]](s32)
; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v33i32_func_void, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31		; GCN-NEXT: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_v33i32_func_void, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31
; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc		; GCN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load (<33 x s32>) from %stack.0, align 256, addrspace 5)		; GCN-NEXT: [[LOAD:%[0-9]+]]:_(<33 x s32>) = G_LOAD [[FRAME_INDEX]](p5) :: (load (<33 x s32>) from %stack.0, align 256, addrspace 5)
; GCN-NEXT: G_STORE [[LOAD]](<33 x s32>), [[DEF]](p1) :: (volatile store (<33 x s32>) into `<33 x i32> addrspace(1)* undef`, align 8, addrspace 1)		; GCN-NEXT: G_STORE [[LOAD]](<33 x s32>), [[DEF]](p1) :: (volatile store (<33 x s32>) into `<33 x i32> addrspace(1)* undef`, align 8, addrspace 1)
; GCN-NEXT: S_ENDPGM 0		; GCN-NEXT: S_ENDPGM 0
%val = call <33 x i32> @external_v33i32_func_void()		%val = call <33 x i32> @external_v33i32_func_void()
store volatile <33 x i32> %val, <33 x i32> addrspace(1)* undef, align 8		store volatile <33 x i32> %val, <33 x i32> addrspace(1)* undef, align 8
▲ Show 20 Lines • Show All 73 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll

Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Lines	define i8 addrspace(4)* @func_kernarg_segment_ptr() {
%ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()		%ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
ret i8 addrspace(4)* %ptr		ret i8 addrspace(4)* %ptr
}		}

declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0		declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0		declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0

attributes #0 = { nounwind readnone }		attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }		attributes #1 = { nounwind "amdgpu-implicitarg-num-bytes"="0" }
attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="48" }		attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="48" }
attributes #3 = { nounwind "amdgpu-implicitarg-num-bytes"="38" }		attributes #3 = { nounwind "amdgpu-implicitarg-num-bytes"="38" }

llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll

	Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Lines
	; GCN: .amdhsa_user_sgpr_flat_scratch_init 1			; GCN: .amdhsa_user_sgpr_flat_scratch_init 1
	; GCN: .amdhsa_user_sgpr_private_segment_size 0			; GCN: .amdhsa_user_sgpr_private_segment_size 0
	; GCN: .amdhsa_system_sgpr_private_segment_wavefront_offset 1			; GCN: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
	; GCN: .amdhsa_system_sgpr_workgroup_id_x 1			; GCN: .amdhsa_system_sgpr_workgroup_id_x 1
	; GCN: .amdhsa_system_sgpr_workgroup_id_y 1			; GCN: .amdhsa_system_sgpr_workgroup_id_y 1
	; GCN: .amdhsa_system_sgpr_workgroup_id_z 1			; GCN: .amdhsa_system_sgpr_workgroup_id_z 1
	; GCN: .amdhsa_system_sgpr_workgroup_info 0			; GCN: .amdhsa_system_sgpr_workgroup_info 0
	; GCN: .amdhsa_system_vgpr_workitem_id 2			; GCN: .amdhsa_system_vgpr_workitem_id 2
	define amdgpu_kernel void @kern_indirect_use_every_sgpr_input_no_kernargs() #1 {			define amdgpu_kernel void @kern_indirect_use_every_sgpr_input_no_kernargs() #2 {
	call void @use_every_sgpr_input()			call void @use_every_sgpr_input()
	ret void			ret void
	}			}

	; GCN-LABEL: {{^}}func_indirect_use_every_sgpr_input:			; GCN-LABEL: {{^}}func_indirect_use_every_sgpr_input:
	; GCN-NOT: s6			; GCN-NOT: s6
	; GCN-NOT: s7			; GCN-NOT: s7
	; GCN-NOT: s8			; GCN-NOT: s8
	▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
	declare noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0			declare noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
	declare noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0			declare noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
	declare noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0			declare noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
	declare i64 @llvm.amdgcn.dispatch.id() #0			declare i64 @llvm.amdgcn.dispatch.id() #0
	declare noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0			declare noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0

	attributes #0 = { nounwind readnone speculatable }			attributes #0 = { nounwind readnone speculatable }
	attributes #1 = { nounwind noinline }			attributes #1 = { nounwind noinline }
				attributes #2 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="0" }

llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll

	Show First 20 Lines • Show All 472 Lines • ▼ Show 20 Lines
	; GCN: enable_sgpr_kernarg_segment_ptr = 0			; GCN: enable_sgpr_kernarg_segment_ptr = 0
	; GCN: enable_sgpr_dispatch_id = 1			; GCN: enable_sgpr_dispatch_id = 1
	; GCN: enable_sgpr_flat_scratch_init = 1			; GCN: enable_sgpr_flat_scratch_init = 1

	; GCN: s_mov_b64 s[10:11], s[8:9]			; GCN: s_mov_b64 s[10:11], s[8:9]
	; GCN: s_mov_b64 s[8:9], 0{{$}}			; GCN: s_mov_b64 s[8:9], 0{{$}}
	; GCN: s_mov_b32 s32, 0			; GCN: s_mov_b32 s32, 0
	; GCN: s_swappc_b64			; GCN: s_swappc_b64
	define amdgpu_kernel void @kern_indirect_use_every_sgpr_input_no_kernargs() #1 {			define amdgpu_kernel void @kern_indirect_use_every_sgpr_input_no_kernargs() #2 {
	call void @use_every_sgpr_input()			call void @use_every_sgpr_input()
	ret void			ret void
	}			}

	; GCN-LABEL: {{^}}func_indirect_use_every_sgpr_input:			; GCN-LABEL: {{^}}func_indirect_use_every_sgpr_input:
	; GCN-NOT: s6			; GCN-NOT: s6
	; GCN-NOT: s7			; GCN-NOT: s7
	; GCN-NOT: s8			; GCN-NOT: s8
	▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
	declare noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0			declare noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
	declare noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0			declare noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
	declare noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0			declare noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
	declare i64 @llvm.amdgcn.dispatch.id() #0			declare i64 @llvm.amdgcn.dispatch.id() #0
	declare noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0			declare noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0

	attributes #0 = { nounwind readnone speculatable }			attributes #0 = { nounwind readnone speculatable }
	attributes #1 = { nounwind noinline }			attributes #1 = { nounwind noinline }
				attributes #2 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="0" }

llvm/test/CodeGen/AMDGPU/cc-update.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines	entry:
%x = alloca i32, align 4, addrspace(5)		%x = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %x, align 4		store volatile i32 0, i32 addrspace(5)* %x, align 4
ret void		ret void
}		}

define amdgpu_kernel void @test_kern_call() local_unnamed_addr #0 {		define amdgpu_kernel void @test_kern_call() local_unnamed_addr #0 {
; GFX803-LABEL: test_kern_call:		; GFX803-LABEL: test_kern_call:
; GFX803: ; %bb.0: ; %entry		; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_add_i32 s10, s10, s15		; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s10, 8		; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_add_u32 s0, s0, s15		; GFX803-NEXT: s_add_u32 s0, s0, s17
; GFX803-NEXT: s_addc_u32 s1, s1, 0		; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: s_mov_b32 s32, 0		; GFX803-NEXT: s_mov_b32 s32, 0
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s11		; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_getpc_b64 s[4:5]		; GFX803-NEXT: s_getpc_b64 s[4:5]
; GFX803-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4		; GFX803-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX803-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12		; GFX803-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX803-NEXT: s_swappc_b64 s[30:31], s[4:5]		; GFX803-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX803-NEXT: s_endpgm		; GFX803-NEXT: s_endpgm
;		;
; GFX900-LABEL: test_kern_call:		; GFX900-LABEL: test_kern_call:
; GFX900: ; %bb.0: ; %entry		; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_add_u32 flat_scratch_lo, s10, s15		; GFX900-NEXT: s_add_u32 flat_scratch_lo, s12, s17
; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s11, 0		; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GFX900-NEXT: s_add_u32 s0, s0, s15		; GFX900-NEXT: s_add_u32 s0, s0, s17
; GFX900-NEXT: s_addc_u32 s1, s1, 0		; GFX900-NEXT: s_addc_u32 s1, s1, 0
; GFX900-NEXT: s_mov_b32 s32, 0		; GFX900-NEXT: s_mov_b32 s32, 0
; GFX900-NEXT: s_getpc_b64 s[4:5]		; GFX900-NEXT: s_getpc_b64 s[4:5]
; GFX900-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4		; GFX900-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX900-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12		; GFX900-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5]		; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX900-NEXT: s_endpgm		; GFX900-NEXT: s_endpgm
;		;
; GFX1010-LABEL: test_kern_call:		; GFX1010-LABEL: test_kern_call:
; GFX1010: ; %bb.0: ; %entry		; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s10, s10, s15		; GFX1010-NEXT: s_add_u32 s12, s12, s17
; GFX1010-NEXT: s_mov_b32 s32, 0		; GFX1010-NEXT: s_mov_b32 s32, 0
; GFX1010-NEXT: s_addc_u32 s11, s11, 0		; GFX1010-NEXT: s_addc_u32 s13, s13, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s10		; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s11		; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
; GFX1010-NEXT: s_add_u32 s0, s0, s15		; GFX1010-NEXT: s_add_u32 s0, s0, s17
; GFX1010-NEXT: s_addc_u32 s1, s1, 0		; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: s_getpc_b64 s[4:5]		; GFX1010-NEXT: s_getpc_b64 s[4:5]
; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4		; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12		; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5]		; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX1010-NEXT: s_endpgm		; GFX1010-NEXT: s_endpgm
entry:		entry:
tail call void @ex() #0		tail call void @ex() #0
ret void		ret void
}		}

define amdgpu_kernel void @test_kern_stack_and_call() local_unnamed_addr #0 {		define amdgpu_kernel void @test_kern_stack_and_call() local_unnamed_addr #0 {
; GFX803-LABEL: test_kern_stack_and_call:		; GFX803-LABEL: test_kern_stack_and_call:
; GFX803: ; %bb.0: ; %entry		; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_add_i32 s10, s10, s15		; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s10, 8		; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_add_u32 s0, s0, s15		; GFX803-NEXT: s_add_u32 s0, s0, s17
; GFX803-NEXT: s_addc_u32 s1, s1, 0		; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_mov_b32_e32 v0, 0		; GFX803-NEXT: v_mov_b32_e32 v0, 0
; GFX803-NEXT: s_movk_i32 s32, 0x400		; GFX803-NEXT: s_movk_i32 s32, 0x400
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s11		; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4		; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX803-NEXT: s_waitcnt vmcnt(0)		; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_getpc_b64 s[4:5]		; GFX803-NEXT: s_getpc_b64 s[4:5]
; GFX803-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4		; GFX803-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX803-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12		; GFX803-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX803-NEXT: s_swappc_b64 s[30:31], s[4:5]		; GFX803-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX803-NEXT: s_endpgm		; GFX803-NEXT: s_endpgm
;		;
; GFX900-LABEL: test_kern_stack_and_call:		; GFX900-LABEL: test_kern_stack_and_call:
; GFX900: ; %bb.0: ; %entry		; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_add_u32 flat_scratch_lo, s10, s15		; GFX900-NEXT: s_add_u32 flat_scratch_lo, s12, s17
; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s11, 0		; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GFX900-NEXT: s_add_u32 s0, s0, s15		; GFX900-NEXT: s_add_u32 s0, s0, s17
; GFX900-NEXT: s_addc_u32 s1, s1, 0		; GFX900-NEXT: s_addc_u32 s1, s1, 0
; GFX900-NEXT: v_mov_b32_e32 v0, 0		; GFX900-NEXT: v_mov_b32_e32 v0, 0
; GFX900-NEXT: s_movk_i32 s32, 0x400		; GFX900-NEXT: s_movk_i32 s32, 0x400
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4		; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX900-NEXT: s_waitcnt vmcnt(0)		; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_getpc_b64 s[4:5]		; GFX900-NEXT: s_getpc_b64 s[4:5]
; GFX900-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4		; GFX900-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX900-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12		; GFX900-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5]		; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX900-NEXT: s_endpgm		; GFX900-NEXT: s_endpgm
;		;
; GFX1010-LABEL: test_kern_stack_and_call:		; GFX1010-LABEL: test_kern_stack_and_call:
; GFX1010: ; %bb.0: ; %entry		; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s10, s10, s15		; GFX1010-NEXT: s_add_u32 s12, s12, s17
; GFX1010-NEXT: s_movk_i32 s32, 0x200		; GFX1010-NEXT: s_movk_i32 s32, 0x200
; GFX1010-NEXT: s_addc_u32 s11, s11, 0		; GFX1010-NEXT: s_addc_u32 s13, s13, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s10		; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s11		; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
; GFX1010-NEXT: v_mov_b32_e32 v0, 0		; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s15		; GFX1010-NEXT: s_add_u32 s0, s0, s17
; GFX1010-NEXT: s_addc_u32 s1, s1, 0		; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: s_getpc_b64 s[4:5]		; GFX1010-NEXT: s_getpc_b64 s[4:5]
; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4		; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12		; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4		; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0		; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5]		; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX1010-NEXT: s_endpgm		; GFX1010-NEXT: s_endpgm
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines	entry:
%x = alloca i32, align 4, addrspace(5)		%x = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %x, align 4		store volatile i32 0, i32 addrspace(5)* %x, align 4
ret void		ret void
}		}

define amdgpu_kernel void @test_force_fp_kern_call() local_unnamed_addr #2 {		define amdgpu_kernel void @test_force_fp_kern_call() local_unnamed_addr #2 {
; GFX803-LABEL: test_force_fp_kern_call:		; GFX803-LABEL: test_force_fp_kern_call:
; GFX803: ; %bb.0: ; %entry		; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_add_i32 s10, s10, s15		; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s10, 8		; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_add_u32 s0, s0, s15		; GFX803-NEXT: s_add_u32 s0, s0, s17
; GFX803-NEXT: s_addc_u32 s1, s1, 0		; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: s_mov_b32 s32, 0		; GFX803-NEXT: s_mov_b32 s32, 0
; GFX803-NEXT: s_mov_b32 s33, 0		; GFX803-NEXT: s_mov_b32 s33, 0
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s11		; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_getpc_b64 s[4:5]		; GFX803-NEXT: s_getpc_b64 s[4:5]
; GFX803-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4		; GFX803-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX803-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12		; GFX803-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX803-NEXT: s_swappc_b64 s[30:31], s[4:5]		; GFX803-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX803-NEXT: s_endpgm		; GFX803-NEXT: s_endpgm
;		;
; GFX900-LABEL: test_force_fp_kern_call:		; GFX900-LABEL: test_force_fp_kern_call:
; GFX900: ; %bb.0: ; %entry		; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_add_u32 flat_scratch_lo, s10, s15		; GFX900-NEXT: s_add_u32 flat_scratch_lo, s12, s17
; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s11, 0		; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GFX900-NEXT: s_add_u32 s0, s0, s15		; GFX900-NEXT: s_add_u32 s0, s0, s17
; GFX900-NEXT: s_addc_u32 s1, s1, 0		; GFX900-NEXT: s_addc_u32 s1, s1, 0
; GFX900-NEXT: s_mov_b32 s32, 0		; GFX900-NEXT: s_mov_b32 s32, 0
; GFX900-NEXT: s_mov_b32 s33, 0		; GFX900-NEXT: s_mov_b32 s33, 0
; GFX900-NEXT: s_getpc_b64 s[4:5]		; GFX900-NEXT: s_getpc_b64 s[4:5]
; GFX900-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4		; GFX900-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX900-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12		; GFX900-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5]		; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX900-NEXT: s_endpgm		; GFX900-NEXT: s_endpgm
;		;
; GFX1010-LABEL: test_force_fp_kern_call:		; GFX1010-LABEL: test_force_fp_kern_call:
; GFX1010: ; %bb.0: ; %entry		; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s10, s10, s15		; GFX1010-NEXT: s_add_u32 s12, s12, s17
; GFX1010-NEXT: s_mov_b32 s32, 0		; GFX1010-NEXT: s_mov_b32 s32, 0
; GFX1010-NEXT: s_mov_b32 s33, 0		; GFX1010-NEXT: s_mov_b32 s33, 0
; GFX1010-NEXT: s_addc_u32 s11, s11, 0		; GFX1010-NEXT: s_addc_u32 s13, s13, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s10		; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s11		; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
; GFX1010-NEXT: s_add_u32 s0, s0, s15		; GFX1010-NEXT: s_add_u32 s0, s0, s17
; GFX1010-NEXT: s_addc_u32 s1, s1, 0		; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: s_getpc_b64 s[4:5]		; GFX1010-NEXT: s_getpc_b64 s[4:5]
; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4		; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12		; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5]		; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX1010-NEXT: s_endpgm		; GFX1010-NEXT: s_endpgm
entry:		entry:
tail call void @ex() #2		tail call void @ex() #2
ret void		ret void
}		}

define amdgpu_kernel void @test_force_fp_kern_stack_and_call() local_unnamed_addr #2 {		define amdgpu_kernel void @test_force_fp_kern_stack_and_call() local_unnamed_addr #2 {
; GFX803-LABEL: test_force_fp_kern_stack_and_call:		; GFX803-LABEL: test_force_fp_kern_stack_and_call:
; GFX803: ; %bb.0: ; %entry		; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_add_i32 s10, s10, s15		; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s10, 8		; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_add_u32 s0, s0, s15		; GFX803-NEXT: s_add_u32 s0, s0, s17
; GFX803-NEXT: s_mov_b32 s33, 0		; GFX803-NEXT: s_mov_b32 s33, 0
; GFX803-NEXT: s_addc_u32 s1, s1, 0		; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_mov_b32_e32 v0, 0		; GFX803-NEXT: v_mov_b32_e32 v0, 0
; GFX803-NEXT: s_movk_i32 s32, 0x400		; GFX803-NEXT: s_movk_i32 s32, 0x400
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s11		; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4		; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX803-NEXT: s_waitcnt vmcnt(0)		; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_getpc_b64 s[4:5]		; GFX803-NEXT: s_getpc_b64 s[4:5]
; GFX803-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4		; GFX803-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX803-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12		; GFX803-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX803-NEXT: s_swappc_b64 s[30:31], s[4:5]		; GFX803-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX803-NEXT: s_endpgm		; GFX803-NEXT: s_endpgm
;		;
; GFX900-LABEL: test_force_fp_kern_stack_and_call:		; GFX900-LABEL: test_force_fp_kern_stack_and_call:
; GFX900: ; %bb.0: ; %entry		; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_add_u32 flat_scratch_lo, s10, s15		; GFX900-NEXT: s_add_u32 flat_scratch_lo, s12, s17
; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s11, 0		; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
; GFX900-NEXT: s_add_u32 s0, s0, s15		; GFX900-NEXT: s_add_u32 s0, s0, s17
; GFX900-NEXT: s_mov_b32 s33, 0		; GFX900-NEXT: s_mov_b32 s33, 0
; GFX900-NEXT: s_addc_u32 s1, s1, 0		; GFX900-NEXT: s_addc_u32 s1, s1, 0
; GFX900-NEXT: v_mov_b32_e32 v0, 0		; GFX900-NEXT: v_mov_b32_e32 v0, 0
; GFX900-NEXT: s_movk_i32 s32, 0x400		; GFX900-NEXT: s_movk_i32 s32, 0x400
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4		; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX900-NEXT: s_waitcnt vmcnt(0)		; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_getpc_b64 s[4:5]		; GFX900-NEXT: s_getpc_b64 s[4:5]
; GFX900-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4		; GFX900-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX900-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12		; GFX900-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5]		; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX900-NEXT: s_endpgm		; GFX900-NEXT: s_endpgm
;		;
; GFX1010-LABEL: test_force_fp_kern_stack_and_call:		; GFX1010-LABEL: test_force_fp_kern_stack_and_call:
; GFX1010: ; %bb.0: ; %entry		; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s10, s10, s15		; GFX1010-NEXT: s_add_u32 s12, s12, s17
; GFX1010-NEXT: s_movk_i32 s32, 0x200		; GFX1010-NEXT: s_movk_i32 s32, 0x200
; GFX1010-NEXT: s_mov_b32 s33, 0		; GFX1010-NEXT: s_mov_b32 s33, 0
; GFX1010-NEXT: s_addc_u32 s11, s11, 0		; GFX1010-NEXT: s_addc_u32 s13, s13, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s10		; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s11		; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
; GFX1010-NEXT: v_mov_b32_e32 v0, 0		; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s15		; GFX1010-NEXT: s_add_u32 s0, s0, s17
; GFX1010-NEXT: s_addc_u32 s1, s1, 0		; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: s_getpc_b64 s[4:5]		; GFX1010-NEXT: s_getpc_b64 s[4:5]
; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4		; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12		; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4		; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0		; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5]		; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX1010-NEXT: s_endpgm		; GFX1010-NEXT: s_endpgm
▲ Show 20 Lines • Show All 85 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll

Show All 40 Lines	; GCN-NEXT: s_endpgm
%alloca = alloca i32, addrspace(5)		%alloca = alloca i32, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca		store volatile i32 0, i32 addrspace(5)* %alloca
ret void		ret void
}		}

define amdgpu_kernel void @kernel_calls_no_stack() {		define amdgpu_kernel void @kernel_calls_no_stack() {
; GCN-LABEL: kernel_calls_no_stack:		; GCN-LABEL: kernel_calls_no_stack:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: s_add_u32 s6, s6, s11		; GCN-NEXT: s_add_u32 s8, s8, s13
; GCN-NEXT: s_mov_b32 s32, 0		; GCN-NEXT: s_mov_b32 s32, 0
; GCN-NEXT: s_addc_u32 s7, s7, 0		; GCN-NEXT: s_addc_u32 s9, s9, 0
; GCN-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s6		; GCN-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s8
; GCN-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s7		; GCN-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s9
; GCN-NEXT: s_getpc_b64 s[0:1]		; GCN-NEXT: s_getpc_b64 s[0:1]
; GCN-NEXT: s_add_u32 s0, s0, extern_func@gotpcrel32@lo+4		; GCN-NEXT: s_add_u32 s0, s0, extern_func@gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s1, s1, extern_func@gotpcrel32@hi+12		; GCN-NEXT: s_addc_u32 s1, s1, extern_func@gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0		; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_swappc_b64 s[30:31], s[0:1]		; GCN-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GCN-NEXT: s_endpgm		; GCN-NEXT: s_endpgm
call void @extern_func()		call void @extern_func()
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llvm/test/CodeGen/AMDGPU/indirect-call.ll

	Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
	; GCN-NEXT: private_element_size = 1			; GCN-NEXT: private_element_size = 1
	; GCN-NEXT: is_ptr64 = 1			; GCN-NEXT: is_ptr64 = 1
	; GCN-NEXT: is_dynamic_callstack = 1			; GCN-NEXT: is_dynamic_callstack = 1
	; GCN-NEXT: is_debug_enabled = 0			; GCN-NEXT: is_debug_enabled = 0
	; GCN-NEXT: is_xnack_enabled = 0			; GCN-NEXT: is_xnack_enabled = 0
	; GCN-NEXT: workitem_private_segment_byte_size = 16384			; GCN-NEXT: workitem_private_segment_byte_size = 16384
	; GCN-NEXT: workgroup_group_segment_byte_size = 0			; GCN-NEXT: workgroup_group_segment_byte_size = 0
	; GCN-NEXT: gds_segment_byte_size = 0			; GCN-NEXT: gds_segment_byte_size = 0
	; GCN-NEXT: kernarg_segment_byte_size = 4			; GCN-NEXT: kernarg_segment_byte_size = 64
	; GCN-NEXT: workgroup_fbarrier_count = 0			; GCN-NEXT: workgroup_fbarrier_count = 0
	; GCN-NEXT: wavefront_sgpr_count = 37			; GCN-NEXT: wavefront_sgpr_count = 37
	; GCN-NEXT: workitem_vgpr_count = 32			; GCN-NEXT: workitem_vgpr_count = 32
	; GCN-NEXT: reserved_vgpr_first = 0			; GCN-NEXT: reserved_vgpr_first = 0
	; GCN-NEXT: reserved_vgpr_count = 0			; GCN-NEXT: reserved_vgpr_count = 0
	; GCN-NEXT: reserved_sgpr_first = 0			; GCN-NEXT: reserved_sgpr_first = 0
	; GCN-NEXT: reserved_sgpr_count = 0			; GCN-NEXT: reserved_sgpr_count = 0
	; GCN-NEXT: debug_wavefront_private_segment_offset_sgpr = 0			; GCN-NEXT: debug_wavefront_private_segment_offset_sgpr = 0
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	; GCN-NEXT: private_element_size = 1			; GCN-NEXT: private_element_size = 1
	; GCN-NEXT: is_ptr64 = 1			; GCN-NEXT: is_ptr64 = 1
	; GCN-NEXT: is_dynamic_callstack = 1			; GCN-NEXT: is_dynamic_callstack = 1
	; GCN-NEXT: is_debug_enabled = 0			; GCN-NEXT: is_debug_enabled = 0
	; GCN-NEXT: is_xnack_enabled = 0			; GCN-NEXT: is_xnack_enabled = 0
	; GCN-NEXT: workitem_private_segment_byte_size = 16384			; GCN-NEXT: workitem_private_segment_byte_size = 16384
	; GCN-NEXT: workgroup_group_segment_byte_size = 0			; GCN-NEXT: workgroup_group_segment_byte_size = 0
	; GCN-NEXT: gds_segment_byte_size = 0			; GCN-NEXT: gds_segment_byte_size = 0
	; GCN-NEXT: kernarg_segment_byte_size = 4			; GCN-NEXT: kernarg_segment_byte_size = 64
	; GCN-NEXT: workgroup_fbarrier_count = 0			; GCN-NEXT: workgroup_fbarrier_count = 0
	; GCN-NEXT: wavefront_sgpr_count = 37			; GCN-NEXT: wavefront_sgpr_count = 37
	; GCN-NEXT: workitem_vgpr_count = 32			; GCN-NEXT: workitem_vgpr_count = 32
	; GCN-NEXT: reserved_vgpr_first = 0			; GCN-NEXT: reserved_vgpr_first = 0
	; GCN-NEXT: reserved_vgpr_count = 0			; GCN-NEXT: reserved_vgpr_count = 0
	; GCN-NEXT: reserved_sgpr_first = 0			; GCN-NEXT: reserved_sgpr_first = 0
	; GCN-NEXT: reserved_sgpr_count = 0			; GCN-NEXT: reserved_sgpr_count = 0
	; GCN-NEXT: debug_wavefront_private_segment_offset_sgpr = 0			; GCN-NEXT: debug_wavefront_private_segment_offset_sgpr = 0
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll

	; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s \| FileCheck -check-prefixes=GCN,HSA %s			; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s \| FileCheck -check-prefixes=GCN,HSA %s
	; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s \| FileCheck -check-prefixes=GCN,MESA %s			; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s \| FileCheck -check-prefixes=GCN,MESA %s

	; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty:			; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty:
				; HSA: enable_sgpr_kernarg_segment_ptr = 1
				; HSA: kernarg_segment_byte_size = 56

				; MESA: enable_sgpr_kernarg_segment_ptr = 1
				; MESA: kernarg_segment_byte_size = 16

				; GCN: s_load_dword s0, s[4:5], 0x0
				define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 {
				%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
				%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
				%load = load volatile i32, i32 addrspace(4)* %cast
				ret void
				}

				; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty_0implicit:
	; HSA: enable_sgpr_kernarg_segment_ptr = 0			; HSA: enable_sgpr_kernarg_segment_ptr = 0
	; HSA: kernarg_segment_byte_size = 0			; HSA: kernarg_segment_byte_size = 0

	; MESA: enable_sgpr_kernarg_segment_ptr = 1			; MESA: enable_sgpr_kernarg_segment_ptr = 1
	; MESA: kernarg_segment_byte_size = 16			; MESA: kernarg_segment_byte_size = 16

	; HSA: s_mov_b64 [[NULL:s\[[0-9]+:[0-9]+\]]], 0{{$}}			; HSA: s_mov_b64 [[NULL:s\[[0-9]+:[0-9]+\]]], 0{{$}}
	; HSA: s_load_dword s0, [[NULL]], 0x0			; HSA: s_load_dword s0, [[NULL]], 0x0

	; MESA: s_load_dword s0, s[4:5], 0x0			; MESA: s_load_dword s0, s[4:5], 0x0
	define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 {			define amdgpu_kernel void @kernel_implicitarg_ptr_empty_0implicit() #3 {
	%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()			%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
	%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*			%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
	%load = load volatile i32, i32 addrspace(4)* %cast			%load = load volatile i32, i32 addrspace(4)* %cast
	ret void			ret void
	}			}

	; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr_empty:			; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr_empty:
	; GCN: enable_sgpr_kernarg_segment_ptr = 1			; GCN: enable_sgpr_kernarg_segment_ptr = 1

	; HSA: kernarg_segment_byte_size = 48			; HSA: kernarg_segment_byte_size = 48
	; MESA: kernarg_segment_byte_size = 16			; MESA: kernarg_segment_byte_size = 16

	; HSA: s_load_dword s0, s[4:5], 0x0			; HSA: s_load_dword s0, s[4:5], 0x0
	define amdgpu_kernel void @opencl_kernel_implicitarg_ptr_empty() #1 {			define amdgpu_kernel void @opencl_kernel_implicitarg_ptr_empty() #1 {
	%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()			%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
	%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*			%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
	%load = load volatile i32, i32 addrspace(4)* %cast			%load = load volatile i32, i32 addrspace(4)* %cast
	ret void			ret void
	}			}

	; GCN-LABEL: {{^}}kernel_implicitarg_ptr:			; GCN-LABEL: {{^}}kernel_implicitarg_ptr:
	; GCN: enable_sgpr_kernarg_segment_ptr = 1			; GCN: enable_sgpr_kernarg_segment_ptr = 1

	; HSA: kernarg_segment_byte_size = 112			; HSA: kernarg_segment_byte_size = 168
	; MESA: kernarg_segment_byte_size = 128			; MESA: kernarg_segment_byte_size = 128

	; HSA: s_load_dword s0, s[4:5], 0x1c			; HSA: s_load_dword s0, s[4:5], 0x1c
	define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 {			define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 {
	%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()			%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
	%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*			%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
	%load = load volatile i32, i32 addrspace(4)* %cast			%load = load volatile i32, i32 addrspace(4)* %cast
	ret void			ret void
	Show All 33 Lines
	define void @opencl_func_implicitarg_ptr() #0 {			define void @opencl_func_implicitarg_ptr() #0 {
	%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()			%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
	%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*			%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
	%load = load volatile i32, i32 addrspace(4)* %cast			%load = load volatile i32, i32 addrspace(4)* %cast
	ret void			ret void
	}			}

	; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty:			; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty:
				; HSA: enable_sgpr_kernarg_segment_ptr = 1
				; HSA: kernarg_segment_byte_size = 56

				; MESA: enable_sgpr_kernarg_segment_ptr = 1
				; MESA: kernarg_segment_byte_size = 16

				; GCN-NOT: s[4:5]
				; GCN-NOT: s4
				; GCN-NOT: s5
				; GCN: s_swappc_b64
				define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty() #0 {
				call void @func_implicitarg_ptr()
				ret void
				}

				; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty_implicit0:
	; HSA: enable_sgpr_kernarg_segment_ptr = 0			; HSA: enable_sgpr_kernarg_segment_ptr = 0
	; HSA: kernarg_segment_byte_size = 0			; HSA: kernarg_segment_byte_size = 0

	; MESA: enable_sgpr_kernarg_segment_ptr = 1			; MESA: enable_sgpr_kernarg_segment_ptr = 1
	; MESA: kernarg_segment_byte_size = 16			; MESA: kernarg_segment_byte_size = 16

	; HSA: s_mov_b64 s[4:5], 0{{$}}			; HSA: s_mov_b64 s[4:5], 0{{$}}
	; MESA-NOT: s[4:5]			; MESA-NOT: s[4:5]
	; MESA-NOT: s4			; MESA-NOT: s4
	; MESA-NOT: s5			; MESA-NOT: s5
	; GCN: s_swappc_b64			; GCN: s_swappc_b64
	define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty() #0 {			define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty_implicit0() #3 {
	call void @func_implicitarg_ptr()			call void @func_implicitarg_ptr()
	ret void			ret void
	}			}

	; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func_empty:			; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func_empty:
	; GCN: enable_sgpr_kernarg_segment_ptr = 1			; GCN: enable_sgpr_kernarg_segment_ptr = 1
	; HSA: kernarg_segment_byte_size = 48			; HSA: kernarg_segment_byte_size = 48
	; MESA: kernarg_segment_byte_size = 16			; MESA: kernarg_segment_byte_size = 16
	; GCN-NOT: s[4:5]			; GCN-NOT: s[4:5]
	; GCN-NOT: s4			; GCN-NOT: s4
	; GCN-NOT: s5			; GCN-NOT: s5
	; GCN: s_swappc_b64			; GCN: s_swappc_b64
	define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func_empty() #1 {			define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func_empty() #1 {
	call void @func_implicitarg_ptr()			call void @func_implicitarg_ptr()
	ret void			ret void
	}			}

	; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func:			; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func:
	; GCN: enable_sgpr_kernarg_segment_ptr = 1			; GCN: enable_sgpr_kernarg_segment_ptr = 1
	; HSA: kernarg_segment_byte_size = 112			; HSA: kernarg_segment_byte_size = 168
	; MESA: kernarg_segment_byte_size = 128			; MESA: kernarg_segment_byte_size = 128

	; HSA: s_add_u32 s4, s4, 0x70			; HSA: s_add_u32 s4, s4, 0x70
	; MESA: s_add_u32 s4, s4, 0x70			; MESA: s_add_u32 s4, s4, 0x70

	; GCN: s_addc_u32 s5, s5, 0{{$}}			; GCN: s_addc_u32 s5, s5, 0{{$}}
	; GCN: s_swappc_b64			; GCN: s_swappc_b64
	define amdgpu_kernel void @kernel_call_implicitarg_ptr_func([112 x i8]) #0 {			define amdgpu_kernel void @kernel_call_implicitarg_ptr_func([112 x i8]) #0 {
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	}			}

	declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #2			declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #2
	declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2			declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2

	attributes #0 = { nounwind noinline }			attributes #0 = { nounwind noinline }
	attributes #1 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="48" }			attributes #1 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="48" }
	attributes #2 = { nounwind readnone speculatable }			attributes #2 = { nounwind readnone speculatable }
				attributes #3 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="0" }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll

Show All 14 Lines	define amdgpu_kernel void @test(i32 addrspace(1)* %out) #1 {
%header.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*		%header.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
%gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10		%gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
%value = load i32, i32 addrspace(4)* %gep		%value = load i32, i32 addrspace(4)* %gep
store i32 %value, i32 addrspace(1)* %out		store i32 %value, i32 addrspace(1)* %out
ret void		ret void
}		}

; ALL-LABEL: {{^}}test_implicit:		; ALL-LABEL: {{^}}test_implicit:
; HSA: kernarg_segment_byte_size = 8		; HSA: kernarg_segment_byte_size = 64
; OS-MESA3D: kernarg_segment_byte_size = 24		; OS-MESA3D: kernarg_segment_byte_size = 24
; CO-V2: kernarg_segment_alignment = 4		; CO-V2: kernarg_segment_alignment = 4

; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x15		; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x15
; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0x15		; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0x15
define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 {		define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 {
%implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()		%implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%header.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*		%header.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
%gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10		%gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
%value = load i32, i32 addrspace(4)* %gep		%value = load i32, i32 addrspace(4)* %gep
store i32 %value, i32 addrspace(1)* %out		store i32 %value, i32 addrspace(1)* %out
ret void		ret void
}		}

; ALL-LABEL: {{^}}test_implicit_alignment:		; ALL-LABEL: {{^}}test_implicit_alignment:
; HSA: kernarg_segment_byte_size = 12		; HSA: kernarg_segment_byte_size = 72
; OS-MESA3D: kernarg_segment_byte_size = 28		; OS-MESA3D: kernarg_segment_byte_size = 28
; CO-V2: kernarg_segment_alignment = 4		; CO-V2: kernarg_segment_alignment = 4


; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc		; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4		; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3		; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]		; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
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llvm/test/CodeGen/AMDGPU/lower-kernargs.ll

Show All 11 Lines
; MESA-LABEL: @kern_noargs(		; MESA-LABEL: @kern_noargs(
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
ret void		ret void
}		}

define amdgpu_kernel void @kern_i8(i8 %arg) #0 {		define amdgpu_kernel void @kern_i8(i8 %arg) #0 {
; HSA-LABEL: @kern_i8(		; HSA-LABEL: @kern_i8(
; HSA-NEXT: [[KERN_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; HSA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_i8(		; MESA-LABEL: @kern_i8(
; MESA-NEXT: [[KERN_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; MESA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; MESA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i8 %arg, i8 addrspace(1)* undef, align 1		store i8 %arg, i8 addrspace(1)* undef, align 1
ret void		ret void
}		}

define amdgpu_kernel void @kern_i16(i16 %arg) #0 {		define amdgpu_kernel void @kern_i16(i16 %arg) #0 {
; HSA-LABEL: @kern_i16(		; HSA-LABEL: @kern_i16(
; HSA-NEXT: [[KERN_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I16_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I16_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; HSA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1		; HSA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_i16(		; MESA-LABEL: @kern_i16(
; MESA-NEXT: [[KERN_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I16_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I16_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; MESA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1		; MESA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i16 %arg, i16 addrspace(1)* undef, align 1		store i16 %arg, i16 addrspace(1)* undef, align 1
ret void		ret void
}		}

define amdgpu_kernel void @kern_f16(half %arg) #0 {		define amdgpu_kernel void @kern_f16(half %arg) #0 {
; HSA-LABEL: @kern_f16(		; HSA-LABEL: @kern_f16(
; HSA-NEXT: [[KERN_F16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_F16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_F16_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_F16_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; HSA-NEXT: [[ARG_LOAD:%.*]] = bitcast i16 [[TMP2]] to half		; HSA-NEXT: [[ARG_LOAD:%.*]] = bitcast i16 [[TMP2]] to half
; HSA-NEXT: store half [[ARG_LOAD]], half addrspace(1)* undef, align 1		; HSA-NEXT: store half [[ARG_LOAD]], half addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_f16(		; MESA-LABEL: @kern_f16(
; MESA-NEXT: [[KERN_F16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_F16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_F16_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_F16_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; MESA-NEXT: [[ARG_LOAD:%.*]] = bitcast i16 [[TMP2]] to half		; MESA-NEXT: [[ARG_LOAD:%.*]] = bitcast i16 [[TMP2]] to half
; MESA-NEXT: store half [[ARG_LOAD]], half addrspace(1)* undef, align 1		; MESA-NEXT: store half [[ARG_LOAD]], half addrspace(1)* undef, align 1
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store half %arg, half addrspace(1)* undef, align 1		store half %arg, half addrspace(1)* undef, align 1
ret void		ret void
}		}

define amdgpu_kernel void @kern_zeroext_i8(i8 zeroext %arg) #0 {		define amdgpu_kernel void @kern_zeroext_i8(i8 zeroext %arg) #0 {
; HSA-LABEL: @kern_zeroext_i8(		; HSA-LABEL: @kern_zeroext_i8(
; HSA-NEXT: [[KERN_ZEROEXT_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_ZEROEXT_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_ZEROEXT_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_ZEROEXT_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; HSA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_zeroext_i8(		; MESA-LABEL: @kern_zeroext_i8(
; MESA-NEXT: [[KERN_ZEROEXT_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_ZEROEXT_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_ZEROEXT_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_ZEROEXT_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; MESA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; MESA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i8 %arg, i8 addrspace(1)* undef, align 1		store i8 %arg, i8 addrspace(1)* undef, align 1
ret void		ret void
}		}

define amdgpu_kernel void @kern_zeroext_i16(i16 zeroext %arg) #0 {		define amdgpu_kernel void @kern_zeroext_i16(i16 zeroext %arg) #0 {
; HSA-LABEL: @kern_zeroext_i16(		; HSA-LABEL: @kern_zeroext_i16(
; HSA-NEXT: [[KERN_ZEROEXT_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_ZEROEXT_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_ZEROEXT_I16_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_ZEROEXT_I16_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; HSA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1		; HSA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_zeroext_i16(		; MESA-LABEL: @kern_zeroext_i16(
; MESA-NEXT: [[KERN_ZEROEXT_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_ZEROEXT_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_ZEROEXT_I16_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_ZEROEXT_I16_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; MESA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1		; MESA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i16 %arg, i16 addrspace(1)* undef, align 1		store i16 %arg, i16 addrspace(1)* undef, align 1
ret void		ret void
}		}

define amdgpu_kernel void @kern_signext_i8(i8 signext %arg) #0 {		define amdgpu_kernel void @kern_signext_i8(i8 signext %arg) #0 {
; HSA-LABEL: @kern_signext_i8(		; HSA-LABEL: @kern_signext_i8(
; HSA-NEXT: [[KERN_SIGNEXT_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_SIGNEXT_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_SIGNEXT_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_SIGNEXT_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; HSA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_signext_i8(		; MESA-LABEL: @kern_signext_i8(
; MESA-NEXT: [[KERN_SIGNEXT_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_SIGNEXT_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_SIGNEXT_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_SIGNEXT_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; MESA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; MESA-NEXT: store i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i8 %arg, i8 addrspace(1)* undef, align 1		store i8 %arg, i8 addrspace(1)* undef, align 1
ret void		ret void
}		}

define amdgpu_kernel void @kern_signext_i16(i16 signext %arg) #0 {		define amdgpu_kernel void @kern_signext_i16(i16 signext %arg) #0 {
; HSA-LABEL: @kern_signext_i16(		; HSA-LABEL: @kern_signext_i16(
; HSA-NEXT: [[KERN_SIGNEXT_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_SIGNEXT_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_SIGNEXT_I16_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_SIGNEXT_I16_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; HSA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1		; HSA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_signext_i16(		; MESA-LABEL: @kern_signext_i16(
; MESA-NEXT: [[KERN_SIGNEXT_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_SIGNEXT_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_SIGNEXT_I16_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_SIGNEXT_I16_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; MESA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1		; MESA-NEXT: store i16 [[TMP2]], i16 addrspace(1)* undef, align 1
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i16 %arg, i16 addrspace(1)* undef, align 1		store i16 %arg, i16 addrspace(1)* undef, align 1
ret void		ret void
}		}

define amdgpu_kernel void @kern_i8_i8(i8 %arg0, i8 %arg1) {		define amdgpu_kernel void @kern_i8_i8(i8 %arg0, i8 %arg1) {
; HSA-LABEL: @kern_i8_i8(		; HSA-LABEL: @kern_i8_i8(
; HSA-NEXT: [[KERN_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8		; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
; HSA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i8 [[TMP5]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP5]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_i8_i8(		; MESA-LABEL: @kern_i8_i8(
; MESA-NEXT: [[KERN_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8		; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
; MESA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; MESA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; MESA-NEXT: store volatile i8 [[TMP5]], i8 addrspace(1)* undef, align 1		; MESA-NEXT: store volatile i8 [[TMP5]], i8 addrspace(1)* undef, align 1
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i8 %arg0, i8 addrspace(1)* undef, align 1		store volatile i8 %arg0, i8 addrspace(1)* undef, align 1
store volatile i8 %arg1, i8 addrspace(1)* undef, align 1		store volatile i8 %arg1, i8 addrspace(1)* undef, align 1
ret void		ret void
}		}

define amdgpu_kernel void @kern_v3i8(<3 x i8> %arg) {		define amdgpu_kernel void @kern_v3i8(<3 x i8> %arg) {
; HSA-LABEL: @kern_v3i8(		; HSA-LABEL: @kern_v3i8(
; HSA-NEXT: [[KERN_V3I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_V3I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V3I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V3I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24
; HSA-NEXT: [[ARG_LOAD:%.*]] = bitcast i24 [[TMP2]] to <3 x i8>		; HSA-NEXT: [[ARG_LOAD:%.*]] = bitcast i24 [[TMP2]] to <3 x i8>
; HSA-NEXT: store <3 x i8> [[ARG_LOAD]], <3 x i8> addrspace(1)* undef, align 4		; HSA-NEXT: store <3 x i8> [[ARG_LOAD]], <3 x i8> addrspace(1)* undef, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_v3i8(		; MESA-LABEL: @kern_v3i8(
; MESA-NEXT: [[KERN_V3I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_V3I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V3I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V3I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24
; MESA-NEXT: [[ARG_LOAD:%.*]] = bitcast i24 [[TMP2]] to <3 x i8>		; MESA-NEXT: [[ARG_LOAD:%.*]] = bitcast i24 [[TMP2]] to <3 x i8>
; MESA-NEXT: store <3 x i8> [[ARG_LOAD]], <3 x i8> addrspace(1)* undef, align 4		; MESA-NEXT: store <3 x i8> [[ARG_LOAD]], <3 x i8> addrspace(1)* undef, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store <3 x i8> %arg, <3 x i8> addrspace(1)* undef, align 4		store <3 x i8> %arg, <3 x i8> addrspace(1)* undef, align 4
ret void		ret void
}		}

define amdgpu_kernel void @kern_i24(i24 %arg0) {		define amdgpu_kernel void @kern_i24(i24 %arg0) {
; HSA-LABEL: @kern_i24(		; HSA-LABEL: @kern_i24(
; HSA-NEXT: [[KERN_I24_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_I24_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I24_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I24_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24
; HSA-NEXT: store i24 [[TMP2]], i24 addrspace(1)* undef, align 4		; HSA-NEXT: store i24 [[TMP2]], i24 addrspace(1)* undef, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_i24(		; MESA-LABEL: @kern_i24(
; MESA-NEXT: [[KERN_I24_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_I24_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I24_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I24_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24
; MESA-NEXT: store i24 [[TMP2]], i24 addrspace(1)* undef, align 4		; MESA-NEXT: store i24 [[TMP2]], i24 addrspace(1)* undef, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i24 %arg0, i24 addrspace(1)* undef		store i24 %arg0, i24 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_i32(i32 %arg0) {		define amdgpu_kernel void @kern_i32(i32 %arg0) {
; HSA-LABEL: @kern_i32(		; HSA-LABEL: @kern_i32(
; HSA-NEXT: [[KERN_I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I32_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I32_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[ARG0_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[ARG0_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: store i32 [[ARG0_LOAD]], i32 addrspace(1)* undef, align 4		; HSA-NEXT: store i32 [[ARG0_LOAD]], i32 addrspace(1)* undef, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_i32(		; MESA-LABEL: @kern_i32(
; MESA-NEXT: [[KERN_I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I32_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I32_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[ARG0_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[ARG0_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: store i32 [[ARG0_LOAD]], i32 addrspace(1)* undef, align 4		; MESA-NEXT: store i32 [[ARG0_LOAD]], i32 addrspace(1)* undef, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i32 %arg0, i32 addrspace(1)* undef		store i32 %arg0, i32 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_f32(float %arg0) {		define amdgpu_kernel void @kern_f32(float %arg0) {
; HSA-LABEL: @kern_f32(		; HSA-LABEL: @kern_f32(
; HSA-NEXT: [[KERN_F32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_F32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_F32_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_F32_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to float addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to float addrspace(4)*
; HSA-NEXT: [[ARG0_LOAD:%.]] = load float, float addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[ARG0_LOAD:%.]] = load float, float addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: store float [[ARG0_LOAD]], float addrspace(1)* undef, align 4		; HSA-NEXT: store float [[ARG0_LOAD]], float addrspace(1)* undef, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_f32(		; MESA-LABEL: @kern_f32(
; MESA-NEXT: [[KERN_F32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_F32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_F32_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_F32_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to float addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to float addrspace(4)*
; MESA-NEXT: [[ARG0_LOAD:%.]] = load float, float addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[ARG0_LOAD:%.]] = load float, float addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: store float [[ARG0_LOAD]], float addrspace(1)* undef, align 4		; MESA-NEXT: store float [[ARG0_LOAD]], float addrspace(1)* undef, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store float %arg0, float addrspace(1)* undef		store float %arg0, float addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_v3i32(<3 x i32> %arg0) {		define amdgpu_kernel void @kern_v3i32(<3 x i32> %arg0) {
; HSA-LABEL: @kern_v3i32(		; HSA-LABEL: @kern_v3i32(
; HSA-NEXT: [[KERN_V3I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(16) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_V3I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V3I32_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V3I32_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to <4 x i32> addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to <4 x i32> addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load <4 x i32>, <4 x i32> addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load <4 x i32>, <4 x i32> addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[ARG0_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>		; HSA-NEXT: [[ARG0_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
; HSA-NEXT: store <3 x i32> [[ARG0_LOAD]], <3 x i32> addrspace(1)* undef, align 4		; HSA-NEXT: store <3 x i32> [[ARG0_LOAD]], <3 x i32> addrspace(1)* undef, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_v3i32(		; MESA-LABEL: @kern_v3i32(
; MESA-NEXT: [[KERN_V3I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(52) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_V3I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V3I32_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V3I32_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to <4 x i32> addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to <4 x i32> addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load <4 x i32>, <4 x i32> addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load <4 x i32>, <4 x i32> addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[ARG0_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>		; MESA-NEXT: [[ARG0_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
; MESA-NEXT: store <3 x i32> [[ARG0_LOAD]], <3 x i32> addrspace(1)* undef, align 4		; MESA-NEXT: store <3 x i32> [[ARG0_LOAD]], <3 x i32> addrspace(1)* undef, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store <3 x i32> %arg0, <3 x i32> addrspace(1)* undef, align 4		store <3 x i32> %arg0, <3 x i32> addrspace(1)* undef, align 4
ret void		ret void
}		}

define amdgpu_kernel void @kern_v8i32(<8 x i32> %arg) #0 {		define amdgpu_kernel void @kern_v8i32(<8 x i32> %arg) #0 {
; HSA-LABEL: @kern_v8i32(		; HSA-LABEL: @kern_v8i32(
; HSA-NEXT: [[KERN_V8I32_KERNARG_SEGMENT:%.]] = call nonnull align 32 dereferenceable(32) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_V8I32_KERNARG_SEGMENT:%.]] = call nonnull align 32 dereferenceable(88) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V8I32_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V8I32_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET]] to <8 x i32> addrspace(4)*		; HSA-NEXT: [[ARG_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET]] to <8 x i32> addrspace(4)*
; HSA-NEXT: [[ARG_LOAD:%.]] = load <8 x i32>, <8 x i32> addrspace(4) [[ARG_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[ARG_LOAD:%.]] = load <8 x i32>, <8 x i32> addrspace(4) [[ARG_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: store <8 x i32> [[ARG_LOAD]], <8 x i32> addrspace(1)* undef, align 32		; HSA-NEXT: store <8 x i32> [[ARG_LOAD]], <8 x i32> addrspace(1)* undef, align 32
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_v8i32(		; MESA-LABEL: @kern_v8i32(
; MESA-NEXT: [[KERN_V8I32_KERNARG_SEGMENT:%.]] = call nonnull align 32 dereferenceable(68) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_V8I32_KERNARG_SEGMENT:%.]] = call nonnull align 32 dereferenceable(88) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V8I32_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V8I32_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET]] to <8 x i32> addrspace(4)*		; MESA-NEXT: [[ARG_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET]] to <8 x i32> addrspace(4)*
; MESA-NEXT: [[ARG_LOAD:%.]] = load <8 x i32>, <8 x i32> addrspace(4) [[ARG_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[ARG_LOAD:%.]] = load <8 x i32>, <8 x i32> addrspace(4) [[ARG_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: store <8 x i32> [[ARG_LOAD]], <8 x i32> addrspace(1)* undef, align 32		; MESA-NEXT: store <8 x i32> [[ARG_LOAD]], <8 x i32> addrspace(1)* undef, align 32
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store <8 x i32> %arg, <8 x i32> addrspace(1)* undef		store <8 x i32> %arg, <8 x i32> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_v8i64(<8 x i64> %arg) #0 {		define amdgpu_kernel void @kern_v8i64(<8 x i64> %arg) #0 {
; HSA-LABEL: @kern_v8i64(		; HSA-LABEL: @kern_v8i64(
; HSA-NEXT: [[KERN_V8I64_KERNARG_SEGMENT:%.]] = call nonnull align 64 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_V8I64_KERNARG_SEGMENT:%.]] = call nonnull align 64 dereferenceable(120) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V8I64_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V8I64_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET]] to <8 x i64> addrspace(4)*		; HSA-NEXT: [[ARG_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET]] to <8 x i64> addrspace(4)*
; HSA-NEXT: [[ARG_LOAD:%.]] = load <8 x i64>, <8 x i64> addrspace(4) [[ARG_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[ARG_LOAD:%.]] = load <8 x i64>, <8 x i64> addrspace(4) [[ARG_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: store <8 x i64> [[ARG_LOAD]], <8 x i64> addrspace(1)* undef, align 64		; HSA-NEXT: store <8 x i64> [[ARG_LOAD]], <8 x i64> addrspace(1)* undef, align 64
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_v8i64(		; MESA-LABEL: @kern_v8i64(
; MESA-NEXT: [[KERN_V8I64_KERNARG_SEGMENT:%.]] = call nonnull align 64 dereferenceable(100) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_V8I64_KERNARG_SEGMENT:%.]] = call nonnull align 64 dereferenceable(120) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V8I64_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V8I64_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET]] to <8 x i64> addrspace(4)*		; MESA-NEXT: [[ARG_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET]] to <8 x i64> addrspace(4)*
; MESA-NEXT: [[ARG_LOAD:%.]] = load <8 x i64>, <8 x i64> addrspace(4) [[ARG_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[ARG_LOAD:%.]] = load <8 x i64>, <8 x i64> addrspace(4) [[ARG_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: store <8 x i64> [[ARG_LOAD]], <8 x i64> addrspace(1)* undef, align 64		; MESA-NEXT: store <8 x i64> [[ARG_LOAD]], <8 x i64> addrspace(1)* undef, align 64
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store <8 x i64> %arg, <8 x i64> addrspace(1)* undef		store <8 x i64> %arg, <8 x i64> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_v16i64(<16 x i64> %arg) #0 {		define amdgpu_kernel void @kern_v16i64(<16 x i64> %arg) #0 {
; HSA-LABEL: @kern_v16i64(		; HSA-LABEL: @kern_v16i64(
; HSA-NEXT: [[KERN_V16I64_KERNARG_SEGMENT:%.]] = call nonnull align 128 dereferenceable(128) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_V16I64_KERNARG_SEGMENT:%.]] = call nonnull align 128 dereferenceable(184) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V16I64_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V16I64_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET]] to <16 x i64> addrspace(4)*		; HSA-NEXT: [[ARG_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET]] to <16 x i64> addrspace(4)*
; HSA-NEXT: [[ARG_LOAD:%.]] = load <16 x i64>, <16 x i64> addrspace(4) [[ARG_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[ARG_LOAD:%.]] = load <16 x i64>, <16 x i64> addrspace(4) [[ARG_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: store <16 x i64> [[ARG_LOAD]], <16 x i64> addrspace(1)* undef, align 128		; HSA-NEXT: store <16 x i64> [[ARG_LOAD]], <16 x i64> addrspace(1)* undef, align 128
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_v16i64(		; MESA-LABEL: @kern_v16i64(
; MESA-NEXT: [[KERN_V16I64_KERNARG_SEGMENT:%.]] = call nonnull align 128 dereferenceable(164) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_V16I64_KERNARG_SEGMENT:%.]] = call nonnull align 128 dereferenceable(184) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V16I64_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_V16I64_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET]] to <16 x i64> addrspace(4)*		; MESA-NEXT: [[ARG_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG_KERNARG_OFFSET]] to <16 x i64> addrspace(4)*
; MESA-NEXT: [[ARG_LOAD:%.]] = load <16 x i64>, <16 x i64> addrspace(4) [[ARG_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[ARG_LOAD:%.]] = load <16 x i64>, <16 x i64> addrspace(4) [[ARG_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: store <16 x i64> [[ARG_LOAD]], <16 x i64> addrspace(1)* undef, align 128		; MESA-NEXT: store <16 x i64> [[ARG_LOAD]], <16 x i64> addrspace(1)* undef, align 128
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store <16 x i64> %arg, <16 x i64> addrspace(1)* undef		store <16 x i64> %arg, <16 x i64> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_i32_v3i32(i32 %arg0, <3 x i32> %arg1) {		define amdgpu_kernel void @kern_i32_v3i32(i32 %arg0, <3 x i32> %arg1) {
; HSA-LABEL: @kern_i32_v3i32(		; HSA-LABEL: @kern_i32_v3i32(
; HSA-NEXT: [[KERN_I32_V3I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(32) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_I32_V3I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(88) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[ARG0_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[ARG0_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 16		; HSA-NEXT: [[ARG1_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 16
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET]] to <4 x i32> addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET]] to <4 x i32> addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load <4 x i32>, <4 x i32> addrspace(4) [[ARG1_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load <4 x i32>, <4 x i32> addrspace(4) [[ARG1_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[ARG1_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>		; HSA-NEXT: [[ARG1_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
; HSA-NEXT: store i32 [[ARG0_LOAD]], i32 addrspace(1)* undef, align 4		; HSA-NEXT: store i32 [[ARG0_LOAD]], i32 addrspace(1)* undef, align 4
; HSA-NEXT: store <3 x i32> [[ARG1_LOAD]], <3 x i32> addrspace(1)* undef, align 4		; HSA-NEXT: store <3 x i32> [[ARG1_LOAD]], <3 x i32> addrspace(1)* undef, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_i32_v3i32(		; MESA-LABEL: @kern_i32_v3i32(
; MESA-NEXT: [[KERN_I32_V3I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(68) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_I32_V3I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(88) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[ARG0_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[ARG0_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[ARG1_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 52		; MESA-NEXT: [[ARG1_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 52
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET]] to <4 x i32> addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET]] to <4 x i32> addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load <4 x i32>, <4 x i32> addrspace(4) [[ARG1_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load <4 x i32>, <4 x i32> addrspace(4) [[ARG1_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[ARG1_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>		; MESA-NEXT: [[ARG1_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
; MESA-NEXT: store i32 [[ARG0_LOAD]], i32 addrspace(1)* undef, align 4		; MESA-NEXT: store i32 [[ARG0_LOAD]], i32 addrspace(1)* undef, align 4
; MESA-NEXT: store <3 x i32> [[ARG1_LOAD]], <3 x i32> addrspace(1)* undef, align 4		; MESA-NEXT: store <3 x i32> [[ARG1_LOAD]], <3 x i32> addrspace(1)* undef, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i32 %arg0, i32 addrspace(1)* undef		store i32 %arg0, i32 addrspace(1)* undef
store <3 x i32> %arg1, <3 x i32> addrspace(1)* undef, align 4		store <3 x i32> %arg1, <3 x i32> addrspace(1)* undef, align 4
ret void		ret void
}		}

%struct.a = type { i32, i8, [4 x i8] }		%struct.a = type { i32, i8, [4 x i8] }
%struct.b.packed = type { i8, i32, [3 x i16], <2 x double> }		%struct.b.packed = type { i8, i32, [3 x i16], <2 x double> }

define amdgpu_kernel void @kern_struct_a(%struct.a %arg0) {		define amdgpu_kernel void @kern_struct_a(%struct.a %arg0) {
; HSA-LABEL: @kern_struct_a(		; HSA-LABEL: @kern_struct_a(
; HSA-NEXT: [[KERN_STRUCT_A_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(12) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_STRUCT_A_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_STRUCT_A_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_STRUCT_A_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to [[STRUCT_A:%.]] addrspace(4)		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to [[STRUCT_A:%.]] addrspace(4)
; HSA-NEXT: [[ARG0_LOAD:%.]] = load [[STRUCT_A]], [[STRUCT_A]] addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[ARG0_LOAD:%.]] = load [[STRUCT_A]], [[STRUCT_A]] addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: store [[STRUCT_A]] [[ARG0_LOAD]], [[STRUCT_A]] addrspace(1)* undef, align 4		; HSA-NEXT: store [[STRUCT_A]] [[ARG0_LOAD]], [[STRUCT_A]] addrspace(1)* undef, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_struct_a(		; MESA-LABEL: @kern_struct_a(
; MESA-NEXT: [[KERN_STRUCT_A_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(48) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_STRUCT_A_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(68) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_STRUCT_A_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_STRUCT_A_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to [[STRUCT_A:%.]] addrspace(4)		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to [[STRUCT_A:%.]] addrspace(4)
; MESA-NEXT: [[ARG0_LOAD:%.]] = load [[STRUCT_A]], [[STRUCT_A]] addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[ARG0_LOAD:%.]] = load [[STRUCT_A]], [[STRUCT_A]] addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: store [[STRUCT_A]] [[ARG0_LOAD]], [[STRUCT_A]] addrspace(1)* undef, align 4		; MESA-NEXT: store [[STRUCT_A]] [[ARG0_LOAD]], [[STRUCT_A]] addrspace(1)* undef, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store %struct.a %arg0, %struct.a addrspace(1)* undef		store %struct.a %arg0, %struct.a addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_struct_b_packed(%struct.b.packed %arg0) #0 {		define amdgpu_kernel void @kern_struct_b_packed(%struct.b.packed %arg0) #0 {
; HSA-LABEL: @kern_struct_b_packed(		; HSA-LABEL: @kern_struct_b_packed(
; HSA-NEXT: [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(32) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(88) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to [[STRUCT_B_PACKED:%.]] addrspace(4)		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to [[STRUCT_B_PACKED:%.]] addrspace(4)
; HSA-NEXT: [[ARG0_LOAD:%.]] = load [[STRUCT_B_PACKED]], [[STRUCT_B_PACKED]] addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[ARG0_LOAD:%.]] = load [[STRUCT_B_PACKED]], [[STRUCT_B_PACKED]] addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: store [[STRUCT_B_PACKED]] [[ARG0_LOAD]], [[STRUCT_B_PACKED]] addrspace(1)* undef, align 16		; HSA-NEXT: store [[STRUCT_B_PACKED]] [[ARG0_LOAD]], [[STRUCT_B_PACKED]] addrspace(1)* undef, align 16
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_struct_b_packed(		; MESA-LABEL: @kern_struct_b_packed(
; MESA-NEXT: [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(68) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(88) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to [[STRUCT_B_PACKED:%.]] addrspace(4)		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to [[STRUCT_B_PACKED:%.]] addrspace(4)
; MESA-NEXT: [[ARG0_LOAD:%.]] = load [[STRUCT_B_PACKED]], [[STRUCT_B_PACKED]] addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[ARG0_LOAD:%.]] = load [[STRUCT_B_PACKED]], [[STRUCT_B_PACKED]] addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: store [[STRUCT_B_PACKED]] [[ARG0_LOAD]], [[STRUCT_B_PACKED]] addrspace(1)* undef, align 16		; MESA-NEXT: store [[STRUCT_B_PACKED]] [[ARG0_LOAD]], [[STRUCT_B_PACKED]] addrspace(1)* undef, align 16
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store %struct.b.packed %arg0, %struct.b.packed addrspace(1)* undef		store %struct.b.packed %arg0, %struct.b.packed addrspace(1)* undef
ret void		ret void
Show All 38 Lines
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i32 %arg1, i32 addrspace(1)* undef		store i32 %arg1, i32 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_lds_ptr(i32 addrspace(3)* %lds) #0 {		define amdgpu_kernel void @kern_lds_ptr(i32 addrspace(3)* %lds) #0 {
; HSA-LABEL: @kern_lds_ptr(		; HSA-LABEL: @kern_lds_ptr(
; HSA-NEXT: [[KERN_LDS_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(8) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_LDS_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[LDS_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_LDS_PTR_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[LDS_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_LDS_PTR_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[LDS_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[LDS_KERNARG_OFFSET]] to i32 addrspace(3)* addrspace(4)*		; HSA-NEXT: [[LDS_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[LDS_KERNARG_OFFSET]] to i32 addrspace(3)* addrspace(4)*
; HSA-NEXT: [[LDS_LOAD:%.]] = load i32 addrspace(3), i32 addrspace(3)* addrspace(4)* [[LDS_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[LDS_LOAD:%.]] = load i32 addrspace(3), i32 addrspace(3)* addrspace(4)* [[LDS_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: store i32 0, i32 addrspace(3)* [[LDS_LOAD]], align 4		; HSA-NEXT: store i32 0, i32 addrspace(3)* [[LDS_LOAD]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_lds_ptr(		; MESA-LABEL: @kern_lds_ptr(
; MESA-NEXT: [[KERN_LDS_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_LDS_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[LDS_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_LDS_PTR_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[LDS_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_LDS_PTR_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[LDS_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[LDS_KERNARG_OFFSET]] to i32 addrspace(3)* addrspace(4)*		; MESA-NEXT: [[LDS_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[LDS_KERNARG_OFFSET]] to i32 addrspace(3)* addrspace(4)*
; MESA-NEXT: [[LDS_LOAD:%.]] = load i32 addrspace(3), i32 addrspace(3)* addrspace(4)* [[LDS_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[LDS_LOAD:%.]] = load i32 addrspace(3), i32 addrspace(3)* addrspace(4)* [[LDS_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: store i32 0, i32 addrspace(3)* [[LDS_LOAD]], align 4		; MESA-NEXT: store i32 0, i32 addrspace(3)* [[LDS_LOAD]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i32 0, i32 addrspace(3)* %lds, align 4		store i32 0, i32 addrspace(3)* %lds, align 4
ret void		ret void
}		}

define amdgpu_kernel void @kern_lds_ptr_si(i32 addrspace(3)* %lds) #2 {		define amdgpu_kernel void @kern_lds_ptr_si(i32 addrspace(3)* %lds) #2 {
; HSA-LABEL: @kern_lds_ptr_si(		; HSA-LABEL: @kern_lds_ptr_si(
; HSA-NEXT: [[KERN_LDS_PTR_SI_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(8) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_LDS_PTR_SI_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: store i32 0, i32 addrspace(3)* [[LDS:%.*]], align 4		; HSA-NEXT: store i32 0, i32 addrspace(3)* [[LDS:%.*]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_lds_ptr_si(		; MESA-LABEL: @kern_lds_ptr_si(
; MESA-NEXT: [[KERN_LDS_PTR_SI_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_LDS_PTR_SI_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: store i32 0, i32 addrspace(3)* [[LDS:%.*]], align 4		; MESA-NEXT: store i32 0, i32 addrspace(3)* [[LDS:%.*]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i32 0, i32 addrspace(3)* %lds, align 4		store i32 0, i32 addrspace(3)* %lds, align 4
ret void		ret void
}		}

define amdgpu_kernel void @kern_realign_i8_i8(i8 %arg0, i8 %arg1) #0 {		define amdgpu_kernel void @kern_realign_i8_i8(i8 %arg0, i8 %arg1) #0 {
; HSA-LABEL: @kern_realign_i8_i8(		; HSA-LABEL: @kern_realign_i8_i8(
; HSA-NEXT: [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8		; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
; HSA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i8 [[TMP5]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP5]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_realign_i8_i8(		; MESA-LABEL: @kern_realign_i8_i8(
; MESA-NEXT: [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8		; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
; MESA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; MESA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; MESA-NEXT: store volatile i8 [[TMP5]], i8 addrspace(1)* undef, align 1		; MESA-NEXT: store volatile i8 [[TMP5]], i8 addrspace(1)* undef, align 1
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i8 %arg0, i8 addrspace(1)* undef		store volatile i8 %arg0, i8 addrspace(1)* undef
store volatile i8 %arg1, i8 addrspace(1)* undef		store volatile i8 %arg1, i8 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_realign_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2) #0 {		define amdgpu_kernel void @kern_realign_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2) #0 {
; HSA-LABEL: @kern_realign_i8_i8_i8(		; HSA-LABEL: @kern_realign_i8_i8_i8(
; HSA-NEXT: [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8		; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
; HSA-NEXT: [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG2_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG2_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP6:%.]] = load i32, i32 addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP6:%.]] = load i32, i32 addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP7:%.*]] = lshr i32 [[TMP6]], 16		; HSA-NEXT: [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
; HSA-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8		; HSA-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8
; HSA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i8 [[TMP5]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP5]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i8 [[TMP8]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP8]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_realign_i8_i8_i8(		; MESA-LABEL: @kern_realign_i8_i8_i8(
; MESA-NEXT: [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
Show All 11 Lines	;
store volatile i8 %arg0, i8 addrspace(1)* undef		store volatile i8 %arg0, i8 addrspace(1)* undef
store volatile i8 %arg1, i8 addrspace(1)* undef		store volatile i8 %arg1, i8 addrspace(1)* undef
store volatile i8 %arg2, i8 addrspace(1)* undef		store volatile i8 %arg2, i8 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_realign_i8_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3) #0 {		define amdgpu_kernel void @kern_realign_i8_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3) #0 {
; HSA-LABEL: @kern_realign_i8_i8_i8_i8(		; HSA-LABEL: @kern_realign_i8_i8_i8_i8(
; HSA-NEXT: [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
Show All 10 Lines
; HSA-NEXT: [[TMP11:%.*]] = trunc i32 [[TMP10]] to i8		; HSA-NEXT: [[TMP11:%.*]] = trunc i32 [[TMP10]] to i8
; HSA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i8 [[TMP5]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP5]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i8 [[TMP8]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP8]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i8 [[TMP11]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP11]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_realign_i8_i8_i8_i8(		; MESA-LABEL: @kern_realign_i8_i8_i8_i8(
; MESA-NEXT: [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
Show All 18 Lines	;
store volatile i8 %arg1, i8 addrspace(1)* undef		store volatile i8 %arg1, i8 addrspace(1)* undef
store volatile i8 %arg2, i8 addrspace(1)* undef		store volatile i8 %arg2, i8 addrspace(1)* undef
store volatile i8 %arg3, i8 addrspace(1)* undef		store volatile i8 %arg3, i8 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_realign_i8_v3i8(i8 %arg0, <3 x i8> %arg1) #0 {		define amdgpu_kernel void @kern_realign_i8_v3i8(i8 %arg0, <3 x i8> %arg1) #0 {
; HSA-LABEL: @kern_realign_i8_v3i8(		; HSA-LABEL: @kern_realign_i8_v3i8(
; HSA-NEXT: [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(8) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 4		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 4
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i24		; HSA-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i24
; HSA-NEXT: [[ARG1_LOAD:%.*]] = bitcast i24 [[TMP4]] to <3 x i8>		; HSA-NEXT: [[ARG1_LOAD:%.*]] = bitcast i24 [[TMP4]] to <3 x i8>
; HSA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile <3 x i8> [[ARG1_LOAD]], <3 x i8> addrspace(1)* undef, align 4		; HSA-NEXT: store volatile <3 x i8> [[ARG1_LOAD]], <3 x i8> addrspace(1)* undef, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_realign_i8_v3i8(		; MESA-LABEL: @kern_realign_i8_v3i8(
; MESA-NEXT: [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 40		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 40
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 8, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 8, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i24		; MESA-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i24
; MESA-NEXT: [[ARG1_LOAD:%.*]] = bitcast i24 [[TMP4]] to <3 x i8>		; MESA-NEXT: [[ARG1_LOAD:%.*]] = bitcast i24 [[TMP4]] to <3 x i8>
; MESA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; MESA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; MESA-NEXT: store volatile <3 x i8> [[ARG1_LOAD]], <3 x i8> addrspace(1)* undef, align 4		; MESA-NEXT: store volatile <3 x i8> [[ARG1_LOAD]], <3 x i8> addrspace(1)* undef, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i8 %arg0, i8 addrspace(1)* undef		store volatile i8 %arg0, i8 addrspace(1)* undef
store volatile <3 x i8> %arg1, <3 x i8> addrspace(1)* undef		store volatile <3 x i8> %arg1, <3 x i8> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_realign_i8_i16(i8 %arg0, i16 %arg1) #0 {		define amdgpu_kernel void @kern_realign_i8_i16(i8 %arg0, i16 %arg1) #0 {
; HSA-LABEL: @kern_realign_i8_i16(		; HSA-LABEL: @kern_realign_i8_i16(
; HSA-NEXT: [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 16		; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 16
; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16		; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
; HSA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i16 [[TMP5]], i16 addrspace(1)* undef, align 2		; HSA-NEXT: store volatile i16 [[TMP5]], i16 addrspace(1)* undef, align 2
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_realign_i8_i16(		; MESA-LABEL: @kern_realign_i8_i16(
; MESA-NEXT: [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 16		; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 16
; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16		; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
; MESA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1		; MESA-NEXT: store volatile i8 [[TMP2]], i8 addrspace(1)* undef, align 1
; MESA-NEXT: store volatile i16 [[TMP5]], i16 addrspace(1)* undef, align 2		; MESA-NEXT: store volatile i16 [[TMP5]], i16 addrspace(1)* undef, align 2
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i8 %arg0, i8 addrspace(1)* undef		store volatile i8 %arg0, i8 addrspace(1)* undef
store volatile i16 %arg1, i16 addrspace(1)* undef		store volatile i16 %arg1, i16 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_realign_i1_i1(i1 %arg0, i1 %arg1) #0 {		define amdgpu_kernel void @kern_realign_i1_i1(i1 %arg0, i1 %arg1) #0 {
; HSA-LABEL: @kern_realign_i1_i1(		; HSA-LABEL: @kern_realign_i1_i1(
; HSA-NEXT: [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1		; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1
; HSA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i1 [[TMP5]], i1 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i1 [[TMP5]], i1 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_realign_i1_i1(		; MESA-LABEL: @kern_realign_i1_i1(
; MESA-NEXT: [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1		; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1
; MESA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1		; MESA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1
; MESA-NEXT: store volatile i1 [[TMP5]], i1 addrspace(1)* undef, align 1		; MESA-NEXT: store volatile i1 [[TMP5]], i1 addrspace(1)* undef, align 1
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i1 %arg0, i1 addrspace(1)* undef		store volatile i1 %arg0, i1 addrspace(1)* undef
store volatile i1 %arg1, i1 addrspace(1)* undef		store volatile i1 %arg1, i1 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_realign_i1_i1_i1(i1 %arg0, i1 %arg1, i1 %arg2) #0 {		define amdgpu_kernel void @kern_realign_i1_i1_i1(i1 %arg0, i1 %arg1, i1 %arg2) #0 {
; HSA-LABEL: @kern_realign_i1_i1_i1(		; HSA-LABEL: @kern_realign_i1_i1_i1(
; HSA-NEXT: [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1		; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1
; HSA-NEXT: [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG2_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG2_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP6:%.]] = load i32, i32 addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP6:%.]] = load i32, i32 addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP7:%.*]] = lshr i32 [[TMP6]], 16		; HSA-NEXT: [[TMP7:%.*]] = lshr i32 [[TMP6]], 16
; HSA-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i1		; HSA-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i1
; HSA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i1 [[TMP5]], i1 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i1 [[TMP5]], i1 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i1 [[TMP8]], i1 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i1 [[TMP8]], i1 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_realign_i1_i1_i1(		; MESA-LABEL: @kern_realign_i1_i1_i1(
; MESA-NEXT: [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
Show All 11 Lines	;
store volatile i1 %arg0, i1 addrspace(1)* undef		store volatile i1 %arg0, i1 addrspace(1)* undef
store volatile i1 %arg1, i1 addrspace(1)* undef		store volatile i1 %arg1, i1 addrspace(1)* undef
store volatile i1 %arg2, i1 addrspace(1)* undef		store volatile i1 %arg2, i1 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_realign_i1_i1_i1_i1(i1 %arg0, i1 %arg1, i1 %arg2, i1 %arg3) #0 {		define amdgpu_kernel void @kern_realign_i1_i1_i1_i1(i1 %arg0, i1 %arg1, i1 %arg2, i1 %arg3) #0 {
; HSA-LABEL: @kern_realign_i1_i1_i1_i1(		; HSA-LABEL: @kern_realign_i1_i1_i1_i1(
; HSA-NEXT: [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
Show All 10 Lines
; HSA-NEXT: [[TMP11:%.*]] = trunc i32 [[TMP10]] to i1		; HSA-NEXT: [[TMP11:%.*]] = trunc i32 [[TMP10]] to i1
; HSA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i1 [[TMP5]], i1 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i1 [[TMP5]], i1 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i1 [[TMP8]], i1 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i1 [[TMP8]], i1 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i1 [[TMP11]], i1 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i1 [[TMP11]], i1 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_realign_i1_i1_i1_i1(		; MESA-LABEL: @kern_realign_i1_i1_i1_i1(
; MESA-NEXT: [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
Show All 18 Lines	;
store volatile i1 %arg1, i1 addrspace(1)* undef		store volatile i1 %arg1, i1 addrspace(1)* undef
store volatile i1 %arg2, i1 addrspace(1)* undef		store volatile i1 %arg2, i1 addrspace(1)* undef
store volatile i1 %arg3, i1 addrspace(1)* undef		store volatile i1 %arg3, i1 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_realign_i1_v3i1(i1 %arg0, <3 x i1> %arg1) #0 {		define amdgpu_kernel void @kern_realign_i1_v3i1(i1 %arg0, <3 x i1> %arg1) #0 {
; HSA-LABEL: @kern_realign_i1_v3i1(		; HSA-LABEL: @kern_realign_i1_v3i1(
; HSA-NEXT: [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i3		; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i3
; HSA-NEXT: [[ARG1_LOAD:%.*]] = bitcast i3 [[TMP5]] to <3 x i1>		; HSA-NEXT: [[ARG1_LOAD:%.*]] = bitcast i3 [[TMP5]] to <3 x i1>
; HSA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile <3 x i1> [[ARG1_LOAD]], <3 x i1> addrspace(1)* undef, align 1		; HSA-NEXT: store volatile <3 x i1> [[ARG1_LOAD]], <3 x i1> addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_realign_i1_v3i1(		; MESA-LABEL: @kern_realign_i1_v3i1(
; MESA-NEXT: [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i3		; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i3
; MESA-NEXT: [[ARG1_LOAD:%.*]] = bitcast i3 [[TMP5]] to <3 x i1>		; MESA-NEXT: [[ARG1_LOAD:%.*]] = bitcast i3 [[TMP5]] to <3 x i1>
; MESA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1		; MESA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1
; MESA-NEXT: store volatile <3 x i1> [[ARG1_LOAD]], <3 x i1> addrspace(1)* undef, align 1		; MESA-NEXT: store volatile <3 x i1> [[ARG1_LOAD]], <3 x i1> addrspace(1)* undef, align 1
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i1 %arg0, i1 addrspace(1)* undef		store volatile i1 %arg0, i1 addrspace(1)* undef
store volatile <3 x i1> %arg1, <3 x i1> addrspace(1)* undef		store volatile <3 x i1> %arg1, <3 x i1> addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_realign_i1_i16(i1 %arg0, i16 %arg1) #0 {		define amdgpu_kernel void @kern_realign_i1_i16(i1 %arg0, i16 %arg1) #0 {
; HSA-LABEL: @kern_realign_i1_i16(		; HSA-LABEL: @kern_realign_i1_i16(
; HSA-NEXT: [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 16		; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 16
; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16		; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
; HSA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i16 [[TMP5]], i16 addrspace(1)* undef, align 2		; HSA-NEXT: store volatile i16 [[TMP5]], i16 addrspace(1)* undef, align 2
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_realign_i1_i16(		; MESA-LABEL: @kern_realign_i1_i16(
; MESA-NEXT: [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 16		; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 16
; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16		; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
; MESA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1		; MESA-NEXT: store volatile i1 [[TMP2]], i1 addrspace(1)* undef, align 1
; MESA-NEXT: store volatile i16 [[TMP5]], i16 addrspace(1)* undef, align 2		; MESA-NEXT: store volatile i16 [[TMP5]], i16 addrspace(1)* undef, align 2
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i1 %arg0, i1 addrspace(1)* undef		store volatile i1 %arg0, i1 addrspace(1)* undef
store volatile i16 %arg1, i16 addrspace(1)* undef		store volatile i16 %arg1, i16 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4, i8 %arg5, i8 %arg6, i8 %arg7) #0 {		define amdgpu_kernel void @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4, i8 %arg5, i8 %arg6, i8 %arg7) #0 {
; HSA-LABEL: @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(		; HSA-LABEL: @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(
; HSA-NEXT: [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(8) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
Show All 28 Lines
; HSA-NEXT: store volatile i8 [[TMP8]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP8]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i8 [[TMP11]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP11]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i8 [[TMP14]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP14]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i8 [[TMP17]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP17]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: store volatile i8 [[TMP20]], i8 addrspace(1)* undef, align 1		; HSA-NEXT: store volatile i8 [[TMP20]], i8 addrspace(1)* undef, align 1
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(		; MESA-LABEL: @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(
; MESA-NEXT: [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8		; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 8
Show All 39 Lines	;
store volatile i8 %arg5, i8 addrspace(1)* undef		store volatile i8 %arg5, i8 addrspace(1)* undef
store volatile i8 %arg6, i8 addrspace(1)* undef		store volatile i8 %arg6, i8 addrspace(1)* undef
store volatile i8 %arg7, i8 addrspace(1)* undef		store volatile i8 %arg7, i8 addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_realign_f16_f16(half %arg0, half %arg1) #0 {		define amdgpu_kernel void @kern_realign_f16_f16(half %arg0, half %arg1) #0 {
; HSA-LABEL: @kern_realign_f16_f16(		; HSA-LABEL: @kern_realign_f16_f16(
; HSA-NEXT: [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16		; HSA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; HSA-NEXT: [[ARG0_LOAD:%.*]] = bitcast i16 [[TMP2]] to half		; HSA-NEXT: [[ARG0_LOAD:%.*]] = bitcast i16 [[TMP2]] to half
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 16		; HSA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 16
; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16		; HSA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
; HSA-NEXT: [[ARG1_LOAD:%.*]] = bitcast i16 [[TMP5]] to half		; HSA-NEXT: [[ARG1_LOAD:%.*]] = bitcast i16 [[TMP5]] to half
; HSA-NEXT: store volatile half [[ARG0_LOAD]], half addrspace(1)* undef, align 2		; HSA-NEXT: store volatile half [[ARG0_LOAD]], half addrspace(1)* undef, align 2
; HSA-NEXT: store volatile half [[ARG1_LOAD]], half addrspace(1)* undef, align 2		; HSA-NEXT: store volatile half [[ARG1_LOAD]], half addrspace(1)* undef, align 2
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_realign_f16_f16(		; MESA-LABEL: @kern_realign_f16_f16(
; MESA-NEXT: [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP1:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16		; MESA-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
; MESA-NEXT: [[ARG0_LOAD:%.*]] = bitcast i16 [[TMP2]] to half		; MESA-NEXT: [[ARG0_LOAD:%.*]] = bitcast i16 [[TMP2]] to half
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]] to i32 addrspace(4)*
; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[TMP3:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 16		; MESA-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 16
; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16		; MESA-NEXT: [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16
; MESA-NEXT: [[ARG1_LOAD:%.*]] = bitcast i16 [[TMP5]] to half		; MESA-NEXT: [[ARG1_LOAD:%.*]] = bitcast i16 [[TMP5]] to half
; MESA-NEXT: store volatile half [[ARG0_LOAD]], half addrspace(1)* undef, align 2		; MESA-NEXT: store volatile half [[ARG0_LOAD]], half addrspace(1)* undef, align 2
; MESA-NEXT: store volatile half [[ARG1_LOAD]], half addrspace(1)* undef, align 2		; MESA-NEXT: store volatile half [[ARG1_LOAD]], half addrspace(1)* undef, align 2
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile half %arg0, half addrspace(1)* undef		store volatile half %arg0, half addrspace(1)* undef
store volatile half %arg1, half addrspace(1)* undef		store volatile half %arg1, half addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_global_ptr(i8 addrspace(1)* %ptr) #0 {		define amdgpu_kernel void @kern_global_ptr(i8 addrspace(1)* %ptr) #0 {
; HSA-LABEL: @kern_global_ptr(		; HSA-LABEL: @kern_global_ptr(
; HSA-NEXT: [[KERN_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(8) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_GLOBAL_PTR_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_GLOBAL_PTR_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8		; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_global_ptr(		; MESA-LABEL: @kern_global_ptr(
; MESA-NEXT: [[KERN_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8		; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i8 addrspace(1)* %ptr, i8 addrspace(1)* addrspace(1)* undef		store volatile i8 addrspace(1)* %ptr, i8 addrspace(1)* addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_global_ptr_dereferencable(i8 addrspace(1)* dereferenceable(42) %ptr) #0 {		define amdgpu_kernel void @kern_global_ptr_dereferencable(i8 addrspace(1)* dereferenceable(42) %ptr) #0 {
; HSA-LABEL: @kern_global_ptr_dereferencable(		; HSA-LABEL: @kern_global_ptr_dereferencable(
; HSA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(8) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0, !dereferenceable !1		; HSA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0, !dereferenceable !1
; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8		; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_global_ptr_dereferencable(		; MESA-LABEL: @kern_global_ptr_dereferencable(
; MESA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable !1		; MESA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable !1
; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8		; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i8 addrspace(1)* %ptr, i8 addrspace(1)* addrspace(1)* undef		store volatile i8 addrspace(1)* %ptr, i8 addrspace(1)* addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_global_ptr_dereferencable_or_null(i8 addrspace(1)* dereferenceable_or_null(128) %ptr) #0 {		define amdgpu_kernel void @kern_global_ptr_dereferencable_or_null(i8 addrspace(1)* dereferenceable_or_null(128) %ptr) #0 {
; HSA-LABEL: @kern_global_ptr_dereferencable_or_null(		; HSA-LABEL: @kern_global_ptr_dereferencable_or_null(
; HSA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(8) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0, !dereferenceable_or_null !2		; HSA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0, !dereferenceable_or_null !2
; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8		; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_global_ptr_dereferencable_or_null(		; MESA-LABEL: @kern_global_ptr_dereferencable_or_null(
; MESA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable_or_null !2		; MESA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !dereferenceable_or_null !2
; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8		; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i8 addrspace(1)* %ptr, i8 addrspace(1)* addrspace(1)* undef		store volatile i8 addrspace(1)* %ptr, i8 addrspace(1)* addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_nonnull_global_ptr(i8 addrspace(1)* nonnull %ptr) #0 {		define amdgpu_kernel void @kern_nonnull_global_ptr(i8 addrspace(1)* nonnull %ptr) #0 {
; HSA-LABEL: @kern_nonnull_global_ptr(		; HSA-LABEL: @kern_nonnull_global_ptr(
; HSA-NEXT: [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(8) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0, !nonnull !0		; HSA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0, !nonnull !0
; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8		; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_nonnull_global_ptr(		; MESA-LABEL: @kern_nonnull_global_ptr(
; MESA-NEXT: [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !nonnull !0		; MESA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !nonnull !0
; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8		; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i8 addrspace(1)* %ptr, i8 addrspace(1)* addrspace(1)* undef		store volatile i8 addrspace(1)* %ptr, i8 addrspace(1)* addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_align32_global_ptr(i8 addrspace(1)* align 1024 %ptr) #0 {		define amdgpu_kernel void @kern_align32_global_ptr(i8 addrspace(1)* align 1024 %ptr) #0 {
; HSA-LABEL: @kern_align32_global_ptr(		; HSA-LABEL: @kern_align32_global_ptr(
; HSA-NEXT: [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(8) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0, !align !3		; HSA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0, !align !3
; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8		; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_align32_global_ptr(		; MESA-LABEL: @kern_align32_global_ptr(
; MESA-NEXT: [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[PTR_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[PTR_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[PTR_KERNARG_OFFSET]] to i8 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !align !3		; MESA-NEXT: [[PTR_LOAD:%.]] = load i8 addrspace(1), i8 addrspace(1)* addrspace(4)* [[PTR_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0, !align !3
; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8		; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i8 addrspace(1)* %ptr, i8 addrspace(1)* addrspace(1)* undef		store volatile i8 addrspace(1)* %ptr, i8 addrspace(1)* addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_noalias_global_ptr(i8 addrspace(1)* noalias %ptr) #0 {		define amdgpu_kernel void @kern_noalias_global_ptr(i8 addrspace(1)* noalias %ptr) #0 {
; HSA-LABEL: @kern_noalias_global_ptr(		; HSA-LABEL: @kern_noalias_global_ptr(
; HSA-NEXT: [[KERN_NOALIAS_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(8) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_NOALIAS_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR:%.]], i8 addrspace(1) addrspace(1)* undef, align 8		; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR:%.]], i8 addrspace(1) addrspace(1)* undef, align 8
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_noalias_global_ptr(		; MESA-LABEL: @kern_noalias_global_ptr(
; MESA-NEXT: [[KERN_NOALIAS_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(44) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_NOALIAS_GLOBAL_PTR_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR:%.]], i8 addrspace(1) addrspace(1)* undef, align 8		; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR:%.]], i8 addrspace(1) addrspace(1)* undef, align 8
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i8 addrspace(1)* %ptr, i8 addrspace(1)* addrspace(1)* undef		store volatile i8 addrspace(1)* %ptr, i8 addrspace(1)* addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @kern_noalias_global_ptr_x2(i8 addrspace(1)* noalias %ptr0, i8 addrspace(1)* noalias %ptr1) #0 {		define amdgpu_kernel void @kern_noalias_global_ptr_x2(i8 addrspace(1)* noalias %ptr0, i8 addrspace(1)* noalias %ptr1) #0 {
; HSA-LABEL: @kern_noalias_global_ptr_x2(		; HSA-LABEL: @kern_noalias_global_ptr_x2(
; HSA-NEXT: [[KERN_NOALIAS_GLOBAL_PTR_X2_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(16) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[KERN_NOALIAS_GLOBAL_PTR_X2_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR0:%.]], i8 addrspace(1) addrspace(1)* undef, align 8		; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR0:%.]], i8 addrspace(1) addrspace(1)* undef, align 8
; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR1:%.]], i8 addrspace(1) addrspace(1)* undef, align 8		; HSA-NEXT: store volatile i8 addrspace(1)* [[PTR1:%.]], i8 addrspace(1) addrspace(1)* undef, align 8
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @kern_noalias_global_ptr_x2(		; MESA-LABEL: @kern_noalias_global_ptr_x2(
; MESA-NEXT: [[KERN_NOALIAS_GLOBAL_PTR_X2_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(52) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[KERN_NOALIAS_GLOBAL_PTR_X2_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR0:%.]], i8 addrspace(1) addrspace(1)* undef, align 8		; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR0:%.]], i8 addrspace(1) addrspace(1)* undef, align 8
; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR1:%.]], i8 addrspace(1) addrspace(1)* undef, align 8		; MESA-NEXT: store volatile i8 addrspace(1)* [[PTR1:%.]], i8 addrspace(1) addrspace(1)* undef, align 8
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store volatile i8 addrspace(1)* %ptr0, i8 addrspace(1)* addrspace(1)* undef		store volatile i8 addrspace(1)* %ptr0, i8 addrspace(1)* addrspace(1)* undef
store volatile i8 addrspace(1)* %ptr1, i8 addrspace(1)* addrspace(1)* undef		store volatile i8 addrspace(1)* %ptr1, i8 addrspace(1)* addrspace(1)* undef
ret void		ret void
}		}

define amdgpu_kernel void @struct_i8_i8_arg({i8, i8} %in) #0 {		define amdgpu_kernel void @struct_i8_i8_arg({i8, i8} %in) #0 {
; HSA-LABEL: @struct_i8_i8_arg(		; HSA-LABEL: @struct_i8_i8_arg(
; HSA-NEXT: entry:		; HSA-NEXT: entry:
; HSA-NEXT: [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to { i8, i8 } addrspace(4)*		; HSA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to { i8, i8 } addrspace(4)*
; HSA-NEXT: [[IN_LOAD:%.]] = load { i8, i8 }, { i8, i8 } addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[IN_LOAD:%.]] = load { i8, i8 }, { i8, i8 } addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[ELT0:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 0		; HSA-NEXT: [[ELT0:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 0
; HSA-NEXT: [[ELT1:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 1		; HSA-NEXT: [[ELT1:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 1
; HSA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4		; HSA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4
; HSA-NEXT: store volatile i8 [[ELT1]], i8 addrspace(1)* null, align 4		; HSA-NEXT: store volatile i8 [[ELT1]], i8 addrspace(1)* null, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @struct_i8_i8_arg(		; MESA-LABEL: @struct_i8_i8_arg(
; MESA-NEXT: entry:		; MESA-NEXT: entry:
; MESA-NEXT: [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to { i8, i8 } addrspace(4)*		; MESA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to { i8, i8 } addrspace(4)*
; MESA-NEXT: [[IN_LOAD:%.]] = load { i8, i8 }, { i8, i8 } addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[IN_LOAD:%.]] = load { i8, i8 }, { i8, i8 } addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[ELT0:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 0		; MESA-NEXT: [[ELT0:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 0
; MESA-NEXT: [[ELT1:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 1		; MESA-NEXT: [[ELT1:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 1
; MESA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4		; MESA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4
; MESA-NEXT: store volatile i8 [[ELT1]], i8 addrspace(1)* null, align 4		; MESA-NEXT: store volatile i8 [[ELT1]], i8 addrspace(1)* null, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
entry:		entry:
%elt0 = extractvalue {i8, i8} %in, 0		%elt0 = extractvalue {i8, i8} %in, 0
%elt1 = extractvalue {i8, i8} %in, 1		%elt1 = extractvalue {i8, i8} %in, 1
store volatile i8 %elt0, i8 addrspace(1)* null, align 4		store volatile i8 %elt0, i8 addrspace(1)* null, align 4
store volatile i8 %elt1, i8 addrspace(1)* null, align 4		store volatile i8 %elt1, i8 addrspace(1)* null, align 4
ret void		ret void
}		}

define amdgpu_kernel void @struct_i8_i16_arg({i8, i16} %in) #0 {		define amdgpu_kernel void @struct_i8_i16_arg({i8, i16} %in) #0 {
; HSA-LABEL: @struct_i8_i16_arg(		; HSA-LABEL: @struct_i8_i16_arg(
; HSA-NEXT: entry:		; HSA-NEXT: entry:
; HSA-NEXT: [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to { i8, i16 } addrspace(4)*		; HSA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to { i8, i16 } addrspace(4)*
; HSA-NEXT: [[IN_LOAD:%.]] = load { i8, i16 }, { i8, i16 } addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[IN_LOAD:%.]] = load { i8, i16 }, { i8, i16 } addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[ELT0:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 0		; HSA-NEXT: [[ELT0:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 0
; HSA-NEXT: [[ELT1:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 1		; HSA-NEXT: [[ELT1:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 1
; HSA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4		; HSA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4
; HSA-NEXT: store volatile i16 [[ELT1]], i16 addrspace(1)* null, align 4		; HSA-NEXT: store volatile i16 [[ELT1]], i16 addrspace(1)* null, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @struct_i8_i16_arg(		; MESA-LABEL: @struct_i8_i16_arg(
; MESA-NEXT: entry:		; MESA-NEXT: entry:
; MESA-NEXT: [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to { i8, i16 } addrspace(4)*		; MESA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to { i8, i16 } addrspace(4)*
; MESA-NEXT: [[IN_LOAD:%.]] = load { i8, i16 }, { i8, i16 } addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[IN_LOAD:%.]] = load { i8, i16 }, { i8, i16 } addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[ELT0:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 0		; MESA-NEXT: [[ELT0:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 0
; MESA-NEXT: [[ELT1:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 1		; MESA-NEXT: [[ELT1:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 1
; MESA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4		; MESA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4
; MESA-NEXT: store volatile i16 [[ELT1]], i16 addrspace(1)* null, align 4		; MESA-NEXT: store volatile i16 [[ELT1]], i16 addrspace(1)* null, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
entry:		entry:
%elt0 = extractvalue {i8, i16} %in, 0		%elt0 = extractvalue {i8, i16} %in, 0
%elt1 = extractvalue {i8, i16} %in, 1		%elt1 = extractvalue {i8, i16} %in, 1
store volatile i8 %elt0, i8 addrspace(1)* null, align 4		store volatile i8 %elt0, i8 addrspace(1)* null, align 4
store volatile i16 %elt1, i16 addrspace(1)* null, align 4		store volatile i16 %elt1, i16 addrspace(1)* null, align 4
ret void		ret void
}		}

define amdgpu_kernel void @array_2xi8_arg([2 x i8] %in) #0 {		define amdgpu_kernel void @array_2xi8_arg([2 x i8] %in) #0 {
; HSA-LABEL: @array_2xi8_arg(		; HSA-LABEL: @array_2xi8_arg(
; HSA-NEXT: entry:		; HSA-NEXT: entry:
; HSA-NEXT: [[ARRAY_2XI8_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[ARRAY_2XI8_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[ARRAY_2XI8_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[ARRAY_2XI8_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to [2 x i8] addrspace(4)*		; HSA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to [2 x i8] addrspace(4)*
; HSA-NEXT: [[IN_LOAD:%.]] = load [2 x i8], [2 x i8] addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[IN_LOAD:%.]] = load [2 x i8], [2 x i8] addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[ELT0:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 0		; HSA-NEXT: [[ELT0:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 0
; HSA-NEXT: [[ELT1:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 1		; HSA-NEXT: [[ELT1:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 1
; HSA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4		; HSA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4
; HSA-NEXT: store volatile i8 [[ELT1]], i8 addrspace(1)* null, align 4		; HSA-NEXT: store volatile i8 [[ELT1]], i8 addrspace(1)* null, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @array_2xi8_arg(		; MESA-LABEL: @array_2xi8_arg(
; MESA-NEXT: entry:		; MESA-NEXT: entry:
; MESA-NEXT: [[ARRAY_2XI8_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[ARRAY_2XI8_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[ARRAY_2XI8_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[ARRAY_2XI8_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to [2 x i8] addrspace(4)*		; MESA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to [2 x i8] addrspace(4)*
; MESA-NEXT: [[IN_LOAD:%.]] = load [2 x i8], [2 x i8] addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[IN_LOAD:%.]] = load [2 x i8], [2 x i8] addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[ELT0:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 0		; MESA-NEXT: [[ELT0:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 0
; MESA-NEXT: [[ELT1:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 1		; MESA-NEXT: [[ELT1:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 1
; MESA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4		; MESA-NEXT: store volatile i8 [[ELT0]], i8 addrspace(1)* null, align 4
; MESA-NEXT: store volatile i8 [[ELT1]], i8 addrspace(1)* null, align 4		; MESA-NEXT: store volatile i8 [[ELT1]], i8 addrspace(1)* null, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
entry:		entry:
%elt0 = extractvalue [2 x i8] %in, 0		%elt0 = extractvalue [2 x i8] %in, 0
%elt1 = extractvalue [2 x i8] %in, 1		%elt1 = extractvalue [2 x i8] %in, 1
store volatile i8 %elt0, i8 addrspace(1)* null, align 4		store volatile i8 %elt0, i8 addrspace(1)* null, align 4
store volatile i8 %elt1, i8 addrspace(1)* null, align 4		store volatile i8 %elt1, i8 addrspace(1)* null, align 4
ret void		ret void
}		}

define amdgpu_kernel void @array_2xi1_arg([2 x i1] %in) #0 {		define amdgpu_kernel void @array_2xi1_arg([2 x i1] %in) #0 {
; HSA-LABEL: @array_2xi1_arg(		; HSA-LABEL: @array_2xi1_arg(
; HSA-NEXT: entry:		; HSA-NEXT: entry:
; HSA-NEXT: [[ARRAY_2XI1_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[ARRAY_2XI1_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[ARRAY_2XI1_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[ARRAY_2XI1_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to [2 x i1] addrspace(4)*		; HSA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to [2 x i1] addrspace(4)*
; HSA-NEXT: [[IN_LOAD:%.]] = load [2 x i1], [2 x i1] addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[IN_LOAD:%.]] = load [2 x i1], [2 x i1] addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[ELT0:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 0		; HSA-NEXT: [[ELT0:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 0
; HSA-NEXT: [[ELT1:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 1		; HSA-NEXT: [[ELT1:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 1
; HSA-NEXT: store volatile i1 [[ELT0]], i1 addrspace(1)* null, align 4		; HSA-NEXT: store volatile i1 [[ELT0]], i1 addrspace(1)* null, align 4
; HSA-NEXT: store volatile i1 [[ELT1]], i1 addrspace(1)* null, align 4		; HSA-NEXT: store volatile i1 [[ELT1]], i1 addrspace(1)* null, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @array_2xi1_arg(		; MESA-LABEL: @array_2xi1_arg(
; MESA-NEXT: entry:		; MESA-NEXT: entry:
; MESA-NEXT: [[ARRAY_2XI1_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[ARRAY_2XI1_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[ARRAY_2XI1_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[IN_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[ARRAY_2XI1_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to [2 x i1] addrspace(4)*		; MESA-NEXT: [[IN_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[IN_KERNARG_OFFSET]] to [2 x i1] addrspace(4)*
; MESA-NEXT: [[IN_LOAD:%.]] = load [2 x i1], [2 x i1] addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[IN_LOAD:%.]] = load [2 x i1], [2 x i1] addrspace(4) [[IN_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[ELT0:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 0		; MESA-NEXT: [[ELT0:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 0
; MESA-NEXT: [[ELT1:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 1		; MESA-NEXT: [[ELT1:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 1
; MESA-NEXT: store volatile i1 [[ELT0]], i1 addrspace(1)* null, align 4		; MESA-NEXT: store volatile i1 [[ELT0]], i1 addrspace(1)* null, align 4
; MESA-NEXT: store volatile i1 [[ELT1]], i1 addrspace(1)* null, align 4		; MESA-NEXT: store volatile i1 [[ELT1]], i1 addrspace(1)* null, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
entry:		entry:
%elt0 = extractvalue [2 x i1] %in, 0		%elt0 = extractvalue [2 x i1] %in, 0
%elt1 = extractvalue [2 x i1] %in, 1		%elt1 = extractvalue [2 x i1] %in, 1
store volatile i1 %elt0, i1 addrspace(1)* null, align 4		store volatile i1 %elt0, i1 addrspace(1)* null, align 4
store volatile i1 %elt1, i1 addrspace(1)* null, align 4		store volatile i1 %elt1, i1 addrspace(1)* null, align 4
ret void		ret void
}		}

define amdgpu_kernel void @only_empty_struct({} %empty) #0 {		define amdgpu_kernel void @only_empty_struct({} %empty) #0 {
; HSA-LABEL: @only_empty_struct(		; HSA-LABEL: @only_empty_struct(
		; HSA-NEXT: [[ONLY_EMPTY_STRUCT_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(56) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @only_empty_struct(		; MESA-LABEL: @only_empty_struct(
; MESA-NEXT: [[ONLY_EMPTY_STRUCT_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(36) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[ONLY_EMPTY_STRUCT_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(56) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
ret void		ret void
}		}

define amdgpu_kernel void @empty_struct_with_other({} %empty, i32 %arg1) #0 {		define amdgpu_kernel void @empty_struct_with_other({} %empty, i32 %arg1) #0 {
; HSA-LABEL: @empty_struct_with_other(		; HSA-LABEL: @empty_struct_with_other(
; HSA-NEXT: [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG1_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG1_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG1_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG1_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[ARG1_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[ARG1_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: store i32 [[ARG1_LOAD]], i32 addrspace(1)* undef, align 4		; HSA-NEXT: store i32 [[ARG1_LOAD]], i32 addrspace(1)* undef, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @empty_struct_with_other(		; MESA-LABEL: @empty_struct_with_other(
; MESA-NEXT: [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG1_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG1_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG1_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG1_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG1_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[ARG1_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[ARG1_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG1_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: store i32 [[ARG1_LOAD]], i32 addrspace(1)* undef, align 4		; MESA-NEXT: store i32 [[ARG1_LOAD]], i32 addrspace(1)* undef, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
store i32 %arg1, i32 addrspace(1)* undef		store i32 %arg1, i32 addrspace(1)* undef
ret void		ret void
}		}

; Should insert code after the allocas		; Should insert code after the allocas
define amdgpu_kernel void @static_alloca_kern_i32(i32 %arg0) {		define amdgpu_kernel void @static_alloca_kern_i32(i32 %arg0) {
; HSA-LABEL: @static_alloca_kern_i32(		; HSA-LABEL: @static_alloca_kern_i32(
; HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)		; HSA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
; HSA-NEXT: [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[ARG0_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[ARG0_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: store volatile i32 [[ARG0_LOAD]], i32 addrspace(5)* [[ALLOCA]], align 4		; HSA-NEXT: store volatile i32 [[ARG0_LOAD]], i32 addrspace(5)* [[ALLOCA]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @static_alloca_kern_i32(		; MESA-LABEL: @static_alloca_kern_i32(
; MESA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)		; MESA-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)
; MESA-NEXT: [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[ARG0_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[ARG0_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[ARG0_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[ARG0_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[ARG0_LOAD:%.]] = load i32, i32 addrspace(4) [[ARG0_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: store volatile i32 [[ARG0_LOAD]], i32 addrspace(5)* [[ALLOCA]], align 4		; MESA-NEXT: store volatile i32 [[ARG0_LOAD]], i32 addrspace(5)* [[ALLOCA]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%alloca = alloca i32, addrspace(5)		%alloca = alloca i32, addrspace(5)
store volatile i32 %arg0, i32 addrspace(5)* %alloca		store volatile i32 %arg0, i32 addrspace(5)* %alloca
ret void		ret void
}		}

; Make sure we don't break the IR if an alloca depends on the		; Make sure we don't break the IR if an alloca depends on the
; kernargs.		; kernargs.
define amdgpu_kernel void @dyn_alloca_kernarg_i32(i32 %n) {		define amdgpu_kernel void @dyn_alloca_kernarg_i32(i32 %n) {
; HSA-LABEL: @dyn_alloca_kernarg_i32(		; HSA-LABEL: @dyn_alloca_kernarg_i32(
; HSA-NEXT: [[ALLOCA0:%.*]] = alloca i32, align 4, addrspace(5)		; HSA-NEXT: [[ALLOCA0:%.*]] = alloca i32, align 4, addrspace(5)
; HSA-NEXT: [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[N_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[N_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[N_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[N_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[N_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[N_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[N_LOAD:%.]] = load i32, i32 addrspace(4) [[N_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[N_LOAD:%.]] = load i32, i32 addrspace(4) [[N_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[ALLOCA1:%.*]] = alloca i32, i32 [[N_LOAD]], align 4, addrspace(5)		; HSA-NEXT: [[ALLOCA1:%.*]] = alloca i32, i32 [[N_LOAD]], align 4, addrspace(5)
; HSA-NEXT: store volatile i32 0, i32 addrspace(5)* [[ALLOCA0]], align 4		; HSA-NEXT: store volatile i32 0, i32 addrspace(5)* [[ALLOCA0]], align 4
; HSA-NEXT: store volatile i32 1, i32 addrspace(5)* [[ALLOCA1]], align 4		; HSA-NEXT: store volatile i32 1, i32 addrspace(5)* [[ALLOCA1]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @dyn_alloca_kernarg_i32(		; MESA-LABEL: @dyn_alloca_kernarg_i32(
; MESA-NEXT: [[ALLOCA0:%.*]] = alloca i32, align 4, addrspace(5)		; MESA-NEXT: [[ALLOCA0:%.*]] = alloca i32, align 4, addrspace(5)
; MESA-NEXT: [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[N_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[N_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[N_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[N_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[N_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[N_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[N_LOAD:%.]] = load i32, i32 addrspace(4) [[N_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[N_LOAD:%.]] = load i32, i32 addrspace(4) [[N_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[ALLOCA1:%.*]] = alloca i32, i32 [[N_LOAD]], align 4, addrspace(5)		; MESA-NEXT: [[ALLOCA1:%.*]] = alloca i32, i32 [[N_LOAD]], align 4, addrspace(5)
; MESA-NEXT: store volatile i32 0, i32 addrspace(5)* [[ALLOCA0]], align 4		; MESA-NEXT: store volatile i32 0, i32 addrspace(5)* [[ALLOCA0]], align 4
; MESA-NEXT: store volatile i32 1, i32 addrspace(5)* [[ALLOCA1]], align 4		; MESA-NEXT: store volatile i32 1, i32 addrspace(5)* [[ALLOCA1]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%alloca0 = alloca i32, addrspace(5)		%alloca0 = alloca i32, addrspace(5)
%alloca1 = alloca i32, i32 %n, addrspace(5)		%alloca1 = alloca i32, i32 %n, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca0		store volatile i32 0, i32 addrspace(5)* %alloca0
store volatile i32 1, i32 addrspace(5)* %alloca1		store volatile i32 1, i32 addrspace(5)* %alloca1
ret void		ret void
}		}

; Byref pointers should only be treated as offsets from kernarg		; Byref pointers should only be treated as offsets from kernarg
define amdgpu_kernel void @byref_constant_i8_arg(i32 addrspace(1)* nocapture %out, i8 addrspace(4)* byref(i8) %in.byref) {		define amdgpu_kernel void @byref_constant_i8_arg(i32 addrspace(1)* nocapture %out, i8 addrspace(4)* byref(i8) %in.byref) {
; HSA-LABEL: @byref_constant_i8_arg(		; HSA-LABEL: @byref_constant_i8_arg(
; HSA-NEXT: [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(12) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 8		; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 8
; HSA-NEXT: [[IN:%.]] = load i8, i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 1		; HSA-NEXT: [[IN:%.]] = load i8, i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 1
; HSA-NEXT: [[EXT:%.*]] = zext i8 [[IN]] to i32		; HSA-NEXT: [[EXT:%.*]] = zext i8 [[IN]] to i32
; HSA-NEXT: store i32 [[EXT]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store i32 [[EXT]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @byref_constant_i8_arg(		; MESA-LABEL: @byref_constant_i8_arg(
; MESA-NEXT: [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(48) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(68) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 44		; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 44
; MESA-NEXT: [[IN:%.]] = load i8, i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 1		; MESA-NEXT: [[IN:%.]] = load i8, i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 1
; MESA-NEXT: [[EXT:%.*]] = zext i8 [[IN]] to i32		; MESA-NEXT: [[EXT:%.*]] = zext i8 [[IN]] to i32
; MESA-NEXT: store i32 [[EXT]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store i32 [[EXT]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%in = load i8, i8 addrspace(4)* %in.byref		%in = load i8, i8 addrspace(4)* %in.byref
%ext = zext i8 %in to i32		%ext = zext i8 %in to i32
store i32 %ext, i32 addrspace(1)* %out, align 4		store i32 %ext, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

define amdgpu_kernel void @byref_constant_i16_arg(i32 addrspace(1)* nocapture %out, i16 addrspace(4)* byref(i16) %in.byref) {		define amdgpu_kernel void @byref_constant_i16_arg(i32 addrspace(1)* nocapture %out, i16 addrspace(4)* byref(i16) %in.byref) {
; HSA-LABEL: @byref_constant_i16_arg(		; HSA-LABEL: @byref_constant_i16_arg(
; HSA-NEXT: [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(12) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 8		; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 8
; HSA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i16 addrspace(4)*		; HSA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i16 addrspace(4)*
; HSA-NEXT: [[IN:%.]] = load i16, i16 addrspace(4) [[TMP1]], align 2		; HSA-NEXT: [[IN:%.]] = load i16, i16 addrspace(4) [[TMP1]], align 2
; HSA-NEXT: [[EXT:%.*]] = zext i16 [[IN]] to i32		; HSA-NEXT: [[EXT:%.*]] = zext i16 [[IN]] to i32
; HSA-NEXT: store i32 [[EXT]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store i32 [[EXT]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @byref_constant_i16_arg(		; MESA-LABEL: @byref_constant_i16_arg(
; MESA-NEXT: [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(48) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(68) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 44		; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 44
; MESA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i16 addrspace(4)*		; MESA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i16 addrspace(4)*
; MESA-NEXT: [[IN:%.]] = load i16, i16 addrspace(4) [[TMP1]], align 2		; MESA-NEXT: [[IN:%.]] = load i16, i16 addrspace(4) [[TMP1]], align 2
; MESA-NEXT: [[EXT:%.*]] = zext i16 [[IN]] to i32		; MESA-NEXT: [[EXT:%.*]] = zext i16 [[IN]] to i32
; MESA-NEXT: store i32 [[EXT]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store i32 [[EXT]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%in = load i16, i16 addrspace(4)* %in.byref		%in = load i16, i16 addrspace(4)* %in.byref
%ext = zext i16 %in to i32		%ext = zext i16 %in to i32
store i32 %ext, i32 addrspace(1)* %out, align 4		store i32 %ext, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

define amdgpu_kernel void @byref_constant_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* byref(i32) %in.byref, i32 %after.offset) {		define amdgpu_kernel void @byref_constant_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* byref(i32) %in.byref, i32 %after.offset) {
; HSA-LABEL: @byref_constant_i32_arg(		; HSA-LABEL: @byref_constant_i32_arg(
; HSA-NEXT: [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(16) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 8		; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 8
; HSA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 12		; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 12
; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; HSA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4		; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4
; HSA-NEXT: store volatile i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store volatile i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @byref_constant_i32_arg(		; MESA-LABEL: @byref_constant_i32_arg(
; MESA-NEXT: [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(52) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 44		; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 44
; MESA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 48		; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 48
; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; MESA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4		; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4
; MESA-NEXT: store volatile i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store volatile i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%in = load i32, i32 addrspace(4)* %in.byref		%in = load i32, i32 addrspace(4)* %in.byref
store volatile i32 %in, i32 addrspace(1)* %out, align 4		store volatile i32 %in, i32 addrspace(1)* %out, align 4
store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4		store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

define amdgpu_kernel void @byref_constant_v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> addrspace(4)* byref(<4 x i32>) %in.byref, i32 %after.offset) {		define amdgpu_kernel void @byref_constant_v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> addrspace(4)* byref(<4 x i32>) %in.byref, i32 %after.offset) {
; HSA-LABEL: @byref_constant_v4i32_arg(		; HSA-LABEL: @byref_constant_v4i32_arg(
; HSA-NEXT: [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(36) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(96) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to <4 x i32> addrspace(1)* addrspace(4)*		; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to <4 x i32> addrspace(1)* addrspace(4)*
; HSA-NEXT: [[OUT_LOAD:%.]] = load <4 x i32> addrspace(1), <4 x i32> addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[OUT_LOAD:%.]] = load <4 x i32> addrspace(1), <4 x i32> addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 16		; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 16
; HSA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to <4 x i32> addrspace(4)*		; HSA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to <4 x i32> addrspace(4)*
; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 32		; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 32
; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN:%.]] = load <4 x i32>, <4 x i32> addrspace(4) [[TMP1]], align 16		; HSA-NEXT: [[IN:%.]] = load <4 x i32>, <4 x i32> addrspace(4) [[TMP1]], align 16
; HSA-NEXT: store volatile <4 x i32> [[IN]], <4 x i32> addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store volatile <4 x i32> [[IN]], <4 x i32> addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: [[OUT_CAST:%.]] = bitcast <4 x i32> addrspace(1) [[OUT_LOAD]] to i32 addrspace(1)*		; HSA-NEXT: [[OUT_CAST:%.]] = bitcast <4 x i32> addrspace(1) [[OUT_LOAD]] to i32 addrspace(1)*
; HSA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_CAST]], align 4		; HSA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_CAST]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @byref_constant_v4i32_arg(		; MESA-LABEL: @byref_constant_v4i32_arg(
; MESA-NEXT: [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(92) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to <4 x i32> addrspace(1)* addrspace(4)*		; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to <4 x i32> addrspace(1)* addrspace(4)*
; MESA-NEXT: [[OUT_LOAD:%.]] = load <4 x i32> addrspace(1), <4 x i32> addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[OUT_LOAD:%.]] = load <4 x i32> addrspace(1), <4 x i32> addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 52		; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 52
; MESA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to <4 x i32> addrspace(4)*		; MESA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to <4 x i32> addrspace(4)*
; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 68		; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 68
; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN:%.]] = load <4 x i32>, <4 x i32> addrspace(4) [[TMP1]], align 16		; MESA-NEXT: [[IN:%.]] = load <4 x i32>, <4 x i32> addrspace(4) [[TMP1]], align 16
; MESA-NEXT: store volatile <4 x i32> [[IN]], <4 x i32> addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store volatile <4 x i32> [[IN]], <4 x i32> addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: [[OUT_CAST:%.]] = bitcast <4 x i32> addrspace(1) [[OUT_LOAD]] to i32 addrspace(1)*		; MESA-NEXT: [[OUT_CAST:%.]] = bitcast <4 x i32> addrspace(1) [[OUT_LOAD]] to i32 addrspace(1)*
; MESA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_CAST]], align 4		; MESA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_CAST]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%in = load <4 x i32>, <4 x i32> addrspace(4)* %in.byref		%in = load <4 x i32>, <4 x i32> addrspace(4)* %in.byref
store volatile <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4		store volatile <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4
%out.cast = bitcast <4 x i32> addrspace(1)* %out to i32 addrspace(1)*		%out.cast = bitcast <4 x i32> addrspace(1)* %out to i32 addrspace(1)*
store volatile i32 %after.offset, i32 addrspace(1)* %out.cast, align 4		store volatile i32 %after.offset, i32 addrspace(1)* %out.cast, align 4
ret void		ret void
}		}

define amdgpu_kernel void @byref_align_constant_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* byref(i32) align(256) %in.byref, i32 %after.offset) {		define amdgpu_kernel void @byref_align_constant_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* byref(i32) align(256) %in.byref, i32 %after.offset) {
; HSA-LABEL: @byref_align_constant_i32_arg(		; HSA-LABEL: @byref_align_constant_i32_arg(
; HSA-NEXT: [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 256 dereferenceable(264) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 256 dereferenceable(320) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 256		; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 256
; HSA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 260		; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 260
; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; HSA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4		; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4
; HSA-NEXT: store volatile i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store volatile i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @byref_align_constant_i32_arg(		; MESA-LABEL: @byref_align_constant_i32_arg(
; MESA-NEXT: [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 256 dereferenceable(300) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 256 dereferenceable(320) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 292		; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 292
; MESA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 296		; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 296
; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 8, !invariant.load !0		; MESA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 8, !invariant.load !0
; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4		; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4
; MESA-NEXT: store volatile i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store volatile i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%in = load i32, i32 addrspace(4)* %in.byref		%in = load i32, i32 addrspace(4)* %in.byref
store volatile i32 %in, i32 addrspace(1)* %out, align 4		store volatile i32 %in, i32 addrspace(1)* %out, align 4
store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4		store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

define amdgpu_kernel void @byref_natural_align_constant_v16i32_arg(i32 addrspace(1)* nocapture %out, i8, <16 x i32> addrspace(4)* byref(<16 x i32>) %in.byref, i32 %after.offset) {		define amdgpu_kernel void @byref_natural_align_constant_v16i32_arg(i32 addrspace(1)* nocapture %out, i8, <16 x i32> addrspace(4)* byref(<16 x i32>) %in.byref, i32 %after.offset) {
; HSA-LABEL: @byref_natural_align_constant_v16i32_arg(		; HSA-LABEL: @byref_natural_align_constant_v16i32_arg(
; HSA-NEXT: [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 64 dereferenceable(132) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 64 dereferenceable(192) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 64		; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 64
; HSA-NEXT: [[TMP2:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to <16 x i32> addrspace(4)*		; HSA-NEXT: [[TMP2:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to <16 x i32> addrspace(4)*
; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 128		; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 128
; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN:%.]] = load <16 x i32>, <16 x i32> addrspace(4) [[TMP2]], align 64		; HSA-NEXT: [[IN:%.]] = load <16 x i32>, <16 x i32> addrspace(4) [[TMP2]], align 64
; HSA-NEXT: [[CAST_OUT:%.]] = bitcast i32 addrspace(1) [[OUT_LOAD]] to <16 x i32> addrspace(1)*		; HSA-NEXT: [[CAST_OUT:%.]] = bitcast i32 addrspace(1) [[OUT_LOAD]] to <16 x i32> addrspace(1)*
; HSA-NEXT: store volatile <16 x i32> [[IN]], <16 x i32> addrspace(1)* [[CAST_OUT]], align 4		; HSA-NEXT: store volatile <16 x i32> [[IN]], <16 x i32> addrspace(1)* [[CAST_OUT]], align 4
; HSA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @byref_natural_align_constant_v16i32_arg(		; MESA-LABEL: @byref_natural_align_constant_v16i32_arg(
; MESA-NEXT: [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 64 dereferenceable(168) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 64 dereferenceable(188) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 100		; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 100
; MESA-NEXT: [[TMP2:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to <16 x i32> addrspace(4)*		; MESA-NEXT: [[TMP2:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to <16 x i32> addrspace(4)*
; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 164		; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 164
; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN:%.]] = load <16 x i32>, <16 x i32> addrspace(4) [[TMP2]], align 64		; MESA-NEXT: [[IN:%.]] = load <16 x i32>, <16 x i32> addrspace(4) [[TMP2]], align 64
; MESA-NEXT: [[CAST_OUT:%.]] = bitcast i32 addrspace(1) [[OUT_LOAD]] to <16 x i32> addrspace(1)*		; MESA-NEXT: [[CAST_OUT:%.]] = bitcast i32 addrspace(1) [[OUT_LOAD]] to <16 x i32> addrspace(1)*
; MESA-NEXT: store volatile <16 x i32> [[IN]], <16 x i32> addrspace(1)* [[CAST_OUT]], align 4		; MESA-NEXT: store volatile <16 x i32> [[IN]], <16 x i32> addrspace(1)* [[CAST_OUT]], align 4
; MESA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%in = load <16 x i32>, <16 x i32> addrspace(4)* %in.byref		%in = load <16 x i32>, <16 x i32> addrspace(4)* %in.byref
%cast.out = bitcast i32 addrspace(1)* %out to <16 x i32> addrspace(1)*		%cast.out = bitcast i32 addrspace(1)* %out to <16 x i32> addrspace(1)*
store volatile <16 x i32> %in, <16 x i32> addrspace(1)* %cast.out, align 4		store volatile <16 x i32> %in, <16 x i32> addrspace(1)* %cast.out, align 4
store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4		store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

; Also accept byref kernel arguments with other global address spaces.		; Also accept byref kernel arguments with other global address spaces.
define amdgpu_kernel void @byref_global_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* byref(i32) %in.byref) {		define amdgpu_kernel void @byref_global_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* byref(i32) %in.byref) {
; HSA-LABEL: @byref_global_i32_arg(		; HSA-LABEL: @byref_global_i32_arg(
; HSA-NEXT: [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(12) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 8		; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 8
; HSA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(1)*		; HSA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(1)*
; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(1) [[TMP1]], align 4		; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(1) [[TMP1]], align 4
; HSA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @byref_global_i32_arg(		; MESA-LABEL: @byref_global_i32_arg(
; MESA-NEXT: [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(48) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(68) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 44		; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 44
; MESA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(1)*		; MESA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(1)*
; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(1) [[TMP1]], align 4		; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(1) [[TMP1]], align 4
; MESA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%in = load i32, i32 addrspace(1)* %in.byref		%in = load i32, i32 addrspace(1)* %in.byref
store i32 %in, i32 addrspace(1)* %out, align 4		store i32 %in, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

define amdgpu_kernel void @byref_flat_i32_arg(i32 addrspace(1)* nocapture %out, i32* byref(i32) %in.byref) {		define amdgpu_kernel void @byref_flat_i32_arg(i32 addrspace(1)* nocapture %out, i32* byref(i32) %in.byref) {
; HSA-LABEL: @byref_flat_i32_arg(		; HSA-LABEL: @byref_flat_i32_arg(
; HSA-NEXT: [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(12) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 8		; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 8
; HSA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32*		; HSA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32*
; HSA-NEXT: [[IN:%.]] = load i32, i32 [[TMP1]], align 4		; HSA-NEXT: [[IN:%.]] = load i32, i32 [[TMP1]], align 4
; HSA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @byref_flat_i32_arg(		; MESA-LABEL: @byref_flat_i32_arg(
; MESA-NEXT: [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(48) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(68) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 44		; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 44
; MESA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32*		; MESA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32*
; MESA-NEXT: [[IN:%.]] = load i32, i32 [[TMP1]], align 4		; MESA-NEXT: [[IN:%.]] = load i32, i32 [[TMP1]], align 4
; MESA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%in = load i32, i32* %in.byref		%in = load i32, i32* %in.byref
store i32 %in, i32 addrspace(1)* %out, align 4		store i32 %in, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

define amdgpu_kernel void @byref_constant_32bit_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(6)* byref(i32) %in.byref) {		define amdgpu_kernel void @byref_constant_32bit_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(6)* byref(i32) %in.byref) {
; HSA-LABEL: @byref_constant_32bit_i32_arg(		; HSA-LABEL: @byref_constant_32bit_i32_arg(
; HSA-NEXT: [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(12) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 8		; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 8
; HSA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(6)*		; HSA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(6)*
; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(6) [[TMP1]], align 4		; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(6) [[TMP1]], align 4
; HSA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @byref_constant_32bit_i32_arg(		; MESA-LABEL: @byref_constant_32bit_i32_arg(
; MESA-NEXT: [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(48) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(68) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 44		; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 44
; MESA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(6)*		; MESA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(6)*
; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(6) [[TMP1]], align 4		; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(6) [[TMP1]], align 4
; MESA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%in = load i32, i32 addrspace(6)* %in.byref		%in = load i32, i32 addrspace(6)* %in.byref
store i32 %in, i32 addrspace(1)* %out, align 4		store i32 %in, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

define amdgpu_kernel void @byref_unknown_as_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(999)* byref(i32) %in.byref) {		define amdgpu_kernel void @byref_unknown_as_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(999)* byref(i32) %in.byref) {
; HSA-LABEL: @byref_unknown_as_i32_arg(		; HSA-LABEL: @byref_unknown_as_i32_arg(
; HSA-NEXT: [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(12) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 8		; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 8
; HSA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(999)*		; HSA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(999)*
; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(999) [[TMP1]], align 4		; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(999) [[TMP1]], align 4
; HSA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @byref_unknown_as_i32_arg(		; MESA-LABEL: @byref_unknown_as_i32_arg(
; MESA-NEXT: [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(48) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(68) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 44		; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 44
; MESA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(999)*		; MESA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(999)*
; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(999) [[TMP1]], align 4		; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(999) [[TMP1]], align 4
; MESA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%in = load i32, i32 addrspace(999)* %in.byref		%in = load i32, i32 addrspace(999)* %in.byref
store i32 %in, i32 addrspace(1)* %out, align 4		store i32 %in, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

; Invalid, but should not crash.		; Invalid, but should not crash.
define amdgpu_kernel void @byref_local_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(3)* byref(i32) %in.byref) {		define amdgpu_kernel void @byref_local_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(3)* byref(i32) %in.byref) {
; HSA-LABEL: @byref_local_i32_arg(		; HSA-LABEL: @byref_local_i32_arg(
; HSA-NEXT: [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(12) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(72) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 8		; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 8
; HSA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(3)*		; HSA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(3)*
; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(3) [[TMP1]], align 4		; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(3) [[TMP1]], align 4
; HSA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @byref_local_i32_arg(		; MESA-LABEL: @byref_local_i32_arg(
; MESA-NEXT: [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(48) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(68) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 44		; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 44
; MESA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(3)*		; MESA-NEXT: [[TMP1:%.]] = addrspacecast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(3)*
; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(3) [[TMP1]], align 4		; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(3) [[TMP1]], align 4
; MESA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; MESA-NEXT: store i32 [[IN]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%in = load i32, i32 addrspace(3)* %in.byref		%in = load i32, i32 addrspace(3)* %in.byref
store i32 %in, i32 addrspace(1)* %out, align 4		store i32 %in, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

define amdgpu_kernel void @multi_byref_constant_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* byref(i32) %in0.byref, i32 addrspace(4)* byref(i32) %in1.byref, i32 %after.offset) {		define amdgpu_kernel void @multi_byref_constant_i32_arg(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* byref(i32) %in0.byref, i32 addrspace(4)* byref(i32) %in1.byref, i32 %after.offset) {
; HSA-LABEL: @multi_byref_constant_i32_arg(		; HSA-LABEL: @multi_byref_constant_i32_arg(
; HSA-NEXT: [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(20) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(80) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; HSA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN0_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 8		; HSA-NEXT: [[IN0_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 8
; HSA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN0_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN0_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[IN1_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 12		; HSA-NEXT: [[IN1_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 12
; HSA-NEXT: [[TMP2:%.]] = bitcast i8 addrspace(4) [[IN1_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[TMP2:%.]] = bitcast i8 addrspace(4) [[IN1_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 16		; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 16
; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0		; HSA-NEXT: [[AFTER_OFFSET_LOAD:%.]] = load i32, i32 addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
; HSA-NEXT: [[IN0:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4		; HSA-NEXT: [[IN0:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4
; HSA-NEXT: [[IN1:%.]] = load i32, i32 addrspace(4) [[TMP2]], align 4		; HSA-NEXT: [[IN1:%.]] = load i32, i32 addrspace(4) [[TMP2]], align 4
; HSA-NEXT: store volatile i32 [[IN0]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store volatile i32 [[IN0]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: store volatile i32 [[IN1]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store volatile i32 [[IN1]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4		; HSA-NEXT: store volatile i32 [[AFTER_OFFSET_LOAD]], i32 addrspace(1)* [[OUT_LOAD]], align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @multi_byref_constant_i32_arg(		; MESA-LABEL: @multi_byref_constant_i32_arg(
; MESA-NEXT: [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(56) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(76) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[OUT_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*		; MESA-NEXT: [[OUT_KERNARG_OFFSET_CAST:%.]] = bitcast i8 addrspace(4) [[OUT_KERNARG_OFFSET]] to i32 addrspace(1)* addrspace(4)*
; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0		; MESA-NEXT: [[OUT_LOAD:%.]] = load i32 addrspace(1), i32 addrspace(1)* addrspace(4)* [[OUT_KERNARG_OFFSET_CAST]], align 4, !invariant.load !0
; MESA-NEXT: [[IN0_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 44		; MESA-NEXT: [[IN0_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 44
; MESA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN0_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN0_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[IN1_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 48		; MESA-NEXT: [[IN1_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 48
; MESA-NEXT: [[TMP2:%.]] = bitcast i8 addrspace(4) [[IN1_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[TMP2:%.]] = bitcast i8 addrspace(4) [[IN1_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 52		; MESA-NEXT: [[AFTER_OFFSET_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 52
Show All 11 Lines	;
store volatile i32 %in0, i32 addrspace(1)* %out, align 4		store volatile i32 %in0, i32 addrspace(1)* %out, align 4
store volatile i32 %in1, i32 addrspace(1)* %out, align 4		store volatile i32 %in1, i32 addrspace(1)* %out, align 4
store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4		store volatile i32 %after.offset, i32 addrspace(1)* %out, align 4
ret void		ret void
}		}

define amdgpu_kernel void @byref_constant_i32_arg_offset0(i32 addrspace(4)* byref(i32) %in.byref) {		define amdgpu_kernel void @byref_constant_i32_arg_offset0(i32 addrspace(4)* byref(i32) %in.byref) {
; HSA-LABEL: @byref_constant_i32_arg_offset0(		; HSA-LABEL: @byref_constant_i32_arg_offset0(
; HSA-NEXT: [[BYREF_CONSTANT_I32_ARG_OFFSET0_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(4) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; HSA-NEXT: [[BYREF_CONSTANT_I32_ARG_OFFSET0_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(64) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_OFFSET0_KERNARG_SEGMENT]], i64 0		; HSA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_OFFSET0_KERNARG_SEGMENT]], i64 0
; HSA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*		; HSA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*
; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4		; HSA-NEXT: [[IN:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4
; HSA-NEXT: store i32 [[IN]], i32 addrspace(1)* undef, align 4		; HSA-NEXT: store i32 [[IN]], i32 addrspace(1)* undef, align 4
; HSA-NEXT: ret void		; HSA-NEXT: ret void
;		;
; MESA-LABEL: @byref_constant_i32_arg_offset0(		; MESA-LABEL: @byref_constant_i32_arg_offset0(
; MESA-NEXT: [[BYREF_CONSTANT_I32_ARG_OFFSET0_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(40) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()		; MESA-NEXT: [[BYREF_CONSTANT_I32_ARG_OFFSET0_KERNARG_SEGMENT:%.]] = call nonnull align 16 dereferenceable(60) i8 addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_OFFSET0_KERNARG_SEGMENT]], i64 36		; MESA-NEXT: [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.]] = getelementptr inbounds i8, i8 addrspace(4) [[BYREF_CONSTANT_I32_ARG_OFFSET0_KERNARG_SEGMENT]], i64 36
; MESA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*		; MESA-NEXT: [[TMP1:%.]] = bitcast i8 addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to i32 addrspace(4)*
; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4		; MESA-NEXT: [[IN:%.]] = load i32, i32 addrspace(4) [[TMP1]], align 4
; MESA-NEXT: store i32 [[IN]], i32 addrspace(1)* undef, align 4		; MESA-NEXT: store i32 [[IN]], i32 addrspace(1)* undef, align 4
; MESA-NEXT: ret void		; MESA-NEXT: ret void
;		;
%in = load i32, i32 addrspace(4)* %in.byref		%in = load i32, i32 addrspace(4)* %in.byref
store i32 %in, i32 addrspace(1)* undef, align 4		store i32 %in, i32 addrspace(1)* undef, align 4
Show All 11 Lines

This is an archive of the discontinued LLVM Phabricator instance.

AMDGPU: Assume all amdhsa kernarg passed implicit arguments by defaultClosedPublic

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Diff 382119

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll

llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll

llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll

llvm/test/CodeGen/AMDGPU/cc-update.ll

llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll

llvm/test/CodeGen/AMDGPU/indirect-call.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll

llvm/test/CodeGen/AMDGPU/lower-kernargs.ll

AMDGPU: Assume all amdhsa kernarg passed implicit arguments by default
ClosedPublic