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[AMDGPU] Implement llvm.amdgcn.mulhi.[i,u]24 intrinsics.
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Authored by abinavpp on Oct 24 2021, 8:18 PM.

Details

Summary

These intrinsics maps to the 24-bit v_mul_hi instructions.

Diff Detail

Event Timeline

abinavpp created this revision.Oct 24 2021, 8:18 PM
abinavpp requested review of this revision.Oct 24 2021, 8:18 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 24 2021, 8:18 PM
foad added inline comments.Oct 25 2021, 7:40 AM
llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
283

Not your fault, but are these mulhi nodes really associative??

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.i24.ll
2

Can you add a -global-isel run line? Does it Just Work?

abinavpp updated this revision to Diff 382271.Oct 26 2021, 4:55 AM

Addressed review comments.

abinavpp marked an inline comment as done.Oct 26 2021, 4:57 AM
abinavpp added inline comments.
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.i24.ll
2

It's not working at the moment. I've added the mir version for now.

foad added inline comments.Oct 26 2021, 5:24 AM
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mulhi.i24.ll
2

It should be trivial to implement, just handle the mulhi intrinsics the same as the mul intrinsics in AMDGPURegisterBankInfo.

abinavpp updated this revision to Diff 382283.Oct 26 2021, 6:16 AM

Rebased; Addressed review comment.

abinavpp marked an inline comment as done.Oct 26 2021, 6:17 AM
foad accepted this revision.Oct 26 2021, 6:20 AM

LGTM, thanks.

This revision is now accepted and ready to land.Oct 26 2021, 6:20 AM
This revision was landed with ongoing or failed builds.Oct 26 2021, 6:23 AM
This revision was automatically updated to reflect the committed changes.