[Mips] Add glue between CopyFromReg, CopyToReg and RDHWR nodes for TLS

[jrtc27]

Summary

The MIPS ABI requires the thread pointer be accessed via rdhwr $3, $r29.
This is currently represented by (CopyToReg $3, (RDHWR $29)) followed by
a (CopyFromReg $3). However, there is no glue between these, meaning
scheduling can break those apart. In particular, PR51691 is a report
where PseudoSELECT_I was moved to between the CopyToReg and CopyFromReg,
and since its expansion uses branches, it split the def and use of the
physical register between two basic blocks, resulting in the def being
eliminated and the use having no def. It also seems possible that a
similar situation could arise splitting up the CopyToReg from the RDHWR,
causing the RDHWR to use a destination register other than $3, violating
the ABI requirement.

Thus, add glue between all three nodes to ensure they aren't split up
during instruction selection. No regression test is added since any test
would be implictly relying on specific scheduling behaviour, so whilst
it might be testing that glue is preventing reordering today, changes to
scheduling behaviour could result in the test no longer being able to
catch a regression here, as the reordering might no longer happen for
other unrelated reasons.

Fixes PR51691.

[atanasyan]

LGTM. Thanks for the fix.

[dim]

This worked OK for building both 32-bit and 64-bit mips worlds on FreeBSD. Thanks!

[jrtc27]

Is this worth backporting to 13, given a change in 13 is what exposed the underlying bug for FreeBSD? We can carry patches for FreeBSD but that won't help other people (or people using non-FreeBSD-originated compilers to compile FreeBSD, i.e. using a system LLVM on macOS or Linux to cross-compile it).

[jrtc27]

Ah I see the PR is already blocking release-13.0.1 (and release-13.0.0, but that ship has sailed).

llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

if (PtrVT == MVT::i32) {
       RdhwrOpc = Mips::RDHWR;
       DestReg = Mips::V1;
     } else {
       RdhwrOpc = Mips::RDHWR64;
       DestReg = Mips::V1_64;
     }
 
     SDNode *Rdhwr =
-        CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0),
+        CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0), MVT::Glue,
                                CurDAG->getRegister(Mips::HWR29, MVT::i32),
                                CurDAG->getTargetConstant(0, DL, MVT::i32));
     SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
-                                         SDValue(Rdhwr, 0));
-    SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
+                                         SDValue(Rdhwr, 0), SDValue(Rdhwr, 1));
+    SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT,
+                                             Chain.getValue(1));
     ReplaceNode(Node, ResNode.getNode());
     return true;
   }
 
   case ISD::BUILD_VECTOR: {
     // Select appropriate ldi.[bhwd] instructions for constant splats of
     // 128-bit when MSA is enabled. Fixup any register class mismatches that
     // occur as a result.

llvm/test/CodeGen/Mips/tls-static.ll

 ; STATICGP64-LABEL: f2:
 ; STATICGP64: lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(f2)))
 ; STATICGP64: daddiu  $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2)))
 ; STATICGP64: ld      $1, %gottprel(t2)($[[GP]])
 
 ; STATIC32-LABEL:   f2:
 ; STATIC32:   lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATIC32:   addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
-; STATIC32:   rdhwr   $3, $29{{$}}
 ; STATIC32:   lw      $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
+; STATIC32:   rdhwr   $3, $29{{$}}
 ; STATIC32:   addu    $[[R1:[0-9]+]], $3, $[[R0]]
 ; STATIC32:   lw      $2, 0($[[R1]])
 
 ; STATIC64-LABEL:   f2:
 ; STATIC64:   lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(f2)))
 ; STATIC64:   daddiu  $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2)))
-; STATIC64:   rdhwr   $3, $29{{$}}
 ; STATIC64:   ld      $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
+; STATIC64:   rdhwr   $3, $29{{$}}
 ; STATIC64:   daddu   $[[R1:[0-9]+]], $3, $[[R0]]
 ; STATIC64:   lw      $2, 0($[[R1]])
 }
 
 @f3.i = internal thread_local unnamed_addr global i32 1, align 4
 
 define dso_local i32 @f3() nounwind {
 entry: