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Differential D111434

[PowerPC] PPC backend optimization on conditional trap intrustions
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Authored by NeHuang on Oct 8 2021, 9:06 AM.

Details

Reviewers
nemanjai
stefanp
amyk
Group Reviewers
Restricted Project
Commits
rGae27ca9a6783: [PowerPC] PPC backend optimization on conditional trap intrustions
Summary

This patch adds PPC back end optimization to analyze the arguments of a conditional trap instruction to execute one of the following

  • Delete it if the condition is never true
  • Replace it with an unconditional trap if the condition is always true
  • Otherwise keep it

Diff Detail

Event Timeline

NeHuang created this revision.Oct 8 2021, 9:06 AM
Herald added subscribers: shchenz, JDevlieghere, kbarton, hiraditya. · View Herald TranscriptOct 8 2021, 9:07 AM
NeHuang requested review of this revision.Oct 8 2021, 9:07 AM
Harbormaster completed remote builds in B127801: Diff 378240.Oct 8 2021, 9:38 AM
NeHuang updated this revision to Diff 378284.Oct 8 2021, 9:51 AM

clang-format

Harbormaster completed remote builds in B127816: Diff 378284.Oct 8 2021, 10:18 AM
NeHuang added a comment.Oct 18 2021, 6:09 PM

gentle ping

NeHuang added a comment.Oct 25 2021, 8:07 AM

gentle ping

NeHuang added a reviewer: amyk.Oct 25 2021, 8:18 AM
nemanjai added inline comments.Oct 26 2021, 5:45 AM
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
1020

Seems that we should be able to handle all 4 in the same block:

  • Check that both operands are LI[8]/LI[S][8]+ORI[8] or an immediate
  • Set the variables for the three constants
  • Determine if this is an unconditional trap or never trap
  • Emit the correct instruction
amyk added inline comments.Oct 26 2021, 7:43 AM
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
1020

+1

1022

nit: Capitalize and add a period (and for all other comments).

NeHuang updated this revision to Diff 385282.Nov 6 2021, 8:54 AM
NeHuang marked 3 inline comments as done.

Address review comments

Harbormaster completed remote builds in B132849: Diff 385282.Nov 6 2021, 9:38 AM
amyk added inline comments.Nov 12 2021, 5:50 AM
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
1027
1029

Do we still need to take into account of the lis+ori that Nemanja mentioned?

1031
1037
nemanjai accepted this revision.Nov 12 2021, 6:49 AM

LGTM. There are some very minor nits that can be addressed on the commit.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
1027

Nit: naming convention - variables start with uppercase letters.

1028

I don't understand this comment. You say we can only do the optimization for the "reg + reg" form but the second condition is actually for the "reg + imm" form.

llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
6

Please add a couple more tests:

  1. Test case where we delete the instruction because it won't trap
  2. Test case(s) where we do some combination of comparisons (NE(24): <>, LE(20): <=, etc.)
This revision is now accepted and ready to land.Nov 12 2021, 6:49 AM
NeHuang marked 7 inline comments as done.Nov 16 2021, 8:09 AM
NeHuang added inline comments.
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
1029

IIUC, the optimization will be triggered if the immediate is a s16Immediate. We had the similar check and conversion in this patch https://reviews.llvm.org/D112285

NeHuang marked an inline comment as done.Nov 16 2021, 8:13 AM
NeHuang updated this revision to Diff 387652.Nov 16 2021, 8:15 AM

Addressed review comments

amyk accepted this revision.Nov 16 2021, 8:22 AM

Thanks for addressing the review comments and answering my question. This LGTM.

Harbormaster completed remote builds in B134536: Diff 387652.Nov 16 2021, 8:49 AM
This revision was landed with ongoing or failed builds.Nov 16 2021, 11:13 AM
Closed by commit rGae27ca9a6783: [PowerPC] PPC backend optimization on conditional trap intrustions (authored by NeHuang). · Explain Why
This revision was automatically updated to reflect the committed changes.
NeHuang added a commit: rGae27ca9a6783: [PowerPC] PPC backend optimization on conditional trap intrustions.

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
54 lines
test/
CodeGen/
PowerPC/
747 lines

Diff 387709

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

Show First 20 Lines • Show All 372 Lines • ▼ Show 20 Lines for (auto RegMBB : PHIOps)
NewPHI.add(RegMBB.first).add(RegMBB.second); NewPHI.add(RegMBB.first).add(RegMBB.second);
ChangedPHIMap[PHI] = NewPHI.getInstr(); ChangedPHIMap[PHI] = NewPHI.getInstr();
} }
} }
// Perform peephole optimizations. // Perform peephole optimizations.
bool PPCMIPeephole::simplifyCode(void) { bool PPCMIPeephole::simplifyCode(void) {
bool Simplified = false; bool Simplified = false;
bool TrapOpt = false;
MachineInstr* ToErase = nullptr; MachineInstr* ToErase = nullptr;
std::map<MachineInstr *, bool> TOCSaves; std::map<MachineInstr *, bool> TOCSaves;
const TargetRegisterInfo *TRI = &TII->getRegisterInfo(); const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
NumFunctionsEnteredInMIPeephole++; NumFunctionsEnteredInMIPeephole++;
if (ConvertRegReg) { if (ConvertRegReg) {
// Fixed-point conversion of reg/reg instructions fed by load-immediate // Fixed-point conversion of reg/reg instructions fed by load-immediate
// into reg/imm instructions. FIXME: This is expensive, control it with // into reg/imm instructions. FIXME: This is expensive, control it with
// an option. // an option.
Show All 25 Lines for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) { for (MachineInstr &MI : MBB) {
// If the previous instruction was marked for elimination, // If the previous instruction was marked for elimination,
// remove it now. // remove it now.
if (ToErase) { if (ToErase) {
ToErase->eraseFromParent(); ToErase->eraseFromParent();
ToErase = nullptr; ToErase = nullptr;
} }
// If a conditional trap instruction got optimized to an
// unconditional trap, eliminate all the instructions between
// the trap and the terminator of the MBB.
if (TrapOpt && !MI.isTerminator()) {
ToErase = &MI;
continue;
}
// Ignore debug instructions. // Ignore debug instructions.
if (MI.isDebugInstr()) if (MI.isDebugInstr())
continue; continue;
// Per-opcode peepholes. // Per-opcode peepholes.
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
▲ Show 20 Lines • Show All 571 Lines • ▼ Show 20 Lines for (MachineInstr &MI : MBB) {
case PPC::RLWINM_rec: case PPC::RLWINM_rec:
case PPC::RLWINM8: case PPC::RLWINM8:
case PPC::RLWINM8_rec: { case PPC::RLWINM8_rec: {
Simplified = TII->combineRLWINM(MI, &ToErase); Simplified = TII->combineRLWINM(MI, &ToErase);
if (Simplified) if (Simplified)
++NumRotatesCollapsed; ++NumRotatesCollapsed;
break; break;
} }
// We will replace TD/TW/TDI/TWI with an unconditional trap if it will
// always trap, we will delete the node if it will never trap.
case PPC::TDI:
case PPC::TWI:
nemanjaiUnsubmitted
Done
ReplyInline Actions

Seems that we should be able to handle all 4 in the same block:

  • Check that both operands are LI[8]/LI[S][8]+ORI[8] or an immediate
  • Set the variables for the three constants
  • Determine if this is an unconditional trap or never trap
  • Emit the correct instruction
nemanjai: Seems that we should be able to handle all 4 in the same block: - Check that both operands are…
amykUnsubmitted
Done
ReplyInline Actions

+1

amyk: +1
case PPC::TD:
case PPC::TW: {
amykUnsubmitted
Done
ReplyInline Actions

nit: Capitalize and add a period (and for all other comments).

amyk: nit: Capitalize and add a period (and for all other comments).
MachineInstr *LiMI1 = getVRegDefOrNull(&MI.getOperand(1), MRI);
MachineInstr *LiMI2 = getVRegDefOrNull(&MI.getOperand(2), MRI);
unsigned Opcode1 = LiMI1->getOpcode();
unsigned Opcode2 = LiMI2->getOpcode();
bool IsOperand2Immediate = MI.getOperand(2).isImm();
amykUnsubmitted
Done
ReplyInline Actions
unsigned Opcode2 = LiMI2->getOpcode();
- bool isOperand2Immeidate = MI.getOperand(2).isImm();
+ bool isOperand2Immediate = MI.getOperand(2).isImm();
// We can only do the optimization for the "reg + reg" form.
amyk:
nemanjaiUnsubmitted
Done
ReplyInline Actions

Nit: naming convention - variables start with uppercase letters.

nemanjai: Nit: naming convention - variables start with uppercase letters.
// We can only do the optimization if we can get immediates
nemanjaiUnsubmitted
Done
ReplyInline Actions

I don't understand this comment. You say we can only do the optimization for the "reg + reg" form but the second condition is actually for the "reg + imm" form.

nemanjai: I don't understand this comment. You say we can only do the optimization for the "reg + reg"…
// from both operands
amykUnsubmitted
Done
ReplyInline Actions

Do we still need to take into account of the lis+ori that Nemanja mentioned?

amyk: Do we still need to take into account of the lis+ori that Nemanja mentioned?
NeHuangAuthorUnsubmitted
Done
ReplyInline Actions

IIUC, the optimization will be triggered if the immediate is a s16Immediate. We had the similar check and conversion in this patch https://reviews.llvm.org/D112285

NeHuang: IIUC, the optimization will be triggered if the immediate is a s16Immediate. We had the similar…
if (!(LiMI1 && (Opcode1 == PPC::LI || Opcode1 == PPC::LI8)))
break;
amykUnsubmitted
Done
ReplyInline Actions
break;
- if (!isOperand2Immeidate &&
+ if (!isOperand2Immediate &&
!(LiMI2 && (Opcode2 == PPC::LI || Opcode2 == PPC::LI8)))
amyk:
if (!IsOperand2Immediate &&
!(LiMI2 && (Opcode2 == PPC::LI || Opcode2 == PPC::LI8)))
break;
auto ImmOperand0 = MI.getOperand(0).getImm();
auto ImmOperand1 = LiMI1->getOperand(1).getImm();
amykUnsubmitted
Done
ReplyInline Actions
auto ImmOperand1 = LiMI1->getOperand(1).getImm();
- auto ImmOperand2 = isOperand2Immeidate ? MI.getOperand(2).getImm()
+ auto ImmOperand2 = isOperand2Immediate ? MI.getOperand(2).getImm()
: LiMI2->getOperand(1).getImm();
amyk:
auto ImmOperand2 = IsOperand2Immediate ? MI.getOperand(2).getImm()
: LiMI2->getOperand(1).getImm();
// We will replace the MI with an unconditional trap if it will always
// trap.
if ((ImmOperand0 == 31) ||
((ImmOperand0 & 0x10) &&
((int64_t)ImmOperand1 < (int64_t)ImmOperand2)) ||
((ImmOperand0 & 0x8) &&
((int64_t)ImmOperand1 > (int64_t)ImmOperand2)) ||
((ImmOperand0 & 0x2) &&
((uint64_t)ImmOperand1 < (uint64_t)ImmOperand2)) ||
((ImmOperand0 & 0x1) &&
((uint64_t)ImmOperand1 > (uint64_t)ImmOperand2)) ||
((ImmOperand0 & 0x4) && (ImmOperand1 == ImmOperand2))) {
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::TRAP));
TrapOpt = true;
}
// We will delete the MI if it will never trap.
ToErase = &MI;
Simplified = true;
break;
}
} }
} }
// If the last instruction was marked for elimination, // If the last instruction was marked for elimination,
// remove it now. // remove it now.
if (ToErase) { if (ToErase) {
ToErase->eraseFromParent(); ToErase->eraseFromParent();
ToErase = nullptr; ToErase = nullptr;
} }
// Reset TrapOpt to false at the end of the basic block.
TrapOpt = false;
} }
// Eliminate all the TOC save instructions which are redundant. // Eliminate all the TOC save instructions which are redundant.
Simplified |= eliminateRedundantTOCSaves(TOCSaves); Simplified |= eliminateRedundantTOCSaves(TOCSaves);
PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>(); PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
if (FI->mustSaveTOC()) if (FI->mustSaveTOC())
NumTOCSavesInPrologue++; NumTOCSavesInPrologue++;
▲ Show 20 Lines • Show All 654 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir

  • This file was added.
# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
# RUN: -verify-machineinstrs -start-before=ppc-mi-peepholes | FileCheck %s
---
name: conditional_trap_opt_reg_implicit_def
alignment: 16
nemanjaiUnsubmitted
Done
ReplyInline Actions

Please add a couple more tests:

  1. Test case where we delete the instruction because it won't trap
  2. Test case(s) where we do some combination of comparisons (NE(24): <>, LE(20): <=, etc.)
nemanjai: Please add a couple more tests: 1. Test case where we delete the instruction because it won't…
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = IMPLICIT_DEF
%1:gprc = IMPLICIT_DEF
%2:g8rc = IMPLICIT_DEF
%3:g8rc = IMPLICIT_DEF
TW 8, %0, %1
TD 8, %2, %3
TWI 24, %0, 0
TDI 24, %2, 0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_reg_implicit_def
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: twgt 3, 3
# CHECK-NEXT: tdgt 3, 3
# CHECK-NEXT: twnei 3, 0
# CHECK-NEXT: tdnei 3, 0
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TW_31
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 3
%1:gprc = LI 0
TW 31, %1, %0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TW_31
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TW_24
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 3
%1:gprc = LI 0
TW 24, %1, %0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TW_24
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_no_trap_TW_24
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 3
%1:gprc = LI 3
TW 24, %1, %0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_no_trap_TW_24
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TW_20
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 3
%1:gprc = LI 3
TW 20, %1, %0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TW_20
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_no_trap_TW_20
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 3
%1:gprc = LI 5
TW 20, %1, %0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_no_trap_TW_20
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: blr
---
name: conditional_trap_opt_no_trap_TW_16
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 5
%1:gprc = LI 1
TW 16, %0, %1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_no_trap_TW_16
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TW_16
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 5
%1:gprc = LI 1
TW 16, %1, %0
TW 16, %0, %1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TW_16
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TW_8
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI -1
%1:gprc = LI 10
TW 8, %1, %0
TW 8, %0, %1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TW_8
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TW_2
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI -1
%1:gprc = LI 2
TW 2, %1, %0
TW 2, %0, %1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TW_2
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TW_1
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI -3
%1:gprc = LI 4
TW 1, %1, %0
TW 1, %0, %1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TW_1
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TW_4
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 5
%1:gprc = LI 1
TW 4, %1, %0
TW 4, %1, %1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TW_4
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TWI_31
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 3
TWI 31, %0, 0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TWI_31
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TWI_24
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 3
TWI 24, %0, 0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TWI_24
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_no_trap_TWI_24
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 0
TWI 24, %0, 0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_no_trap_TWI_24
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TWI_20
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 3
TWI 20, %0, 3
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TWI_20
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_no_trap_TWI_20
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 3
TWI 20, %0, 0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_no_trap_TWI_20
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: blr
---
name: conditional_trap_opt_no_trap_TWI_16
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 5
TWI 16, %0, 1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_no_trap_TWI_16
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TWI_16
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 5
%1:gprc = LI 1
TWI 16, %1, 5
TWI 16, %0, 1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TWI_16
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TWI_8
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI -1
%1:gprc = LI 10
TWI 8, %1, -1
TWI 8, %0, 10
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TWI_8
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TWI_2
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI -1
%1:gprc = LI 2
TWI 2, %1, -1
TWI 2, %0, 2
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TWI_2
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TWI_1
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI -3
%1:gprc = LI 4
TWI 1, %1, -3
TWI 1, %0, 4
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TWI_1
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TWI_4
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 5
%1:gprc = LI 1
TWI 4, %1, 5
TWI 4, %1, 1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TWI_4
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TD_31
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 3
%1:g8rc = LI8 0
TD 31, %1, %0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TD_31
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TD_24
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 3
%1:g8rc = LI8 0
TD 24, %1, %0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TD_24
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_no_trap_TD_24
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 3
%1:g8rc = LI8 3
TD 24, %1, %0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_no_trap_TD_24
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TD_20
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 3
%1:g8rc = LI8 3
TD 20, %1, %0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TD_20
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_no_trap_TD_20
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 3
%1:g8rc = LI8 5
TD 20, %1, %0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_no_trap_TD_20
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: blr
---
name: conditional_trap_opt_no_trap_TD_16
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 5
%1:g8rc = LI8 1
TD 16, %0, %1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_no_trap_TD_16
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TD_16
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 5
%1:g8rc = LI8 1
TD 16, %1, %0
TD 16, %0, %1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TD_16
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TD_8
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 -1
%1:g8rc = LI8 10
TD 8, %1, %0
TD 8, %0, %1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TD_8
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TD_2
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 -1
%1:g8rc = LI8 2
TD 2, %1, %0
TD 2, %0, %1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TD_2
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TD_1
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 -3
%1:g8rc = LI8 4
TD 1, %1, %0
TD 1, %0, %1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TD_1
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TD_4
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 5
%1:g8rc = LI8 1
TD 4, %1, %0
TD 4, %1, %1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TD_4
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TDI_31
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 3
TDI 31, %0, 0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TDI_31
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TDI_24
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 3
TDI 24, %0, 0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TDI_24
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_no_trap_TDI_24
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 0
TDI 24, %0, 0
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_no_trap_TDI_24
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TDI_20
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 3
TDI 20, %0, 3
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TDI_20
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_no_trap_TDI_20
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 5
TDI 20, %0, 3
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_no_trap_TDI_20
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: blr
---
name: conditional_trap_opt_no_trap_TDI_16
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 5
TDI 16, %0, 1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_no_trap_TDI_16
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TDI_16
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 5
%1:g8rc = LI8 1
TDI 16, %1, 5
TDI 16, %0, 1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TDI_16
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TDI_8
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 -1
%1:g8rc = LI8 10
TDI 8, %1, -1
TDI 8, %0, 10
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TDI_8
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TDI_2
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 -1
%1:g8rc = LI8 2
TDI 2, %1, -1
TDI 2, %0, 2
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TDI_2
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TDI_1
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 -3
%1:g8rc = LI8 4
TDI 1, %1, -3
TDI 1, %0, 4
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TDI_1
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_TDI_4
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:g8rc = LI8 5
%1:g8rc = LI8 1
TDI 4, %1, 5
TDI 4, %1, 1
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_TDI_4
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr
---
name: conditional_trap_opt_multiple_traps
alignment: 16
tracksRegLiveness: true
body: |
bb.0.entry:
%0:gprc = LI 5
%1:gprc = LI 1
%2:g8rc = LI8 -1
%3:g8rc = LI8 0
TWI 31, %1, 5
TDI 31, %3, 0
TW 31, %0, %1
TD 31, %2, %2
BLR8 implicit $lr8, implicit $rm
...
# CHECK-LABEL: conditional_trap_opt_multiple_traps
# CHECK: # %bb.0: # %entry
# CHECK-NEXT: trap
# CHECK-NEXT: blr