This is an archive of the discontinued LLVM Phabricator instance.

[lldb] Remove "dwarf dynamic register size expressions" from RegisterInfo
ClosedPublic

Authored by labath on Oct 1 2021, 3:09 AM.

Details

Summary

These were added to support some mips registers on linux, but linux mips
support has now been removed due.

They are still referenced in the freebds mips implementation, but the
completeness of that implementation is also unknown. All other
architectures just set these fields to zero, which is a cause of
significant bloat in our register info definitions.

Arm also has registers with variable sizes, but they were implemented in
a more gdb-compatible fashion and don't use this feature.

Diff Detail

Event Timeline

labath created this revision.Oct 1 2021, 3:09 AM
labath requested review of this revision.Oct 1 2021, 3:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 1 2021, 3:09 AM
jrtc27 added a comment.Oct 1 2021, 4:18 AM

Is this removing this going to be a problem for RISC-V, where the floating-point registers could be 32-bit or 64-bit (or 128-bit in future), depending on which extensions you have?

labath added a comment.Oct 1 2021, 4:26 AM

Is this removing this going to be a problem for RISC-V, where the floating-point registers could be 32-bit or 64-bit (or 128-bit in future), depending on which extensions you have?

Is the size of the register fixed for the lifetime of a process ? If yes (it sounds like this is the case), then this is not a problem, as you'd just need to provide the correct definitions when the process is created.

And if their size can change, then it's still should not be a problem, as you can copy the ARM SVE model. (One of the reasons for removing this is to avoid having two ways of doing the same thing.)

mgorny accepted this revision.Oct 1 2021, 5:29 AM

Thanks for doing this. The baseline code LGTM but I haven't verified the register enumerations ;-).

This revision is now accepted and ready to land.Oct 1 2021, 5:29 AM
jrtc27 added a comment.Oct 6 2021, 5:23 AM

Is this removing this going to be a problem for RISC-V, where the floating-point registers could be 32-bit or 64-bit (or 128-bit in future), depending on which extensions you have?

Is the size of the register fixed for the lifetime of a process ? If yes (it sounds like this is the case), then this is not a problem, as you'd just need to provide the correct definitions when the process is created.

And if their size can change, then it's still should not be a problem, as you can copy the ARM SVE model. (One of the reasons for removing this is to avoid having two ways of doing the same thing.)

Meant to reply to this (and thought I had) but somehow didn't end up doing it...

Technically no if you write to hardware configuration registers to change what extensions are enabled (which limits it to kernels and higher, not userspace), but I doubt anyone expects that to work nicely in a debugger.