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Differential D110802

[GlobalISel] Extend CombinerHelper::matchConstantOp() to match constant splat vectors
ClosedPublic

Authored by aemerson on Sep 30 2021, 12:31 AM.

Details

Reviewers
paquette
foad
arsenm
Commits
rGca8316b7048d: [GlobalISel] Extend CombinerHelper::matchConstantOp() to match constant splat…
Summary

This allows the "x op 0 -> x" fold to optimize vector constant RHSs.

Diff Detail

Event Timeline

aemerson created this revision.Sep 30 2021, 12:31 AM
Herald added subscribers: hiraditya, rovka. · View Herald TranscriptSep 30 2021, 12:31 AM
aemerson requested review of this revision.Sep 30 2021, 12:31 AM
Herald added a subscriber: wdng. · View Herald TranscriptSep 30 2021, 12:31 AM
aemerson added a parent revision: D110786: [GlobalISel] Extend G_SELECT of known condition combine to vectors..Sep 30 2021, 12:31 AM
foad added inline comments.Sep 30 2021, 12:57 AM
llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir
33–36

Could you regenerate the checks and commit before this patch, to avoid all the CHECK-NEXT churn?

Harbormaster completed remote builds in B126501: Diff 376118.Sep 30 2021, 1:13 AM
aemerson mentioned this in rG2e7deee376aa: [AArch64][GlobalISel] Re-generate some tests for D110802..Sep 30 2021, 4:16 AM
aemerson updated this revision to Diff 376157.Sep 30 2021, 4:18 AM

Rebase after test re-gen.

Harbormaster completed remote builds in B126523: Diff 376157.Sep 30 2021, 5:08 AM
foad accepted this revision.Sep 30 2021, 5:11 AM
This revision is now accepted and ready to land.Sep 30 2021, 5:11 AM
Closed by commit rGca8316b7048d: [GlobalISel] Extend CombinerHelper::matchConstantOp() to match constant splat… (authored by aemerson). · Explain WhySep 30 2021, 2:31 PM
This revision was automatically updated to reflect the committed changes.
aemerson added a commit: rGca8316b7048d: [GlobalISel] Extend CombinerHelper::matchConstantOp() to match constant splat….

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
6 lines
test/
CodeGen/
AArch64/
GlobalISel/
18 lines
32 lines

Diff 376371

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Show First 20 Lines • Show All 2,334 Lines • ▼ Show 20 Lines return I1->findRegisterDefOperandIdx(InstAndDef1->Reg) ==
I2->findRegisterDefOperandIdx(InstAndDef2->Reg); I2->findRegisterDefOperandIdx(InstAndDef2->Reg);
} }
return false; return false;
} }
bool CombinerHelper::matchConstantOp(const MachineOperand &MOP, int64_t C) { bool CombinerHelper::matchConstantOp(const MachineOperand &MOP, int64_t C) {
if (!MOP.isReg()) if (!MOP.isReg())
return false; return false;
// MIPatternMatch doesn't let us look through G_ZEXT etc. auto *MI = MRI.getVRegDef(MOP.getReg());
auto ValAndVReg = getIConstantVRegValWithLookThrough(MOP.getReg(), MRI); auto MaybeCst = isConstantOrConstantSplatVector(*MI, MRI);
return ValAndVReg && ValAndVReg->Value == C; return MaybeCst.hasValue() && MaybeCst->getSExtValue() == C;
} }
bool CombinerHelper::replaceSingleDefInstWithOperand(MachineInstr &MI, bool CombinerHelper::replaceSingleDefInstWithOperand(MachineInstr &MI,
unsigned OpIdx) { unsigned OpIdx) {
assert(MI.getNumExplicitDefs() == 1 && "Expected one explicit def?"); assert(MI.getNumExplicitDefs() == 1 && "Expected one explicit def?");
Register OldReg = MI.getOperand(0).getReg(); Register OldReg = MI.getOperand(0).getReg();
Register Replacement = MI.getOperand(OpIdx).getReg(); Register Replacement = MI.getOperand(OpIdx).getReg();
assert(canReplaceReg(OldReg, Replacement, MRI) && "Cannot replace register?"); assert(canReplaceReg(OldReg, Replacement, MRI) && "Cannot replace register?");
▲ Show 20 Lines • Show All 2,063 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/combine-mul.mir

Show All 25 Lines
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
maxAlignment: 1 maxAlignment: 1
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0: bb.0:
liveins: $q0 liveins: $q0
; Currently not implemented.
; CHECK-LABEL: name: mul_vector_by_zero ; CHECK-LABEL: name: mul_vector_by_zero
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32) ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[COPY]], [[BUILD_VECTOR]] ; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)
; CHECK-NEXT: $q0 = COPY [[MUL]](<4 x s32>)
%0:_(<4 x s32>) = COPY $q0 %0:_(<4 x s32>) = COPY $q0
%1:_(s32) = G_CONSTANT i32 0 %1:_(s32) = G_CONSTANT i32 0
%2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32) %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
%3:_(<4 x s32>) = G_MUL %0, %2(<4 x s32>) %3:_(<4 x s32>) = G_MUL %0, %2(<4 x s32>)
$q0 = COPY %3(<4 x s32>) $q0 = COPY %3(<4 x s32>)
... ...
--- ---
name: mul_by_one name: mul_by_one
Show All 20 Lines
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
maxAlignment: 1 maxAlignment: 1
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0: bb.0:
liveins: $q0 liveins: $q0
; Currently not implemented.
; CHECK-LABEL: name: mul_vector_by_one ; CHECK-LABEL: name: mul_vector_by_one
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: $q0 = COPY [[COPY]](<4 x s32>)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[COPY]], [[BUILD_VECTOR]]
; CHECK-NEXT: $q0 = COPY [[MUL]](<4 x s32>)
%0:_(<4 x s32>) = COPY $q0 %0:_(<4 x s32>) = COPY $q0
%1:_(s32) = G_CONSTANT i32 1 %1:_(s32) = G_CONSTANT i32 1
%2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32) %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
%3:_(<4 x s32>) = G_MUL %0, %2(<4 x s32>) %3:_(<4 x s32>) = G_MUL %0, %2(<4 x s32>)
$q0 = COPY %3(<4 x s32>) $q0 = COPY %3(<4 x s32>)
... ...
--- ---
name: mul_by_neg_one name: mul_by_neg_one
Show All 22 Lines
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
maxAlignment: 1 maxAlignment: 1
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0: bb.0:
liveins: $q0 liveins: $q0
; Currently not implemented.
; CHECK-LABEL: name: mul_vector_by_neg_one ; CHECK-LABEL: name: mul_vector_by_neg_one
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32) ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[COPY]], [[BUILD_VECTOR]] ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[BUILD_VECTOR]], [[COPY]]
; CHECK-NEXT: $q0 = COPY [[MUL]](<4 x s32>) ; CHECK-NEXT: $q0 = COPY [[SUB]](<4 x s32>)
%0:_(<4 x s32>) = COPY $q0 %0:_(<4 x s32>) = COPY $q0
%1:_(s32) = G_CONSTANT i32 -1 %1:_(s32) = G_CONSTANT i32 -1
%2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32) %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
%3:_(<4 x s32>) = G_MUL %0, %2(<4 x s32>) %3:_(<4 x s32>) = G_MUL %0, %2(<4 x s32>)
$q0 = COPY %3(<4 x s32>) $q0 = COPY %3(<4 x s32>)
... ...

llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir

Show All 24 Lines
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $w0 liveins: $w0
; Fold (x + 0) -> x ; Fold (x + 0) -> x
; ;
; CHECK-LABEL: name: right_ident_add ; CHECK-LABEL: name: right_ident_add
; CHECK: liveins: $w0 ; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0 ; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: $w0 = COPY %x(s32) ; CHECK-NEXT: $w0 = COPY %x(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0 ; CHECK-NEXT: RET_ReallyLR implicit $w0
foadUnsubmitted
Not Done
ReplyInline Actions

Could you regenerate the checks and commit before this patch, to avoid all the CHECK-NEXT churn?

foad: Could you regenerate the checks and commit before this patch, to avoid all the CHECK-NEXT churn?
%x:_(s32) = COPY $w0 %x:_(s32) = COPY $w0
%cst:_(s32) = G_CONSTANT i32 0 %cst:_(s32) = G_CONSTANT i32 0
%op:_(s32) = G_ADD %x(s32), %cst %op:_(s32) = G_ADD %x(s32), %cst
$w0 = COPY %op(s32) $w0 = COPY %op(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
--- ---
▲ Show 20 Lines • Show All 328 Lines • ▼ Show 20 Lines bb.0:
; CHECK-NEXT: $w0 = COPY %copy(s32) ; CHECK-NEXT: $w0 = COPY %copy(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0 ; CHECK-NEXT: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0 %copy:_(s32) = COPY $w0
%zero:_(s32) = G_CONSTANT i32 0 %zero:_(s32) = G_CONSTANT i32 0
%rot:_(s32) = G_ROTR %copy(s32), %zero(s32) %rot:_(s32) = G_ROTR %copy(s32), %zero(s32)
$w0 = COPY %rot(s32) $w0 = COPY %rot(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
---
name: lshr_of_vec_zero
body: |
bb.1:
liveins: $q0
; CHECK-LABEL: name: lshr_of_vec_zero
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: $q0 = COPY [[COPY]](<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<8 x s16>) = COPY $q0
%5:_(s16) = G_CONSTANT i16 0
%zero_vec:_(<8 x s16>) = G_BUILD_VECTOR %5(s16), %5(s16), %5(s16), %5(s16), %5(s16), %5(s16), %5(s16), %5(s16)
%shift:_(<8 x s16>) = G_LSHR %0, %zero_vec(<8 x s16>)
$q0 = COPY %shift(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: ptradd_of_vec_zero
body: |
bb.1:
liveins: $q0
; CHECK-LABEL: name: ptradd_of_vec_zero
; CHECK: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
; CHECK-NEXT: $q0 = COPY [[COPY]](<2 x p0>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<2 x p0>) = COPY $q0
%5:_(s64) = G_CONSTANT i64 0
%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %5(s64), %5(s64)
%ptr:_(<2 x p0>) = G_PTR_ADD %0, %zero_vec(<2 x s64>)
$q0 = COPY %ptr(<2 x p0>)
RET_ReallyLR implicit $q0
...