BPF: implement isLegalAddressingMode() properly

[yonghong-song]

Summary

Latest upstream llvm caused the kernel bpf selftest emitting the
following warnings:

In file included from progs/profiler3.c:6:
progs/profiler.inc.h:489:2: warning: loop not unrolled:
  the optimizer was unable to perform the requested transformation;
  the transformation might be disabled or specified as part of an unsupported
  transformation ordering [-Wpass-failed=transform-warning]
        for (int i = 0; i < MAX_PATH_DEPTH; i++) {
        ^

Further bisecting shows this SimplifyCFG patch ([1]) changed
the condition on how to fold branch to common dest. This caused
some unroll pragma is not honored in selftests/bpf.

The patch [1] test getUserCost() as the condition to
perform the certain basic block folding transformation.
For the above example, before the loop unroll pass, the control flow
looks like:

cond_block:
   branch target: body_block, cleanup_block
body_block:
   branch target: cleanup_block, end_block
end_block:
   branch target: cleanup_block, end10_block
end10_block:
   %add.ptr = getelementptr i8, i8* %payload.addr.0, i64 %call2
   %inc = add nuw nsw i32 %i.0, 1
   branch target: cond_block

In the above, %call2 is an unknown scalar.

Before patch [1], end10_block will be folded into end_block, forming
the code like

cond_block:
   branch target: body_block, cleanup_block 
body_block:
   branch target: cleanup_block, end_block
end_block:
   branch target: cleanup_block, cond_block

and the compiler is happy to perform unrolling.

With patch [1], getUserCost(), which calls getGEPCost(), which calls
isLegalAddressingMode() in TargetLoweringBase.cpp, considers IR

%add.ptr = getelementptr i8, i8* %payload.addr.0, i64 %call2

is free, so the above basic block folding transformation is not performed
and unrolling does not happen.

For BPF target, the IR

%add.ptr = getelementptr i8, i8* %payload.addr.0, i64 %call2

is not free and we don't have ld/st instruction address with 'r+r' mode.

This patch implemented a BPF hook for isLegalAddressingMode(), which is
identical to Mips isLegalAddressingMode() implementation where
the address pattern like 'r+r', 'r+r+i' or '2*r' are not allowed.
With testing kernel bpf selftests, all loop not unrolled warnings
are gone and all selftests run successfully.

[1] https://reviews.llvm.org/D108837

[yonghong-song]

Implement isLegalAddressingMode() instead of getGEPCost()

llvm/lib/Target/BPF/BPFISelLowering.h

private:
   //   ctx = ctx + reloc_offset
   //   ... (*(u8 *)(ctx + 1)) & 0x80 ...
   // which will be rejected by the verifier.
   bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
                              EVT NewVT) const override {
     return false;
   }
 
+  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
+                             Type *Ty, unsigned AS,
+                             Instruction *I = nullptr) const override;
+
   // isTruncateFree - Return true if it's free to truncate a value of
   // type Ty1 to type Ty2. e.g. On BPF at alu32 mode, it's free to truncate
   // a i64 value in register R1 to i32 by referencing its sub-register W1.
   bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
   bool isTruncateFree(EVT VT1, EVT VT2) const override;
 
   // For 32bit ALU result zext to 64bit is free.
   bool isZExtFree(Type *Ty1, Type *Ty2) const override;

llvm/lib/Target/BPF/BPFISelLowering.cpp

EVT BPFTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
                                           EVT VT) const {
   return getHasAlu32() ? MVT::i32 : MVT::i64;
 }
 
 MVT BPFTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
                                               EVT VT) const {
   return (getHasAlu32() && VT == MVT::i32) ? MVT::i32 : MVT::i64;
 }
+
+bool BPFTargetLowering::isLegalAddressingMode(const DataLayout &DL,
+                                              const AddrMode &AM, Type *Ty,
+                                              unsigned AS,
+                                              Instruction *I) const {
+  // No global is ever allowed as a base.
+  if (AM.BaseGV)
+    return false;
+
+  switch (AM.Scale) {
+  case 0: // "r+i" or just "i", depending on HasBaseReg.
+    break;
+  case 1:
+    if (!AM.HasBaseReg) // allow "r+i".
+      break;
+    return false; // disallow "r+r" or "r+r+i".
+  default:
+    return false;
+  }
+
+  return true;
+}