[ARM] Fold ARMISD::ADDC with no carry uses to ISD::ADD

[dmgreen]

Summary

An ARMISD::ADDC (which is really an ADDS), for which the flags (second output value) are never used is equivalent to a normal ADD. Same goes for ARMISD:SUBC -> SUB, which helps prevent an infinite loop during DAG combining.

[efriedma]

LGTM. (please clang-format patch before merging.)

[dmgreen]

I missed a couple of tests here, where uadd.sat is a little worse now as it does not realize it can fold conditions any more after creating add, as opposed to adds.

In the meantime, before that is fixed, I've put a simpler fix in a2332d5332c3ede49adf1c71481e9efab7ca88c7 to prevent the infinite combining.

llvm/lib/Target/ARM/ARMISelLowering.cpp

static SDValue AddCombineTo64bitUMAAL(SDNode *AddeNode,
   // as the addend, and it's handled in PerformUMLALCombine.
 
   if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
     return AddCombineTo64bitMLAL(AddeNode, DCI, Subtarget);
 
   // Check that we have a glued ADDC node.
   SDNode* AddcNode = AddeNode->getOperand(2).getNode();
   if (AddcNode->getOpcode() != ARMISD::ADDC)
     return SDValue();
 
   // Find the converted UMAAL or quit if it doesn't exist.
   SDNode *UmlalNode = nullptr;
   SDValue AddHi;
   if (AddcNode->getOperand(0).getOpcode() == ARMISD::UMLAL) {
     UmlalNode = AddcNode->getOperand(0).getNode();
     AddHi = AddcNode->getOperand(1);
   } else if (AddcNode->getOperand(1).getOpcode() == ARMISD::UMLAL) {
else
     return SDValue();
 }
 
 static SDValue PerformAddcSubcCombine(SDNode *N,
                                       TargetLowering::DAGCombinerInfo &DCI,
                                       const ARMSubtarget *Subtarget) {
   SelectionDAG &DAG(DCI.DAG);
 
+  if (!N->hasAnyUseOfValue(1)) {
+    SDValue Add = DCI.DAG.getNode(
+        (N->getOpcode() == ARMISD::ADDC) ? ISD::ADD : ISD::SUB, SDLoc(N),
+        MVT::i32, N->getOperand(0), N->getOperand(1));
+    return DCI.CombineTo(N, Add, DCI.DAG.getUNDEF(MVT::i32));
+  }
+
   if (N->getOpcode() == ARMISD::SUBC) {
     // (SUBC (ADDE 0, 0, C), 1) -> C
     SDValue LHS = N->getOperand(0);
     SDValue RHS = N->getOperand(1);
     if (LHS->getOpcode() == ARMISD::ADDE &&
         isNullConstant(LHS->getOperand(0)) &&
         isNullConstant(LHS->getOperand(1)) && isOneConstant(RHS)) {
       return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2));

llvm/test/CodeGen/ARM/select_const.ll

 ; THUMB-NEXT:  @ %bb.4:
 ; THUMB-NEXT:  .LCPI25_0:
 ; THUMB-NEXT:    .long 65537 @ 0x10001
   %sel = select i1 %cond, i64 65537, i64 23
   %bo = and i64 %sel, 65537
   ret i64 %bo
 }
 
+define i64 @func(i64 %arg) {
+; ARM-LABEL: func:
+; ARM:       @ %bb.0: @ %entry
+; ARM-NEXT:    adds r0, r0, #1
+; ARM-NEXT:    mov r2, #0
+; ARM-NEXT:    adcs r0, r1, #0
+; ARM-NEXT:    mov r1, #0
+; ARM-NEXT:    adcs r0, r2, #0
+; ARM-NEXT:    movne r0, #8
+; ARM-NEXT:    mov pc, lr
+;
+; THUMB2-LABEL: func:
+; THUMB2:       @ %bb.0: @ %entry
+; THUMB2-NEXT:    adds r0, #1
+; THUMB2-NEXT:    mov.w r2, #0
+; THUMB2-NEXT:    adcs r0, r1, #0
+; THUMB2-NEXT:    mov.w r1, #0
+; THUMB2-NEXT:    adcs r0, r2, #0
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #8
+; THUMB2-NEXT:    bx lr
+;
+; THUMB-LABEL: func:
+; THUMB:       @ %bb.0: @ %entry
+; THUMB-NEXT:    .save {r4, lr}
+; THUMB-NEXT:    push {r4, lr}
+; THUMB-NEXT:    movs r2, #0
+; THUMB-NEXT:    adds r3, r0, #1
+; THUMB-NEXT:    push {r1}
+; THUMB-NEXT:    pop {r3}
+; THUMB-NEXT:    adcs r3, r2
+; THUMB-NEXT:    push {r2}
+; THUMB-NEXT:    pop {r3}
+; THUMB-NEXT:    adcs r3, r2
+; THUMB-NEXT:    subs r4, r3, #1
+; THUMB-NEXT:    adds r0, r0, #1
+; THUMB-NEXT:    adcs r1, r2
+; THUMB-NEXT:    sbcs r3, r4
+; THUMB-NEXT:    lsls r0, r3, #3
+; THUMB-NEXT:    movs r1, r2
+; THUMB-NEXT:    pop {r4}
+; THUMB-NEXT:    pop {r2}
+; THUMB-NEXT:    bx r2
+entry:
+  %0 = add i64 %arg, 1
+  %1 = icmp ult i64 %0, 1
+  %2 = select i1 %1, i64 8, i64 0
+  ret i64 %2
+}