[PowerPC] Guard XSRSP in P8 for FastISel

[jsji]

Summary

This is exposed by enabling FastIsel on 64bit AIX.
We are generating XSRSP regardless of the arch,
which may be wrong when -mcpu=pwr7.

The fix is to guard the generation in P8 only.

[qiucf]

Thanks for the fix. LGTM

llvm/lib/Target/PowerPC/PPCFastISel.cpp

bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
   if (!SrcReg)
     return false;
 
   // Round the result to single precision.
   unsigned DestReg;
   auto RC = MRI.getRegClass(SrcReg);
   if (Subtarget->hasSPE()) {
     DestReg = createResultReg(&PPC::GPRCRegClass);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-      TII.get(PPC::EFSCFD), DestReg)
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::EFSCFD),
+            DestReg)
         .addReg(SrcReg);
-  } else if (isVSFRCRegClass(RC)) {
+  } else if (Subtarget->hasP8Vector() && isVSFRCRegClass(RC)) {
     DestReg = createResultReg(&PPC::VSSRCRegClass);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-      TII.get(PPC::XSRSP), DestReg)
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::XSRSP),
+            DestReg)
         .addReg(SrcReg);
   } else {
+    SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg);
     DestReg = createResultReg(&PPC::F4RCRegClass);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
       TII.get(PPC::FRSP), DestReg)
       .addReg(SrcReg);
   }
 
   updateValueMap(I, DestReg);
   return true;

llvm/test/CodeGen/PowerPC/fast-isel-rsp.ll

 ; RUN: llc -mcpu=generic -mtriple=powerpc64le-unknown-unknown -O0 < %s \ 
 ; RUN:   -verify-machineinstrs | FileCheck %s --check-prefix=GENERIC
 ; RUN: llc -mcpu=ppc -mtriple=powerpc64le-unknown-unknown -O0 < %s \
 ; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -O0 < %s \
+; RUN:   -verify-machineinstrs | FileCheck %s
+
+
 
 define float @testRSP(double %x) {
 entry:
   %0 = fptrunc double %x to float
   ret float %0
 ; CHECK: frsp 1, 1
 ; GENERIC: xsrsp 1, 1
 }