[X86] Fold (and (or (xor X, -1), Y), Z) -> PTERNLOG Z, Y, X, 0xD0

[RKSimon]

We do most TERNLOG matching inside X86DAGToDAGISel::tryVPTERNLOG (which has a 'FIXME: Handle inverted inputs?' comment) - might it be possible to handle this there?

[pengfei]

In D109273#2983658, @RKSimon wrote:

We do most TERNLOG matching inside X86DAGToDAGISel::tryVPTERNLOG (which has a 'FIXME: Handle inverted inputs?' comment) - might it be possible to handle this there?

As far as I learnt it, it's hard to do so. We have 3 difficulties:

1. We need a new ORNP node for pre-processing and the logic in tryVPTERNLOG, but ORNP isn't a canonical node like AND, ANDNP etc. that can be used for permutation;
2. Even we have a ORNP, we have to change the logic to prioritise ORNP over other nodes and ignore the permutation math;
3. Even we achieved 1 and 2, we have to change matchVPTERNLOG, because it assumes the operands are commutable while it's not true for this combine;

[craig.topper]

In D109273#2983998, @pengfei wrote:

In D109273#2983658, @RKSimon wrote:

We do most TERNLOG matching inside X86DAGToDAGISel::tryVPTERNLOG (which has a 'FIXME: Handle inverted inputs?' comment) - might it be possible to handle this there?

As far as I learnt it, it's hard to do so. We have 3 difficulties:

1. We need a new ORNP node for pre-processing and the logic in tryVPTERNLOG, but ORNP isn't a canonical node like AND, ANDNP etc. that can be used for permutation;
2. Even we have a ORNP, we have to change the logic to prioritise ORNP over other nodes and ignore the permutation math;
3. Even we achieved 1 and 2, we have to change matchVPTERNLOG, because it assumes the operands are commutable while it's not true for this combine;

In matchVPTERNLOG, why can’t we just check if each input is a single use xor with -1 after calculating the immediate and then change then change the mask appropriately. No new nodes needed

[craig.topper]

In D109273#2984072, @craig.topper wrote:

In D109273#2983998, @pengfei wrote:

In D109273#2983658, @RKSimon wrote:

We do most TERNLOG matching inside X86DAGToDAGISel::tryVPTERNLOG (which has a 'FIXME: Handle inverted inputs?' comment) - might it be possible to handle this there?

As far as I learnt it, it's hard to do so. We have 3 difficulties:

1. We need a new ORNP node for pre-processing and the logic in tryVPTERNLOG, but ORNP isn't a canonical node like AND, ANDNP etc. that can be used for permutation;
2. Even we have a ORNP, we have to change the logic to prioritise ORNP over other nodes and ignore the permutation math;
3. Even we achieved 1 and 2, we have to change matchVPTERNLOG, because it assumes the operands are commutable while it's not true for this combine;

In matchVPTERNLOG, why can’t we just check if each input is a single use xor with -1 after calculating the immediate and then change then change the mask appropriately. No new nodes needed

Sorry it should probably be in tryVPTERNLOG.

[craig.topper]

I posted an improvement to tryVPTERNLOG here D109295. This handles the basic case but doesn't peek through bitcasts or push broadcast through a not. Are those cases important for what you're trying to do here? I don't see any tests for them.

[pengfei]

In D109273#2984236, @craig.topper wrote:

I posted an improvement to tryVPTERNLOG here D109295. This handles the basic case but doesn't peek through bitcasts or push broadcast through a not. Are those cases important for what you're trying to do here? I don't see any tests for them.

No, thanks.

llvm/lib/Target/X86/X86ISelLowering.cpp

           return OneBitOfTruth;
         }
       }
     }
   }
   return SDValue();
 }
 
+static SDValue GetNot(SDValue V, SelectionDAG &DAG, MVT VT) {
+  // Basic X = NOT(Y) detection.
+  if (SDValue Not = IsNOT(V, DAG))
+    return Not;
+  // Fold BROADCAST(NOT(Y)) -> BROADCAST(Y).
+  if (V.getOpcode() == X86ISD::VBROADCAST) {
+    SDValue Src = V.getOperand(0);
+    EVT SrcVT = Src.getValueType();
+    if (!SrcVT.isVector())
+      return SDValue();
+    if (SDValue Not = IsNOT(Src, DAG))
+      return DAG.getNode(X86ISD::VBROADCAST, SDLoc(V), VT,
+                         DAG.getBitcast(SrcVT, Not));
+  }
+  return SDValue();
+}
+
 /// Try to fold: (and (xor X, -1), Y) -> (andnp X, Y).
 static SDValue combineANDXORWithAllOnesIntoANDNP(SDNode *N, SelectionDAG &DAG) {
   assert(N->getOpcode() == ISD::AND);
 
   MVT VT = N->getSimpleValueType(0);
   if (!VT.is128BitVector() && !VT.is256BitVector() && !VT.is512BitVector())
     return SDValue();
 
   SDValue X, Y;
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
 
-  auto GetNot = [&VT, &DAG](SDValue V) {
-    // Basic X = NOT(Y) detection.
-    if (SDValue Not = IsNOT(V, DAG))
-      return Not;
-    // Fold BROADCAST(NOT(Y)) -> BROADCAST(Y).
-    if (V.getOpcode() == X86ISD::VBROADCAST) {
-      SDValue Src = V.getOperand(0);
-      EVT SrcVT = Src.getValueType();
-      if (!SrcVT.isVector())
-        return SDValue();
-      if (SDValue Not = IsNOT(Src, DAG))
-        return DAG.getNode(X86ISD::VBROADCAST, SDLoc(V), VT,
-                           DAG.getBitcast(SrcVT, Not));
-    }
-    return SDValue();
-  };
-
-  if (SDValue Not = GetNot(N0)) {
+  if (SDValue Not = GetNot(N0, DAG, VT)) {
     X = Not;
     Y = N1;
-  } else if (SDValue Not = GetNot(N1)) {
+  } else if (SDValue Not = GetNot(N1, DAG, VT)) {
     X = Not;
     Y = N0;
   } else
     return SDValue();
 
   X = DAG.getBitcast(VT, X);
   Y = DAG.getBitcast(VT, Y);
   return DAG.getNode(X86ISD::ANDNP, SDLoc(N), VT, X, Y);
 }
 
+/// Try to fold: (and (or (xor X, -1), Y), Z) -> PTERNLOG Z, Y, X, 0xD0
+static SDValue
+combineANDORXORWithAllOnesIntoPTERNLOG(SDNode *N, SelectionDAG &DAG,
+                                       const X86Subtarget &Subtarget) {
+  assert(N->getOpcode() == ISD::AND);
+
+  MVT VT = N->getSimpleValueType(0);
+  if (!VT.is128BitVector() && !VT.is256BitVector() && !VT.is512BitVector())
+    return SDValue();
+
+  SDValue X, Y, Z;
+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+
+  if (!((Subtarget.hasAVX512() && VT.is512BitVector()) || Subtarget.hasVLX()))
+    return SDValue();
+
+  auto GetORNot = [&VT, &DAG](SDValue V, SDValue &X, SDValue &Y) {
+    if (V.getOpcode() != ISD::OR)
+      return false;
+
+    SDValue N0 = V.getOperand(0);
+    SDValue N1 = V.getOperand(1);
+    if (SDValue Not = GetNot(N0, DAG, VT)) {
+      X = Not;
+      Y = N1;
+    } else if (SDValue Not = GetNot(N1, DAG, VT)) {
+      X = Not;
+      Y = N0;
+    } else
+      return false;
+
+    return true;
+  };
+
+  if (GetORNot(N0, X, Y))
+    Z = N1;
+  else if (GetORNot(N1, X, Y))
+    Z = N0;
+  else
+    return SDValue();
+
+  SDValue Imm = DAG.getTargetConstant(0xD0, SDLoc(N), MVT::i8);
+  return DAG.getNode(X86ISD::VPTERNLOG, SDLoc(N), VT, Z, Y, X, Imm);
+}
+
 // Try to widen AND, OR and XOR nodes to VT in order to remove casts around
 // logical operations, like in the example below.
 //   or (and (truncate x, truncate y)),
 //      (xor (truncate z, build_vector (constants)))
 // Given a target type \p VT, we generate
 //   or (and x, y), (xor z, zext(build_vector (constants)))
 // given x, y and z are of type \p VT. We can do so, if operands are either
 // truncates from VT types, the second operand is a vector of constants or can

     return R;
 
   if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
     return FPLogic;
 
   if (SDValue R = combineANDXORWithAllOnesIntoANDNP(N, DAG))
     return R;
 
+  if (SDValue R = combineANDORXORWithAllOnesIntoPTERNLOG(N, DAG, Subtarget))
+    return R;
+
   if (SDValue ShiftRight = combineAndMaskToShift(N, DAG, Subtarget))
     return ShiftRight;
 
   if (SDValue R = combineAndLoadToBZHI(N, DAG, Subtarget))
     return R;
 
   // Attempt to recursively combine a bitmask AND with shuffles.
   if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) {

llvm/test/CodeGen/X86/avx512vl-logic.ll

 ; CHECK-NEXT:    vpternlogd $206, %xmm1, %xmm2, %xmm0
 ; CHECK-NEXT:    retq
   %a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = and <4 x i32> %y, %a
   %c = or <4 x i32> %b, %z
   ret <4 x i32> %c
 }
 
+define <4 x i32> @ternlog_and_orn(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
+; CHECK-LABEL: ternlog_and_orn:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    vpternlogd $208, %xmm2, %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %a = xor <4 x i32> %z, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %b = or <4 x i32> %a, %y
+  %c = and <4 x i32> %b, %x
+  ret <4 x i32> %c
+}
+
 define <4 x i32> @ternlog_xor_andn(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
 ; CHECK-LABEL: ternlog_xor_andn:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    vpternlogd $198, %xmm1, %xmm2, %xmm0
 ; CHECK-NEXT:    retq
   %a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %b = and <4 x i32> %y, %a
   %c = xor <4 x i32> %b, %z