[mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions

[hvarga]

Summary

The patch creates microMIPS64r6 subtarget and implements DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions.

[hvarga]

Added new empty line in valid.s file.

[dsanders]

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

850

hasMips64r6() isn't needed. The predicates are cumulative so hasMips32r6() is true for MIPS64r6 too.

lib/Target/Mips/MicroMips32r6InstrInfo.td

286

I'm on the fence about this. For consistency with the other namespaces, we shouldn't add '_64r6' but equally more descriptive names are generally a good thing.

lib/Target/Mips/MicroMips64r6InstrFormats.td

1

80 cols?

14

Please use the naming convention we used for MIPS32r6/MIPS64r6.

The prefix should match the major opcode name. Then (where necessary) something to disambiguate variations of the major opcode. Lastly a '_FM' suffix.

For example:

DOUBLE_ADD_UPPER_IMM -> DAUI_FM.
DOUBLE_EXT_BIT_FIELD -> POOL32S_EXTBITS_FM.
CONCAT_EXTRACT -> POOL32S_DALIGN_FM.

lib/Target/Mips/MicroMips64r6InstrInfo.td

1

80 cols?

43

Optional nit: DAHI_DATI_DESC_BASE? It's easier to format when the names aren't so long and we generally don't expand the mnemonic to the words it stands for.

Similarly for the other lengthy *_DESC_BASE's below.

43–45

Indentation

56–57

Indendation

90–100

Why do some of these use StdMMR6Rel and others use R6MM6Rel?

[hvarga]

Updated according to the comments from dsanders.

[dsanders]

LGTM with the '-*- tablegen -*-' issue fixed.

lib/Target/Mips/MicroMips64r6InstrFormats.td

2–3

Unfortunately, this bit needs to be on the first line. It tells emacs (and presumably other editors) what the file format is.

I'd drop the redundant 'Mips64r6' in 'Mips64r6 Instruction Formats'.

lib/Target/Mips/MicroMips64r6InstrInfo.td

3

Likewise

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
         IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
         IsBigEndian(IsBigEndian) {}
 
   bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
   bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
   bool hasMips32r6() const {
     return STI.getFeatureBits()[Mips::FeatureMips32r6];
   }
+  bool hasMips64r6() const {
+    return STI.getFeatureBits()[Mips::FeatureMips64r6];
+  }
 
   bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
 
   bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
 
   bool hasCOP3() const {
     // Only present in MIPS-I and MIPS-II
     return !hasMips32() && !hasMips3();
if (Result != MCDisassembler::Fail) {
       Size = 2;
       return Result;
     }
 
     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
     if (Result == MCDisassembler::Fail)
       return MCDisassembler::Fail;
 
-    if (hasMips32r6()) {
+    if (hasMips32r6() || hasMips64r6()) {
       DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
       // Calling the auto-generated decoder function.
-      Result = decodeInstruction(DecoderTableMicroMips32r632, Instr, Insn, Address,
+      Result = decodeInstruction(DecoderTableMicroMips32r6_64r632, Instr, Insn, Address,
                                  this, STI);
     } else {
       DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
       // Calling the auto-generated decoder function.
       Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
                                  this, STI);
     }
+
     if (Result != MCDisassembler::Fail) {
       Size = 4;
       return Result;
     }
     return MCDisassembler::Fail;
   }
 
   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);

lib/Target/Mips/MicroMips32r6InstrInfo.td

 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
-let DecoderNamespace = "MicroMips32r6" in {
+let DecoderNamespace = "MicroMips32r6_64r6" in {
 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
                   ISA_MICROMIPS32R6;
 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;

lib/Target/Mips/MicroMips64r6InstrFormats.td

+//=- MicroMips64r6InstrFormats.td - Mips64r6 Instruction Formats -*- tablegen -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes microMIPS64r6 instruction formats.
+//
+//===----------------------------------------------------------------------===//
+
+class DOUBLE_ADD_UPPER_IMM {
+  bits<5> rt;
+  bits<5> rs;
+  bits<16> imm;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b111100;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-0}  = imm;
+}
+
+class DOUBLE_ADD_HIGHER_TOP_IMM<bits<5> funct> {
+  bits<5> rs;
+  bits<16> imm;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010000;
+  let Inst{25-21} = funct;
+  let Inst{20-16} = rs;
+  let Inst{15-0} = imm;
+}
+
+class DOUBLE_EXT_BIT_FIELD<bits<6> funct> {
+  bits<5> rt;
+  bits<5> rs;
+  bits<5> size;
+  bits<5> pos;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = size;
+  let Inst{10-6}  = pos;
+  let Inst{5-0}   = funct;
+}
+
+class CONCAT_EXTRACT {
+  bits<5> rs;
+  bits<5> rt;
+  bits<5> rd;
+  bits<3> bp;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rs;
+  let Inst{20-16} = rt;
+  let Inst{15-11} = rd;
+  let Inst{10-8}  = bp;
+  let Inst{7-6}   = 0b00;
+  let Inst{5-0}   = 0b011100;
+}

lib/Target/Mips/MicroMips64r6InstrInfo.td

+//=- MicroMips64r6InstrInfo.td - MicroMips64r6 Instruction Information -*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes MicroMips64r6 instructions.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//
+// Instruction Encodings
+//
+//===----------------------------------------------------------------------===//
+
+class DAUI_MMR6_ENC : DOUBLE_ADD_UPPER_IMM;
+class DAHI_MMR6_ENC : DOUBLE_ADD_HIGHER_TOP_IMM<0b10001>;
+class DATI_MMR6_ENC : DOUBLE_ADD_HIGHER_TOP_IMM<0b10000>;
+class DEXT_MMR6_ENC : DOUBLE_EXT_BIT_FIELD<0b101100>;
+class DEXTM_MMR6_ENC : DOUBLE_EXT_BIT_FIELD<0b100100>;
+class DEXTU_MMR6_ENC : DOUBLE_EXT_BIT_FIELD<0b010100>;
+class DALIGN_MMR6_ENC : CONCAT_EXTRACT;
+
+//===----------------------------------------------------------------------===//
+//
+// Instruction Descriptions
+//
+//===----------------------------------------------------------------------===//
+
+class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+    : MMR6Arch<instr_asm>, MipsR6Inst {
+  dag OutOperandList = (outs GPROpnd:$rt);
+  dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
+  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
+  list<dag> Pattern = [];
+}
+class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd>;
+
+class DOUBLE_ADD_HIGHER_TOP_MMR6_DESC_BASE<string instr_asm,
+                                           RegisterOperand GPROpnd> :
+                                               MMR6Arch<instr_asm>, MipsR6Inst {
+  dag OutOperandList = (outs GPROpnd:$rs);
+  dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
+  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
+  string Constraints = "$rs = $rt";
+}
+class DAHI_MMR6_DESC : DOUBLE_ADD_HIGHER_TOP_MMR6_DESC_BASE<"dahi", GPR64Opnd>;
+class DATI_MMR6_DESC : DOUBLE_ADD_HIGHER_TOP_MMR6_DESC_BASE<"dati", GPR64Opnd>;
+
+class DOUBLE_EXT_BIT_FIELD_BASE<string instr_asm, RegisterOperand RO,
+                                Operand PosOpnd,
+                                SDPatternOperator Op = null_frag> :
+                                  MMR6Arch<instr_asm>, MipsR6Inst {
+  dag OutOperandList = (outs RO:$rt);
+  dag InOperandList = (ins RO:$rs, PosOpnd:$pos, size_ext:$size);
+  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
+  list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
+  InstrItinClass Itinerary = II_EXT;
+  Format Form = FrmR;
+  string BaseOpcode = instr_asm;
+}
+class DEXT_MMR6_DESC : DOUBLE_EXT_BIT_FIELD_BASE<"dext", GPR64Opnd, uimm6,
+                                                 MipsExt>;
+class DEXTM_MMR6_DESC : DOUBLE_EXT_BIT_FIELD_BASE<"dextm", GPR64Opnd, uimm6,
+                                                  MipsExt>;
+class DEXTU_MMR6_DESC : DOUBLE_EXT_BIT_FIELD_BASE<"dextu", GPR64Opnd, uimm6,
+                                                  MipsExt>;
+
+class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+                      Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst {
+  dag OutOperandList = (outs GPROpnd:$rd);
+  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
+  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
+  list<dag> Pattern = [];
+}
+
+class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
+
+//===----------------------------------------------------------------------===//
+//
+// Instruction Definitions
+//
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "MicroMips32r6_64r6" in {
+  def DAUI_MM64R6 : R6MMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
+  def DAHI_MM64R6 : R6MMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6;
+  def DATI_MM64R6 : R6MMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6;
+  def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
+                    ISA_MICROMIPS64R6;
+  def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
+                     ISA_MICROMIPS64R6;
+  def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
+                     ISA_MICROMIPS64R6;
+  def DALIGN_MM64R6 : R6MMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
+                      ISA_MICROMIPS64R6;
+}

lib/Target/Mips/Mips64InstrInfo.td

 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
 
 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
 
 let isCodeGenOnly = 1 in
 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
 
+let AdditionalPredicates = [NotInMicroMips] in {
   def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
-def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
   def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
+  def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
+}
 
 def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
 
 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
   def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
                      "dsll\t$rd, $rt, 32", [], II_DSLL>;

lib/Target/Mips/Mips64r6InstrInfo.td

 class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
-def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
-def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
   def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
+  def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
   def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
+  def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
+}
 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
 def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
 def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
 def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
 def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6;
 def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;

lib/Target/Mips/MipsInstrInfo.td

 def HasMips64r2  :    Predicate<"Subtarget->hasMips64r2()">,
                       AssemblerPredicate<"FeatureMips64r2">;
 def HasMips64r6  :    Predicate<"Subtarget->hasMips64r6()">,
                       AssemblerPredicate<"FeatureMips64r6">;
 def NotMips64r6  :    Predicate<"!Subtarget->hasMips64r6()">,
                       AssemblerPredicate<"!FeatureMips64r6">;
 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
                        AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
+def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
+                       AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
 def InMips16Mode :    Predicate<"Subtarget->inMips16Mode()">,
                       AssemblerPredicate<"FeatureMips16">;
 def HasCnMips    :    Predicate<"Subtarget->hasCnMips()">,
                       AssemblerPredicate<"FeatureCnMips">;
 def RelocStatic :     Predicate<"TM.getRelocationModel() == Reloc::Static">;
 def RelocPIC    :     Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
 def NoNaNsFPMath :    Predicate<"TM.Options.NoNaNsFPMath">;
 def HasStdEnc :       Predicate<"Subtarget->hasStandardEncoding()">,
class ISA_MIPS64_NOT_64R6 {
   list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
 }
 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
 class ISA_MICROMIPS32R6 {
   list<Predicate> InsnPredicates = [HasMicroMips32r6];
 }
+class ISA_MICROMIPS64R6 {
+  list<Predicate> InsnPredicates = [HasMicroMips64r6];
+}
 
 // The portions of MIPS-III that were also added to MIPS32
 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
 
 // The portions of MIPS-III that were also added to MIPS32 but were removed in
 // MIPS32r6 and MIPS64r6.
 class INSN_MIPS3_32_NOT_32R6_64R6 {
   list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];

 // Micromips
 include "MicroMipsInstrFormats.td"
 include "MicroMipsInstrInfo.td"
 include "MicroMipsInstrFPU.td"
 
 // Micromips r6
 include "MicroMips32r6InstrFormats.td"
 include "MicroMips32r6InstrInfo.td"
+
+// Micromips64 r6
+include "MicroMips64r6InstrFormats.td"
+include "MicroMips64r6InstrInfo.td"

lib/Target/Mips/MipsSubtarget.h

public:
   // but to use a runtime library for soft float that is written with
   // native mips32 floating point instructions (those runtime routines
   // run in mips32 hard float mode).
   bool inMips16HardFloat() const {
     return inMips16Mode() && InMips16HardFloat;
   }
   bool inMicroMipsMode() const { return InMicroMipsMode; }
   bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
+  bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
   bool hasDSP() const { return HasDSP; }
   bool hasDSPR2() const { return HasDSPR2; }
   bool hasMSA() const { return HasMSA; }
   bool useSmallSection() const { return UseSmallSection; }
 
   bool hasStandardEncoding() const { return !inMips16Mode(); }
 
   bool useSoftFloat() const { return IsSoftFloat; }

test/MC/Disassembler/Mips/micromips64r6.txt

+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r6 -mattr=micromips | FileCheck %s
+
+0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5
+
+0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4
+
+0x42 0x03 0x00 0x04 # CHECK: dati $3, 4
+
+0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7
+
+0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 7
+
+0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 3, 7
+
+0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5

test/MC/Mips/micromips64r6/valid.s

+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 -mattr=micromips | FileCheck %s
+a:
+        .set noat
+        daui $3, $4, 5           # CHECK: daui $3, $4, 5        # encoding: [0xf0,0x64,0x00,0x05]
+        dahi $3, 4               # CHECK: dahi $3, 4            # encoding: [0x42,0x23,0x00,0x04]
+        dati $3, 4               # CHECK: dati $3, 4            # encoding: [0x42,0x03,0x00,0x04]
+        dext $9, $6, 3, 7        # CHECK: dext $9, $6, 3, 7     # encoding: [0x59,0x26,0x30,0xec]
+        dextm $9, $6, 3, 7       # CHECK: dextm $9, $6, 3, 7    # encoding: [0x59,0x26,0x30,0xe4]
+        dextu $9, $6, 3, 7       # CHECK: dextu $9, $6, 3, 7    # encoding: [0x59,0x26,0x30,0xd4]
+        dalign $4, $2, $3, 5     # CHECK: dalign $4, $2, $3, 5  # encoding: [0x58,0x43,0x25,0x1c]
+
+1: