[mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions

[hvarga]

Summary

The patch implements microMIPS32r6 and microMIPS64r6 BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions.

[hvarga]

Duplicate of D11292.

lib/Target/Mips/MicroMips32r6InstrFormats.td

class POOL16C_NOT16_FM_MMR6 {
   bits<16> Inst;
 
   let Inst{15-10} = 0x11;
   let Inst{9-7}   = rt;
   let Inst{6-4}   = rs;
   let Inst{3-0}   = 0b0000;
 }
 
-class POOL16C_OR16_FM_MMR6 {
+class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
   bits<3> rt;
   bits<3> rs;
 
   bits<16> Inst;
 
   let Inst{15-10} = 0b010001;
   let Inst{9-7}   = rt;
   let Inst{6-4}   = rs;
-  let Inst{3-0}   = 0b1001;
+  let Inst{3-0}   = op;
+}
+
+class POOL16C_FM_MMR6<bits<6> op> {
+  bits<4> code_;
+  bits<16> Inst;
+
+  let Inst{15-10} = 0b010001;
+  let Inst{9-6}   = code_;
+  let Inst{5-0}   = op;
+}
+
+class POOL16A_SUBU16_FM_MMR6 {
+  bits<3> rs;
+  bits<3> rt;
+  bits<3> rd;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = 0b000001;
+  let Inst{9-7}   = rs;
+  let Inst{6-4}   = rt;
+  let Inst{3-1}   = rd;
+  let Inst{0}     = 0b1;
 }

lib/Target/Mips/MicroMips32r6InstrInfo.td

 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>;
 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
-class OR16_MMR6_ENC : POOL16C_OR16_FM_MMR6;
+class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>;
 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>;
+class BREAK16_MMR6_ENC : POOL16C_FM_MMR6<0b011011>;
+class LI16_MMR6_ENC : LI_FM_MM16;
+class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
+class SDBBP16_MMR6_ENC : POOL16C_FM_MMR6<0b111011>;
+class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
+class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
 
 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
                                   RegisterOperand GPROpnd>
     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
   dag OutOperandList = (outs);
   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
   list<Register> Defs = [AT];

 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">,
   MicroMipsR6Inst16;
 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
   MMR6Arch<"or16">, MicroMipsR6Inst16;
 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
   MMR6Arch<"sll16">, MicroMipsR6Inst16;
 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
   MMR6Arch<"srl16">, MicroMipsR6Inst16;
+class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">,
+  MicroMipsR6Inst16;
+class LI16_MMR6_DESC : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>,
+  MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
+class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">,
+  MicroMipsR6Inst16;
+class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
+  MicroMipsR6Inst16;
+class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
+  MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
+class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
+  MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {

 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
                   ISA_MICROMIPS32R6;
 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
                   ISA_MICROMIPS32R6;
 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
                   ISA_MICROMIPS32R6;
 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
                   ISA_MICROMIPS32R6;
+def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
 }
 
 //===----------------------------------------------------------------------===//
 //
 // MicroMips instruction aliases
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;

test/MC/Disassembler/Mips/micromips32r6.txt

 0x46 0x70 # CHECK: not16 $4, $7
 
 0x45 0xf9 # CHECK: or16 $3, $7
 
 0x25 0xe0 # CHECK: sll16 $3, $6, 8
 
 0x25 0xe1 # CHECK: srl16 $3, $6, 8
 
+0x46 0x1B # CHECK: break16 8
+
+0xed 0xff # CHECK: li16 $3, -1
+
+0x0c 0x65 # CHECK: move16 $3, $5
+
+0x46 0x3b # CHECK: sdbbp16 8
+
+0x04 0x3b # CHECK: subu16 $5, $16, $3
+
+0x44 0xd8 # CHECK: xor16 $17, $5
+

test/MC/Disassembler/Mips/micromips64r6.txt

 
 0x46 0x70 # CHECK: not16 $4, $7
 
 0x45 0xf9 # CHECK: or16 $3, $7
 
 0x25 0xe0 # CHECK: sll16 $3, $6, 8
 
 0x25 0xe1 # CHECK: srl16 $3, $6, 8
+
+0x46 0x1B # CHECK: break16 8
+
+0xed 0xff # CHECK: li16 $3, -1
+
+0x0c 0x65 # CHECK: move16 $3, $5
+
+0x46 0x3b # CHECK: sdbbp16 8
+
+0x04 0x3b # CHECK: subu16 $5, $16, $3
+
+0x44 0xd8 # CHECK: xor16 $17, $5

test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   xori $3, $4, 1234        # CHECK: xori $3, $4, 1234   # encoding: [0x70,0x64,0x04,0xd2]
   addu16 $6, $17, $4       # CHECK: addu16 $6, $17, $4  # encoding: [0x04,0xcc]
   and16 $16, $2            # CHECK: and16 $16, $2       # encoding: [0x44,0x21]
   andi16 $4, $5, 8         # CHECK: andi16 $4, $5, 8    # encoding: [0x2e,0x56]
   not16 $4, $7             # CHECK: not16 $4, $7        # encoding: [0x46,0x70]
   or16 $3, $7              # CHECK: or16 $3, $7         # encoding: [0x45,0xf9]
   sll16 $3, $6, 8          # CHECK: sll16 $3, $6, 8     # encoding: [0x25,0xe0]
   srl16 $3, $6, 8          # CHECK: srl16 $3, $6, 8     # encoding: [0x25,0xe1]
+  break16 8                # CHECK: break16 8           # encoding: [0x46,0x1b]
+  li16 $3, -1              # CHECK: li16 $3, -1         # encoding: [0xed,0xff]
+  move16 $3, $5            # CHECK: move16 $3, $5       # encoding: [0x0c,0x65]
+  sdbbp16 8                # CHECK: sdbbp16 8           # encoding: [0x46,0x3b]
+  subu16 $5, $16, $3       # CHECK: subu16 $5, $16, $3  # encoding: [0x04,0x3b]
+  xor16 $17, $5            # CHECK: xor16 $17, $5       # encoding: [0x44,0xd8]
 

test/MC/Mips/micromips64r6/valid.s

 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 -mattr=micromips | FileCheck %s
 a:
         .set noat
         daui $3, $4, 5           # CHECK: daui $3, $4, 5        # encoding: [0xf0,0x64,0x00,0x05]
         dahi $3, 4               # CHECK: dahi $3, 4            # encoding: [0x42,0x23,0x00,0x04]
         dati $3, 4               # CHECK: dati $3, 4            # encoding: [0x42,0x03,0x00,0x04]
         dext $9, $6, 3, 7        # CHECK: dext $9, $6, 3, 7     # encoding: [0x59,0x26,0x30,0xec]
         dextm $9, $6, 3, 7       # CHECK: dextm $9, $6, 3, 7    # encoding: [0x59,0x26,0x30,0xe4]
         dextu $9, $6, 3, 7       # CHECK: dextu $9, $6, 3, 7    # encoding: [0x59,0x26,0x30,0xd4]
         dalign $4, $2, $3, 5     # CHECK: dalign $4, $2, $3, 5  # encoding: [0x58,0x43,0x25,0x1c]
         addu16 $6, $17, $4       # CHECK: addu16 $6, $17, $4    # encoding: [0x04,0xcc]
         and16 $16, $2            # CHECK: and16 $16, $2         # encoding: [0x44,0x21]
         andi16 $4, $5, 8         # CHECK: andi16 $4, $5, 8      # encoding: [0x2e,0x56]
         not16 $4, $7             # CHECK: not16 $4, $7          # encoding: [0x46,0x70]
-        or16 $3, $7              # CHECK: or16 $3, $7         # encoding: [0x45,0xf9]
-        sll16 $3, $6, 8          # CHECK: sll16 $3, $6, 8     # encoding: [0x25,0xe0]
-        srl16 $3, $6, 8          # CHECK: srl16 $3, $6, 8     # encoding: [0x25,0xe1]
+        or16 $3, $7              # CHECK: or16 $3, $7           # encoding: [0x45,0xf9]
+        sll16 $3, $6, 8          # CHECK: sll16 $3, $6, 8       # encoding: [0x25,0xe0]
+        srl16 $3, $6, 8          # CHECK: srl16 $3, $6, 8       # encoding: [0x25,0xe1]
+        break16 8                # CHECK: break16 8             # encoding: [0x46,0x1b]
+        li16 $3, -1              # CHECK: li16 $3, -1           # encoding: [0xed,0xff]
+        move16 $3, $5            # CHECK: move16 $3, $5         # encoding: [0x0c,0x65]
+        sdbbp16 8                # CHECK: sdbbp16 8             # encoding: [0x46,0x3b]
+        subu16 $5, $16, $3       # CHECK: subu16 $5, $16, $3    # encoding: [0x04,0x3b]
+        xor16 $17, $5            # CHECK: xor16 $17, $5         # encoding: [0x44,0xd8]
 
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