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Commit 366783e

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author
Zoran Jovanovic
committedAug 12, 2015
[mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions
Differential Revision: http://reviews.llvm.org/D10923 llvm-svn: 244744
·
llvmorg-21-initllvmorg-3.8.0-rc1
1 parent 0c8beb1 commit 366783e

9 files changed

+207
-9
lines changed
 

Diff for: ‎llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -847,14 +847,15 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
847847
if (hasMips32r6()) {
848848
DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
849849
// Calling the auto-generated decoder function.
850-
Result = decodeInstruction(DecoderTableMicroMips32r632, Instr, Insn, Address,
850+
Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
851851
this, STI);
852852
} else {
853853
DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
854854
// Calling the auto-generated decoder function.
855855
Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
856856
this, STI);
857857
}
858+
858859
if (Result != MCDisassembler::Fail) {
859860
Size = 4;
860861
return Result;

Diff for: ‎llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td

+1-1
Original file line numberDiff line numberDiff line change
@@ -283,7 +283,7 @@ class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
283283
//
284284
//===----------------------------------------------------------------------===//
285285

286-
let DecoderNamespace = "MicroMips32r6" in {
286+
let DecoderNamespace = "MicroMipsR6" in {
287287
def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
288288
def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
289289
def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;

Diff for: ‎llvm/lib/Target/Mips/MicroMips64r6InstrFormats.td

+70
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,70 @@
1+
//=- MicroMips64r6InstrFormats.td - Instruction Formats -*- tablegen -* -=//
2+
//
3+
// The LLVM Compiler Infrastructure
4+
//
5+
// This file is distributed under the University of Illinois Open Source
6+
// License. See LICENSE.TXT for details.
7+
//
8+
//===----------------------------------------------------------------------===//
9+
//
10+
// This file describes microMIPS64r6 instruction formats.
11+
//
12+
//===----------------------------------------------------------------------===//
13+
14+
class DAUI_FM_MMR6 {
15+
bits<5> rt;
16+
bits<5> rs;
17+
bits<16> imm;
18+
19+
bits<32> Inst;
20+
21+
let Inst{31-26} = 0b111100;
22+
let Inst{25-21} = rt;
23+
let Inst{20-16} = rs;
24+
let Inst{15-0} = imm;
25+
}
26+
27+
class POOL32I_ADD_IMM_FM_MMR6<bits<5> funct> {
28+
bits<5> rs;
29+
bits<16> imm;
30+
31+
bits<32> Inst;
32+
33+
let Inst{31-26} = 0b010000;
34+
let Inst{25-21} = funct;
35+
let Inst{20-16} = rs;
36+
let Inst{15-0} = imm;
37+
}
38+
39+
class POOL32S_EXTBITS_FM_MMR6<bits<6> funct> {
40+
bits<5> rt;
41+
bits<5> rs;
42+
bits<5> size;
43+
bits<5> pos;
44+
45+
bits<32> Inst;
46+
47+
let Inst{31-26} = 0b010110;
48+
let Inst{25-21} = rt;
49+
let Inst{20-16} = rs;
50+
let Inst{15-11} = size;
51+
let Inst{10-6} = pos;
52+
let Inst{5-0} = funct;
53+
}
54+
55+
class POOL32S_DALIGN_FM_MMR6 {
56+
bits<5> rs;
57+
bits<5> rt;
58+
bits<5> rd;
59+
bits<3> bp;
60+
61+
bits<32> Inst;
62+
63+
let Inst{31-26} = 0b010110;
64+
let Inst{25-21} = rs;
65+
let Inst{20-16} = rt;
66+
let Inst{15-11} = rd;
67+
let Inst{10-8} = bp;
68+
let Inst{7-6} = 0b00;
69+
let Inst{5-0} = 0b011100;
70+
}

Diff for: ‎llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td

+98
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,98 @@
1+
//=- MicroMips64r6InstrInfo.td - Instruction Information -*- tablegen -*- -=//
2+
//
3+
// The LLVM Compiler Infrastructure
4+
//
5+
// This file is distributed under the University of Illinois Open Source
6+
// License. See LICENSE.TXT for details.
7+
//
8+
//===----------------------------------------------------------------------===//
9+
//
10+
// This file describes MicroMips64r6 instructions.
11+
//
12+
//===----------------------------------------------------------------------===//
13+
14+
//===----------------------------------------------------------------------===//
15+
//
16+
// Instruction Encodings
17+
//
18+
//===----------------------------------------------------------------------===//
19+
20+
class DAUI_MMR6_ENC : DAUI_FM_MMR6;
21+
class DAHI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10001>;
22+
class DATI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10000>;
23+
class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
24+
class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
25+
class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
26+
class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
27+
28+
//===----------------------------------------------------------------------===//
29+
//
30+
// Instruction Descriptions
31+
//
32+
//===----------------------------------------------------------------------===//
33+
34+
class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
35+
: MMR6Arch<instr_asm>, MipsR6Inst {
36+
dag OutOperandList = (outs GPROpnd:$rt);
37+
dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
38+
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
39+
list<dag> Pattern = [];
40+
}
41+
class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd>;
42+
43+
class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
44+
: MMR6Arch<instr_asm>, MipsR6Inst {
45+
dag OutOperandList = (outs GPROpnd:$rs);
46+
dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
47+
string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
48+
string Constraints = "$rs = $rt";
49+
}
50+
class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd>;
51+
class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd>;
52+
53+
class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
54+
SDPatternOperator Op = null_frag> : MMR6Arch<instr_asm>, MipsR6Inst {
55+
dag OutOperandList = (outs RO:$rt);
56+
dag InOperandList = (ins RO:$rs, PosOpnd:$pos, size_ext:$size);
57+
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
58+
list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
59+
InstrItinClass Itinerary = II_EXT;
60+
Format Form = FrmR;
61+
string BaseOpcode = instr_asm;
62+
}
63+
class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm6,
64+
MipsExt>;
65+
class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm6,
66+
MipsExt>;
67+
class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm6,
68+
MipsExt>;
69+
70+
class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
71+
Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst {
72+
dag OutOperandList = (outs GPROpnd:$rd);
73+
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
74+
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
75+
list<dag> Pattern = [];
76+
}
77+
78+
class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
79+
80+
//===----------------------------------------------------------------------===//
81+
//
82+
// Instruction Definitions
83+
//
84+
//===----------------------------------------------------------------------===//
85+
86+
let DecoderNamespace = "MicroMipsR6" in {
87+
def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
88+
def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6;
89+
def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6;
90+
def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
91+
ISA_MICROMIPS64R6;
92+
def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
93+
ISA_MICROMIPS64R6;
94+
def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
95+
ISA_MICROMIPS64R6;
96+
def DALIGN_MM64R6 : StdMMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
97+
ISA_MICROMIPS64R6;
98+
}

Diff for: ‎llvm/lib/Target/Mips/Mips64InstrInfo.td

+5-3
Original file line numberDiff line numberDiff line change
@@ -276,9 +276,11 @@ def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
276276
let isCodeGenOnly = 1 in
277277
def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
278278

279-
def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
280-
def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
281-
def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
279+
let AdditionalPredicates = [NotInMicroMips] in {
280+
def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
281+
def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
282+
def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
283+
}
282284

283285
def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
284286
def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;

Diff for: ‎llvm/lib/Target/Mips/Mips64r6InstrInfo.td

+6-4
Original file line numberDiff line numberDiff line change
@@ -81,10 +81,12 @@ class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
8181
//
8282
//===----------------------------------------------------------------------===//
8383

84-
def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
85-
def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
86-
def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
87-
def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
84+
let AdditionalPredicates = [NotInMicroMips] in {
85+
def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
86+
def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
87+
def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
88+
def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
89+
}
8890
def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
8991
def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
9092
def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;

Diff for: ‎llvm/lib/Target/Mips/MipsInstrInfo.td

+9
Original file line numberDiff line numberDiff line change
@@ -186,6 +186,8 @@ def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
186186
AssemblerPredicate<"!FeatureMips64r6">;
187187
def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
188188
AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
189+
def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
190+
AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
189191
def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
190192
AssemblerPredicate<"FeatureMips16">;
191193
def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
@@ -255,6 +257,9 @@ class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
255257
class ISA_MICROMIPS32R6 {
256258
list<Predicate> InsnPredicates = [HasMicroMips32r6];
257259
}
260+
class ISA_MICROMIPS64R6 {
261+
list<Predicate> InsnPredicates = [HasMicroMips64r6];
262+
}
258263

259264
// The portions of MIPS-III that were also added to MIPS32
260265
class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
@@ -1981,3 +1986,7 @@ include "MicroMipsInstrFPU.td"
19811986
// Micromips r6
19821987
include "MicroMips32r6InstrFormats.td"
19831988
include "MicroMips32r6InstrInfo.td"
1989+
1990+
// Micromips64 r6
1991+
include "MicroMips64r6InstrFormats.td"
1992+
include "MicroMips64r6InstrInfo.td"

Diff for: ‎llvm/lib/Target/Mips/MipsSubtarget.h

+1
Original file line numberDiff line numberDiff line change
@@ -228,6 +228,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
228228
}
229229
bool inMicroMipsMode() const { return InMicroMipsMode; }
230230
bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
231+
bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
231232
bool hasDSP() const { return HasDSP; }
232233
bool hasDSPR2() const { return HasDSPR2; }
233234
bool hasMSA() const { return HasMSA; }

Diff for: ‎llvm/test/MC/Disassembler/Mips/micromips64r6.txt

+15
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r6 -mattr=micromips | FileCheck %s
2+
3+
0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5
4+
5+
0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4
6+
7+
0x42 0x03 0x00 0x04 # CHECK: dati $3, 4
8+
9+
0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7
10+
11+
0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 7
12+
13+
0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 3, 7
14+
15+
0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5

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