[mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions

[hvarga]

Summary

The patch implements microMIPSr6 BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions.

[dsanders]

LGTM with a couple nits

lib/Target/Mips/MicroMips32r6InstrFormats.td

341 ↗

(On Diff #29990)

POOL16C contains a wide variety of instructions so we should probably have some disambiguating text between the 'POOL16C_' and the 'FM_MMR6'

lib/Target/Mips/MicroMips32r6InstrInfo.td

299–324 ↗

(On Diff #29990)

Indentation.

411–422 ↗

(On Diff #29990)

The indentation is off by one on some of these.

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td

class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
   bits<16> Inst;
 
   let Inst{15-10} = 0x11;
   let Inst{9-7}   = rt;
   let Inst{6-4}   = rs;
   let Inst{3-0}   = 0b0000;
 }
 
-class POOL16C_OR16_FM_MMR6 : MicroMipsR6Inst16 {
+class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
   bits<3> rt;
   bits<3> rs;
 
   bits<16> Inst;
 
   let Inst{15-10} = 0b010001;
   let Inst{9-7}   = rt;
   let Inst{6-4}   = rs;
-  let Inst{3-0}   = 0b1001;
+  let Inst{3-0}   = op;
+}
+
+class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> {
+  bits<4> code_;
+  bits<16> Inst;
+
+  let Inst{15-10} = 0b010001;
+  let Inst{9-6}   = code_;
+  let Inst{5-0}   = op;
+}
+
+class POOL16A_SUBU16_FM_MMR6 {
+  bits<3> rs;
+  bits<3> rt;
+  bits<3> rd;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = 0b000001;
+  let Inst{9-7}   = rs;
+  let Inst{6-4}   = rt;
+  let Inst{3-1}   = rd;
+  let Inst{0}     = 0b1;
 }
 
 class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst {
   bits<5> rt;
   bits<5> rs;
 
   bits<32> Inst;
 
   let Inst{31-26} = 0x00;
   let Inst{25-21} = rt;
   let Inst{20-16} = rs;
   let Inst{15-6}  = funct;
   let Inst{5-0}   = 0x3c;
 }

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

 class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 
 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
-class OR16_MMR6_ENC : POOL16C_OR16_FM_MMR6;
+class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
+class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
+class LI16_MMR6_ENC : LI_FM_MM16;
+class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
+class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
+class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
+class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
 
 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
                                   RegisterOperand GPROpnd>
     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
   dag OutOperandList = (outs);
   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
   list<Register> Defs = [AT];
class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
   dag InOperandList = (ins mem_mm_12:$addr);
   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   string DecoderMethod = "DecodeMemMMImm9";
   bit mayLoad = 1;
 }
 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
       MMR6Arch<"addu16">;
 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
       MMR6Arch<"and16">;
 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
       MMR6Arch<"andi16">;
 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
       MMR6Arch<"or16">;
 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
       MMR6Arch<"sll16">;
 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
       MMR6Arch<"srl16">;
+class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">,
+      MicroMipsR6Inst16;
+class LI16_MMR6_DESC : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>,
+      MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
+class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">,
+      MicroMipsR6Inst16;
+class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
+      MicroMipsR6Inst16;
+class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
+      MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
+class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
+      MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
 
 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
   dag OutOperandList = (outs GPR32Opnd:$rt);
   dag InOperandList = (ins mem:$addr);
   string AsmString = "lw\t$rt, $addr";
   let DecoderMethod = "DecodeMemMMImm16";
   let canFoldAsLoad = 1;
   let mayLoad = 1;

 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
                   ISA_MICROMIPS32R6;
 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
                   ISA_MICROMIPS32R6;
 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
                   ISA_MICROMIPS32R6;
 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
                   ISA_MICROMIPS32R6;
+def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
+                   ISA_MICROMIPS32R6;
+def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
+                ISA_MICROMIPS32R6;
+def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
+                   ISA_MICROMIPS32R6;
+def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
+                 ISA_MICROMIPS32R6;
 }
 
 //===----------------------------------------------------------------------===//
 //
 // MicroMips instruction aliases
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
                                       !strconcat("b", "\t$offset")> {
   string DecoderNamespace = "MicroMipsR6";
 }

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
     ISA_MICROMIPS_NOT_32R6_64R6;
 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
     SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
     SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
 
 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
-                ARITH_FM_MM16<1>;
+                ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
-               LOGIC_FM_MM16<0x1>;
+               LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6_64R6;
 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
                         mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
                         mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
                       LOAD_STORE_FM_MM16<0x1a>;
 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
                         II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;

 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
                 BEQNEZ_FM_MM16<0x23>;
 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
                 BEQNEZ_FM_MM16<0x2b>;
 def B16_MM : UncondBranchMM16<"b16">, B16_FM;
-def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>;
-def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>;
+def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>,
+    ISA_MICROMIPS_NOT_32R6_64R6;
+def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>,
+    ISA_MICROMIPS_NOT_32R6_64R6;
 
 class WaitMM<string opstr> :
   InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
          NoItinerary, FrmOther, opstr>;
 
 let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   /// Compact Branch Instructions
   def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,

llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt

 0x03 0x96 0x04 0x3c # CHECK: tgeu $22, $gp
 0x01 0xd4 0xf4 0x3c # CHECK: tgeu $20, $14, 15
 0x01 0xaf 0x08 0x3c # CHECK: tlt $15, $13
 0x02 0x62 0xf8 0x3c # CHECK: tlt $2, $19, 15
 0x02 0x0b 0x0a 0x3c # CHECK: tltu $11, $16
 0x03 0xb0 0xfa 0x3c # CHECK: tltu $16, $sp, 15
 0x02 0x26 0x0c 0x3c # CHECK: tne $6, $17
 0x01 0x07 0xfc 0x3c # CHECK: tne $7, $8, 15
+0x65 0x88 # CHECK: lw $3, 32($gp)
+0x48 0x66 # CHECK: lw $3, 24($sp)
+0x6a 0x12 # CHECK: lw16 $4, 8($17)
+0x29 0x82 # CHECK: lhu16 $3, 4($16)
+0x09 0x94 # CHECK: lbu16 $3, 4($17)
+0x09 0x9f # CHECK: lbu16 $3, -1($17)
+0x04 0xcc # CHECK: addu16 $6, $17, $4
+0x44 0x21 # CHECK: and16 $16, $2
+0x2e 0x56 # CHECK: andi16 $4, $5, 8
+0x46 0x70 # CHECK: not16 $4, $7
+0x45 0xf9 # CHECK: or16 $3, $7
+0x25 0xe0 # CHECK: sll16 $3, $6, 8
+0x25 0xe1 # CHECK: srl16 $3, $6, 8
+0x46 0x1B # CHECK: break16 8
+0xed 0xff # CHECK: li16 $3, -1
+0x0c 0x65 # CHECK: move16 $3, $5
+0x46 0x3b # CHECK: sdbbp16 8
+0x04 0x3b # CHECK: subu16 $5, $16, $3
+0x44 0xd8 # CHECK: xor16 $17, $5

llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x02 0x62 0xf8 0x3c # CHECK: tlt $2, $19, 15
 0x02 0x0b 0x0a 0x3c # CHECK: tltu $11, $16
 0x03 0xb0 0xfa 0x3c # CHECK: tltu $16, $sp, 15
 0x02 0x26 0x0c 0x3c # CHECK: tne $6, $17
 0x01 0x07 0xfc 0x3c # CHECK: tne $7, $8, 15
 0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5)
 0x00 0x64 0xf1 0x7c # CHECK: wrpgpr $3, $4
 0x00 0x64 0x7b 0x3c # CHECK: wsbh $3, $4
+0x65 0x88 # CHECK: lw $3, 32($gp)
+0x48 0x66 # CHECK: lw $3, 24($sp)
+0x6a 0x12 # CHECK: lw16 $4, 8($17)
+0x29 0x82 # CHECK: lhu16 $3, 4($16)
+0x09 0x94 # CHECK: lbu16 $3, 4($17)
+0x09 0x9f # CHECK: lbu16 $3, -1($17)
+0x46 0x1B # CHECK: break16 8
+0xed 0xff # CHECK: li16 $3, -1
+0x0c 0x65 # CHECK: move16 $3, $5
+0x46 0x3b # CHECK: sdbbp16 8
+0x04 0x3b # CHECK: subu16 $5, $16, $3
+0x44 0xd8 # CHECK: xor16 $17, $5

llvm/trunk/test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   tgeu $22, $gp            # CHECK: tgeu $22, $gp       # encoding: [0x03,0x96,0x04,0x3c]
   tgeu $20, $14, 15        # CHECK: tgeu $20, $14, 15   # encoding: [0x01,0xd4,0xf4,0x3c]
   tlt $15, $13             # CHECK: tlt $15, $13        # encoding: [0x01,0xaf,0x08,0x3c]
   tlt $2, $19, 15          # CHECK: tlt $2, $19, 15     # encoding: [0x02,0x62,0xf8,0x3c]
   tltu $11, $16            # CHECK: tltu $11, $16       # encoding: [0x02,0x0b,0x0a,0x3c]
   tltu $16, $sp, 15        # CHECK: tltu $16, $sp, 15   # encoding: [0x03,0xb0,0xfa,0x3c]
   tne $6, $17              # CHECK: tne $6, $17         # encoding: [0x02,0x26,0x0c,0x3c]
   tne $7, $8, 15           # CHECK: tne $7, $8, 15      # encoding: [0x01,0x07,0xfc,0x3c]
+  break16 8                # CHECK: break16 8           # encoding: [0x46,0x1b]
+  li16 $3, -1              # CHECK: li16 $3, -1         # encoding: [0xed,0xff]
+  move16 $3, $5            # CHECK: move16 $3, $5       # encoding: [0x0c,0x65]
+  sdbbp16 8                # CHECK: sdbbp16 8           # encoding: [0x46,0x3b]
+  subu16 $5, $16, $3       # CHECK: subu16 $5, $16, $3  # encoding: [0x04,0x3b]
+  xor16 $17, $5            # CHECK: xor16 $17, $5       # encoding: [0x44,0xd8]

llvm/trunk/test/MC/Mips/micromips64r6/valid.s

a:
         tne $6, $17              # CHECK: tne $6, $17         # encoding: [0x02,0x26,0x0c,0x3c]
         tne $7, $8, 15           # CHECK: tne $7, $8, 15      # encoding: [0x01,0x07,0xfc,0x3c]
         cachee 1, 8($5)          # CHECK: cachee 1, 8($5)     # encoding: [0x60,0x25,0xa6,0x08]
         wrpgpr $3, $4            # CHECK: wrpgpr $3, $4       # encoding: [0x00,0x64,0xf1,0x7c]
         wsbh $3, $4              # CHECK: wsbh $3, $4         # encoding: [0x00,0x64,0x7b,0x3c]
         jalr $9                  # CHECK: jalr $9             # encoding: [0x45,0x2b]
         jrc16 $9                 # CHECK: jrc16 $9            # encoding: [0x45,0x23]
         jrcaddiusp 20            # CHECK: jrcaddiusp 20       # encoding: [0x44,0xb3]
+        break16 8                # CHECK: break16 8                # encoding: [0x46,0x1b]
+        li16 $3, -1              # CHECK: li16 $3, -1              # encoding: [0xed,0xff]
+        move16 $3, $5            # CHECK: move16 $3, $5            # encoding: [0x0c,0x65]
+        sdbbp16 8                # CHECK: sdbbp16 8                # encoding: [0x46,0x3b]
+        subu16 $5, $16, $3       # CHECK: subu16 $5, $16, $3       # encoding: [0x04,0x3b]
+        xor16 $17, $5            # CHECK: xor16 $17, $5            # encoding: [0x44,0xd8]
 
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