[X86] Don't clobber EBX in stackprobes

[staticfloat]

Summary

On X86, the stackprobe emission code chooses the R11D register, which
is illegal on i686. This ends up wrapping around to EBX, which does
not get properly callee-saved within the stack probing prologue,
clobbering the register for the callers.

We fix this by explicitly using EAX as the stack probe register.

[vtjnash]

Need a test fix, but lgtm

[pengfei]

llvm/lib/Target/X86/X86FrameLowering.cpp

674–676

How about x32, a model that using 32 bit pointer on 64bit target? Can we use

Register FinalStackProbed = Uses64BitFramePtr ? X86::R11 : Is64Bit ? X86::R11D : X86::EAX;

1097–1099

ditto.

[staticfloat]

Fix test, address review comments

[staticfloat]

llvm/lib/Target/X86/X86FrameLowering.cpp

674–676

Ah, good thinking. Better to use these registers when we can. Updated.

[pengfei]

llvm/test/CodeGen/X86/stack-clash-large.ll

1–3

We'd better add a RUN for the X64-32 case. How about

; RUN: llc -mtriple=x86_64-linux-android < %s | FileCheck -check-prefix=CHECK-X64 %s 
; RUN: llc -mtriple=i686-linux-android < %s | FileCheck -check-prefix=CHECK-X86 %s 
; RUN: llc -mtriple=x86_64-linux-gnux32 < %s | FileCheck -check-prefix=CHECK-X32 %s

We prefer to use prefix "X32" for the X64-32 case only and use X86 for the common 32 bit case.

[pengfei]

llvm/lib/Target/X86/X86FrameLowering.cpp

675

Change to the format Lint suggested?

[staticfloat]

Add new testing configuration for x32 hardware, apply lint format.

[staticfloat]

Tests expanded, and lint output applied.

llvm/lib/Target/X86/X86FrameLowering.cpp

675

Funnily enough, the arc diff HEAD~ command told me to lint it the old way. Manually re-formatting (as I just did in my latest change) causes the local arc lint step to complain, but I overrode it.

[pengfei]

LGTM. Thanks!

[vtjnash]

rebase on main

llvm/lib/Target/X86/X86FrameLowering.cpp

 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the X86 implementation of TargetFrameLowering class.
void X86FrameLowering::emitStackProbeInlineGenericLoop(
 
   MachineBasicBlock *testMBB = MF.CreateMachineBasicBlock(LLVM_BB);
   MachineBasicBlock *tailMBB = MF.CreateMachineBasicBlock(LLVM_BB);
 
   MachineFunction::iterator MBBIter = ++MBB.getIterator();
   MF.insert(MBBIter, testMBB);
   MF.insert(MBBIter, tailMBB);
 
-  Register FinalStackProbed = Uses64BitFramePtr ? X86::R11 : X86::R11D;
+  Register FinalStackProbed = Uses64BitFramePtr ? X86::R11
+                              : Is64Bit         ? X86::R11D
+                                                : X86::EAX;
   BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::COPY), FinalStackProbed)
       .addReg(StackPtr)
       .setMIFlag(MachineInstr::FrameSetup);
 
   // save loop bound
   {
     const unsigned SUBOpc = getSUBriOpcode(Uses64BitFramePtr, Offset);
     BuildMI(MBB, MBBI, DL, TII.get(SUBOpc), FinalStackProbed)
if (Reg == StackPtr && EmitInlineStackProbe && MaxAlign >= StackProbeSize) {
           MF.CreateMachineBasicBlock(MBB.getBasicBlock());
 
       MachineFunction::iterator MBBIter = MBB.getIterator();
       MF.insert(MBBIter, entryMBB);
       MF.insert(MBBIter, headMBB);
       MF.insert(MBBIter, bodyMBB);
       MF.insert(MBBIter, footMBB);
       const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
-      Register FinalStackProbed = Uses64BitFramePtr ? X86::R11 : X86::R11D;
+      Register FinalStackProbed = Uses64BitFramePtr ? X86::R11
+                                  : Is64Bit         ? X86::R11D
+                                                    : X86::EAX;
 
       // Setup entry block
       {
 
         entryMBB->splice(entryMBB->end(), &MBB, MBB.begin(), MBBI);
         BuildMI(entryMBB, DL, TII.get(TargetOpcode::COPY), FinalStackProbed)
             .addReg(StackPtr)
             .setMIFlag(MachineInstr::FrameSetup);

llvm/test/CodeGen/X86/stack-clash-large.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_sp
-; RUN: llc -mtriple=x86_64-linux-android < %s | FileCheck -check-prefix=CHECK-X86-64 %s
-; RUN: llc -mtriple=i686-linux-android < %s | FileCheck -check-prefix=CHECK-X86-32 %s
+; RUN: llc -mtriple=x86_64-linux-android < %s | FileCheck -check-prefix=CHECK-X64 %s
+; RUN: llc -mtriple=i686-linux-android < %s | FileCheck -check-prefix=CHECK-X86 %s
+; RUN: llc -mtriple=x86_64-linux-gnux32 < %s | FileCheck -check-prefix=CHECK-X32 %s
 
 define i32 @foo() local_unnamed_addr #0 {
-; CHECK-X86-64-LABEL: foo:
-; CHECK-X86-64:       # %bb.0:
-; CHECK-X86-64-NEXT:    movq %rsp, %r11
-; CHECK-X86-64-NEXT:    subq $69632, %r11 # imm = 0x11000
-; CHECK-X86-64-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
-; CHECK-X86-64-NEXT:    subq $4096, %rsp # imm = 0x1000
-; CHECK-X86-64-NEXT:    movq $0, (%rsp)
-; CHECK-X86-64-NEXT:    cmpq %r11, %rsp
-; CHECK-X86-64-NEXT:    jne .LBB0_1
-; CHECK-X86-64-NEXT:  # %bb.2:
-; CHECK-X86-64-NEXT:    subq $2248, %rsp # imm = 0x8C8
-; CHECK-X86-64-NEXT:    .cfi_def_cfa_offset 71888
-; CHECK-X86-64-NEXT:    movl $1, 264(%rsp)
-; CHECK-X86-64-NEXT:    movl $1, 28664(%rsp)
-; CHECK-X86-64-NEXT:    movl -128(%rsp), %eax
-; CHECK-X86-64-NEXT:    addq $71880, %rsp # imm = 0x118C8
-; CHECK-X86-64-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-X86-64-NEXT:    retq
+; CHECK-X64-LABEL: foo:
+; CHECK-X64:       # %bb.0:
+; CHECK-X64-NEXT:    movq %rsp, %r11
+; CHECK-X64-NEXT:    subq $69632, %r11 # imm = 0x11000
+; CHECK-X64-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-X64-NEXT:    subq $4096, %rsp # imm = 0x1000
+; CHECK-X64-NEXT:    movq $0, (%rsp)
+; CHECK-X64-NEXT:    cmpq %r11, %rsp
+; CHECK-X64-NEXT:    jne .LBB0_1
+; CHECK-X64-NEXT:  # %bb.2:
+; CHECK-X64-NEXT:    subq $2248, %rsp # imm = 0x8C8
+; CHECK-X64-NEXT:    .cfi_def_cfa_offset 71888
+; CHECK-X64-NEXT:    movl $1, 264(%rsp)
+; CHECK-X64-NEXT:    movl $1, 28664(%rsp)
+; CHECK-X64-NEXT:    movl -128(%rsp), %eax
+; CHECK-X64-NEXT:    addq $71880, %rsp # imm = 0x118C8
+; CHECK-X64-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-X64-NEXT:    retq
 ;
-; CHECK-X86-32-LABEL: foo:
-; CHECK-X86-32:       # %bb.0:
-; CHECK-X86-32-NEXT:    movl %esp, %r11d
-; CHECK-X86-32-NEXT:    subl $69632, %r11d # imm = 0x11000
-; CHECK-X86-32-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
-; CHECK-X86-32-NEXT:    subl $4096, %esp # imm = 0x1000
-; CHECK-X86-32-NEXT:    movl $0, (%esp)
-; CHECK-X86-32-NEXT:    cmpl %r11d, %esp
-; CHECK-X86-32-NEXT:    jne .LBB0_1
-; CHECK-X86-32-NEXT:  # %bb.2:
-; CHECK-X86-32-NEXT:    subl $2380, %esp # imm = 0x94C
-; CHECK-X86-32-NEXT:    .cfi_def_cfa_offset 72016
-; CHECK-X86-32-NEXT:    movl $1, 392(%esp)
-; CHECK-X86-32-NEXT:    movl $1, 28792(%esp)
-; CHECK-X86-32-NEXT:    movl (%esp), %eax
-; CHECK-X86-32-NEXT:    addl $72012, %esp # imm = 0x1194C
-; CHECK-X86-32-NEXT:    .cfi_def_cfa_offset 4
-; CHECK-X86-32-NEXT:    retl
+; CHECK-X86-LABEL: foo:
+; CHECK-X86:       # %bb.0:
+; CHECK-X86-NEXT:    movl %esp, %eax
+; CHECK-X86-NEXT:    subl $69632, %eax # imm = 0x11000
+; CHECK-X86-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-X86-NEXT:    subl $4096, %esp # imm = 0x1000
+; CHECK-X86-NEXT:    movl $0, (%esp)
+; CHECK-X86-NEXT:    cmpl %eax, %esp
+; CHECK-X86-NEXT:    jne .LBB0_1
+; CHECK-X86-NEXT:  # %bb.2:
+; CHECK-X86-NEXT:    subl $2380, %esp # imm = 0x94C
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 72016
+; CHECK-X86-NEXT:    movl $1, 392(%esp)
+; CHECK-X86-NEXT:    movl $1, 28792(%esp)
+; CHECK-X86-NEXT:    movl (%esp), %eax
+; CHECK-X86-NEXT:    addl $72012, %esp # imm = 0x1194C
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-X86-NEXT:    retl
+;
+; CHECK-X32-LABEL: foo:
+; CHECK-X32:       # %bb.0:
+; CHECK-X32-NEXT:    movl %esp, %r11d
+; CHECK-X32-NEXT:    subl $69632, %r11d # imm = 0x11000
+; CHECK-X32-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; CHECK-X32-NEXT:    subl $4096, %esp # imm = 0x1000
+; CHECK-X32-NEXT:    movq $0, (%esp)
+; CHECK-X32-NEXT:    cmpl %r11d, %esp
+; CHECK-X32-NEXT:    jne .LBB0_1
+; CHECK-X32-NEXT:  # %bb.2:
+; CHECK-X32-NEXT:    subl $2248, %esp # imm = 0x8C8
+; CHECK-X32-NEXT:    .cfi_def_cfa_offset 71888
+; CHECK-X32-NEXT:    movl $1, 264(%esp)
+; CHECK-X32-NEXT:    movl $1, 28664(%esp)
+; CHECK-X32-NEXT:    movl -128(%esp), %eax
+; CHECK-X32-NEXT:    addl $71880, %esp # imm = 0x118C8
+; CHECK-X32-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-X32-NEXT:    retq
   %a = alloca i32, i64 18000, align 16
   %b0 = getelementptr inbounds i32, i32* %a, i64 98
   %b1 = getelementptr inbounds i32, i32* %a, i64 7198
   store volatile i32 1, i32* %b0
   store volatile i32 1, i32* %b1
   %c = load volatile i32, i32* %a
   ret i32 %c
 }
 
 attributes #0 =  {"probe-stack"="inline-asm"}