[AMDGPU] Use S_BITCMP1_* to replace AND in optimizeCompareInstr

[rampitec]

Updated comment describing the transformation.

[rampitec]

Updated comment again.

[rampitec]

Rebased

[rampitec]

Fixed typo in the comment.

[arsenm]

LGTM although this looks identical in terms of code size and cycles

[rampitec]

In D109082#2978137, @arsenm wrote:

LGTM although this looks identical in terms of code size and cycles

Yes, but is saves one SGPR used for AND.

[foad]

Shouldn't we have normal instructions selection patterns for s_bitcmp0/1? Would this patch still be required if we had that?

[rampitec]

In D109082#2978991, @foad wrote:

Shouldn't we have normal instructions selection patterns for s_bitcmp0/1? Would this patch still be required if we had that?

I don't think so. First you cannot probably cover all scenarios with selection patterns, including patterns introduced by user's code. Second the moment you will introduce these instructions you will have to handle it everywhere, starting with moveToVALU. My idea it is better to stick with normal compares and replace it later when you done with potential transformations.

One thing which can be done is to also add this to SIShrinkInstructions, so it does not depend on the presence of a compare. That however will not allow reversing of the condition like in the subsequent patch as it needs to work together with a compare.

Lastly this optimization is independent of the selection, so agnostic to the type of ISel.

I.e. to my view relying on an ISel is a layering violation. ISel is like an FE for MI passes, they shall handle whatever is dumped on them as good as they can unless information is lost in the selection, just like a BE shall handle whatever an unoptimized FE creates unless it loses semantics info.

[foad]

I.e. to my view relying on an ISel is a layering violation.

In my view ISel is responsible for selection of instructions, and anything which changes those instructions to different ones later on is a bit of a hack :)

But I take your point about moveToVALU. That does sound a bit awkward.

[rampitec]

In D109082#2979040, @foad wrote:

I.e. to my view relying on an ISel is a layering violation.

In my view ISel is responsible for selection of instructions, and anything which changes those instructions to different ones later on is a bit of a hack :)

But I take your point about moveToVALU. That does sound a bit awkward.

Everything about VALU to SALU relationship is awkward. We basically have two separate engines tied together and that does not make compiler life easy. For example x86 has finally killed their x87 coprocessor because it is awkward to deal with.

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

 bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
                                        Register SrcReg2, int64_t CmpMask,
                                        int64_t CmpValue,
                                        const MachineRegisterInfo *MRI) const {
   if (SrcReg2 || SrcReg.isPhysical())
     return false;
 
   const auto optimizeCmpAnd = [&CmpInstr, SrcReg, CmpValue, MRI,
-                               this](int64_t ExpectedValue) -> bool {
+                               this](int64_t ExpectedValue,
+                                     unsigned SrcSize) -> bool {
     // s_cmp_eq_u32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
     // s_cmp_eq_i32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
     // s_cmp_ge_u32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
     // s_cmp_ge_i32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
     // s_cmp_eq_u64 (s_and_b64 $src, 1), 1 => s_and_b64 $src, 1
     // s_cmp_lg_u32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
     // s_cmp_lg_i32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
     // s_cmp_gt_u32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
     // s_cmp_gt_i32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
     // s_cmp_lg_u64 (s_and_b64 $src, 1), 0 => s_and_b64 $src, 1
-
-    // TODO: Fold this into s_bitcmp* if result of an AND is unused.
-    // TODO: If s_bitcmp can be used we are not limited to 1 and 0 but can
-    //       process any power of 2.
+    //
+    // If result of the AND is unused except in the compare:
+    // s_and_b(32|64) $src, 1 => s_bitcmp1_b(32|64) $src, 0
 
     if (CmpValue != ExpectedValue)
       return false;
 
     MachineInstr *Def = MRI->getUniqueVRegDef(SrcReg);
     if (!Def || Def->getParent() != CmpInstr.getParent())
       return false;
 
     if (Def->getOpcode() != AMDGPU::S_AND_B32 &&
         Def->getOpcode() != AMDGPU::S_AND_B64)
       return false;
 
-    if ((!Def->getOperand(1).isImm() || Def->getOperand(1).getImm() != 1) &&
-        (!Def->getOperand(2).isImm() || Def->getOperand(2).getImm() != 1))
+    MachineOperand *SrcOp = &Def->getOperand(1);
+    if (SrcOp->isImm() && SrcOp->getImm() == 1)
+      SrcOp = &Def->getOperand(2);
+    else if (!Def->getOperand(2).isImm() || Def->getOperand(2).getImm() != 1)
       return false;
 
     for (auto I = std::next(Def->getIterator()), E = CmpInstr.getIterator();
          I != E; ++I) {
       if (I->modifiesRegister(AMDGPU::SCC, &RI) ||
           I->killsRegister(AMDGPU::SCC, &RI))
         return false;
     }
 
     MachineOperand *SccDef = Def->findRegisterDefOperand(AMDGPU::SCC);
     SccDef->setIsDead(false);
     CmpInstr.eraseFromParent();
 
+    if (!MRI->use_nodbg_empty(Def->getOperand(0).getReg()))
+      return true;
+
+    // Replace AND with unused result with a S_BITCMP.
+    // TODO: If s_bitcmp can be used we are not limited to 1 and 0 but can
+    //       process any power of 2.
+    MachineBasicBlock *MBB = Def->getParent();
+
+    // TODO: Reverse conditions can use S_BITCMP0_*.
+    unsigned NewOpc = (SrcSize == 32) ? AMDGPU::S_BITCMP1_B32
+                                      : AMDGPU::S_BITCMP1_B64;
+
+    BuildMI(*MBB, Def, Def->getDebugLoc(), get(NewOpc))
+      .add(*SrcOp)
+      .addImm(0);
+    Def->eraseFromParent();
+
     return true;
   };
 
   switch (CmpInstr.getOpcode()) {
   default:
     break;
   case AMDGPU::S_CMP_EQ_U32:
   case AMDGPU::S_CMP_EQ_I32:
   case AMDGPU::S_CMP_GE_U32:
   case AMDGPU::S_CMP_GE_I32:
-  case AMDGPU::S_CMP_EQ_U64:
   case AMDGPU::S_CMPK_EQ_U32:
   case AMDGPU::S_CMPK_EQ_I32:
   case AMDGPU::S_CMPK_GE_U32:
   case AMDGPU::S_CMPK_GE_I32:
-    return optimizeCmpAnd(1);
+    return optimizeCmpAnd(1, 32);
+  case AMDGPU::S_CMP_EQ_U64:
+    return optimizeCmpAnd(1, 64);
   case AMDGPU::S_CMP_LG_U32:
   case AMDGPU::S_CMP_LG_I32:
   case AMDGPU::S_CMP_GT_U32:
   case AMDGPU::S_CMP_GT_I32:
-  case AMDGPU::S_CMP_LG_U64:
   case AMDGPU::S_CMPK_LG_U32:
   case AMDGPU::S_CMPK_LG_I32:
   case AMDGPU::S_CMPK_GT_U32:
   case AMDGPU::S_CMPK_GT_I32:
-    return optimizeCmpAnd(0);
+    return optimizeCmpAnd(0, 32);
+  case AMDGPU::S_CMP_LG_U64:
+    return optimizeCmpAnd(0, 64);
   }
 
   return false;
 }

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll

 ; IR-NEXT:    ret void
 ;
 ; GCN-LABEL: select_add_lhs_const_i16:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dword s0, s[4:5], 0x0
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0x83
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0x80
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_and_b32 s0, 1, s0
+; GCN-NEXT:    s_bitcmp1_b32 s0, 0
 ; GCN-NEXT:    s_cselect_b64 vcc, -1, 0
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GCN-NEXT:    flat_store_short v[0:1], v0
 ; GCN-NEXT:    s_endpgm
   %select = select i1 %cond, i16 5, i16 8
   %op = add i16 %select, 123
   store i16 %op, i16 addrspace(1)* undef
   ret void

llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll

 ; GCN-LABEL: v3i16_registers:
 ; GCN:       ; %bb.0: ; %entry
 ; GCN-NEXT:    s_load_dword s4, s[4:5], 0x0
 ; GCN-NEXT:    s_add_u32 flat_scratch_lo, s6, s9
 ; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s7, 0
 ; GCN-NEXT:    s_add_u32 s0, s0, s9
 ; GCN-NEXT:    s_addc_u32 s1, s1, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_and_b32 s4, 1, s4
+; GCN-NEXT:    s_bitcmp1_b32 s4, 0
 ; GCN-NEXT:    s_cselect_b64 s[4:5], -1, 0
 ; GCN-NEXT:    s_and_b64 vcc, exec, s[4:5]
 ; GCN-NEXT:    s_mov_b32 s32, 0
 ; GCN-NEXT:    s_cbranch_vccnz BB4_2
 ; GCN-NEXT:  ; %bb.1: ; %if.else
 ; GCN-NEXT:    s_getpc_b64 s[4:5]
 ; GCN-NEXT:    s_add_u32 s4, s4, func_v3i16@rel32@lo+4
 ; GCN-NEXT:    s_addc_u32 s5, s5, func_v3i16@rel32@hi+12

 ; GCN-LABEL: v3f16_registers:
 ; GCN:       ; %bb.0: ; %entry
 ; GCN-NEXT:    s_load_dword s4, s[4:5], 0x0
 ; GCN-NEXT:    s_add_u32 flat_scratch_lo, s6, s9
 ; GCN-NEXT:    s_addc_u32 flat_scratch_hi, s7, 0
 ; GCN-NEXT:    s_add_u32 s0, s0, s9
 ; GCN-NEXT:    s_addc_u32 s1, s1, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_and_b32 s4, 1, s4
+; GCN-NEXT:    s_bitcmp1_b32 s4, 0
 ; GCN-NEXT:    s_cselect_b64 s[4:5], -1, 0
 ; GCN-NEXT:    s_and_b64 vcc, exec, s[4:5]
 ; GCN-NEXT:    s_mov_b32 s32, 0
 ; GCN-NEXT:    s_cbranch_vccnz BB5_2
 ; GCN-NEXT:  ; %bb.1: ; %if.else
 ; GCN-NEXT:    s_getpc_b64 s[4:5]
 ; GCN-NEXT:    s_add_u32 s4, s4, func_v3f16@rel32@lo+4
 ; GCN-NEXT:    s_addc_u32 s5, s5, func_v3f16@rel32@hi+12

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll

 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c
 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x25
 
 ; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c
 ; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x70
 ; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x94
 
-; GCN-DAG: s_and_b32 [[AND_I1:s[0-9]+]], 1, s{{[0-9]+}}
+; GCN-DAG: s_bitcmp1_b32 s{{[0-9]+}}, 0
 
 ; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
 ; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
 ; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
 ; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], [[VC]]
 ; GCN: buffer_store_dword [[RESULT]],
 define amdgpu_kernel void @test_div_fmas_f32(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b, [8 x i32], float %c, [8 x i32], i1 %d) nounwind {
   %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone

llvm/test/CodeGen/AMDGPU/optimize-compare.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=peephole-opt --verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
 
 ---
 name:            and_1_cmp_eq_u32_1
 body:             |
   ; GCN-LABEL: name: and_1_cmp_eq_u32_1
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
+  ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
+  ; GCN:   S_BRANCH %bb.1
+  ; GCN: bb.1:
+  ; GCN:   successors: %bb.2(0x80000000)
+  ; GCN: bb.2:
+  ; GCN:   S_ENDPGM 0
+  bb.0:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: $sgpr0, $vgpr0_vgpr1
+
+    %0:sreg_32 = COPY $sgpr0
+    %1:sreg_32 = S_AND_B32 1, killed %0, implicit-def dead $scc
+    S_CMP_EQ_U32 killed %1:sreg_32, 1, implicit-def $scc
+    S_CBRANCH_SCC0 %bb.2, implicit $scc
+    S_BRANCH %bb.1
+
+  bb.1:
+    successors: %bb.2(0x80000000)
+
+  bb.2:
+    S_ENDPGM 0
+
+...
+
+---
+name:            and_1_cmp_eq_u32_1_used_and
+body:             |
+  ; GCN-LABEL: name: and_1_cmp_eq_u32_1_used_and
+  ; GCN: bb.0:
+  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_NOP 0, implicit [[S_AND_B32_]]
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $sgpr0, $vgpr0_vgpr1
 
     %0:sreg_32 = COPY $sgpr0
     %1:sreg_32 = S_AND_B32 1, killed %0, implicit-def dead $scc
+    S_NOP 0, implicit %1
     S_CMP_EQ_U32 killed %1:sreg_32, 1, implicit-def $scc
     S_CBRANCH_SCC0 %bb.2, implicit $scc
     S_BRANCH %bb.1
 
   bb.1:
     successors: %bb.2(0x80000000)
 
   bb.2:
     S_ENDPGM 0
 
 ...
 
 ---
 name:            and_1_cmp_eq_i32_1
 body:             |
   ; GCN-LABEL: name: and_1_cmp_eq_i32_1
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            commuted_and_1_cmp_eq_1
 body:             |
   ; GCN-LABEL: name: commuted_and_1_cmp_eq_1
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 killed [[COPY]], 1, implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmp_ge_u32_1
 body:             |
   ; GCN-LABEL: name: and_1_cmp_ge_u32_1
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmp_ge_i32_1
 body:             |
   ; GCN-LABEL: name: and_1_cmp_ge_i32_1
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmp_gt_u32_0
 body:             |
   ; GCN-LABEL: name: and_1_cmp_gt_u32_0
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmp_gt_i32_0
 body:             |
   ; GCN-LABEL: name: and_1_cmp_gt_i32_0
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmp_lg_u32_0
 body:             |
   ; GCN-LABEL: name: and_1_cmp_lg_u32_0
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmp_lg_i32_0
 body:             |
   ; GCN-LABEL: name: and_1_cmp_lg_i32_0
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmp_eq_u64_1
 body:             |
   ; GCN-LABEL: name: and_1_cmp_eq_u64_1
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
-  ; GCN:   [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B64 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmp_lg_u64_0
 body:             |
   ; GCN-LABEL: name: and_1_cmp_lg_u64_0
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
-  ; GCN:   [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B64 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmpk_eq_u32_1
 body:             |
   ; GCN-LABEL: name: and_1_cmpk_eq_u32_1
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmpk_eq_i32_1
 body:             |
   ; GCN-LABEL: name: and_1_cmpk_eq_i32_1
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmpk_ge_u32_1
 body:             |
   ; GCN-LABEL: name: and_1_cmpk_ge_u32_1
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmpk_ge_i32_1
 body:             |
   ; GCN-LABEL: name: and_1_cmpk_ge_i32_1
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmpk_lg_u32_0
 body:             |
   ; GCN-LABEL: name: and_1_cmpk_lg_u32_0
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmpk_lg_i32_0
 body:             |
   ; GCN-LABEL: name: and_1_cmpk_lg_i32_0
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmpk_gt_u32_0
 body:             |
   ; GCN-LABEL: name: and_1_cmpk_gt_u32_0
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)

 
 ---
 name:            and_1_cmpk_gt_i32_0
 body:             |
   ; GCN-LABEL: name: and_1_cmpk_gt_i32_0
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
-  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, killed [[COPY]], implicit-def $scc
+  ; GCN:   S_BITCMP1_B32 killed [[COPY]], 0, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $sgpr0, $vgpr0_vgpr1
 
     %0:sreg_32 = COPY $sgpr0
     %1:sreg_32 = S_AND_B32 1, killed %0, implicit-def dead $scc
     S_CMPK_GT_I32 killed %1:sreg_32, 0, implicit-def $scc
     S_CBRANCH_SCC0 %bb.2, implicit $scc
     S_BRANCH %bb.1
 
   bb.1:
     successors: %bb.2(0x80000000)
 
   bb.2:
     S_ENDPGM 0
 
 ...
+
+---
+name:            and_1_cmp_eq_u32_1_imm_src
+body:             |
+  ; GCN-LABEL: name: and_1_cmp_eq_u32_1_imm_src
+  ; GCN: bb.0:
+  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN:   S_BITCMP1_B32 11, 0, implicit-def $scc
+  ; GCN:   S_CBRANCH_SCC0 %bb.2, implicit $scc
+  ; GCN:   S_BRANCH %bb.1
+  ; GCN: bb.1:
+  ; GCN:   successors: %bb.2(0x80000000)
+  ; GCN: bb.2:
+  ; GCN:   S_ENDPGM 0
+  bb.0:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: $sgpr0, $vgpr0_vgpr1
+
+    %0:sreg_32 = S_AND_B32 1, 11, implicit-def dead $scc
+    S_CMP_EQ_U32 killed %0:sreg_32, 1, implicit-def $scc
+    S_CBRANCH_SCC0 %bb.2, implicit $scc
+    S_BRANCH %bb.1
+
+  bb.1:
+    successors: %bb.2(0x80000000)
+
+  bb.2:
+    S_ENDPGM 0
+
+...

llvm/test/CodeGen/AMDGPU/select-i1.ll

define amdgpu_kernel void @select_i1(i1 addrspace(1)* %out, i32 %cond, i1 %a, i1 %b) nounwind {
   %cmp = icmp ugt i32 %cond, 5
   %sel = select i1 %cmp, i1 %a, i1 %b
   store i1 %sel, i1 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}s_minmax_i1:
 ; GCN: s_load_dword [[LOAD:s[0-9]+]],
-; GCN: s_and_b32 [[COND:s[0-9]+]], 1, [[LOAD]]
+; GCN: s_bitcmp1_b32 [[LOAD]], 0
 ; GCN: s_cselect_b64 vcc, -1, 0
 ; GCN-DAG: s_lshr_b32 [[A:s[0-9]+]], [[LOAD]], 8
 ; GCN-DAG: s_lshr_b32 [[B:s[0-9]+]], [[LOAD]], 16
 
 ; GCN: v_mov_b32_e32 [[V_B:v[0-9]+]], [[B]]
 ; GCN: v_mov_b32_e32 [[V_A:v[0-9]+]], [[A]]
 ; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], [[V_B]], [[V_A]]
 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, [[SEL]]
 define amdgpu_kernel void @s_minmax_i1(i1 addrspace(1)* %out, [8 x i32], i1 zeroext %cond, i1 zeroext %a, i1 zeroext %b) nounwind {
   %cmp = icmp slt i1 %cond, false
   %sel = select i1 %cmp, i1 %a, i1 %b
   store i1 %sel, i1 addrspace(1)* %out, align 4
   ret void
 }

llvm/test/CodeGen/AMDGPU/trunc.ll

define amdgpu_kernel void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
   %result = select i1 %trunc, i32 1, i32 0
   store i32 %result, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}s_trunc_i64_to_i1:
 ; SI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x13
 ; VI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x4c
-; GCN: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]
+; GCN: s_bitcmp1_b32 s[[SLO]], 0
 ; SI: s_cselect_b64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], -1, 0
 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]
 ; VI: s_cselect_b32 {{s[0-9]+}}, 63, -12
 define amdgpu_kernel void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, [8 x i32], i64 %x) {
   %trunc = trunc i64 %x to i1
   %sel = select i1 %trunc, i32 63, i32 -12
   store i32 %sel, i32 addrspace(1)* %out
   ret void

llvm/test/CodeGen/AMDGPU/wave32.ll

define i64 @test_mad_u64_u32(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
   %sext0 = zext i32 %arg0 to i64
   %sext1 = zext i32 %arg1 to i64
   %mul = mul i64 %sext0, %sext1
   %mad = add i64 %mul, %arg2
   ret i64 %mad
 }
 
 ; GCN-LABEL: {{^}}test_div_fmas_f32:
-; GCN:     s_and_b32 s{{[0-9]+}}, 1
+; GCN:     s_bitcmp1_b32 s{{[0-9]+}}, 0
 ; GFX1032: s_cselect_b32 vcc_lo, -1, 0
 ; GFX1064: s_cselect_b64 vcc, -1, 0
 ; GCN:     v_div_fmas_f32 v{{[0-9]+}}, {{[vs][0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 define amdgpu_kernel void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
   %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone
   store float %result, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_div_fmas_f64:
-; GCN: s_and_b32 s{{[0-9]+}}, 1
+; GCN:     s_bitcmp1_b32 s{{[0-9]+}}, 0
 ; GFX1032: s_cselect_b32 vcc_lo, -1, 0
 ; GFX1064: s_cselect_b64 vcc, -1, 0
 ; GCN-DAG: v_div_fmas_f64 v[{{[0-9:]+}}], {{[vs]}}[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}]
 define amdgpu_kernel void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind {
   %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone
   store double %result, double addrspace(1)* %out, align 8
   ret void
 }