Fix typo in RISCVSchedSiFive7.td

[apivovarov]

Summary

Fix typo in "microarchitecure"

[craig.topper]

LGTM

[jrtc27]

FYI this kind of change is one of the examples explicitly mentioned in the developer policy that doesn't need review:

You are allowed to commit patches without approval which you think are obvious. This is clearly a subjective decision — we simply expect you to use good judgement. Examples include: fixing build breakage, reverting obviously broken patches, documentation/comment changes, any other minor changes.

[apivovarov]

Thank you, Jessica, for the hint! I've just sent the commit access request to Chris.

[apivovarov]

Craig, can you push it? I have not got any replies from @lattner regarding granting commit access.

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

def SiFive7Model : SchedMachineModel {
   let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order.
   let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = 0;
   let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg];
 }
 
-// The SiFive7 microarchitecure has two pipelines: A and B.
+// The SiFive7 microarchitecture has two pipelines: A and B.
 // Pipe A can handle memory, integer alu and vector operations.
 // Pipe B can handle integer alu, control flow, integer multiply and divide,
 // and floating point computation.
 let SchedModel = SiFive7Model in {
 let BufferSize = 0 in {
 def SiFive7PipeA       : ProcResource<1>;
 def SiFive7PipeB       : ProcResource<1>;
 }