[AArch64] Support target specific isSuitableForJumpTable

[jaykang10]

Summary

On TargetLowering::isSuitableForJumpTable, the minimum size is not checked. This patch checks it on AArch64's isSuitableForJumpTable.

We could want to set setMinimumJumpTableEntries in order to adjust the minimum size of jump table. At the beginning of findJumpTables, it is compared to the number of clusters without considering each cluster which might be optimized for adjacent cases with same destination block. I think it would be better to check the minimum size of jump table on isSuitableForJumpTable to consider the each cluster.

As you can see, this patch affects existing tests which are related to jump table on AArch64. If there were certain assumptions of the jump table size on AArch64, please let me know.

I have checked the benchmark scores and the scores are as below.

spec2017 Ofast	score improvement(%)
500.perlbench_r	1.120718061
502.gcc_r	0.21566066
505.mcf_r	-0.377692164
520.omnetpp_r	-0.033963362
523.xalancbmk_r	-0.710515296
525.x264_r	-0.009670442
531.deepsjeng_r	-0.151793551
541.leela_r	0.000412303
548.exchange2_r	-0.005073052
557.xz_r	0.14042818
	
spec2017 O3 lto	score improvement(%)
500.perlbench_r	0.499563704
502.gcc_r	1.243011689
505.mcf_r	-0.448723782
520.omnetpp_r	-0.343839249
523.xalancbmk_r	-0.857326043
525.x264_r	0.1447399
531.deepsjeng_r	0.271570876
541.leela_r	-0.008724735
548.exchange2_r	-0.004679532
557.xz_r	-0.131507228
	
spec2006 O3 lto	score improvement(%)
400.perlbench	0.606229456
401.bzip2	-0.855386753
403.gcc	0.674752856
429.mcf	-0.007256516
445.gobmk	-0.175565964
456.hmmer	0.225698132
458.sjeng	0.016811133
462.libquantum	-0.366765648
464.h264ref	1.29015527
471.omnetpp	1.148017212
473.astar	-0.114839198
483.xalancbmk	0.1115539

Tests: 778
Same hash: 313 (filtered out) 
Remaining: 465
Metric: exec_time

Program                                        results.org results.mod diff 
 test-suite...128UniformDivisor<__uint128_t>    12.37       12.37       0.0%
 test-suite...emCmp<3, GreaterThanZero, Mid>   2737.85     2737.85      0.0% 
 test-suite...emCmp<4, GreaterThanZero, Mid>   1634.42     1634.42      0.0% 
 test-suite...Cmp<4, GreaterThanZero, First>   1627.17     1627.17      0.0% 
 test-suite...mCmp<4, GreaterThanZero, None>   1633.03     1633.03      0.0% 
 test-suite..._MemCmp<4, LessThanZero, Last>   1504.30     1504.30      0.0% 
 test-suite...M_MemCmp<4, LessThanZero, Mid>   1510.02     1510.02      0.0% 
 test-suite...MemCmp<4, LessThanZero, First>   1503.89     1503.89      0.0% 
 test-suite..._MemCmp<4, LessThanZero, None>   1503.94     1503.94      0.0% 
 test-suite...est:BM_MemCmp<4, EqZero, Last>   953.13      953.13       0.0%
 test-suite...test:BM_MemCmp<4, EqZero, Mid>   994.46      994.46       0.0%
 test-suite...st:BM_MemCmp<4, EqZero, First>   953.40      953.40       0.0%
 test-suite...est:BM_MemCmp<4, EqZero, None>   957.15      957.15       0.0%
 test-suite...mCmp<3, GreaterThanZero, Last>   2883.71     2883.71      0.0% 
 test-suite...Cmp<3, GreaterThanZero, First>   2766.46     2766.46      0.0% 
 Geomean difference                                                     0.0%
         results.org    results.mod   diff 
count  465.000000     465.000000     465.0
mean   3433.740927    3433.740927    0.0  
std    33459.989197   33459.989197   0.0  
min    0.052810       0.052810       0.0
25%    25.266975      25.266975      0.0  
50%    334.556472     334.556472     0.0  
75%    1036.344130    1036.344130    0.0  
max    507694.300000  507694.300000  0.0

[dmgreen]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

10753

Where did the number 16 come from? Just from benchmarks? Unless there are jump tables in hot areas of the code this is more likely to be measuring the knock-on effects of changing code alignment than anything actually to do with the jump tables. It just turns into noise that doesn't stand up over time as other changes get made by the compiler.

It would likely be best to at least have it as an option. Some of the tests below could then keep small testing jumptables.

llvm/test/CodeGen/AArch64/jump-table.ll

6

Any of these test checking for the structure of jump tables are probably best left testing jump tables, perhaps with an option to overwrite the default.

[jaykang10]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

10753

Thanks for comment @dmgreen

As you know, AArch64 target generates jump table as below.

// %bb.0:                               // %entry
	sub	w8, w0, #1
	cmp	w8, #3
	b.hi	.LBB0_6
// %bb.1:                               // %entry
	adrp	x9, .LJTI0_0
	add	x9, x9, :lo12:.LJTI0_0
	adr	x10, .LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
...
.LJTI0_0:
	.byte	(.LBB0_2-.LBB0_2)>>2
	.byte	(.LBB0_3-.LBB0_2)>>2
	.byte	(.LBB0_4-.LBB0_2)>>2
	.byte	(.LBB0_5-.LBB0_2)>>2

Let's say we consider only the number of instructions rather than instruction cycle and latency information. There are usually 9 instructions for jump table. If we do not generate jump table, there are cmp and branch instructions per each case. It means that if there are switch instruction with 4 cases, jump table could be slower than the combination of cmp and branch instructions. For other case, if the cmp and branch instructions at the beginning are taken, the jump table could be slower. If we consider each architecture's cycle information, it will be more complex to decide the number...

At this moment, AArch64 target is using the default setMinimumJumpTableEntries(4) but it does not consider each cluster which might be optimized for adjacent cases with same destination block. It could be good to implement AArch64 specific isSuitableForJumpTable.

I agree with you. It will be better to have option to tune it.

Let me think about this patch more carefully.

llvm/test/CodeGen/AArch64/jump-table.ll

6

Yep, I agree with you.

llvm/lib/Target/AArch64/AArch64ISelLowering.h

public:
 
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
 
   /// Return true if the given shuffle mask can be codegen'd directly, or if it
   /// should be stack expanded.
   bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
 
+  /// Return true if lowering to a jump table is suitable for a set of case
+  /// clusters which may contain NumCases cases, Range range of values.
+  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
+                                      uint64_t Range, ProfileSummaryInfo *PSI,
+                                      BlockFrequencyInfo *BFI) const;
+
   /// Return the ISD::SETCC ValueType.
   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
                          EVT VT) const override;
 
   SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
 
   MachineBasicBlock *EmitF128CSEL(MachineInstr &MI,
                                   MachineBasicBlock *BB) const;

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
           isZIPMask(M, VT, DummyUnsigned) ||
           isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
           isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
           isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
           isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
           isConcatMask(M, VT, VT.getSizeInBits() == 128));
 }
 
+bool AArch64TargetLowering::isSuitableForJumpTable(
+    const SwitchInst *SI, uint64_t NumCases, uint64_t Range,
+    ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const {
+  // On TargetLowering::isSuitableForJumpTable, the minimum size is not checked.
+  // Check the minimum NumCases. The number 16 has been decided by benchmark
+  // scores.
+  if (NumCases <= 16)
+    return false;
+  return TargetLowering::isSuitableForJumpTable(SI, NumCases, Range, PSI, BFI);
+}
+
 /// getVShiftImm - Check if this is a valid build_vector for the immediate
 /// operand of a vector shift operation, where all the elements of the
 /// build_vector must have the same constant integer value.
 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
   // Ignore bit_converts.
   while (Op.getOpcode() == ISD::BITCAST)
     Op = Op.getOperand(0);
   BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll

define i32 @switch(i32 %argc) {
   ; CHECK:   G_BR %bb.5
   ; CHECK: bb.3.case100:
   ; CHECK:   successors: %bb.5(0x80000000)
   ; CHECK:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C3]]
   ; CHECK:   G_BR %bb.5
   ; CHECK: bb.4.case200:
   ; CHECK:   successors: %bb.5(0x80000000)
   ; CHECK:   [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+  ; CHECK:   G_BR %bb.5
   ; CHECK: bb.5.return:
   ; CHECK:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.2, [[ADD1]](s32), %bb.3, [[ADD2]](s32), %bb.4
   ; CHECK:   $w0 = COPY [[PHI]](s32)
   ; CHECK:   RET_ReallyLR implicit $w0
 entry:
   switch i32 %argc, label %default [
     i32 100, label %case100
     i32 200, label %case200

 phi.block:
   %res = phi i32 [1, %entry], [1, %entry], [42, %next]
   ret i32 12
 }
 
 define i32 @jt_test(i32 %x) {
   ; CHECK-LABEL: name: jt_test
   ; CHECK: bb.1.entry:
-  ; CHECK:   successors: %bb.4(0x40000000), %bb.5(0x40000000)
+  ; CHECK:   successors: %bb.3(0x40000000), %bb.5(0x40000000)
   ; CHECK:   liveins: $w0
   ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
-  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 71
-  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
-  ; CHECK:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-  ; CHECK:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-  ; CHECK:   [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C4]]
-  ; CHECK:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32)
-  ; CHECK:   [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32)
-  ; CHECK:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[ZEXT]](s64), [[ZEXT1]]
-  ; CHECK:   G_BRCOND [[ICMP]](s1), %bb.4
+  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 34
+  ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 40
+  ; CHECK:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 56
+  ; CHECK:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 75
+  ; CHECK:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+  ; CHECK:   [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+  ; CHECK:   [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; CHECK:   [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C]]
+  ; CHECK:   [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+  ; CHECK:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[SUB]](s32), [[C8]]
+  ; CHECK:   G_BRCOND [[ICMP]](s1), %bb.3
+  ; CHECK:   G_BR %bb.5
   ; CHECK: bb.5.entry:
-  ; CHECK:   successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
-  ; CHECK:   [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
-  ; CHECK:   G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[ZEXT]](s64)
+  ; CHECK:   successors: %bb.2(0x40000000), %bb.6(0x40000000)
+  ; CHECK:   [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C1]]
+  ; CHECK:   [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK:   [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[SUB1]](s32), [[C9]]
+  ; CHECK:   G_BRCOND [[ICMP1]](s1), %bb.2
+  ; CHECK:   G_BR %bb.6
+  ; CHECK: bb.6.entry:
+  ; CHECK:   successors: %bb.2(0x40000000), %bb.7(0x40000000)
+  ; CHECK:   [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C2]]
+  ; CHECK:   G_BRCOND [[ICMP2]](s1), %bb.2
+  ; CHECK:   G_BR %bb.7
+  ; CHECK: bb.7.entry:
+  ; CHECK:   successors: %bb.2(0x40000000), %bb.8(0x40000000)
+  ; CHECK:   [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C3]]
+  ; CHECK:   G_BRCOND [[ICMP3]](s1), %bb.2
+  ; CHECK:   G_BR %bb.8
+  ; CHECK: bb.8.entry:
+  ; CHECK:   successors: %bb.2(0x40000000), %bb.4(0x40000000)
+  ; CHECK:   [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C4]]
+  ; CHECK:   G_BRCOND [[ICMP4]](s1), %bb.2
+  ; CHECK:   G_BR %bb.4
   ; CHECK: bb.2.sw.bb:
   ; CHECK:   successors: %bb.4(0x80000000)
-  ; CHECK:   [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[C2]]
+  ; CHECK:   [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[C6]]
   ; CHECK:   G_BR %bb.4
   ; CHECK: bb.3.sw.bb1:
   ; CHECK:   successors: %bb.4(0x80000000)
-  ; CHECK:   [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY]], [[C1]]
+  ; CHECK:   [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY]], [[C5]]
+  ; CHECK:   G_BR %bb.4
   ; CHECK: bb.4.return:
-  ; CHECK:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[MUL]](s32), %bb.3, [[ADD]](s32), %bb.2, [[C3]](s32), %bb.1, [[C3]](s32), %bb.5
+  ; CHECK:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[MUL]](s32), %bb.3, [[ADD]](s32), %bb.2, [[C7]](s32), %bb.8
   ; CHECK:   $w0 = COPY [[PHI]](s32)
   ; CHECK:   RET_ReallyLR implicit $w0
 entry:
   switch i32 %x, label %return [
     i32 75, label %sw.bb
     i32 34, label %sw.bb
     i32 56, label %sw.bb
     i32 35, label %sw.bb
define void @jt_multiple_jump_tables(%1* %arg, i32 %arg1, i32* %arg2) {
   ; CHECK: bb.53.bb54:
   ; CHECK:   successors: %bb.56(0x80000000)
   ; CHECK:   G_BR %bb.56
   ; CHECK: bb.54.bb55:
   ; CHECK:   successors: %bb.56(0x80000000)
   ; CHECK:   G_BR %bb.56
   ; CHECK: bb.55.bb56:
   ; CHECK:   successors: %bb.56(0x80000000)
+  ; CHECK:   G_BR %bb.56
   ; CHECK: bb.56.bb57:
   ; CHECK:   successors: %bb.59(0x80000000)
   ; CHECK:   [[PHI:%[0-9]+]]:_(s64) = G_PHI [[C56]](s64), %bb.1, [[C57]](s64), %bb.2, [[C58]](s64), %bb.3, [[C59]](s64), %bb.4, [[C60]](s64), %bb.5, [[C61]](s64), %bb.6, [[C62]](s64), %bb.7, [[C63]](s64), %bb.8, [[C64]](s64), %bb.9, [[C65]](s64), %bb.10, [[C66]](s64), %bb.11, [[C67]](s64), %bb.12, [[C68]](s64), %bb.13, [[C69]](s64), %bb.14, [[C70]](s64), %bb.15, [[C71]](s64), %bb.16, [[C72]](s64), %bb.17, [[C73]](s64), %bb.18, [[C74]](s64), %bb.19, [[C75]](s64), %bb.20, [[C76]](s64), %bb.21, [[C77]](s64), %bb.22, [[C78]](s64), %bb.23, [[C79]](s64), %bb.24, [[C80]](s64), %bb.25, [[C81]](s64), %bb.26, [[C82]](s64), %bb.27, [[C83]](s64), %bb.28, [[C84]](s64), %bb.29, [[C85]](s64), %bb.30, [[C86]](s64), %bb.31, [[C87]](s64), %bb.32, [[C88]](s64), %bb.33, [[C89]](s64), %bb.34, [[C90]](s64), %bb.35, [[C91]](s64), %bb.36, [[C92]](s64), %bb.37, [[C93]](s64), %bb.38, [[C94]](s64), %bb.39, [[C95]](s64), %bb.40, [[C96]](s64), %bb.41, [[C97]](s64), %bb.42, [[C98]](s64), %bb.43, [[C99]](s64), %bb.44, [[C100]](s64), %bb.45, [[C101]](s64), %bb.46, [[C102]](s64), %bb.47, [[C103]](s64), %bb.48, [[C104]](s64), %bb.49, [[C105]](s64), %bb.50, [[C106]](s64), %bb.51, [[C107]](s64), %bb.52, [[C108]](s64), %bb.53, [[C109]](s64), %bb.54, [[C110]](s64), %bb.55
   ; CHECK:   [[C111:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
   ; CHECK:   [[MUL:%[0-9]+]]:_(s64) = G_MUL [[PHI]], [[C111]]
   ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[MUL]](s64)
   ; CHECK:   [[C112:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
   ; CHECK:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C112]](s64)
define void @jt_multiple_jump_tables(%1* %arg, i32 %arg1, i32* %arg2) {
   ; CHECK:   BL @baz, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $x1
   ; CHECK:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
   ; CHECK:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
   ; CHECK:   $x0 = COPY [[COPY]](p0)
   ; CHECK:   $x1 = COPY [[COPY5]](p0)
   ; CHECK:   BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1
   ; CHECK:   [[COPY6:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
   ; CHECK:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+  ; CHECK:   G_BR %bb.59
   ; CHECK: bb.59.bb68:
   ; CHECK:   RET_ReallyLR
   ; CHECK: bb.60.bb69:
   ; CHECK:   successors: %bb.58(0x40000000), %bb.57(0x40000000)
   ; CHECK:   [[ICMP55:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](p0), [[C55]]
   ; CHECK:   G_BRCOND [[ICMP55]](s1), %bb.58
   ; CHECK:   G_BR %bb.57
 bb:
define void @jt_2_tables_phi_edge_from_second() {
   ; CHECK: bb.13.sw.bb8.i:
   ; CHECK:   successors: %bb.16(0x80000000)
   ; CHECK:   G_BR %bb.16
   ; CHECK: bb.14.sw.bb9.i:
   ; CHECK:   successors: %bb.16(0x80000000)
   ; CHECK:   G_BR %bb.16
   ; CHECK: bb.15.sw.bb12.i:
   ; CHECK:   successors: %bb.16(0x80000000)
+  ; CHECK:   G_BR %bb.16
   ; CHECK: bb.16.land.rhs.lr.ph:
   ; CHECK:   successors: %bb.17(0x40000000), %bb.18(0x40000000)
   ; CHECK:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C13]](s32), %bb.24, [[C14]](s32), %bb.9, [[C15]](s32), %bb.10, [[C16]](s32), %bb.11, [[C17]](s32), %bb.12, [[C18]](s32), %bb.13, [[C19]](s32), %bb.14, [[C20]](s32), %bb.15
   ; CHECK:   G_BRCOND [[DEF2]](s1), %bb.17
   ; CHECK:   G_BR %bb.18
   ; CHECK: bb.17.while.body:
   ; CHECK:   successors:
   ; CHECK:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
define i32 @range_test(i32 %x) {
   ; CHECK:   G_BR %bb.4
   ; CHECK: bb.2.sw.bb:
   ; CHECK:   successors: %bb.4(0x80000000)
   ; CHECK:   [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[C3]]
   ; CHECK:   G_BR %bb.4
   ; CHECK: bb.3.sw.bb1:
   ; CHECK:   successors: %bb.4(0x80000000)
   ; CHECK:   [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY]], [[C2]]
+  ; CHECK:   G_BR %bb.4
   ; CHECK: bb.4.return:
   ; CHECK:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[MUL]](s32), %bb.3, [[ADD]](s32), %bb.2, [[C4]](s32), %bb.5
   ; CHECK:   $w0 = COPY [[PHI]](s32)
   ; CHECK:   RET_ReallyLR implicit $w0
 entry:
   switch i32 %x, label %return [
     i32 24, label %sw.bb
     i32 25, label %sw.bb
define i64* @test_range_phi_switch_cycle() {
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
   ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 305
   ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 307
   ; CHECK:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 497
   ; CHECK:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
   ; CHECK:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
   ; CHECK:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; CHECK:   G_BR %bb.2
   ; CHECK: bb.2.bb1:
   ; CHECK:   successors: %bb.2(0x40000000), %bb.6(0x40000000)
   ; CHECK:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[DEF]](s32), %bb.1, [[C3]](s32), %bb.3, [[C4]](s32), %bb.4, [[C5]](s32), %bb.2
   ; CHECK:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF]](s32), [[C]]
   ; CHECK:   G_BRCOND [[ICMP]](s1), %bb.2
   ; CHECK:   G_BR %bb.6
   ; CHECK: bb.6.bb1:
   ; CHECK:   successors: %bb.3(0x40000000), %bb.7(0x40000000)

llvm/test/CodeGen/AArch64/arm64-jumptable.ll

exit.sink.split:
   %.sink = phi i32 [ 5, %bb4 ], [ %b, %bb1 ], [ 3, %bb3 ], [ %a, %entry ]
   store i32 %.sink, i32* %to
   br label %exit
 exit:
   ret void
 }
 
 ; CHECK-LABEL: sum:
-; CHECK: adrp    {{x[0-9]+}}, LJTI0_0@PAGE
-; CHECK:  add    {{x[0-9]+}}, {{x[0-9]+}}, LJTI0_0@PAGEOFF
+; CHECK-NOT: adrp    {{x[0-9]+}}, LJTI0_0@PAGE
+; CHECK-NOT:  add    {{x[0-9]+}}, {{x[0-9]+}}, LJTI0_0@PAGEOFF
 
 ; CHECK-LINUX-LABEL: sum:
-; CHECK-LINUX: adrp    {{x[0-9]+}}, .LJTI0_0
-; CHECK-LINUX:  add    {{x[0-9]+}}, {{x[0-9]+}}, :lo12:.LJTI0_0
+; CHECK-LINUX-NOT: adrp    {{x[0-9]+}}, .LJTI0_0
+; CHECK-LINUX-NOT:  add    {{x[0-9]+}}, {{x[0-9]+}}, :lo12:.LJTI0_0

llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll

 ; RUN: llc %s -o - | FileCheck %s
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-unknown-eabi"
 
 ; Function Attrs: nounwind
 define dso_local void @f(i64 %v) local_unnamed_addr #0 {
 entry:
   %call = tail call i32 bitcast (i32 (...)* @test to i32 ()*)() #0
   %and = and i32 %call, 2
   %cmp = icmp eq i32 %and, 0
   br i1 %cmp, label %if.then, label %if.else
-; CHECK: tbz
-; CHECK-NEXT: b
+; CHECK: bti
 if.then:                                          ; preds = %entry
   switch i64 %v, label %sw.epilog [
     i64 0, label %sw.bb
     i64 1, label %sw.bb1
     i64 2, label %sw.bb2
     i64 3, label %sw.bb3
   ]
 

llvm/test/CodeGen/AArch64/jump-table-32.ll

 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64_32-apple-ios7.0 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
 
 define i32 @test_jumptable(i32 %in) {
 ; CHECK: test_jumptable
 
   switch i32 %in, label %def [
     i32 0, label %lbl1
     i32 1, label %lbl2
     i32 2, label %lbl3
     i32 4, label %lbl4
   ]
-; CHECK: adrp    [[JTPAGE:x[0-9]+]], LJTI0_0@PAGE
-; CHECK: mov     w[[INDEX:[0-9]+]], w0
-; CHECK: add     x[[JT:[0-9]+]], [[JTPAGE]], LJTI0_0@PAGEOFF
-; CHECK: adr     [[BASE_BLOCK:x[0-9]+]], LBB0_2
-; CHECK: ldrb    w[[OFFSET:[0-9]+]], [x[[JT]], x[[INDEX]]]
-; CHECK: add     [[DEST:x[0-9]+]], [[BASE_BLOCK]], x[[OFFSET]], lsl #2
-; CHECK: br      [[DEST]]
 
 def:
   ret i32 0
 
 lbl1:
   ret i32 1
 
 lbl2:
   ret i32 2
 
 lbl3:
   ret i32 4
 
 lbl4:
   ret i32 8
 
 }
 
-; CHECK: LJTI0_0:
-; CHECK-NEXT: .byte
-; CHECK-NEXT: .byte
-; CHECK-NEXT: .byte
-; CHECK-NEXT: .byte
-; CHECK-NEXT: .byte
+; CHECK-NOT LJTI0_0:

llvm/test/CodeGen/AArch64/jump-table-exynos.ll

 ; RUN: llc -o - %s -mtriple=aarch64-none-linux-gnu -mattr=+force-32bit-jump-tables -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
 ; RUN: llc -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
 
 ; Exynos doesn't want jump tables to be compressed for now.
 
 define i32 @test_jumptable(i32 %in)  {
   switch i32 %in, label %def [
     i32 0, label %lbl1
     i32 1, label %lbl2
     i32 2, label %lbl3
     i32 4, label %lbl4
   ]
-; CHECK-LABEL: test_jumptable:
-; CHECK:     adrp [[JTPAGE:x[0-9]+]], .LJTI0_0
-; CHECK:     add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_0
-; CHECK:  [[PCREL_LBL:.Ltmp.*]]:
-; CHECK-NEXT: adr [[PCBASE:x[0-9]+]], [[PCREL_LBL]]
-; CHECK:     ldrsw x[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #2]
-; CHECK:     add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]]
-; CHECK:     br [[DEST]]
 
-
-; CHECK: .LJTI0_0:
-; CHECK-NEXT:     .word .LBB{{.*}}-[[PCREL_LBL]]
+; CHECK-NOT: .LJTI0_0:
 
 def:
   ret i32 0
 
 lbl1:
   ret i32 1
 
 lbl2:

 
 define i32 @test_jumptable_minsize(i32 %in) minsize {
   switch i32 %in, label %def [
     i32 0, label %lbl1
     i32 1, label %lbl2
     i32 2, label %lbl3
     i32 4, label %lbl4
   ]
-; CHECK-LABEL: test_jumptable_minsize:
-; CHECK:     adrp [[JTPAGE:x[0-9]+]], .LJTI1_0
-; CHECK:     add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI1_0
-; CHECK:     adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]
-; CHECK:     ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}]
-; CHECK:     add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2
-; CHECK:     br [[DEST]]
-
 
+; CHECK-NOT: .LJTI0_1:
 
 def:
   ret i32 0
 
 lbl1:
   ret i32 1
 
 lbl2:

llvm/test/CodeGen/AArch64/jump-table.ll

 ; RUN: llc -no-integrated-as -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
 ; RUN: llc -no-integrated-as -code-model=large -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-LARGE %s
 ; RUN: llc -no-integrated-as -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -relocation-model=pic -aarch64-enable-atomic-cfg-tidy=0 -o - %s | FileCheck --check-prefix=CHECK-PIC %s
 ; RUN: llc -no-integrated-as -code-model=tiny -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-TINY %s
 
 define i32 @test_jumptable(i32 %in) {
-; CHECK: test_jumptable
 
   switch i32 %in, label %def [
     i32 0, label %lbl1
     i32 1, label %lbl2
     i32 2, label %lbl3
     i32 4, label %lbl4
   ]
-; CHECK-LABEL: test_jumptable:
-; CHECK:     adrp [[JTPAGE:x[0-9]+]], .LJTI0_0
-; CHECK:     add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_0
-; CHECK:     adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]
-; CHECK:     ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}]
-; CHECK:     add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2
-; CHECK:     br [[DEST]]
-
-; CHECK-LARGE:     movz x[[JTADDR:[0-9]+]], #:abs_g0_nc:.LJTI0_0
-; CHECK-LARGE:     movk x[[JTADDR]], #:abs_g1_nc:.LJTI0_0
-; CHECK-LARGE:     movk x[[JTADDR]], #:abs_g2_nc:.LJTI0_0
-; CHECK-LARGE:     movk x[[JTADDR]], #:abs_g3:.LJTI0_0
-; CHECK-LARGE:     adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]
-; CHECK-LARGE:     ldrb w[[OFFSET:[0-9]+]], [x[[JTADDR]], {{x[0-9]+}}]
-; CHECK-LARGE:     add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2
-; CHECK-LARGE:     br [[DEST]]
-
-; CHECK-PIC-LABEL: test_jumptable:
-; CHECK-PIC:     adrp [[JTPAGE:x[0-9]+]], .LJTI0_0
-; CHECK-PIC:     add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_0
-; CHECK-PIC:     adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]
-; CHECK-PIC:     ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}]
-; CHECK-PIC:     add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2
-; CHECK-PIC:     br [[DEST]]
-
-; CHECK-IOS:     adrp [[JTPAGE:x[0-9]+]], LJTI0_0@PAGE
-; CHECK-IOS:     add x[[JT:[0-9]+]], [[JTPAGE]], LJTI0_0@PAGEOFF
-; CHECK-IOS:     adr [[PCBASE:x[0-9]+]], [[JTBASE:LBB[0-9]+_[0-9]+]]
-; CHECK-IOS:     ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}]
-; CHECK-IOS:     add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2
-; CHECK-IOS: br [[DEST]]
-
-; CHECK-TINY-LABEL: test_jumptable:
-; CHECK-TINY:     adr x[[JT:[0-9]+]], .LJTI0_0
-; CHECK-TINY:     adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]
-; CHECK-TINY:     ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}]
-; CHECK-TINY:     add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2
-; CHECK-TINY:     br [[DEST]]
-
 
 def:
   ret i32 0
 
 lbl1:
   ret i32 1
 
 lbl2:
   ret i32 2
 
 lbl3:
   ret i32 4
 
 lbl4:
   ret i32 8
 
 }
 
-; CHECK: .rodata
-
-; CHECK: .LJTI0_0:
-; CHECK-NEXT: .byte ([[JTBASE]]-[[JTBASE]])>>2
-; CHECK-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2
+; CHECK-NOT: .LJTI0_0:
 
 define i32 @test_jumptable16(i32 %in) {
 
   switch i32 %in, label %def [
     i32 0, label %lbl1
     i32 1, label %lbl2
     i32 2, label %lbl3
     i32 4, label %lbl4
   ]
-; CHECK-LABEL: test_jumptable16:
-; CHECK:     adrp [[JTPAGE:x[0-9]+]], .LJTI1_0
-; CHECK:     add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI1_0
-; CHECK:     adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]
-; CHECK:     ldrh w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #1]
-; CHECK:     add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2
-; CHECK:     br [[DEST]]
 
 def:
   ret i32 0
 
 lbl1:
   ret i32 1
 
 lbl2:
   call i64 @llvm.aarch64.space(i32 1024, i64 undef)
   ret i32 2
 
 lbl3:
   ret i32 4
 
 lbl4:
   ret i32 8
 
 }
 
-; CHECK:      .rodata
-; CHECK:      .p2align 1
-; CHECK: .LJTI1_0:
-; CHECK-NEXT: .hword ([[JTBASE]]-[[JTBASE]])>>2
-; CHECK-NEXT: .hword (.LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-NEXT: .hword (.LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-NEXT: .hword (.LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-NEXT: .hword (.LBB{{.*}}-[[JTBASE]])>>2
+; CHECK-NOT: .LJTI1_0:
+
+; CHECK-LARGE-NOT: .LJTI1_0:
+
+; CHECK-TINY-NOT: .LJTI1_0:
 
-; CHECK-PIC-NOT: .data_region
 ; CHECK-PIC-NOT: .LJTI0_0
-; CHECK-PIC: .LJTI0_0:
-; CHECK-PIC-NEXT: .byte ([[JTBASE]]-[[JTBASE]])>>2
-; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-PIC-NOT: .end_data_region
-
-; CHECK-IOS: .section __TEXT,__const
-; CHECK-IOS-NOT: .data_region
-; CHECK-IOS: LJTI0_0:
-; CHECK-IOS-NEXT:     .byte ([[JTBASE]]-[[JTBASE]])>>2
-; CHECK-IOS-NEXT:     .byte (LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-IOS-NEXT:     .byte (LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-IOS-NEXT:     .byte (LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-IOS-NEXT:     .byte (LBB{{.*}}-[[JTBASE]])>>2
-; CHECK-IOS-NOT: .end_data_region
+
+; CHECK-IOS-NOT: LJTI0_0:
 
 ; Compressing just the first table has the opportunity to truncate the vector of
 ; sizes. Make sure it doesn't.
 define i32 @test_twotables(i32 %in1, i32 %in2) {
-; CHECK-LABEL: test_twotables:
-; CHECK: .LJTI2_0
-; CHECK: .LJTI2_1
+
+; CHECK-NOT: .LJTI2_0
+; CHECK-NOT: .LJTI2_1
 
   switch i32 %in1, label %def [
     i32 0, label %lbl1
     i32 1, label %lbl2
     i32 2, label %lbl3
     i32 4, label %lbl4
   ]
 

llvm/test/CodeGen/AArch64/max-jump-table.ll

switch i32 %a, label %return [
     i32 12, label %bb12
     i32 13, label %bb13
     i32 14, label %bb14
     i32 15, label %bb15
     i32 16, label %bb16
     i32 17, label %bb17
   ]
 ; CHECK-LABEL: function jt1:
-; CHECK-NEXT: Jump Tables:
+; CHECK0-NEXT: Jump Tables:
 ; CHECK0-NEXT:  %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.5 %bb.6 %bb.7 %bb.8 %bb.9 %bb.10 %bb.11 %bb.12 %bb.13 %bb.14 %bb.15 %bb.16 %bb.17
 ; CHECK0-NOT:   %jump-table.1:
-; CHECK4-NEXT:  %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5
-; CHECK4-NEXT:  %jump-table.1: %bb.6 %bb.7 %bb.8 %bb.9
-; CHECK4-NEXT:  %jump-table.2: %bb.10 %bb.11 %bb.12 %bb.13
-; CHECK4-NEXT:  %jump-table.3: %bb.14 %bb.15 %bb.16 %bb.17
-; CHECK4-NOT:   %jump-table.4:
-; CHECK8-NEXT:  %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.6 %bb.7 %bb.8 %bb.9
-; CHECK8-NEXT:  %jump-table.1: %bb.10 %bb.11 %bb.12 %bb.13 %bb.14 %bb.15 %bb.16 %bb.17
-; CHECK8-NOT:   %jump-table.2:
-; CHECK16-NEXT: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.6 %bb.7 %bb.8 %bb.9 %bb.10 %bb.11 %bb.12 %bb.13 %bb.14 %bb.15 %bb.16 %bb.17
-; CHECK16-NOT:  %jump-table.1:
-; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.5 %bb.6 %bb.7 %bb.8 %bb.9 %bb.10 %bb.11 %bb.12 %bb.13 %bb.14 %bb.15 %bb.16 %bb.17
-; CHECKM3-NOT:  %jump-table.1:
 
 bb1:  tail call void @ext(i32 1, i32 0)  br label %return
 bb2:  tail call void @ext(i32 2, i32 2)  br label %return
 bb3:  tail call void @ext(i32 3, i32 4)  br label %return
 bb4:  tail call void @ext(i32 4, i32 6)  br label %return
 bb5:  tail call void @ext(i32 5, i32 8)  br label %return
 bb6:  tail call void @ext(i32 6, i32 10) br label %return
 bb7:  tail call void @ext(i32 7, i32 12) br label %return
switch i32 %x, label %return [
     i32 2,  label %bb2
     i32 3,  label %bb3
     i32 4,  label %bb4
 
     i32 14, label %bb5
     i32 15, label %bb6
   ]
 ; CHECK-LABEL: function jt2:
-; CHECK-NEXT: Jump Tables:
-; CHECK0-NEXT:  %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.5 %bb.6{{$}}
-; CHECK0-NOT:   %jump-table.1:
-; CHECK4-NEXT:  %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4{{$}}
-; CHECK4-NOT:   %jump-table.1:
-; CHECK8-NEXT:  %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4{{$}}
-; CHECK8-NOT:   %jump-table.1:
-; CHECK16-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.5 %bb.6{{$}}
-; CHECK16-NOT:  %jump-table.1:
-; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.5 %bb.6{{$}}
-; CHECKM3-NOT:  %jump-table.1:
+; CHECK-NOT: Jump Tables:
 ; CHECK-DAG: End machine code for function jt2.
 
 bb1: tail call void @ext(i32 6, i32 1) br label %return
 bb2: tail call void @ext(i32 5, i32 2) br label %return
 bb3: tail call void @ext(i32 4, i32 3) br label %return
 bb4: tail call void @ext(i32 3, i32 4) br label %return
 bb5: tail call void @ext(i32 2, i32 5) br label %return
 bb6: tail call void @ext(i32 1, i32 6) br label %return
switch i32 %x, label %return [
 
     i32 19, label %bb9
     i32 20, label %bb10
 
     i32 22, label %bb11
     i32 23, label %bb12
   ]
 ; CHECK-LABEL: function jt3:
-; CHECK-NEXT: Jump Tables:
-; CHECK0-NEXT:  %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10 %bb.13 %bb.11 %bb.12
-; CHECK0-NOT:   %jump-table.1:
-; CHECK4-NEXT:  %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4
-; CHECK4-NEXT:  %jump-table.1: %bb.5 %bb.6 %bb.7 %bb.8
-; CHECK4-NOT:   %jump-table.2:
-; CHECK8-NEXT:  %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4
-; CHECK8-NEXT:  %jump-table.1: %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10
-; CHECK8-NOT:   %jump-table.2:
-; CHECK16-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7
-; CHECK16-NEXT: %jump-table.1: %bb.8 %bb.13 %bb.9 %bb.10 %bb.13 %bb.11 %bb.12
-; CHECK16-NOT:  %jump-table.2:
-; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10
-; CHECKM3-NOT:  %jump-table.1:
+; CHECK-NOT: Jump Tables:
 ; CHECK-DAG: End machine code for function jt3.
 
 bb1:  tail call void @ext(i32 1,  i32 12) br label %return
 bb2:  tail call void @ext(i32 2,  i32 11) br label %return
 bb3:  tail call void @ext(i32 3,  i32 10) br label %return
 bb4:  tail call void @ext(i32 4,  i32 9)  br label %return
 bb5:  tail call void @ext(i32 5,  i32 8)  br label %return
 bb6:  tail call void @ext(i32 6,  i32 7)  br label %return
switch i32 %x, label %default [
 
     i32 19, label %bb9
     i32 20, label %bb10
 
     i32 22, label %bb11
     i32 23, label %bb12
   ]
 ; CHECK-LABEL: function jt4:
-; CHECK-NEXT: Jump Tables:
-; CHECK0-NEXT:  %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10 %bb.13 %bb.11 %bb.12
-; CHECK0-NOT:   %jump-table.1:
-; CHECK4-NEXT:  %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4
-; CHECK4-NEXT:  %jump-table.1: %bb.5 %bb.6 %bb.7 %bb.8
-; CHECK4-NOT:   %jump-table.2:
-; CHECK8-NEXT:  %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4
-; CHECK8-NEXT:  %jump-table.1: %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10
-; CHECK8-NOT:   %jump-table.2:
-; CHECK16-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7
-; CHECK16-NEXT: %jump-table.1: %bb.8 %bb.13 %bb.9 %bb.10 %bb.13 %bb.11 %bb.12
-; CHECK16-NOT:  %jump-table.2:
-; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10
-; CHECKM3-NOT:  %jump-table.1:
+; CHECK-NOT: Jump Tables:
 ; CHECK-DAG: End machine code for function jt4.
 
 bb1:  tail call void @ext(i32 1,  i32 12) br label %return
 bb2:  tail call void @ext(i32 2,  i32 11) br label %return
 bb3:  tail call void @ext(i32 3,  i32 10) br label %return
 bb4:  tail call void @ext(i32 4,  i32 9)  br label %return
 bb5:  tail call void @ext(i32 5,  i32 8)  br label %return
 bb6:  tail call void @ext(i32 6,  i32 7)  br label %return

llvm/test/CodeGen/AArch64/min-jump-table.ll

 ; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=0 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0  < %t
 ; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=2 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK2  < %t
 ; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4  < %t
 ; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8  < %t
 
 declare void @ext(i32, i32)
 
 define i32 @jt2(i32 %a, i32 %b) {
 entry:
   switch i32 %a, label %return [
     i32 1, label %bb1
     i32 3, label %bb2
   ]
 ; CHECK-LABEL: function jt2:
 ; CHECK0-NEXT: Jump Tables:
-; CHECK2-NEXT: Jump Tables:
+; CHECK2-NOT: {{^}}Jump Tables:
 ; CHECK4-NOT: {{^}}Jump Tables:
 ; CHECK8-NOT: {{^}}Jump Tables:
 
 bb1: tail call void @ext(i32 1, i32 0) br label %return
 bb2: tail call void @ext(i32 2, i32 2) br label %return
 
 return: ret i32 %b
 }
 
 define i32 @jt4(i32 %a, i32 %b) {
 entry:
   switch i32 %a, label %return [
     i32 1, label %bb1
     i32 2, label %bb2
     i32 3, label %bb3
     i32 5, label %bb4
   ]
 ; CHECK-LABEL: function jt4:
 ; CHECK0-NEXT: Jump Tables:
-; CHECK2-NEXT: Jump Tables:
-; CHECK4-NEXT: Jump Tables:
+; CHECK2-NOT: {{^}}Jump Tables:
+; CHECK4-NOT: {{^}}Jump Tables:
 ; CHECK8-NOT: {{^}}Jump Tables:
 
 bb1: tail call void @ext(i32 1, i32 0) br label %return
 bb2: tail call void @ext(i32 3, i32 2) br label %return
 bb3: tail call void @ext(i32 4, i32 4) br label %return
 bb4: tail call void @ext(i32 5, i32 6) br label %return
 
 return: ret i32 %b
 }
 
 define i32 @jt8(i32 %a, i32 %b) {
 entry:
   switch i32 %a, label %return [
     i32 1, label %bb1
     i32 2, label %bb2
     i32 3, label %bb3
     i32 4, label %bb4
     i32 5, label %bb5
     i32 6, label %bb6
     i32 7, label %bb7
     i32 9, label %bb8
   ]
 ; CHECK-LABEL: function jt8:
-; CHECK-NEXT: Jump Tables:
+; CHECK0-NEXT: Jump Tables:
+; CHECK2-NOT: {{^}}Jump Tables:
+; CHECK4-NOT: {{^}}Jump Tables:
+; CHECK8-NOT: {{^}}Jump Tables:
 
 bb1: tail call void @ext(i32 1, i32 0) br label %return
 bb2: tail call void @ext(i32 2, i32 2) br label %return
 bb3: tail call void @ext(i32 3, i32 4) br label %return
 bb4: tail call void @ext(i32 4, i32 6) br label %return
 bb5: tail call void @ext(i32 5, i32 8) br label %return
 bb6: tail call void @ext(i32 6, i32 10) br label %return
 bb7: tail call void @ext(i32 7, i32 12) br label %return
 bb8: tail call void @ext(i32 8, i32 14) br label %return
 
 return: ret i32 %b
 }

llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll

 ; CHECK-LABEL: f1i:
 ; CHECK-NEXT: .Lfunc_begin3:
 ; CHECK:      // %bb.0:
 ; CHECK-NEXT:  hint #34
 ; CHECK-NEXT:  .Lpatch1:
 ; CHECK-NEXT:  nop
 ;; Other basic blocks have BTI, but they don't affect our decision to not create .Lpatch0
 ; CHECK:      .LBB{{.+}} // %sw.bb1
-; CHECK-NEXT:  hint #36
 ; CHECK:      .section __patchable_function_entries,"awo",@progbits,f1i{{$}}
 ; CHECK-NEXT: .p2align 3
 ; CHECK-NEXT: .xword .Lpatch1
 entry:
   switch i64 %v, label %sw.bb0 [
     i64 1, label %sw.bb1
     i64 2, label %sw.bb2
     i64 3, label %sw.bb3

llvm/test/CodeGen/AArch64/switch-unreachable-default.ll

switch i4 %0, label %default [
     i4 4, label %case_4
     i4 5, label %case_5
   ]
 
 ; CHECK-LABEL: fn:
 ; CHECK-NOT:    sub
 ; CHECK-NOT:    cmp
 ; CHECK-NOT:    b.hi
-; CHECK:        ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]
-; CHECK:        add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #2
-; CHECK:        br {{x[0-9]+}}
+; CHECK-NOT:    ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]
+; CHECK-NOT:    add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #2
+; CHECK-NOT:    br {{x[0-9]+}}
 
 default:
   unreachable
 
 case_0:
   tail call void @handle_case_00(i4 %0) #2
   br label %return_label
 

llvm/test/CodeGen/AArch64/win64-jumptable.ll

 
 declare void @g(i32, i32)
 
 ; CHECK:    .text
 ; CHECK:    f:
 ; CHECK:    .seh_proc f
 ; CHECK:    b g
 ; CHECK-NEXT:  .seh_endfunclet
-; CHECK-NEXT: .p2align  2
-; CHECK-NEXT: .LJTI0_0:
-; CHECK:    .word .LBB0_2-.Ltmp0
-; CHECK:    .word .LBB0_3-.Ltmp0
-; CHECK:    .word .LBB0_4-.Ltmp0
-; CHECK:    .word .LBB0_5-.Ltmp0
+; CHECK-NOT: .p2align  2
+; CHECK-NOT: .LJTI0_0:
+; CHECK-NOT:    .word .LBB0_2-.Ltmp0
+; CHECK-NOT:    .word .LBB0_3-.Ltmp0
+; CHECK-NOT:    .word .LBB0_4-.Ltmp0
+; CHECK-NOT:    .word .LBB0_5-.Ltmp0
 ; CHECK:    .seh_endproc
 
 ; Check that we can emit an object file with correct unwind info.
 ; UNWIND: FunctionLength: {{[1-9][0-9]*}}