[lldb] [ABI/X86] Support combining xmm* and ymm*h regs into ymm*

[mgorny]

Summary

gdbserver does not expose combined ymm* registers but rather XSAVE-style
split xmm* and ymm*h portions. Extend value_regs to support combining
multiple registers and use it to create user-friendly ymm* registers
that are combined from split xmm* and ymm*h portions.

[mgorny]

Rebase to use the new ABIX86::AugmentRegisterInfo() API.

[labath]

I like the solution with multiple value_regs.

However, I am wondering if instead of the various piecemeal maps we couldn't just have one uber-map to rule them all. I'm imagining something like

enum (class?) RegKind { GPR, FPR, XMM, ...};
struct RegData {
  size_t index;
  StringRef name;
  SmallVector<StringRef> subregs;
};

map<pair<RegKind, unsigned>, RegData> reg_map = makeRegMap(); // whichever kind of a map
// or possibly, map<RegKind, map<unsigned, RegData>> = ...

for (const auto &kv : reg_map)
  subreg_name_set.insert(kv.second.subregs.begin(), kv.second.subregs.end());

for (const auto &x : llvm::enumerate(regs)) {
  llvm::StringRef reg_name = x.value().name.GetStringRef();
  if (llvm::is_contained(subreg_name_set, reg_name))
    return;
  if (Optional<pair<RegKind, size_t>> reg = get_reg(reg_name))
    reg_map[reg].index = x.index(); 
}

...

This would allow us to factor out two tedious jobs (constructing the register map and identifying registers) into separate functions, leaving only the only (simplified, I hope) core logic for the main function. The get_reg function could use whichever method is easiest for the translation of register names, or even a combination of methods (a StringSwitch for gprs and some consume_fronts for the regularly-named registers).

WDYT?

lldb/source/Plugins/ABI/X86/ABIX86.cpp

171 ↗

(On Diff #380058)

For a simple list like this, I'd probably remove the trailing comma to have clang-format format it more succinctly.

[mgorny]

I'm not sure what exactly you're proposing and whether your proposal would work but I think it's a step in the right direction.

Let's start by reiterating what we need:

1. A way to iterate over all subregisters of given RegKind, sorted by base register index, yielding base register index and subregister name (map<RegKind, vector<...>>.
2. A way to match register name against all *expected* subregisters in order to abort if any of them exists (set<StringRef>).
3. A way to match register name against all known base registers and store their indices (map<StringRef, ...>).
4. We should be able to construct all of the above from some readable input.

lldb/source/Plugins/ABI/X86/ABIX86.cpp

171 ↗

(On Diff #380058)

Heh, I was wondering why clang-format chooses one format sometimes, and the other sometimes but it wouldn't occur to me that it's due to the trailing comma ;-).

[mgorny]

WIP alternative approach.

[labath]

I think I like this.

lldb/source/Plugins/ABI/X86/ABIX86.cpp

261 ↗

(On Diff #380366)

llvm::Optional gives you this assert for free.

321 ↗

(On Diff #380366)

It would be nice to have some comment explaining the purpose of this variable (I guess its there to ensure matching register order).

[mgorny]

Major refactoring of the generator function.

[labath]

Looks good. Thanks for your patience.

lldb/source/Plugins/ABI/X86/ABIX86.cpp

36–52 ↗

(On Diff #380453)

anonymous namespace here

lldb/include/lldb/lldb-private-types.h

struct RegisterInfo {
   /// Default display format.
   lldb::Format format;
   /// Holds all of the various register numbers for all register kinds.
   uint32_t kinds[lldb::kNumRegisterKinds]; //
   /// List of registers (terminated with LLDB_INVALID_REGNUM). If this value is
   /// not null, all registers in this list will be read first, at which point
   /// the value for this register will be valid. For example, the value list
   /// for ah would be eax (x86) or rax (x64). Register numbers are
-  /// of eRegisterKindProcessPlugin.
+  /// of eRegisterKindProcessPlugin. If multiple registers are listed, the final
+  /// value will be the concatenation of them.
   uint32_t *value_regs;
   /// List of registers (terminated with LLDB_INVALID_REGNUM). If this value is
   /// not null, all registers in this list will be invalidated when the value of
   /// this register changes. For example, the invalidate list for eax would be
   /// rax ax, ah, and al. Register numbers are of eRegisterKindProcessPlugin.
   uint32_t *invalidate_regs;
   /// A DWARF expression that when evaluated gives the byte size of this
   /// register.

lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp

void DynamicRegisterInfo::Finalize(const ArchSpec &arch) {
   m_finalized = true;
   const size_t num_sets = m_sets.size();
   for (size_t set = 0; set < num_sets; ++set) {
     assert(m_sets.size() == m_set_reg_nums.size());
     m_sets[set].num_registers = m_set_reg_nums[set].size();
     m_sets[set].registers = m_set_reg_nums[set].data();
   }
 
-  // sort and unique all value registers and make sure each is terminated with
-  // LLDB_INVALID_REGNUM
-
+  // Make sure all value elements are terminated with LLDB_INVALID_REGNUM
   for (reg_to_regs_map::iterator pos = m_value_regs_map.begin(),
                                  end = m_value_regs_map.end();
        pos != end; ++pos) {
-    if (pos->second.size() > 1) {
-      llvm::sort(pos->second.begin(), pos->second.end());
-      reg_num_collection::iterator unique_end =
-          std::unique(pos->second.begin(), pos->second.end());
-      if (unique_end != pos->second.end())
-        pos->second.erase(unique_end, pos->second.end());
-    }
     assert(!pos->second.empty());
     if (pos->second.back() != LLDB_INVALID_REGNUM)
       pos->second.push_back(LLDB_INVALID_REGNUM);
   }
 
   // Now update all value_regs with each register info as needed
   const size_t num_regs = m_regs.size();
   for (size_t i = 0; i < num_regs; ++i) {
if (m_regs[regnum_pair.second].byte_offset == LLDB_INVALID_INDEX32 &&
       reg_offset = m_regs[regnum_pair.second].byte_offset +
                    m_regs[regnum_pair.second].byte_size;
     }
   }
 
   // Now update all value_regs with each register info as needed
   for (auto &reg : m_regs) {
     if (reg.value_regs != nullptr) {
-      // Assign a valid offset to all pseudo registers if not assigned by stub.
-      // Pseudo registers with value_regs list populated will share same offset
-      // as that of their corresponding primary register in value_regs list.
+      // Assign a valid offset to all pseudo registers that have only a single
+      // parent register in value_regs list, if not assigned by stub.  Pseudo
+      // registers with value_regs list populated will share same offset as
+      // that of their corresponding parent register.
       if (reg.byte_offset == LLDB_INVALID_INDEX32) {
         uint32_t value_regnum = reg.value_regs[0];
-        if (value_regnum != LLDB_INVALID_INDEX32)
+        if (value_regnum != LLDB_INVALID_INDEX32 &&
+            reg.value_regs[1] == LLDB_INVALID_INDEX32)
           reg.byte_offset =
               GetRegisterInfoAtIndex(remote_to_local_regnum_map[value_regnum])
                   ->byte_offset;
       }
     }
 
     reg_offset = reg.byte_offset + reg.byte_size;
     if (m_reg_data_byte_size < reg_offset)

lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp

 
 bool GDBRemoteRegisterContext::ReadRegister(const RegisterInfo *reg_info,
                                             RegisterValue &value) {
   // Read the register
   if (ReadRegisterBytes(reg_info)) {
     const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
     if (m_reg_valid[reg] == false)
       return false;
+    if (reg_info->value_regs &&
+        reg_info->value_regs[0] != LLDB_INVALID_REGNUM &&
+        reg_info->value_regs[1] != LLDB_INVALID_REGNUM) {
+      std::vector<char> combined_data;
+      uint32_t offset = 0;
+      for (int i = 0; reg_info->value_regs[i] != LLDB_INVALID_REGNUM; i++) {
+        const RegisterInfo *parent_reg = GetRegisterInfo(
+            eRegisterKindProcessPlugin, reg_info->value_regs[i]);
+        if (!parent_reg)
+          return false;
+        combined_data.resize(offset + parent_reg->byte_size);
+        if (m_reg_data.CopyData(parent_reg->byte_offset, parent_reg->byte_size,
+                                combined_data.data() + offset) !=
+            parent_reg->byte_size)
+          return false;
+        offset += parent_reg->byte_size;
+      }
+
+      Status error;
+      return value.SetFromMemoryData(
+                 reg_info, combined_data.data(), combined_data.size(),
+                 m_reg_data.GetByteOrder(), error) == combined_data.size();
+    } else {
       const bool partial_data_ok = false;
       Status error(value.SetValueFromData(
           reg_info, m_reg_data, reg_info->byte_offset, partial_data_ok));
       return error.Success();
     }
+  }
   return false;
 }
 
 bool GDBRemoteRegisterContext::PrivateSetRegisterValue(
     uint32_t reg, llvm::ArrayRef<uint8_t> data) {
   const RegisterInfo *reg_info = GetRegisterInfoAtIndex(reg);
   if (reg_info == nullptr)
     return false;
bool GDBRemoteRegisterContext::ReadRegisterBytes(const RegisterInfo *reg_info) {
   }
 
   return true;
 }
 
 bool GDBRemoteRegisterContext::WriteRegister(const RegisterInfo *reg_info,
                                              const RegisterValue &value) {
   DataExtractor data;
-  if (value.GetData(data))
+  if (value.GetData(data)) {
+    if (reg_info->value_regs &&
+        reg_info->value_regs[0] != LLDB_INVALID_REGNUM &&
+        reg_info->value_regs[1] != LLDB_INVALID_REGNUM) {
+      uint32_t combined_size = 0;
+      for (int i = 0; reg_info->value_regs[i] != LLDB_INVALID_REGNUM; i++) {
+        const RegisterInfo *parent_reg = GetRegisterInfo(
+            eRegisterKindProcessPlugin, reg_info->value_regs[i]);
+        if (!parent_reg)
+          return false;
+        combined_size += parent_reg->byte_size;
+      }
+
+      if (data.GetByteSize() < combined_size)
+        return false;
+
+      uint32_t offset = 0;
+      for (int i = 0; reg_info->value_regs[i] != LLDB_INVALID_REGNUM; i++) {
+        const RegisterInfo *parent_reg = GetRegisterInfo(
+            eRegisterKindProcessPlugin, reg_info->value_regs[i]);
+        assert(parent_reg);
+
+        DataExtractor parent_data{data, offset, parent_reg->byte_size};
+        if (!WriteRegisterBytes(parent_reg, parent_data, 0))
+          return false;
+        offset += parent_reg->byte_size;
+      }
+      assert(offset == combined_size);
+      return true;
+    } else
       return WriteRegisterBytes(reg_info, data, 0);
+  }
   return false;
 }
 
 // Helper function for GDBRemoteRegisterContext::WriteRegisterBytes().
 bool GDBRemoteRegisterContext::SetPrimordialRegister(
     const RegisterInfo *reg_info, GDBRemoteCommunicationClient &gdb_comm) {
   StreamString packet;
   StringExtractorGDBRemote response;

lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext_x86_64.cpp

static std::array<MMReg, 16> mm_regs = {{
     {"st2", "mm2"},
     {"st3", "mm3"},
     {"st4", "mm4"},
     {"st5", "mm5"},
     {"st6", "mm6"},
     {"st7", "mm7"},
 }};
 
+struct YMMReg {
+  const char *name;
+  const char *xmmreg;
+  const char *ymmhreg;
+
+  // extra storage used for pointers
+  uint32_t value_regs[3];
+};
+
+static std::array<YMMReg, 16> ymm_regs = {{
+    {"ymm0", "xmm0", "ymm0h"},
+    {"ymm1", "xmm1", "ymm1h"},
+    {"ymm2", "xmm2", "ymm2h"},
+    {"ymm3", "xmm3", "ymm3h"},
+    {"ymm4", "xmm4", "ymm4h"},
+    {"ymm5", "xmm5", "ymm5h"},
+    {"ymm6", "xmm6", "ymm6h"},
+    {"ymm7", "xmm7", "ymm7h"},
+    {"ymm8", "xmm8", "ymm8h"},
+    {"ymm9", "xmm9", "ymm9h"},
+    {"ymm10", "xmm10", "ymm10h"},
+    {"ymm11", "xmm11", "ymm11h"},
+    {"ymm12", "xmm12", "ymm12h"},
+    {"ymm13", "xmm13", "ymm13h"},
+    {"ymm14", "xmm14", "ymm14h"},
+    {"ymm15", "xmm15", "ymm15h"},
+}};
+
 void GDBRemoteDynamicRegisterInfo::PreFinalize_x86_64() {
   uint32_t max_regnum = 0;
   uint32_t next_regindex = m_regs.size();
   for (const RegisterInfo &reg : m_regs)
     max_regnum = std::max(max_regnum, reg.kinds[eRegisterKindProcessPlugin]);
 
   ConstString group;
   group.SetCString("partial registers");
struct RegisterInfo new_reg {
           mmreg.value_regs, nullptr, nullptr, 0
     };
 
     ConstString name;
     ConstString alt_name;
     name.SetCString(new_reg.name);
     AddRegister(new_reg, name, alt_name, group);
   }
+
+  for (YMMReg &ymmreg : ymm_regs) {
+    const RegisterInfo *xmmreg = GetRegisterInfo(ymmreg.xmmreg);
+    const RegisterInfo *ymmhreg = GetRegisterInfo(ymmreg.ymmhreg);
+    if (!xmmreg || !ymmhreg)
+      continue;
+    assert(xmmreg->byte_size == 16);
+    assert(ymmhreg->byte_size == 16);
+
+    if (GetRegisterInfo(ymmreg.name))
+      continue;
+
+    ymmreg.value_regs[0] = xmmreg->kinds[eRegisterKindProcessPlugin];
+    ymmreg.value_regs[1] = ymmhreg->kinds[eRegisterKindProcessPlugin];
+    ymmreg.value_regs[2] = LLDB_INVALID_REGNUM;
+
+    struct RegisterInfo new_reg {
+      ymmreg.name, nullptr, 32, LLDB_INVALID_INDEX32, eEncodingVector,
+          eFormatVectorOfUInt8,
+          {
+              LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+              ++max_regnum,        next_regindex++,
+          },
+          ymmreg.value_regs, nullptr, nullptr, 0
+    };
+
+    ConstString name;
+    ConstString alt_name;
+    name.SetCString(new_reg.name);
+    AddRegister(new_reg, name, alt_name, group);
+  }
 }
 
 void GDBRemoteDynamicRegisterInfo::PostFinalize_x86_64() {
   for (PartialGPRRegSet &partial_regset : partial_gpr_regs) {
     if (!partial_regset.r[eRegKind8h].name)
       continue;
 
     llvm::StringRef reg8h_name = partial_regset.r[eRegKind8h].name;

lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp

feature_node.ForEachChildElementWithName(
             reg_info.encoding = eEncodingUint;
           } else if (gdb_type == "data_ptr" || gdb_type == "code_ptr") {
             reg_info.format = eFormatAddressInfo;
             reg_info.encoding = eEncodingUint;
           } else if (gdb_type == "float") {
             reg_info.format = eFormatFloat;
             reg_info.encoding = eEncodingIEEE754;
           } else if (llvm::StringRef(gdb_type).startswith("vec") ||
-                     gdb_type == "i387_ext") {
+                     gdb_type == "i387_ext" || gdb_type == "uint128") {
+            // lldb doesn't handle 128-bit uints correctly (for ymm*h), so treat
+            // them as vector (similarly to xmm/ymm)
             reg_info.format = eFormatVectorOfUInt8;
             reg_info.encoding = eEncodingVector;
           }
         }
 
         // Only update the register set name if we didn't get a "reg_set"
         // attribute. "set_name" will be empty if we didn't have a "reg_set"
         // attribute.

lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py

def test_x86_64_regs(self):
             "2122232425262728292a"  # st2..st7
         ] + [
             "8182838485868788898a8b8c8d8e8f90",  # xmm0
             "9192939495969798999a9b9c9d9e9fa0",  # xmm1
         ] + 14 * [
             "a1a2a3a4a5a6a7a8a9aaabacadaeafb0",  # xmm2..xmm15
         ] + [
             "00000000",  # mxcsr
+        ] + [
+            "b1b2b3b4b5b6b7b8b9babbbcbdbebfc0",  # ymm0h
+            "c1c2c3c4c5c6c7c8c9cacbcccdcecfd0",  # ymm1h
+        ] + 14 * [
+            "d1d2d3d4d5d6d7d8d9dadbdcdddedfe0",  # ymm2h..ymm15h
         ]
 
         class MyResponder(MockGDBServerResponder):
             def qXferRead(self, obj, annex, offset, length):
                 if annex == "target.xml":
                     return """<?xml version="1.0"?>
                         <!DOCTYPE feature SYSTEM "gdb-target.dtd">
                         <target>
def test_x86_64_regs(self):
                             <reg name="xmm10" bitsize="128" type="vec128" regnum="50"/>
                             <reg name="xmm11" bitsize="128" type="vec128" regnum="51"/>
                             <reg name="xmm12" bitsize="128" type="vec128" regnum="52"/>
                             <reg name="xmm13" bitsize="128" type="vec128" regnum="53"/>
                             <reg name="xmm14" bitsize="128" type="vec128" regnum="54"/>
                             <reg name="xmm15" bitsize="128" type="vec128" regnum="55"/>
                             <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="56" group="vector"/>
                           </feature>
+                          <feature name="org.gnu.gdb.i386.avx">
+                            <reg name="ymm0h" bitsize="128" type="uint128" regnum="60"/>
+                            <reg name="ymm1h" bitsize="128" type="uint128" regnum="61"/>
+                            <reg name="ymm2h" bitsize="128" type="uint128" regnum="62"/>
+                            <reg name="ymm3h" bitsize="128" type="uint128" regnum="63"/>
+                            <reg name="ymm4h" bitsize="128" type="uint128" regnum="64"/>
+                            <reg name="ymm5h" bitsize="128" type="uint128" regnum="65"/>
+                            <reg name="ymm6h" bitsize="128" type="uint128" regnum="66"/>
+                            <reg name="ymm7h" bitsize="128" type="uint128" regnum="67"/>
+                            <reg name="ymm8h" bitsize="128" type="uint128" regnum="68"/>
+                            <reg name="ymm9h" bitsize="128" type="uint128" regnum="69"/>
+                            <reg name="ymm10h" bitsize="128" type="uint128" regnum="70"/>
+                            <reg name="ymm11h" bitsize="128" type="uint128" regnum="71"/>
+                            <reg name="ymm12h" bitsize="128" type="uint128" regnum="72"/>
+                            <reg name="ymm13h" bitsize="128" type="uint128" regnum="73"/>
+                            <reg name="ymm14h" bitsize="128" type="uint128" regnum="74"/>
+                            <reg name="ymm15h" bitsize="128" type="uint128" regnum="75"/>
+                          </feature>
                         </target>""", False
                 else:
                     return None, False
 
             def readRegister(self, regnum):
                 return ""
 
             def readRegisters(self):
def test_x86_64_regs(self):
                    ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"])
         self.match("register read xmm0",
                    ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 "
                     "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"])
         self.match("register read xmm1",
                    ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 "
                     "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"])
 
+        # test recombining ymmX
+        self.match("register read ymm0h",
+                   ["ymm0h = {0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 "
+                    "0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"])
+        self.match("register read ymm0",
+                   ["ymm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a "
+                    "0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0xb1 0xb2 0xb3 0xb4 0xb5 "
+                    "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"])
+        self.match("register read ymm1h",
+                   ["ymm1h = {0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 "
+                    "0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0}"])
+        self.match("register read ymm1",
+                   ["ymm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a "
+                    "0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xc1 0xc2 0xc3 0xc4 0xc5 "
+                    "0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0}"])
+
         # test writing into pseudo-registers
         self.runCmd("register write ecx 0xfffefdfc")
         reg_data[0] = "fcfdfeff05060708"
         self.assertPacketLogContains(["G" + "".join(reg_data)])
         self.match("register read rcx",
                    ["rcx = 0x08070605fffefdfc"])
 
         self.runCmd("register write cx 0xfbfa")
def test_x86_64_regs(self):
         self.match("register read rcx",
                    ["rcx = 0x08070605fffef9f8"])
 
         self.runCmd("register write mm0 0xfffefdfcfbfaf9f8")
         reg_data[10] = "f8f9fafbfcfdfeff090a"
         self.assertPacketLogContains(["G" + "".join(reg_data)])
         self.match("register read st0",
                    ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"])
+
+        self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 "
+                    "0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"")
+        reg_data[18] = "fffefdfcfbfaf9f8f7f6f5f4f3f2f1f0"
+        self.assertPacketLogContains(["G" + "".join(reg_data)])
+        self.match("register read ymm0",
+                   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+                    "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 "
+                    "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"])
+
+        self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 "
+                    "0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"")
+        reg_data[35] = "efeeedecebeae9e8e7e6e5e4e3e2e1e0"
+        self.assertPacketLogContains(["G" + "".join(reg_data)])
+        self.match("register read ymm0",
+                   ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 "
+                    "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb "
+                    "0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"])
+
+        self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 "
+                    "0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 "
+                    "0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec "
+                    "0xed 0xee 0xef}\"")
+        reg_data[18] = "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"
+        reg_data[35] = "e0e1e2e3e4e5e6e7e8e9eaebecedeeef"
+        self.assertPacketLogContains(["G" + "".join(reg_data)])
+        self.match("register read ymm0",
+                   ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 "
+                    "0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 "
+                    "0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"])