[M68k] Add parsing support for more operand types

[ricky26]

Summary

Fixes PR49862.

This adds parsing support for the remaining address modes:

• address register indirect w/ index (with size & scale)
• memory indirect (pre- & post-indexed)

Some of these are not supported by codegen yet.

[jrtc27]

I'd prefer to see the style changes separated out, there are a few too many for me to be bundled with functional changes, and there are places where it takes a moment to check whether something's a functional change or not.

llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

86

Needs rebasing to use KindTy

268

This kind of thing seems like a bad idea, just asking for expressions to go missing and get silently converted to 0. The places where this can happen should really be creating an MCConstantExpr of 0.

325

Ditto

llvm/test/MC/M68k/instructions.s

1

Don't combine error and non-error cases in the same test, otherwise there could be errors triggered by the believed-non-error cases that you fail to catch

14

This is... really weird. I don't think it makes any sense to add parsing before it can actually be used for anything.

64

That probably means you shouldn't be supporting parsing them yet. Also CodeGen its above the MC layer, not below it, so what CodeGen does is irrelevant. The issue is the lack of MC support, not a lack of CodeGen patterns.

[ricky26]

llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

86

Actually, that's a different enum. KindTy is in M68kOperand. Perhaps I should rename this one too?

268

I agree but at the moment this is working as a mechanism to preserve the existing functionality.

Ideally we should pick ARII/ARID instructions based on whether the displacement is 0, rather than null. However, that causes a lot of changes to tests and particularly sometimes causes the assembler to pick a 'worse' instruction (using an ARID instruction when an ARII one exists).

I put a couple of comments elsewhere in the file which I hoped covered this sentiment.

llvm/test/MC/M68k/instructions.s

14

That's fair - I implemented them as I was going through the checklist for all the addressing modes in the CPU manual (the additional addressing modes were fallout from the initial AsmParser work). I figured that completeness for this one section (even without MC support) would be more beneficial than the smaller patch with just the ones we can currently support. I expected we were going to need the MC part for the backend to graduate from experimental anyway.

I did consider adding the relevant move instruction formats in a separate patch first but I'm lament to add to that area whilst (at least in my mind) there's still a bit of a sword of Damocles hanging over the instruction representation in the tablegen files.

[jrtc27]

llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

86

Oh right. This one's fine, the variable's called Op so no conflicts.

[myhsu]

Thank you for taking a look into this :-)
If we use the addressing mode designators listed here, I think the problem here is that you want to implement asm parsing logic for 'v', 'u', and 'g'. But we don't even have those addressing modes in the instruction definitions yet (almost all supported addressing modes are listed here).
I prefer to have complete codegen + asm parsing support for these three addressing modes instead of only the asm parsing part as presented here. You can, for example, have three separate patches in which each of them contains full support for one of the said addressing modes.

[ricky26]

Fair enough, makes good sense. I was trying to chip away at things which didn't involve messing with the instruction definitions (since they feel a little up in the air still).

Either way I can shelve these for now and reconstitute them into separate patches at a later date along with the relevant functionality.

Thanks all for the feedback. :)

I might post a message on the llvm-dev mailing list asking about some of the next steps.

llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp

 //===---- M68kAsmParser.cpp - Parse M68k assembly to MCInst instructions --===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "M68kInstrInfo.h"
 #include "M68kRegisterInfo.h"
 #include "TargetInfo/M68kTargetInfo.h"
 
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/TargetRegistry.h"
#include "M68kGenAsmMatcher.inc"
 
   // Parser functions.
   void eatComma();
 
   bool isExpr();
   OperandMatchResultTy parseImm(OperandVector &Operands);
   OperandMatchResultTy parseMemOp(OperandVector &Operands);
   OperandMatchResultTy parseRegOrMoveMask(OperandVector &Operands);
+  OperandMatchResultTy parseMemIndirect(OperandVector &Operands);
+  OperandMatchResultTy parseRegisterIndex(unsigned &Register, uint8_t &Size,
+                                          uint8_t &Scale);
+  OperandMatchResultTy parseOperandSize(uint8_t &Size);
 
 public:
   M68kAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
                 const MCInstrInfo &MII, const MCTargetOptions &Options)
       : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
     MCAsmParserExtension::Initialize(Parser);
     MRI = getContext().getRegisterInfo();
 
public:
   bool ParseDirective(AsmToken DirectiveID) override;
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override;
 };
 
 struct M68kMemOp {
   enum class Kind {
     Addr,
     RegMask,
     Reg,
     RegIndirect,
+    RegIndirectIndex,
     RegPostIncrement,
     RegPreDecrement,
-    RegIndirectDisplacement,
-    RegIndirectDisplacementIndex,
+    MemIndirectPreIndex,
+    MemIndirectPostIndex,
   };
 
   // These variables are used for the following forms:
-  // Addr: (OuterDisp)
+  // Addr: (OuterDisp).Size
   // RegMask: RegMask (as register mask)
   // Reg: %OuterReg
-  // RegIndirect: (%OuterReg)
+  // RegIndirect: (OuterDisp, %OuterReg)
   // RegPostIncrement: (%OuterReg)+
   // RegPreDecrement: -(%OuterReg)
-  // RegIndirectDisplacement: OuterDisp(%OuterReg)
-  // RegIndirectDisplacementIndex:
+  // RegIndirectIndex:
   //   OuterDisp(%OuterReg, %InnerReg.Size * Scale, InnerDisp)
+  // MemIndirectPreIndex:
+  //   ([OuterDisp, %OuterReg, %InnerReg.Size * Scale], InnerDisp)
+  // MemIndirectPostIndex:
+  //   ([OuterDisp, %OuterReg], %InnerReg.Size * Scale, InnerDisp)
 
   Kind Op;
   unsigned OuterReg;
   unsigned InnerReg;
   const MCExpr *OuterDisp;
   const MCExpr *InnerDisp;
-  uint8_t Size : 4;
-  uint8_t Scale : 4;
+  uint8_t Size;
+  uint8_t Scale;
   const MCExpr *Expr;
   uint16_t RegMask;
 
   M68kMemOp() {}
   M68kMemOp(Kind Op) : Op(Op) {}
 
   void print(raw_ostream &OS) const;
 };
static inline unsigned getRegisterIndex(unsigned Register) {
   case M68k::CCR:
     return 16;
 
   default:
     llvm_unreachable("unexpected register number");
   }
 }
 
+static inline void printExpr(raw_ostream &OS, const MCExpr *Expr) {
+  if (Expr != nullptr) {
+    OS << *Expr;
+  } else {
+    OS << '0';
+  }
+}
+
 void M68kMemOp::print(raw_ostream &OS) const {
   switch (Op) {
   case Kind::Addr:
-    OS << OuterDisp;
+    printExpr(OS, OuterDisp);
     break;
   case Kind::RegMask:
     OS << "RegMask(" << format("%04x", RegMask) << ")";
     break;
   case Kind::Reg:
     OS << '%' << OuterReg;
     break;
   case Kind::RegIndirect:
-    OS << "(%" << OuterReg << ')';
+    OS << "(";
+    printExpr(OS, OuterDisp);
+    OS << ",%" << OuterReg << ')';
     break;
   case Kind::RegPostIncrement:
     OS << "(%" << OuterReg << ")+";
     break;
   case Kind::RegPreDecrement:
     OS << "-(%" << OuterReg << ")";
     break;
-  case Kind::RegIndirectDisplacement:
-    OS << OuterDisp << "(%" << OuterReg << ")";
-    break;
-  case Kind::RegIndirectDisplacementIndex:
-    OS << OuterDisp << "(%" << OuterReg << ", " << InnerReg << "." << Size
-       << ", " << InnerDisp << ")";
+  case Kind::RegIndirectIndex:
+    OS << "(";
+    printExpr(OS, OuterDisp);
+    OS << ",%" << OuterReg << ", %" << InnerReg << "." << (unsigned)Size << "*"
+       << (unsigned)Scale << ", ";
+    printExpr(OS, InnerDisp);
+    OS << ")";
+    break;
+  case Kind::MemIndirectPreIndex:
+    OS << "([";
+    printExpr(OS, OuterDisp);
+    OS << ",%" << OuterReg << ",%" << InnerReg << "." << (unsigned)Size << "*"
+       << (unsigned)Scale << "],";
+    printExpr(OS, InnerDisp);
+    OS << ")";
+    break;
+  case Kind::MemIndirectPostIndex:
+    OS << "([";
+    printExpr(OS, OuterDisp);
+    OS << ",%" << OuterReg << "],%" << InnerReg << "." << (unsigned)Size << "*"
+       << (unsigned)Scale << ",";
+    printExpr(OS, InnerDisp);
+    OS << ")";
     break;
   }
 }
 
 void M68kOperand::addExpr(MCInst &Inst, const MCExpr *Expr) {
+  if (Expr == nullptr) {
+    // The given displacement wasn't specified but is needed for this particular
+    // instruction - just emit 0.
+    Inst.addOperand(MCOperand::createImm(0));
+    return;
+  }
+
   if (auto Const = dyn_cast<MCConstantExpr>(Expr)) {
     Inst.addOperand(MCOperand::createImm(Const->getValue()));
     return;
   }
 
   Inst.addOperand(MCOperand::createExpr(Expr));
 }
 
template <unsigned N> bool M68kOperand::isAddrN() const {
   return false;
 }
 void M68kOperand::addAddrOperands(MCInst &Inst, unsigned N) const {
   M68kOperand::addExpr(Inst, MemOp.OuterDisp);
 }
 
 // ARI
 bool M68kOperand::isARI() const {
-  return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirect &&
-         M68k::AR32RegClass.contains(MemOp.OuterReg);
+  if (!isMemOp())
+    return false;
+
+  if (MemOp.Op != M68kMemOp::Kind::RegIndirect)
+    return false;
+
+  if (!M68k::AR32RegClass.contains(MemOp.OuterReg))
+    return false;
+
+  // Only allow instructions where the displacement was omitted entirely
+  // from the source (as opposed to being specified as 0).
+  // This allows forcing a displacement instruction via assembly, but might
+  // be undesirable if the 0 is calculated via assembly macros or similar.
+  if (MemOp.OuterDisp != nullptr)
+    return false;
+
+  return true;
 }
+
 void M68kOperand::addARIOperands(MCInst &Inst, unsigned N) const {
   Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
 }
 
 // ARID
 bool M68kOperand::isARID() const {
-  return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacement &&
-         M68k::AR32RegClass.contains(MemOp.OuterReg);
+  if (!isMemOp())
+    return false;
+
+  if (MemOp.Op != M68kMemOp::Kind::RegIndirect)
+    return false;
+
+  if (!M68k::AR32RegClass.contains(MemOp.OuterReg))
+    return false;
+
+  // Omit instructions which don't specify a displacement, even though we
+  // could generate those instructions with a 0 displacement. This omits
+  // some valid instructions but at the moment the assembler won't prefer
+  // simpler instructions otherwise.
+  if (MemOp.OuterDisp == nullptr)
+    return false;
+
+  return true;
 }
+
 void M68kOperand::addARIDOperands(MCInst &Inst, unsigned N) const {
   M68kOperand::addExpr(Inst, MemOp.OuterDisp);
   Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
 }
 
 // ARII
 bool M68kOperand::isARII() const {
-  return isMemOp() &&
-         MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacementIndex &&
+  return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirectIndex &&
          M68k::AR32RegClass.contains(MemOp.OuterReg);
 }
 void M68kOperand::addARIIOperands(MCInst &Inst, unsigned N) const {
   M68kOperand::addExpr(Inst, MemOp.OuterDisp);
   Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
   Inst.addOperand(MCOperand::createReg(MemOp.InnerReg));
 }
 
return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegPostIncrement &&
          M68k::AR32RegClass.contains(MemOp.OuterReg);
 }
 void M68kOperand::addARIPIOperands(MCInst &Inst, unsigned N) const {
   Inst.addOperand(MCOperand::createReg(MemOp.OuterReg));
 }
 
 // PCD
 bool M68kOperand::isPCD() const {
-  return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacement &&
+  return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirect &&
          MemOp.OuterReg == M68k::PC;
 }
 void M68kOperand::addPCDOperands(MCInst &Inst, unsigned N) const {
   M68kOperand::addExpr(Inst, MemOp.OuterDisp);
 }
 
 // PCI
 bool M68kOperand::isPCI() const {
-  return isMemOp() &&
-         MemOp.Op == M68kMemOp::Kind::RegIndirectDisplacementIndex &&
+  return isMemOp() && MemOp.Op == M68kMemOp::Kind::RegIndirectIndex &&
          MemOp.OuterReg == M68k::PC;
 }
 void M68kOperand::addPCIOperands(MCInst &Inst, unsigned N) const {
   M68kOperand::addExpr(Inst, MemOp.OuterDisp);
   Inst.addOperand(MCOperand::createReg(MemOp.InnerReg));
 }
 
 static inline bool checkRegisterClass(unsigned RegNo, bool Data, bool Address,
OperandMatchResultTy M68kAsmParser::parseRegister(unsigned &RegNo) {
   bool HasPercent = false;
   AsmToken PercentToken;
 
   LLVM_DEBUG(dbgs() << "parseRegister "; getTok().dump(dbgs()); dbgs() << "\n");
 
   if (getTok().is(AsmToken::Percent)) {
     HasPercent = true;
     PercentToken = Lex();
-  } else if (!RegisterPrefixOptional.getValue()) {
+  } else if (!RegisterPrefixOptional.getValue())
     return MatchOperand_NoMatch;
-  }
 
   if (!Parser.getTok().is(AsmToken::Identifier)) {
-    if (HasPercent) {
+    if (HasPercent)
       getLexer().UnLex(PercentToken);
-    }
     return MatchOperand_NoMatch;
   }
 
-  auto RegisterName = Parser.getTok().getString();
+  StringRef RegisterName = Parser.getTok().getString();
+
+  // If a register name contains a dot, it's probably a length specifier,
+  // for example: %r0.l. Trim off the rest from the dot so that we only try
+  // and parse the register's name.
+  StringRef ExtraIdentifier;
+  auto FirstDot = RegisterName.find('.');
+  if (FirstDot != std::string::npos) {
+    ExtraIdentifier = RegisterName.substr(FirstDot);
+    RegisterName = RegisterName.substr(0, FirstDot);
+  }
+
   if (!parseRegisterName(RegNo, Parser.getLexer().getLoc(), RegisterName)) {
-    if (HasPercent) {
+    if (HasPercent)
       getLexer().UnLex(PercentToken);
-    }
     return MatchOperand_NoMatch;
   }
 
   Parser.Lex();
+
+  // Push a token to the front of the lexer's queue with the remainder
+  // of the identifier
+  if (FirstDot != std::string::npos)
+    getLexer().UnLex(AsmToken(AsmToken::Identifier, ExtraIdentifier));
+
   return MatchOperand_Success;
 }
 
 bool M68kAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
                                   SMLoc &EndLoc) {
   auto Result = tryParseRegister(RegNo, StartLoc, EndLoc);
   if (Result != MatchOperand_Success) {
     return Error(StartLoc, "expected register");
OperandMatchResultTy M68kAsmParser::parseImm(OperandVector &Operands) {
   Operands.push_back(M68kOperand::createImm(Expr, Start, End));
   return MatchOperand_Success;
 }
 
 OperandMatchResultTy M68kAsmParser::parseMemOp(OperandVector &Operands) {
   SMLoc Start = getLexer().getLoc();
   bool IsPD = false;
   M68kMemOp MemOp;
+  MemOp.OuterDisp = MemOp.InnerDisp = nullptr;
 
   // Check for a plain register or register mask.
   auto Result = parseRegOrMoveMask(Operands);
-  if (Result != llvm::MatchOperand_NoMatch) {
+  if (Result != llvm::MatchOperand_NoMatch)
     return Result;
-  }
 
   // Check for pre-decrement & outer displacement.
   bool HasDisplacement = false;
   if (getLexer().is(AsmToken::Minus)) {
     IsPD = true;
     Parser.Lex();
   } else if (isExpr()) {
-    if (Parser.parseExpression(MemOp.OuterDisp)) {
+    if (Parser.parseExpression(MemOp.OuterDisp))
       return MatchOperand_ParseFail;
-    }
+
     HasDisplacement = true;
   }
 
   if (getLexer().isNot(AsmToken::LParen)) {
     if (HasDisplacement) {
       MemOp.Op = M68kMemOp::Kind::Addr;
       Operands.push_back(
           M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
       return MatchOperand_Success;
-    } else if (IsPD) {
+    }
+
+    if (IsPD) {
       Error(getLexer().getLoc(), "expected (");
       return MatchOperand_ParseFail;
     }
 
     return MatchOperand_NoMatch;
   }
   Parser.Lex();
 
+  // Handle memory pre & post indexing
+  if (getLexer().is(AsmToken::LBrac)) {
+    Parser.Lex();
+    return parseMemIndirect(Operands);
+  }
+
   // Check for constant dereference & MIT-style displacement
   if (!HasDisplacement && isExpr()) {
-    if (Parser.parseExpression(MemOp.OuterDisp)) {
+    if (Parser.parseExpression(MemOp.OuterDisp))
       return MatchOperand_ParseFail;
-    }
     HasDisplacement = true;
 
     // If we're not followed by a comma, we're a constant dereference.
     if (getLexer().isNot(AsmToken::Comma)) {
+      if (getLexer().isNot(AsmToken::RParen)) {
+        Error(getLexer().getLoc(), "expected )");
+        return MatchOperand_ParseFail;
+      }
+
+      Parser.Lex();
+
       MemOp.Op = M68kMemOp::Kind::Addr;
+
+      if (parseOperandSize(MemOp.Size) == MatchOperand_ParseFail)
+        return MatchOperand_ParseFail;
+
       Operands.push_back(
           M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
       return MatchOperand_Success;
     }
 
     Parser.Lex();
   }
 
   Result = parseRegister(MemOp.OuterReg);
-  if (Result == MatchOperand_ParseFail) {
-    return MatchOperand_ParseFail;
-  }
-
   if (Result != MatchOperand_Success) {
-    Error(getLexer().getLoc(), "expected register");
+    Error(getLexer().getLoc(), "expected base register");
     return MatchOperand_ParseFail;
   }
 
   // Check for Index.
   bool HasIndex = false;
   if (Parser.getTok().is(AsmToken::Comma)) {
     Parser.Lex();
 
-    Result = parseRegister(MemOp.InnerReg);
-    if (Result == MatchOperand_ParseFail) {
-      return Result;
+    Result = parseRegisterIndex(MemOp.InnerReg, MemOp.Size, MemOp.Scale);
+    if (Result != MatchOperand_Success) {
+      Error(getLexer().getLoc(), "expected index register");
+      return MatchOperand_ParseFail;
     }
 
-    if (Result == MatchOperand_NoMatch) {
-      Error(getLexer().getLoc(), "expected register");
+    // Inner displacement
+    if (getLexer().is(AsmToken::Comma)) {
+      Parser.Lex();
+
+      if (!Parser.parseExpression(MemOp.InnerDisp)) {
+        Error(getLexer().getLoc(), "expected constant displacement");
         return MatchOperand_ParseFail;
       }
+    }
 
-    // TODO: parse size, scale and inner displacement.
-    MemOp.Size = 4;
-    MemOp.Scale = 1;
-    MemOp.InnerDisp = MCConstantExpr::create(0, Parser.getContext(), true, 4);
     HasIndex = true;
   }
 
   if (Parser.getTok().isNot(AsmToken::RParen)) {
     Error(getLexer().getLoc(), "expected )");
     return MatchOperand_ParseFail;
   }
   Parser.Lex();
if (OpCount > 1) {
     return MatchOperand_ParseFail;
   }
 
   if (IsPD) {
     MemOp.Op = M68kMemOp::Kind::RegPreDecrement;
   } else if (IsPI) {
     MemOp.Op = M68kMemOp::Kind::RegPostIncrement;
   } else if (HasIndex) {
-    MemOp.Op = M68kMemOp::Kind::RegIndirectDisplacementIndex;
-  } else if (HasDisplacement) {
-    MemOp.Op = M68kMemOp::Kind::RegIndirectDisplacement;
+    MemOp.Op = M68kMemOp::Kind::RegIndirectIndex;
   } else {
     MemOp.Op = M68kMemOp::Kind::RegIndirect;
   }
 
   Operands.push_back(M68kOperand::createMemOp(MemOp, Start, End));
   return MatchOperand_Success;
 }
 
for (;;) {
     getLexer().Lex();
   }
 
   Operands.push_back(
       M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
   return MatchOperand_Success;
 }
 
+OperandMatchResultTy M68kAsmParser::parseMemIndirect(OperandVector &Operands) {
+  SMLoc Start = getLexer().getLoc();
+  M68kMemOp MemOp;
+  MemOp.OuterDisp = nullptr;
+  MemOp.InnerDisp = nullptr;
+
+  // ([ has already been lexed and trimmed.
+
+  if (isExpr()) {
+    if (Parser.parseExpression(MemOp.OuterDisp)) {
+      Error(getLexer().getLoc(),
+            "displacement should be an integer expression");
+      return MatchOperand_ParseFail;
+    }
+
+    if (getLexer().isNot(AsmToken::Comma)) {
+      Error(getLexer().getLoc(), "expected ,");
+      return MatchOperand_ParseFail;
+    }
+
+    Parser.Lex();
+  }
+
+  auto Result = parseRegister(MemOp.OuterReg);
+  if (Result != llvm::MatchOperand_Success) {
+    Error(getLexer().getLoc(), "expected register");
+    return MatchOperand_ParseFail;
+  }
+
+  if (getLexer().is(AsmToken::RBrac)) {
+    // Post-indexing
+    Parser.Lex();
+    MemOp.Op = M68kMemOp::Kind::MemIndirectPostIndex;
+  } else {
+    // Pre-indexing
+    MemOp.Op = M68kMemOp::Kind::MemIndirectPreIndex;
+  }
+
+  // Both memory indirect addressing modes require another register
+  if (getLexer().isNot(AsmToken::Comma)) {
+    Error(getLexer().getLoc(), "expected , before index register");
+    return MatchOperand_ParseFail;
+  }
+
+  Parser.Lex();
+
+  Result = parseRegisterIndex(MemOp.InnerReg, MemOp.Size, MemOp.Scale);
+  if (Result != MatchOperand_Success)
+    return MatchOperand_ParseFail;
+
+  if (MemOp.Op == M68kMemOp::Kind::MemIndirectPreIndex) {
+    if (getLexer().isNot(AsmToken::RBrac)) {
+      Error(getLexer().getLoc(), "expected ]");
+      return MatchOperand_ParseFail;
+    }
+
+    Parser.Lex();
+  }
+
+  if (getLexer().is(AsmToken::Comma)) {
+    // Indexed displacement
+    Parser.Lex();
+
+    if (Parser.parseExpression(MemOp.InnerDisp)) {
+      Error(getLexer().getLoc(), "indexed displacement must be an expression");
+      return MatchOperand_ParseFail;
+    }
+  }
+
+  if (getLexer().isNot(AsmToken::RParen)) {
+    Error(getLexer().getLoc(), "expected )");
+    return MatchOperand_ParseFail;
+  }
+
+  Parser.Lex();
+  Operands.push_back(
+      M68kOperand::createMemOp(MemOp, Start, getLexer().getLoc()));
+  return MatchOperand_Success;
+}
+
+OperandMatchResultTy M68kAsmParser::parseRegisterIndex(unsigned &Register,
+                                                       uint8_t &Size,
+                                                       uint8_t &Scale) {
+  int64_t TempValue;
+  Size = 4;
+  Scale = 1;
+
+  auto Result = parseRegister(Register);
+  if (Result != MatchOperand_Success) {
+    Error(getLexer().getLoc(), "expected register");
+    return MatchOperand_ParseFail;
+  }
+
+  if (parseOperandSize(Size) == MatchOperand_ParseFail)
+    return MatchOperand_ParseFail;
+
+  if (getLexer().is(AsmToken::Star)) {
+    Parser.Lex();
+
+    if (Parser.parseIntToken(TempValue, "scale must be an integer"))
+      return MatchOperand_ParseFail;
+
+    Scale = TempValue;
+  }
+
+  return MatchOperand_Success;
+}
+
+OperandMatchResultTy M68kAsmParser::parseOperandSize(uint8_t &Size) {
+  // Operations default to 32-bits.
+  Size = 4;
+
+  bool HasDot = getLexer().is(AsmToken::Dot);
+  if (HasDot)
+    Parser.Lex();
+
+  if (getLexer().isNot(AsmToken::Identifier)) {
+    if (HasDot) {
+      Error(getLexer().getLoc(), "expected either .L or .W");
+      return MatchOperand_ParseFail;
+    }
+
+    return MatchOperand_NoMatch;
+  }
+
+  StringRef Ident = getLexer().getTok().getString();
+
+  if (!HasDot) {
+    if (!Ident.startswith("."))
+      return MatchOperand_NoMatch;
+
+    Ident = Ident.substr(1);
+  }
+
+  if (Ident.equals_insensitive("W")) {
+    Size = 2;
+  } else if (!Ident.equals_insensitive("L")) {
+    Error(getLexer().getLoc(), "expected either .L or .W");
+    return MatchOperand_ParseFail;
+  }
+
+  Parser.Lex();
+  return MatchOperand_Success;
+}
+
 void M68kAsmParser::eatComma() {
   if (Parser.getTok().is(AsmToken::Comma)) {
     Parser.Lex();
   }
 }
 
 bool M68kAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                                      SMLoc NameLoc, OperandVector &Operands) {

llvm/test/MC/M68k/instructions.s

-; RUN: llvm-mc -triple m68k -show-encoding -motorola-integers %s | FileCheck %s
+; RUN: not llvm-mc -triple m68k -show-encoding -motorola-integers %s --show-inst-operands 2>&1 | FileCheck %s
 
 ; At the moment, all encoding tests for M68k live in llvm/test/CodeGen/M68k/.
 ; This is the first test included as part of the AsmMatcher and lacks encoding checks.
 ; The current migration plan is to consolidate all of the encoding tests in this
 ; directory along with AsmMatcher/ Disassembler tests like the other platforms.
 ; For more information and status updates see bug #49865.
 
 .global ext_fn
 
+; These checks have to appear first since they are printed during parsing, not
+; at the end like the others. They are printed as info because the instructions
+; don't (yet) support this operand format.
+; CHECK: 'move.l', %6, ([50,%6],%7.4*2,20)
+move.l %a0, ([50, %a0], %a1.L * 2, 20)
+; CHECK: 'move.l', %6, ([50,%6,%7.4*2],20)
+move.l %a0, ([50, %a0, %a1.L * 2], 20)
+
 ; CHECK: move.l %a1, %a0
 move.l %a1, %a0
 ; CHECK: adda.l %a0, %a1
 adda.l %a0, %a1
 ; CHECK: addx.l %d1, %d2
 addx.l %d1, %d2
 ; CHECK: sub.w #4, %d1
 sub.w #4, %d1

 ; CHECK: nop
 nop
 ; CHECK: rts
 rts
 ; CHECK: movem.l %d0-%d6/%a0, (%sp)
 movem.l %d0-%d6/%a0, (%sp)
 ; CHECK: movem.l (10,%sp), %d0-%d6/%a0
 movem.l (10,%sp), %d0-%d6/%a0
+; CHECK: move.l (%a0), $100
+move.l (%a0), ($100).L
+
+; TODO: the size & scale are not preserved here because they are not supported
+; at codegen time (yet).
+; CHECK: move.l %d0, (0,%a0,%a1)
+move.l %d0, (%a0, %a1.L * 2)