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Differential D108673

[CodeExtractor] Preserve topological order for the return blocks.
ClosedPublic

Authored by vzakhari on Aug 24 2021, 4:25 PM.

Details

Reviewers
AndrewLitteken
jroelofs
Commits
rG2e192ab1f457: [CodeExtractor] Preserve topological order for the return blocks.
Summary

Place the extracted blocks after the entry block of the new function to keep the created return blocks topologically ordered to the original blocks.

Diff Detail

Unit TestsFailed

TimeTest
530 msx64 debian > Clang.OpenMP::cancel_codegen.cpp
400 msx64 debian > Clang.OpenMP::parallel_codegen.cpp
630 msx64 windows > Clang.OpenMP::cancel_codegen.cpp
490 msx64 windows > Clang.OpenMP::parallel_codegen.cpp

Event Timeline

vzakhari created this revision.Aug 24 2021, 4:25 PM
Herald added subscribers: ormris, hiraditya. · View Herald TranscriptAug 24 2021, 4:25 PM
vzakhari requested review of this revision.Aug 24 2021, 4:25 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 24 2021, 4:25 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
jroelofs accepted this revision.Aug 24 2021, 5:01 PM
This revision is now accepted and ready to land.Aug 24 2021, 5:01 PM
Harbormaster completed remote builds in B121067: Diff 368494.Aug 24 2021, 5:06 PM
vzakhari updated this revision to Diff 368531.Aug 24 2021, 6:48 PM
Harbormaster completed remote builds in B121092: Diff 368531.Aug 24 2021, 7:24 PM
This revision was landed with ongoing or failed builds.Aug 25 2021, 8:09 AM
Closed by commit rG2e192ab1f457: [CodeExtractor] Preserve topological order for the return blocks. (authored by vzakhari). · Explain Why
This revision was automatically updated to reflect the committed changes.
vzakhari added a commit: rG2e192ab1f457: [CodeExtractor] Preserve topological order for the return blocks..
Herald added a project: Restricted Project. · View Herald TranscriptAug 25 2021, 8:09 AM
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Revision Contents

PathSize
llvm/
lib/
Transforms/
IPO/
3 lines
Utils/
7 lines
test/
Transforms/
CodeExtractor/
8 lines
4 lines
8 lines
6 lines
4 lines
HotColdSplit/
12 lines
IROutliner/
10 lines
12 lines
OpenMP/
88 lines
tools/
llvm-extract/
18 lines

Diff 368494

llvm/lib/Transforms/IPO/IROutliner.cpp

Show First 20 Lines • Show All 428 Lines • ▼ Show 20 Lines
/// Move each BasicBlock in \p Old to \p New. /// Move each BasicBlock in \p Old to \p New.
/// ///
/// \param [in] Old - The function to move the basic blocks from. /// \param [in] Old - The function to move the basic blocks from.
/// \param [in] New - The function to move the basic blocks to. /// \param [in] New - The function to move the basic blocks to.
/// \returns the first return block for the function in New. /// \returns the first return block for the function in New.
static BasicBlock *moveFunctionData(Function &Old, Function &New) { static BasicBlock *moveFunctionData(Function &Old, Function &New) {
Function::iterator CurrBB, NextBB, FinalBB; Function::iterator CurrBB, NextBB, FinalBB;
BasicBlock *NewEnd = nullptr; BasicBlock *NewEnd = nullptr;
std::vector<Instruction *> DebugInsts;
for (CurrBB = Old.begin(), FinalBB = Old.end(); CurrBB != FinalBB; for (CurrBB = Old.begin(), FinalBB = Old.end(); CurrBB != FinalBB;
CurrBB = NextBB) { CurrBB = NextBB) {
NextBB = std::next(CurrBB); NextBB = std::next(CurrBB);
CurrBB->removeFromParent(); CurrBB->removeFromParent();
CurrBB->insertInto(&New); CurrBB->insertInto(&New);
Instruction *I = CurrBB->getTerminator(); Instruction *I = CurrBB->getTerminator();
if (isa<ReturnInst>(I)) if (isa<ReturnInst>(I))
NewEnd = &(*CurrBB); NewEnd = &(*CurrBB);
std::vector<Instruction *> DebugInsts;
for (Instruction &Val : *CurrBB) { for (Instruction &Val : *CurrBB) {
// We must handle the scoping of called functions differently than // We must handle the scoping of called functions differently than
// other outlined instructions. // other outlined instructions.
if (!isa<CallInst>(&Val)) { if (!isa<CallInst>(&Val)) {
// Remove the debug information for outlined functions. // Remove the debug information for outlined functions.
Val.setDebugLoc(DebugLoc()); Val.setDebugLoc(DebugLoc());
continue; continue;
} }
▲ Show 20 Lines • Show All 1,386 Lines • Show Last 20 Lines

llvm/lib/Transforms/Utils/CodeExtractor.cpp

Show First 20 Lines • Show All 1,383 Lines • ▼ Show 20 LinesCallInst *CodeExtractor::emitCallAndSwitchStatement(Function *newFunction,
return call; return call;
} }
void CodeExtractor::moveCodeToFunction(Function *newFunction) { void CodeExtractor::moveCodeToFunction(Function *newFunction) {
Function *oldFunc = (*Blocks.begin())->getParent(); Function *oldFunc = (*Blocks.begin())->getParent();
Function::BasicBlockListType &oldBlocks = oldFunc->getBasicBlockList(); Function::BasicBlockListType &oldBlocks = oldFunc->getBasicBlockList();
Function::BasicBlockListType &newBlocks = newFunction->getBasicBlockList(); Function::BasicBlockListType &newBlocks = newFunction->getBasicBlockList();
auto newFuncIt = newFunction->front().getIterator();
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: invalid case style for variable 'newFuncIt' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 'newFuncIt' [readability-identifier…
for (BasicBlock *Block : Blocks) { for (BasicBlock *Block : Blocks) {
// Delete the basic block from the old function, and the list of blocks // Delete the basic block from the old function, and the list of blocks
oldBlocks.remove(Block); oldBlocks.remove(Block);
// Insert this basic block into the new function // Insert this basic block into the new function
newBlocks.push_back(Block); // Insert the original blocks after the entry block created
// for the new function. The entry block may be followed
// by a set of exit blocks at this point, but these exit
// blocks better be placed at the end of the new function.
newFuncIt = newBlocks.insertAfter(newFuncIt, Block);
} }
} }
void CodeExtractor::calculateNewCallTerminatorWeights( void CodeExtractor::calculateNewCallTerminatorWeights(
BasicBlock *CodeReplacer, BasicBlock *CodeReplacer,
DenseMap<BasicBlock *, BlockFrequency> &ExitWeights, DenseMap<BasicBlock *, BlockFrequency> &ExitWeights,
BranchProbabilityInfo *BPI) { BranchProbabilityInfo *BPI) {
using Distribution = BlockFrequencyInfoImplBase::Distribution; using Distribution = BlockFrequencyInfoImplBase::Distribution;
▲ Show 20 Lines • Show All 406 Lines • Show Last 20 Lines

llvm/test/Transforms/CodeExtractor/LoopExtractor.ll

Show All 36 Linesexit: ; preds = %loop.1
ret void ret void
} }
declare void @foo() declare void @foo()
; CHECK-LABEL: define internal void @test3.loop.1() ; CHECK-LABEL: define internal void @test3.loop.1()
; CHECK-NEXT: newFuncRoot: ; CHECK-NEXT: newFuncRoot:
; CHECK-NEXT: br label %loop.1 ; CHECK-NEXT: br label %loop.1
; CHECK: exit.exitStub:
; CHECK-NEXT: ret void
; CHECK: loop.1: ; CHECK: loop.1:
; CHECK-NEXT: %index.1 = phi i32 [ %next.1, %loop.1.loop.1_crit_edge ], [ 10, %newFuncRoot ] ; CHECK-NEXT: %index.1 = phi i32 [ %next.1, %loop.1.loop.1_crit_edge ], [ 10, %newFuncRoot ]
; CHECK-NEXT: tail call void @foo() ; CHECK-NEXT: tail call void @foo()
; CHECK-NEXT: %next.1 = add nsw i32 %index.1, -1 ; CHECK-NEXT: %next.1 = add nsw i32 %index.1, -1
; CHECK-NEXT: %repeat.1 = icmp sgt i32 %index.1, 1 ; CHECK-NEXT: %repeat.1 = icmp sgt i32 %index.1, 1
; CHECK-NEXT: br i1 %repeat.1, label %loop.1.loop.1_crit_edge, label %exit.exitStub ; CHECK-NEXT: br i1 %repeat.1, label %loop.1.loop.1_crit_edge, label %exit.exitStub
; CHECK: loop.1.loop.1_crit_edge: ; CHECK: loop.1.loop.1_crit_edge:
; CHECK-NEXT: br label %loop.1 ; CHECK-NEXT: br label %loop.1
; CHECK: exit.exitStub:
; CHECK-NEXT: ret void
; CHECK-LABEL: define internal void @test3.loop.0() ; CHECK-LABEL: define internal void @test3.loop.0()
; CHECK-NEXT: newFuncRoot: ; CHECK-NEXT: newFuncRoot:
; CHECK-NEXT: br label %loop.0 ; CHECK-NEXT: br label %loop.0
; CHECK: loop.0.loop.1_crit_edge.exitStub:
; CHECK-NEXT: ret void
; CHECK: loop.0: ; CHECK: loop.0:
; CHECK-NEXT: %index.0 = phi i32 [ 10, %newFuncRoot ], [ %next.0, %loop.0.loop.0_crit_edge ] ; CHECK-NEXT: %index.0 = phi i32 [ 10, %newFuncRoot ], [ %next.0, %loop.0.loop.0_crit_edge ]
; CHECK-NEXT: tail call void @foo() ; CHECK-NEXT: tail call void @foo()
; CHECK-NEXT: %next.0 = add nsw i32 %index.0, -1 ; CHECK-NEXT: %next.0 = add nsw i32 %index.0, -1
; CHECK-NEXT: %repeat.0 = icmp sgt i32 %index.0, 1 ; CHECK-NEXT: %repeat.0 = icmp sgt i32 %index.0, 1
; CHECK-NEXT: br i1 %repeat.0, label %loop.0.loop.0_crit_edge, label %loop.0.loop.1_crit_edge.exitStub ; CHECK-NEXT: br i1 %repeat.0, label %loop.0.loop.0_crit_edge, label %loop.0.loop.1_crit_edge.exitStub
; CHECK: loop.0.loop.0_crit_edge: ; CHECK: loop.0.loop.0_crit_edge:
; CHECK-NEXT: br label %loop.0 ; CHECK-NEXT: br label %loop.0
; CHECK: loop.0.loop.1_crit_edge.exitStub:
; CHECK-NEXT: ret void

llvm/test/Transforms/CodeExtractor/LoopExtractor_crash.ll

Show All 31 Linesexit: ; preds = %loopexit
ret void ret void
} }
declare void @foo() declare void @foo()
; CHECK-LABEL: define internal void @test.loopentry() ; CHECK-LABEL: define internal void @test.loopentry()
; CHECK-NEXT: newFuncRoot: ; CHECK-NEXT: newFuncRoot:
; CHECK-NEXT: br label %loopentry ; CHECK-NEXT: br label %loopentry
; CHECK: loopexit.exitStub:
; CHECK-NEXT: ret void
; CHECK: loopentry: ; CHECK: loopentry:
; CHECK-NEXT: br i1 false, label %loopbody, label %loopexit.exitStub ; CHECK-NEXT: br i1 false, label %loopbody, label %loopexit.exitStub
; CHECK: loopbody: ; CHECK: loopbody:
; CHECK-NEXT: call void @foo() ; CHECK-NEXT: call void @foo()
; CHECK-NEXT: br label %loopentry ; CHECK-NEXT: br label %loopentry
; CHECK: loopexit.exitStub:
; CHECK-NEXT: ret void

llvm/test/Transforms/CodeExtractor/LoopExtractor_infinite.ll

Show All 29 Lines
exit.1: ; preds = %loopentry exit.1: ; preds = %loopentry
ret void ret void
} }
; CHECK-LABEL: define internal i1 @test.loopentry() ; CHECK-LABEL: define internal i1 @test.loopentry()
; CHECK-NEXT: newFuncRoot: ; CHECK-NEXT: newFuncRoot:
; CHECK-NEXT: br label %loopentry ; CHECK-NEXT: br label %loopentry
; CHECK: exit.1.exitStub:
; CHECK-NEXT: ret i1 true
; CHECK: exit.0.exitStub:
; CHECK-NEXT: ret i1 false
; CHECK: loopentry: ; CHECK: loopentry:
; CHECK-NEXT: br i1 true, label %exit.1.exitStub, label %loopexit ; CHECK-NEXT: br i1 true, label %exit.1.exitStub, label %loopexit
; CHECK: loopexit: ; CHECK: loopexit:
; CHECK-NEXT: br i1 false, label %loopexit.loopentry_crit_edge, label %exit.0.exitStub ; CHECK-NEXT: br i1 false, label %loopexit.loopentry_crit_edge, label %exit.0.exitStub
; CHECK: loopexit.loopentry_crit_edge: ; CHECK: loopexit.loopentry_crit_edge:
; CHECK-NEXT: br label %loopentry ; CHECK-NEXT: br label %loopentry
; CHECK: exit.1.exitStub:
; CHECK-NEXT: ret i1 true
; CHECK: exit.0.exitStub:
; CHECK-NEXT: ret i1 false

llvm/test/Transforms/CodeExtractor/live_shrink_unsafe.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Linesbb:
tail call void @_Z3foo_unknown_calli(i32 %tmp) tail call void @_Z3foo_unknown_calli(i32 %tmp)
ret void ret void
} }
; CHECK-LABEL: define internal void @_Z3foo_unknown_calli.1.bb3 ; CHECK-LABEL: define internal void @_Z3foo_unknown_calli.1.bb3
; CHECK: newFuncRoot: ; CHECK: newFuncRoot:
; CHECK-NEXT: br label %bb3 ; CHECK-NEXT: br label %bb3
; CHECK: bb4.exitStub:
; CHECK-NEXT: ret void
; CHECK: bb3: ; CHECK: bb3:
; CHECK-NOT: lifetime.ed ; CHECK-NOT: lifetime.ed
; CHECK: br label %bb4.exitStub ; CHECK: br label %bb4.exitStub
; CHECK: bb4.exitStub:
; CHECK-NEXT: ret void
!llvm.module.flags = !{!0} !llvm.module.flags = !{!0}
!llvm.ident = !{!1} !llvm.ident = !{!1}
!0 = !{i32 1, !"wchar_size", i32 4} !0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{!"clang version 5.0.0 (trunk 304489)"} !1 = !{!"clang version 5.0.0 (trunk 304489)"}
!2 = !{!3, !3, i64 0} !2 = !{!3, !3, i64 0}
!3 = !{!"any pointer", !4, i64 0} !3 = !{!"any pointer", !4, i64 0}
!4 = !{!"omnipotent char", !5, i64 0} !4 = !{!"omnipotent char", !5, i64 0}
!5 = !{!"Simple C++ TBAA"} !5 = !{!"Simple C++ TBAA"}
!6 = !{!7, !7, i64 0} !6 = !{!7, !7, i64 0}
!7 = !{!"int", !4, i64 0} !7 = !{!"int", !4, i64 0}

llvm/test/Transforms/CodeExtractor/unreachable-block.ll

; RUN: opt -S -partial-inliner %s | FileCheck %s ; RUN: opt -S -partial-inliner %s | FileCheck %s
; CHECK-LABEL: define void @dipsy( ; CHECK-LABEL: define void @dipsy(
; CHECK-NEXT: call void @tinkywinky.1.ontrue() ; CHECK-NEXT: call void @tinkywinky.1.ontrue()
; CHECK-NEXT: call void @patatuccio() ; CHECK-NEXT: call void @patatuccio()
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK-NEXT: } ; CHECK-NEXT: }
; CHECK-LABEL: define internal void @tinkywinky.1.ontrue() { ; CHECK-LABEL: define internal void @tinkywinky.1.ontrue() {
; CHECK-NEXT: newFuncRoot: ; CHECK-NEXT: newFuncRoot:
; CHECK-NEXT: br label %ontrue ; CHECK-NEXT: br label %ontrue
; CHECK: onfalse{{.*}}:
; CHECK-NEXT: ret void
; CHECK: ontrue: ; CHECK: ontrue:
; CHECK-NEXT: call void @patatino() ; CHECK-NEXT: call void @patatino()
; CHECK-NEXT: br label %onfalse{{.*}} ; CHECK-NEXT: br label %onfalse{{.*}}
; CHECK: onfalse{{.*}}:
; CHECK-NEXT: ret void
; CHECK-NEXT: } ; CHECK-NEXT: }
declare void @patatino() declare void @patatino()
declare void @patatuccio() declare void @patatuccio()
define fastcc void @tinkywinky() { define fastcc void @tinkywinky() {
br i1 true, label %ontrue, label %onfalse br i1 true, label %ontrue, label %onfalse
ontrue: ontrue:
Show All 12 Lines

llvm/test/Transforms/HotColdSplit/multiple-exits.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Linesexit2: ; preds = %if.then
br label %return br label %return
return: ; preds = %exit2, %exit1 return: ; preds = %exit2, %exit1
ret void ret void
} }
; CHECK-LABEL: define {{.*}}@foo.cold.1( ; CHECK-LABEL: define {{.*}}@foo.cold.1(
; CHECK: br ; CHECK: br
; CHECK: [[exit1Stub:.*]]:
; CHECK-NEXT: ret i1 true
; CHECK: [[returnStub:.*]]:
; CHECK-NEXT: ret i1 false
; CHECK: call {{.*}}@sink ; CHECK: call {{.*}}@sink
; CHECK-NEXT: [[cmp:%.*]] = icmp ; CHECK-NEXT: [[cmp:%.*]] = icmp
; CHECK-NEXT: br i1 [[cmp]], label %[[exit1Stub]], label %exit2 ; CHECK-NEXT: br i1 [[cmp]], label %[[exit1Stub:.*]], label %exit2
; CHECK-LABEL: exit2: ; CHECK-LABEL: exit2:
; CHECK-NEXT: call {{.*}}@sideeffect(i32 2) ; CHECK-NEXT: call {{.*}}@sideeffect(i32 2)
; CHECK-NEXT: br label %[[returnStub]] ; CHECK-NEXT: br label %[[returnStub:.*]]
; CHECK: [[exit1Stub]]:
; CHECK-NEXT: ret i1 true
; CHECK: [[returnStub]]:
; CHECK-NEXT: ret i1 false
declare void @sink(...) cold declare void @sink(...) cold
declare void @sideeffect(i32) declare void @sideeffect(i32)

llvm/test/Transforms/IROutliner/outlining-different-output-blocks.ll

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Linesentry:
store i32 %add, i32* %output, align 4 store i32 %add, i32* %output, align 4
%2 = load i32, i32* %output, align 4 %2 = load i32, i32* %output, align 4
%mul = mul i32 %2, %sub %mul = mul i32 %2, %sub
store i32 %mul, i32* %result, align 4 store i32 %mul, i32* %result, align 4
ret void ret void
} }
; CHECK: define internal void @outlined_ir_func_0(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]], i32* [[ARG2:%.*]], i32* [[ARG3:%.*]], i32* [[ARG4:%.*]], i32 [[ARG5:%.*]]) #1 { ; CHECK: define internal void @outlined_ir_func_0(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]], i32* [[ARG2:%.*]], i32* [[ARG3:%.*]], i32* [[ARG4:%.*]], i32 [[ARG5:%.*]]) #1 {
; CHECK: _after_outline.exitStub:
; CHECK-NEXT: switch i32 [[ARG5]], label [[BLOCK:%.*]] [
; CHECK-NEXT: i32 0, label %[[BLOCK_0:.*]]
; CHECK-NEXT: i32 1, label %[[BLOCK_1:.*]]
; CHECK: entry_to_outline: ; CHECK: entry_to_outline:
; CHECK-NEXT: store i32 2, i32* [[ARG0]], align 4 ; CHECK-NEXT: store i32 2, i32* [[ARG0]], align 4
; CHECK-NEXT: store i32 3, i32* [[ARG1]], align 4 ; CHECK-NEXT: store i32 3, i32* [[ARG1]], align 4
; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARG0]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARG0]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG1]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG1]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP0]], [[TMP1]]
; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[TMP0]], [[TMP1]]
; CHECK-NEXT: store i32 [[ADD]], i32* [[ARG2]], align 4 ; CHECK-NEXT: store i32 [[ADD]], i32* [[ARG2]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG2]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG2]], align 4
; CHECK: _after_outline.exitStub:
; CHECK-NEXT: switch i32 [[ARG5]], label [[BLOCK:%.*]] [
; CHECK-NEXT: i32 0, label %[[BLOCK_0:.*]]
; CHECK-NEXT: i32 1, label %[[BLOCK_1:.*]]
; CHECK: [[BLOCK_0]]: ; CHECK: [[BLOCK_0]]:
; CHECK-NEXT: store i32 [[ADD]], i32* [[ARG3]], align 4 ; CHECK-NEXT: store i32 [[ADD]], i32* [[ARG3]], align 4
; CHECK-NEXT: store i32 [[TMP2]], i32* [[ARG4]], align 4 ; CHECK-NEXT: store i32 [[TMP2]], i32* [[ARG4]], align 4
; CHECK: [[BLOCK_1]]: ; CHECK: [[BLOCK_1]]:
; CHECK-NEXT: store i32 [[SUB]], i32* [[ARG3]], align 4 ; CHECK-NEXT: store i32 [[SUB]], i32* [[ARG3]], align 4
; CHECK-NEXT: store i32 [[TMP2]], i32* [[ARG4]], align 4 ; CHECK-NEXT: store i32 [[TMP2]], i32* [[ARG4]], align 4

llvm/test/Transforms/IROutliner/outlining-same-output-blocks.ll

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Linesentry:
store i32 %add, i32* %output, align 4 store i32 %add, i32* %output, align 4
%2 = load i32, i32* %output, align 4 %2 = load i32, i32* %output, align 4
%mul = mul i32 %2, %add %mul = mul i32 %2, %add
store i32 %mul, i32* %result, align 4 store i32 %mul, i32* %result, align 4
ret void ret void
} }
; CHECK: define internal void @outlined_ir_func_0(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]], i32* [[ARG2:%.*]], i32* [[ARG3:%.*]], i32* [[ARG4:%.*]]) #1 { ; CHECK: define internal void @outlined_ir_func_0(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]], i32* [[ARG2:%.*]], i32* [[ARG3:%.*]], i32* [[ARG4:%.*]]) #1 {
; CHECK: entry_after_outline.exitStub:
; CHECK-NEXT: store i32 [[ADD:%.*]], i32* [[ARG3]], align 4
; CHECK-NEXT: store i32 [[TMP2:%.*]], i32* [[ARG4]], align 4
; CHECK: entry_to_outline: ; CHECK: entry_to_outline:
; CHECK-NEXT: store i32 2, i32* [[ARG0]], align 4 ; CHECK-NEXT: store i32 2, i32* [[ARG0]], align 4
; CHECK-NEXT: store i32 3, i32* [[ARG1]], align 4 ; CHECK-NEXT: store i32 3, i32* [[ARG1]], align 4
; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARG0]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARG0]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG1]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG1]], align 4
; CHECK-NEXT: [[ADD]] = add i32 [[TMP0]], [[TMP1]] ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP0]], [[TMP1]]
; CHECK-NEXT: store i32 [[ADD]], i32* [[ARG2]], align 4 ; CHECK-NEXT: store i32 [[ADD]], i32* [[ARG2]], align 4
; CHECK-NEXT: [[TMP2]] = load i32, i32* [[ARG2]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARG2]], align 4
; CHECK: entry_after_outline.exitStub:
; CHECK-NEXT: store i32 [[ADD]], i32* [[ARG3]], align 4
; CHECK-NEXT: store i32 [[TMP2]], i32* [[ARG4]], align 4

llvm/test/Transforms/OpenMP/parallel_region_merging.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,709 Lines • ▼ Show 20 Lines
; CHECK1-LABEL: define {{[^@]+}}@merge..omp_par ; CHECK1-LABEL: define {{[^@]+}}@merge..omp_par
; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK1-NEXT: omp.par.entry: ; CHECK1-NEXT: omp.par.entry:
; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; CHECK1: omp.par.region: ; CHECK1: omp.par.region:
; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK1: omp.par.merged: ; CHECK1: omp.par.merged:
; CHECK1-NEXT: call void @.omp_outlined.(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined.(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK1-NEXT: call void @.omp_outlined..1(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..1(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK1-NEXT: br label [[ENTRY_SPLIT:%.*]] ; CHECK1-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK1: entry.split: ; CHECK1: entry.split:
; CHECK1-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
; CHECK1: omp.par.region.split: ; CHECK1: omp.par.region.split:
; CHECK1-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]
; CHECK1: omp.par.pre_finalize: ; CHECK1: omp.par.pre_finalize:
; CHECK1-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; ;
; ;
; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. ; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK1-NEXT: entry: ; CHECK1-NEXT: entry:
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK1-NEXT: call void @use(i32 [[TMP0]]) ; CHECK1-NEXT: call void @use(i32 [[TMP0]])
; CHECK1-NEXT: ret void ; CHECK1-NEXT: ret void
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
; CHECK1-LABEL: define {{[^@]+}}@merge_seq..omp_par ; CHECK1-LABEL: define {{[^@]+}}@merge_seq..omp_par
; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] { ; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] {
; CHECK1-NEXT: omp.par.entry: ; CHECK1-NEXT: omp.par.entry:
; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; CHECK1: omp.par.region: ; CHECK1: omp.par.region:
; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK1: omp.par.merged: ; CHECK1: omp.par.merged:
; CHECK1-NEXT: call void @.omp_outlined..8(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..8(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
Show All 19 Lines
; CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 ; CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
; CHECK1-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 ; CHECK1-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK1: omp.par.merged.split: ; CHECK1: omp.par.merged.split:
; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK1: omp_region.body.split: ; CHECK1: omp_region.body.split:
; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK1-NEXT: br label [[OMP_REGION_END]] ; CHECK1-NEXT: br label [[OMP_REGION_END]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; ;
; ;
; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 ; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8
; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK1-NEXT: entry: ; CHECK1-NEXT: entry:
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK1-NEXT: call void @use(i32 [[TMP0]]) ; CHECK1-NEXT: call void @use(i32 [[TMP0]])
; CHECK1-NEXT: ret void ; CHECK1-NEXT: ret void
Show All 31 Lines
; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], float* [[F_RELOADED:%.*]], float* [[F_ADDR:%.*]], float* [[P:%.*]]) #[[ATTR0]] { ; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], float* [[F_RELOADED:%.*]], float* [[F_ADDR:%.*]], float* [[P:%.*]]) #[[ATTR0]] {
; CHECK1-NEXT: omp.par.entry: ; CHECK1-NEXT: omp.par.entry:
; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F_RELOADED]], align 4 ; CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F_RELOADED]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; CHECK1: omp.par.region: ; CHECK1: omp.par.region:
; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK1: omp.par.merged: ; CHECK1: omp.par.merged:
; CHECK1-NEXT: call void @.omp_outlined..10(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], float* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[F_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..10(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], float* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[F_ADDR]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
Show All 18 Lines
; CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], 0x40091EB860000000 ; CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], 0x40091EB860000000
; CHECK1-NEXT: store float [[ADD]], float* [[P]], align 4 ; CHECK1-NEXT: store float [[ADD]], float* [[P]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK1: omp.par.merged.split: ; CHECK1: omp.par.merged.split:
; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK1: omp_region.body.split: ; CHECK1: omp_region.body.split:
; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK1-NEXT: br label [[OMP_REGION_END]] ; CHECK1-NEXT: br label [[OMP_REGION_END]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; ;
; ;
; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 ; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10
; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], float* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[F:%.*]]) { ; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], float* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[F:%.*]]) {
; CHECK1-NEXT: entry: ; CHECK1-NEXT: entry:
; CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[F]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[F]], align 4
; CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP0]] to i32 ; CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP0]] to i32
; CHECK1-NEXT: call void @use(i32 [[CONV]]) ; CHECK1-NEXT: call void @use(i32 [[CONV]])
Show All 33 Lines
; CHECK1-LABEL: define {{[^@]+}}@merge_seq_firstprivate..omp_par ; CHECK1-LABEL: define {{[^@]+}}@merge_seq_firstprivate..omp_par
; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]], i64* [[A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC:%.*]]) #[[ATTR0]] { ; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]], i64* [[A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC:%.*]]) #[[ATTR0]] {
; CHECK1-NEXT: omp.par.entry: ; CHECK1-NEXT: omp.par.entry:
; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; CHECK1: omp.par.region: ; CHECK1: omp.par.region:
; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK1: omp.par.merged: ; CHECK1: omp.par.merged:
; CHECK1-NEXT: call void @.omp_outlined..12(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..12(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
Show All 22 Lines
; CHECK1-NEXT: [[A_CASTED_SROA_0_0_INSERT_EXT:%.*]] = zext i32 [[ADD]] to i64 ; CHECK1-NEXT: [[A_CASTED_SROA_0_0_INSERT_EXT:%.*]] = zext i32 [[ADD]] to i64
; CHECK1-NEXT: store i64 [[A_CASTED_SROA_0_0_INSERT_EXT]], i64* [[A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC]], align 8 ; CHECK1-NEXT: store i64 [[A_CASTED_SROA_0_0_INSERT_EXT]], i64* [[A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC]], align 8
; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK1: omp.par.merged.split: ; CHECK1: omp.par.merged.split:
; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK1: omp_region.body.split: ; CHECK1: omp_region.body.split:
; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK1-NEXT: br label [[OMP_REGION_END]] ; CHECK1-NEXT: br label [[OMP_REGION_END]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; ;
; ;
; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 ; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12
; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK1-NEXT: entry: ; CHECK1-NEXT: entry:
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK1-NEXT: call void @use(i32 [[TMP0]]) ; CHECK1-NEXT: call void @use(i32 [[TMP0]])
; CHECK1-NEXT: ret void ; CHECK1-NEXT: ret void
Show All 29 Lines
; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] { ; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] {
; CHECK1-NEXT: omp.par.entry: ; CHECK1-NEXT: omp.par.entry:
; CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 ; CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; CHECK1: omp.par.region: ; CHECK1: omp.par.region:
; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK1: omp.par.merged: ; CHECK1: omp.par.merged:
; CHECK1-NEXT: call void @.omp_outlined..14(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..14(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
Show All 22 Lines
; CHECK1-NEXT: store i32 [[TMP5]], i32* [[B]], align 4 ; CHECK1-NEXT: store i32 [[TMP5]], i32* [[B]], align 4
; CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 4, i8* noundef nonnull [[TMP3]]) ; CHECK1-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 4, i8* noundef nonnull [[TMP3]])
; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK1: omp.par.merged.split: ; CHECK1: omp.par.merged.split:
; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK1: omp_region.body.split: ; CHECK1: omp_region.body.split:
; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK1-NEXT: br label [[OMP_REGION_END]] ; CHECK1-NEXT: br label [[OMP_REGION_END]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; ;
; ;
; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 ; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14
; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK1-NEXT: entry: ; CHECK1-NEXT: entry:
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK1-NEXT: call void @use(i32 [[TMP0]]) ; CHECK1-NEXT: call void @use(i32 [[TMP0]])
; CHECK1-NEXT: ret void ; CHECK1-NEXT: ret void
Show All 36 Lines
; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_RELOADED:%.*]], i32* [[A_ADDR:%.*]], i32* [[B:%.*]]) #[[ATTR0]] { ; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_RELOADED:%.*]], i32* [[A_ADDR:%.*]], i32* [[B:%.*]]) #[[ATTR0]] {
; CHECK1-NEXT: omp.par.entry: ; CHECK1-NEXT: omp.par.entry:
; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_RELOADED]], align 4 ; CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_RELOADED]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; CHECK1: omp.par.region: ; CHECK1: omp.par.region:
; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK1: omp.par.merged: ; CHECK1: omp.par.merged:
; CHECK1-NEXT: call void @.omp_outlined..16(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..16(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
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; CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 ; CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
; CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 ; CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK1: omp.par.merged.split: ; CHECK1: omp.par.merged.split:
; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK1: omp_region.body.split: ; CHECK1: omp_region.body.split:
; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK1-NEXT: br label [[OMP_REGION_END]] ; CHECK1-NEXT: br label [[OMP_REGION_END]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; ;
; ;
; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 ; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16
; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK1-NEXT: entry: ; CHECK1-NEXT: entry:
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK1-NEXT: call void @use(i32 [[TMP0]]) ; CHECK1-NEXT: call void @use(i32 [[TMP0]])
; CHECK1-NEXT: ret void ; CHECK1-NEXT: ret void
Show All 32 Lines
; CHECK1-LABEL: define {{[^@]+}}@merge_cancellable_regions..omp_par ; CHECK1-LABEL: define {{[^@]+}}@merge_cancellable_regions..omp_par
; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[CANCEL1_ADDR:%.*]], i32* [[CANCEL2_ADDR:%.*]]) #[[ATTR0]] { ; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[CANCEL1_ADDR:%.*]], i32* [[CANCEL2_ADDR:%.*]]) #[[ATTR0]] {
; CHECK1-NEXT: omp.par.entry: ; CHECK1-NEXT: omp.par.entry:
; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; CHECK1: omp.par.region: ; CHECK1: omp.par.region:
; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK1: omp.par.merged: ; CHECK1: omp.par.merged:
; CHECK1-NEXT: call void @.omp_outlined..18(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..18(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1_ADDR]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK1-NEXT: call void @.omp_outlined..19(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL2_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..19(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL2_ADDR]])
; CHECK1-NEXT: br label [[ENTRY_SPLIT:%.*]] ; CHECK1-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK1: entry.split: ; CHECK1: entry.split:
; CHECK1-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
; CHECK1: omp.par.region.split: ; CHECK1: omp.par.region.split:
; CHECK1-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]
; CHECK1: omp.par.pre_finalize: ; CHECK1: omp.par.pre_finalize:
; CHECK1-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; ;
; ;
; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..18 ; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..18
; CHECK1-SAME: (i32* noalias nocapture nofree readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1:%.*]]) { ; CHECK1-SAME: (i32* noalias nocapture nofree readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1:%.*]]) {
; CHECK1-NEXT: entry: ; CHECK1-NEXT: entry:
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CANCEL1]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CANCEL1]], align 4
; CHECK1-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0 ; CHECK1-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0
; CHECK1-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END:%.*]], label [[IF_THEN:%.*]] ; CHECK1-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[CANCEL1_RELOADED:%.*]], i32* [[CANCEL1_ADDR:%.*]], i32* [[CANCEL2_ADDR:%.*]]) #[[ATTR0]] { ; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[CANCEL1_RELOADED:%.*]], i32* [[CANCEL1_ADDR:%.*]], i32* [[CANCEL2_ADDR:%.*]]) #[[ATTR0]] {
; CHECK1-NEXT: omp.par.entry: ; CHECK1-NEXT: omp.par.entry:
; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CANCEL1_RELOADED]], align 4 ; CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CANCEL1_RELOADED]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; CHECK1: omp.par.region: ; CHECK1: omp.par.region:
; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK1: omp.par.merged: ; CHECK1: omp.par.merged:
; CHECK1-NEXT: call void @.omp_outlined..20(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..20(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1_ADDR]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
Show All 19 Lines
; CHECK1-NEXT: [[LNOT_EXT:%.*]] = zext i1 [[TOBOOL_NOT]] to i32 ; CHECK1-NEXT: [[LNOT_EXT:%.*]] = zext i1 [[TOBOOL_NOT]] to i32
; CHECK1-NEXT: store i32 [[LNOT_EXT]], i32* [[CANCEL2_ADDR]], align 4 ; CHECK1-NEXT: store i32 [[LNOT_EXT]], i32* [[CANCEL2_ADDR]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK1: omp.par.merged.split: ; CHECK1: omp.par.merged.split:
; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK1: omp_region.body.split: ; CHECK1: omp_region.body.split:
; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK1-NEXT: br label [[OMP_REGION_END]] ; CHECK1-NEXT: br label [[OMP_REGION_END]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; ;
; ;
; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..20 ; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..20
; CHECK1-SAME: (i32* noalias nocapture nofree readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1:%.*]]) { ; CHECK1-SAME: (i32* noalias nocapture nofree readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1:%.*]]) {
; CHECK1-NEXT: entry: ; CHECK1-NEXT: entry:
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CANCEL1]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CANCEL1]], align 4
; CHECK1-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0 ; CHECK1-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0
; CHECK1-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END:%.*]], label [[IF_THEN:%.*]] ; CHECK1-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
Show All 40 Lines
; CHECK1-LABEL: define {{[^@]+}}@merge_3..omp_par ; CHECK1-LABEL: define {{[^@]+}}@merge_3..omp_par
; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] { ; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] {
; CHECK1-NEXT: omp.par.entry: ; CHECK1-NEXT: omp.par.entry:
; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; CHECK1: omp.par.region: ; CHECK1: omp.par.region:
; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK1: omp.par.merged: ; CHECK1: omp.par.merged:
; CHECK1-NEXT: call void @.omp_outlined..22(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..22(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK1-NEXT: call void @.omp_outlined..23(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..23(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM1]]) ; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
; CHECK1-NEXT: call void @.omp_outlined..24(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..24(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK1-NEXT: br label [[ENTRY_SPLIT:%.*]] ; CHECK1-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK1: entry.split: ; CHECK1: entry.split:
; CHECK1-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
; CHECK1: omp.par.region.split: ; CHECK1: omp.par.region.split:
; CHECK1-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]
; CHECK1: omp.par.pre_finalize: ; CHECK1: omp.par.pre_finalize:
; CHECK1-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; ;
; ;
; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..22 ; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..22
; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK1-NEXT: entry: ; CHECK1-NEXT: entry:
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK1-NEXT: call void @use(i32 [[TMP0]]) ; CHECK1-NEXT: call void @use(i32 [[TMP0]])
; CHECK1-NEXT: ret void ; CHECK1-NEXT: ret void
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_RELOADED:%.*]], i32* [[A_ADDR:%.*]], i32* [[ADD_SEQ_OUTPUT_ALLOC:%.*]], i32* [[ADD1_SEQ_OUTPUT_ALLOC:%.*]]) #[[ATTR0]] { ; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_RELOADED:%.*]], i32* [[A_ADDR:%.*]], i32* [[ADD_SEQ_OUTPUT_ALLOC:%.*]], i32* [[ADD1_SEQ_OUTPUT_ALLOC:%.*]]) #[[ATTR0]] {
; CHECK1-NEXT: omp.par.entry: ; CHECK1-NEXT: omp.par.entry:
; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_RELOADED]], align 4 ; CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_RELOADED]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; CHECK1: omp.par.region: ; CHECK1: omp.par.region:
; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK1: omp.par.merged: ; CHECK1: omp.par.merged:
; CHECK1-NEXT: call void @.omp_outlined..25(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..25(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
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; CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 ; CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
; CHECK1-NEXT: store i32 [[ADD]], i32* [[ADD_SEQ_OUTPUT_ALLOC]], align 4 ; CHECK1-NEXT: store i32 [[ADD]], i32* [[ADD_SEQ_OUTPUT_ALLOC]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK1: omp.par.merged.split: ; CHECK1: omp.par.merged.split:
; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK1: omp_region.body.split: ; CHECK1: omp_region.body.split:
; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK1-NEXT: br label [[OMP_REGION_END]] ; CHECK1-NEXT: br label [[OMP_REGION_END]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; ;
; ;
; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..25 ; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..25
; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK1-NEXT: entry: ; CHECK1-NEXT: entry:
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK1-NEXT: call void @use(i32 [[TMP0]]) ; CHECK1-NEXT: call void @use(i32 [[TMP0]])
; CHECK1-NEXT: ret void ; CHECK1-NEXT: ret void
▲ Show 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
; CHECK1-LABEL: define {{[^@]+}}@merge_2_unmergable_1..omp_par ; CHECK1-LABEL: define {{[^@]+}}@merge_2_unmergable_1..omp_par
; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] { ; CHECK1-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] {
; CHECK1-NEXT: omp.par.entry: ; CHECK1-NEXT: omp.par.entry:
; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK1-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK1-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; CHECK1: omp.par.region: ; CHECK1: omp.par.region:
; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK1: omp.par.merged: ; CHECK1: omp.par.merged:
; CHECK1-NEXT: call void @.omp_outlined..37(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..37(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK1-NEXT: call void @.omp_outlined..38(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK1-NEXT: call void @.omp_outlined..38(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK1-NEXT: br label [[ENTRY_SPLIT:%.*]] ; CHECK1-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK1: entry.split: ; CHECK1: entry.split:
; CHECK1-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
; CHECK1: omp.par.region.split: ; CHECK1: omp.par.region.split:
; CHECK1-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]
; CHECK1: omp.par.pre_finalize: ; CHECK1: omp.par.pre_finalize:
; CHECK1-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] ; CHECK1-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]
; CHECK1: omp.par.outlined.exit.exitStub:
; CHECK1-NEXT: ret void
; ;
; ;
; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..37 ; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..37
; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK1-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK1-NEXT: entry: ; CHECK1-NEXT: entry:
; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK1-NEXT: call void @use(i32 [[TMP0]]) ; CHECK1-NEXT: call void @use(i32 [[TMP0]])
; CHECK1-NEXT: ret void ; CHECK1-NEXT: ret void
Show All 36 Lines
; CHECK2-LABEL: define {{[^@]+}}@merge..omp_par ; CHECK2-LABEL: define {{[^@]+}}@merge..omp_par
; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK2-NEXT: omp.par.entry: ; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; CHECK2: omp.par.region: ; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged: ; CHECK2: omp.par.merged:
; CHECK2-NEXT: call void @.omp_outlined.(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined.(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: call void @.omp_outlined..1(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..1(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]] ; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split: ; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
; CHECK2: omp.par.region.split: ; CHECK2: omp.par.region.split:
; CHECK2-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]
; CHECK2: omp.par.pre_finalize: ; CHECK2: omp.par.pre_finalize:
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; ;
; ;
; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. ; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK2-NEXT: entry: ; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK2-NEXT: call void @use(i32 [[TMP0]]) ; CHECK2-NEXT: call void @use(i32 [[TMP0]])
; CHECK2-NEXT: ret void ; CHECK2-NEXT: ret void
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
; CHECK2-LABEL: define {{[^@]+}}@merge_seq..omp_par ; CHECK2-LABEL: define {{[^@]+}}@merge_seq..omp_par
; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] { ; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry: ; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; CHECK2: omp.par.region: ; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged: ; CHECK2: omp.par.merged:
; CHECK2-NEXT: call void @.omp_outlined..8(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..8(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
Show All 19 Lines
; CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 ; CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
; CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 ; CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK2: omp.par.merged.split: ; CHECK2: omp.par.merged.split:
; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK2: omp_region.body.split: ; CHECK2: omp_region.body.split:
; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: br label [[OMP_REGION_END]] ; CHECK2-NEXT: br label [[OMP_REGION_END]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; ;
; ;
; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 ; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8
; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK2-NEXT: entry: ; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK2-NEXT: call void @use(i32 [[TMP0]]) ; CHECK2-NEXT: call void @use(i32 [[TMP0]])
; CHECK2-NEXT: ret void ; CHECK2-NEXT: ret void
Show All 31 Lines
; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], float* [[F_RELOADED:%.*]], float* [[F_ADDR:%.*]], float* [[P:%.*]]) #[[ATTR0]] { ; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], float* [[F_RELOADED:%.*]], float* [[F_ADDR:%.*]], float* [[P:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry: ; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F_RELOADED]], align 4 ; CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F_RELOADED]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; CHECK2: omp.par.region: ; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged: ; CHECK2: omp.par.merged:
; CHECK2-NEXT: call void @.omp_outlined..10(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], float* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[F_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..10(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], float* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[F_ADDR]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
Show All 18 Lines
; CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], 0x40091EB860000000 ; CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], 0x40091EB860000000
; CHECK2-NEXT: store float [[ADD]], float* [[P]], align 4 ; CHECK2-NEXT: store float [[ADD]], float* [[P]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK2: omp.par.merged.split: ; CHECK2: omp.par.merged.split:
; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK2: omp_region.body.split: ; CHECK2: omp_region.body.split:
; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: br label [[OMP_REGION_END]] ; CHECK2-NEXT: br label [[OMP_REGION_END]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; ;
; ;
; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 ; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10
; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], float* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[F:%.*]]) { ; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], float* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[F:%.*]]) {
; CHECK2-NEXT: entry: ; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[F]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[F]], align 4
; CHECK2-NEXT: [[CONV:%.*]] = fptosi float [[TMP0]] to i32 ; CHECK2-NEXT: [[CONV:%.*]] = fptosi float [[TMP0]] to i32
; CHECK2-NEXT: call void @use(i32 [[CONV]]) ; CHECK2-NEXT: call void @use(i32 [[CONV]])
Show All 33 Lines
; CHECK2-LABEL: define {{[^@]+}}@merge_seq_firstprivate..omp_par ; CHECK2-LABEL: define {{[^@]+}}@merge_seq_firstprivate..omp_par
; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]], i64* [[A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC:%.*]]) #[[ATTR0]] { ; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]], i64* [[A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry: ; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; CHECK2: omp.par.region: ; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged: ; CHECK2: omp.par.merged:
; CHECK2-NEXT: call void @.omp_outlined..12(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..12(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
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; CHECK2-NEXT: [[A_CASTED_SROA_0_0_INSERT_EXT:%.*]] = zext i32 [[ADD]] to i64 ; CHECK2-NEXT: [[A_CASTED_SROA_0_0_INSERT_EXT:%.*]] = zext i32 [[ADD]] to i64
; CHECK2-NEXT: store i64 [[A_CASTED_SROA_0_0_INSERT_EXT]], i64* [[A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC]], align 8 ; CHECK2-NEXT: store i64 [[A_CASTED_SROA_0_0_INSERT_EXT]], i64* [[A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC]], align 8
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK2: omp.par.merged.split: ; CHECK2: omp.par.merged.split:
; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK2: omp_region.body.split: ; CHECK2: omp_region.body.split:
; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: br label [[OMP_REGION_END]] ; CHECK2-NEXT: br label [[OMP_REGION_END]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; ;
; ;
; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12 ; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12
; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK2-NEXT: entry: ; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK2-NEXT: call void @use(i32 [[TMP0]]) ; CHECK2-NEXT: call void @use(i32 [[TMP0]])
; CHECK2-NEXT: ret void ; CHECK2-NEXT: ret void
Show All 29 Lines
; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] { ; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry: ; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 ; CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; CHECK2: omp.par.region: ; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged: ; CHECK2: omp.par.merged:
; CHECK2-NEXT: call void @.omp_outlined..14(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..14(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
Show All 22 Lines
; CHECK2-NEXT: store i32 [[TMP5]], i32* [[B]], align 4 ; CHECK2-NEXT: store i32 [[TMP5]], i32* [[B]], align 4
; CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 4, i8* noundef nonnull [[TMP3]]) ; CHECK2-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 4, i8* noundef nonnull [[TMP3]])
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK2: omp.par.merged.split: ; CHECK2: omp.par.merged.split:
; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK2: omp_region.body.split: ; CHECK2: omp_region.body.split:
; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: br label [[OMP_REGION_END]] ; CHECK2-NEXT: br label [[OMP_REGION_END]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; ;
; ;
; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 ; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14
; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK2-NEXT: entry: ; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK2-NEXT: call void @use(i32 [[TMP0]]) ; CHECK2-NEXT: call void @use(i32 [[TMP0]])
; CHECK2-NEXT: ret void ; CHECK2-NEXT: ret void
Show All 36 Lines
; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_RELOADED:%.*]], i32* [[A_ADDR:%.*]], i32* [[B:%.*]]) #[[ATTR0]] { ; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_RELOADED:%.*]], i32* [[A_ADDR:%.*]], i32* [[B:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry: ; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_RELOADED]], align 4 ; CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_RELOADED]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; CHECK2: omp.par.region: ; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged: ; CHECK2: omp.par.merged:
; CHECK2-NEXT: call void @.omp_outlined..16(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..16(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
Show All 19 Lines
; CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 ; CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
; CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4 ; CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK2: omp.par.merged.split: ; CHECK2: omp.par.merged.split:
; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK2: omp_region.body.split: ; CHECK2: omp_region.body.split:
; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: br label [[OMP_REGION_END]] ; CHECK2-NEXT: br label [[OMP_REGION_END]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; ;
; ;
; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16 ; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16
; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK2-NEXT: entry: ; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK2-NEXT: call void @use(i32 [[TMP0]]) ; CHECK2-NEXT: call void @use(i32 [[TMP0]])
; CHECK2-NEXT: ret void ; CHECK2-NEXT: ret void
Show All 32 Lines
; CHECK2-LABEL: define {{[^@]+}}@merge_cancellable_regions..omp_par ; CHECK2-LABEL: define {{[^@]+}}@merge_cancellable_regions..omp_par
; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[CANCEL1_ADDR:%.*]], i32* [[CANCEL2_ADDR:%.*]]) #[[ATTR0]] { ; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[CANCEL1_ADDR:%.*]], i32* [[CANCEL2_ADDR:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry: ; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; CHECK2: omp.par.region: ; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged: ; CHECK2: omp.par.merged:
; CHECK2-NEXT: call void @.omp_outlined..18(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..18(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1_ADDR]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: call void @.omp_outlined..19(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL2_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..19(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL2_ADDR]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]] ; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split: ; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
; CHECK2: omp.par.region.split: ; CHECK2: omp.par.region.split:
; CHECK2-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]
; CHECK2: omp.par.pre_finalize: ; CHECK2: omp.par.pre_finalize:
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; ;
; ;
; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..18 ; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..18
; CHECK2-SAME: (i32* noalias nocapture nofree readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1:%.*]]) { ; CHECK2-SAME: (i32* noalias nocapture nofree readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1:%.*]]) {
; CHECK2-NEXT: entry: ; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CANCEL1]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CANCEL1]], align 4
; CHECK2-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0 ; CHECK2-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0
; CHECK2-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END:%.*]], label [[IF_THEN:%.*]] ; CHECK2-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[CANCEL1_RELOADED:%.*]], i32* [[CANCEL1_ADDR:%.*]], i32* [[CANCEL2_ADDR:%.*]]) #[[ATTR0]] { ; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[CANCEL1_RELOADED:%.*]], i32* [[CANCEL1_ADDR:%.*]], i32* [[CANCEL2_ADDR:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry: ; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CANCEL1_RELOADED]], align 4 ; CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CANCEL1_RELOADED]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; CHECK2: omp.par.region: ; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged: ; CHECK2: omp.par.merged:
; CHECK2-NEXT: call void @.omp_outlined..20(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..20(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1_ADDR]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
Show All 19 Lines
; CHECK2-NEXT: [[LNOT_EXT:%.*]] = zext i1 [[TOBOOL_NOT]] to i32 ; CHECK2-NEXT: [[LNOT_EXT:%.*]] = zext i1 [[TOBOOL_NOT]] to i32
; CHECK2-NEXT: store i32 [[LNOT_EXT]], i32* [[CANCEL2_ADDR]], align 4 ; CHECK2-NEXT: store i32 [[LNOT_EXT]], i32* [[CANCEL2_ADDR]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK2: omp.par.merged.split: ; CHECK2: omp.par.merged.split:
; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK2: omp_region.body.split: ; CHECK2: omp_region.body.split:
; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: br label [[OMP_REGION_END]] ; CHECK2-NEXT: br label [[OMP_REGION_END]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; ;
; ;
; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..20 ; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..20
; CHECK2-SAME: (i32* noalias nocapture nofree readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1:%.*]]) { ; CHECK2-SAME: (i32* noalias nocapture nofree readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[CANCEL1:%.*]]) {
; CHECK2-NEXT: entry: ; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CANCEL1]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CANCEL1]], align 4
; CHECK2-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0 ; CHECK2-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0
; CHECK2-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END:%.*]], label [[IF_THEN:%.*]] ; CHECK2-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
Show All 40 Lines
; CHECK2-LABEL: define {{[^@]+}}@merge_3..omp_par ; CHECK2-LABEL: define {{[^@]+}}@merge_3..omp_par
; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] { ; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry: ; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; CHECK2: omp.par.region: ; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged: ; CHECK2: omp.par.merged:
; CHECK2-NEXT: call void @.omp_outlined..22(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..22(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: call void @.omp_outlined..23(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..23(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM1]]) ; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
; CHECK2-NEXT: call void @.omp_outlined..24(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..24(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]] ; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split: ; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
; CHECK2: omp.par.region.split: ; CHECK2: omp.par.region.split:
; CHECK2-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]
; CHECK2: omp.par.pre_finalize: ; CHECK2: omp.par.pre_finalize:
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; ;
; ;
; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..22 ; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..22
; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK2-NEXT: entry: ; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK2-NEXT: call void @use(i32 [[TMP0]]) ; CHECK2-NEXT: call void @use(i32 [[TMP0]])
; CHECK2-NEXT: ret void ; CHECK2-NEXT: ret void
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_RELOADED:%.*]], i32* [[A_ADDR:%.*]], i32* [[ADD_SEQ_OUTPUT_ALLOC:%.*]], i32* [[ADD1_SEQ_OUTPUT_ALLOC:%.*]]) #[[ATTR0]] { ; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_RELOADED:%.*]], i32* [[A_ADDR:%.*]], i32* [[ADD_SEQ_OUTPUT_ALLOC:%.*]], i32* [[ADD1_SEQ_OUTPUT_ALLOC:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry: ; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_RELOADED]], align 4 ; CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_RELOADED]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; CHECK2: omp.par.region: ; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged: ; CHECK2: omp.par.merged:
; CHECK2-NEXT: call void @.omp_outlined..25(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..25(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]]) ; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 ; CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
; CHECK2-NEXT: store i32 [[ADD]], i32* [[ADD_SEQ_OUTPUT_ALLOC]], align 4 ; CHECK2-NEXT: store i32 [[ADD]], i32* [[ADD_SEQ_OUTPUT_ALLOC]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK2: omp.par.merged.split: ; CHECK2: omp.par.merged.split:
; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
; CHECK2: omp_region.body.split: ; CHECK2: omp_region.body.split:
; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: call void @__kmpc_end_master(%struct.ident_t* @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: br label [[OMP_REGION_END]] ; CHECK2-NEXT: br label [[OMP_REGION_END]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; ;
; ;
; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..25 ; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..25
; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK2-NEXT: entry: ; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK2-NEXT: call void @use(i32 [[TMP0]]) ; CHECK2-NEXT: call void @use(i32 [[TMP0]])
; CHECK2-NEXT: ret void ; CHECK2-NEXT: ret void
▲ Show 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
; CHECK2-LABEL: define {{[^@]+}}@merge_2_unmergable_1..omp_par ; CHECK2-LABEL: define {{[^@]+}}@merge_2_unmergable_1..omp_par
; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] { ; CHECK2-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[A_ADDR:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry: ; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 ; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: store i32 [[TMP0]], i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 ; CHECK2-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; CHECK2: omp.par.region: ; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged: ; CHECK2: omp.par.merged:
; CHECK2-NEXT: call void @.omp_outlined..37(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..37(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) ; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]]) ; CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: call void @.omp_outlined..38(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]]) ; CHECK2-NEXT: call void @.omp_outlined..38(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]] ; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split: ; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
; CHECK2: omp.par.region.split: ; CHECK2: omp.par.region.split:
; CHECK2-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]
; CHECK2: omp.par.pre_finalize: ; CHECK2: omp.par.pre_finalize:
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] ; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]
; CHECK2: omp.par.outlined.exit.exitStub:
; CHECK2-NEXT: ret void
; ;
; ;
; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..37 ; CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..37
; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) { ; CHECK2-SAME: (i32* noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A:%.*]]) {
; CHECK2-NEXT: entry: ; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 ; CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
; CHECK2-NEXT: call void @use(i32 [[TMP0]]) ; CHECK2-NEXT: call void @use(i32 [[TMP0]])
; CHECK2-NEXT: ret void ; CHECK2-NEXT: ret void
Show All 17 Lines

llvm/test/tools/llvm-extract/extract-blocks-with-groups.ll

; RUN: llvm-extract -bb 'foo:if;then;else' -bb 'bar:bb14;bb20' -S %s | FileCheck %s ; RUN: llvm-extract -bb 'foo:if;then;else' -bb 'bar:bb14;bb20' -S %s | FileCheck %s
; Extract two groups of basic blocks in two different functions. ; Extract two groups of basic blocks in two different functions.
; The first extracted function is the region composed by the ; The first extracted function is the region composed by the
; blocks if, then, and else from foo. ; blocks if, then, and else from foo.
; CHECK: define dso_local void @foo.if.split(i32 %arg1, i32 %arg, i32* %tmp.0.ce.out) { ; CHECK: define dso_local void @foo.if.split(i32 %arg1, i32 %arg, i32* %tmp.0.ce.out) {
; CHECK: newFuncRoot: ; CHECK: newFuncRoot:
; CHECK: br label %if.split ; CHECK: br label %if.split
; ;
; CHECK: end.exitStub: ; preds = %end.split
; CHECK: ret void
;
; CHECK: then: ; preds = %if.split ; CHECK: then: ; preds = %if.split
; CHECK: %tmp12 = shl i32 %arg1, 2 ; CHECK: %tmp12 = shl i32 %arg1, 2
; CHECK: %tmp13 = add nsw i32 %tmp12, %arg ; CHECK: %tmp13 = add nsw i32 %tmp12, %arg
; CHECK: br label %end.split ; CHECK: br label %end.split
; ;
; CHECK: else: ; preds = %if.split ; CHECK: else: ; preds = %if.split
; CHECK: %tmp22 = mul nsw i32 %arg, 3 ; CHECK: %tmp22 = mul nsw i32 %arg, 3
; CHECK: %tmp24 = sdiv i32 %arg1, 6 ; CHECK: %tmp24 = sdiv i32 %arg1, 6
; CHECK: %tmp25 = add nsw i32 %tmp24, %tmp22 ; CHECK: %tmp25 = add nsw i32 %tmp24, %tmp22
; CHECK: br label %end.split ; CHECK: br label %end.split
; ;
; CHECK: if.split: ; preds = %newFuncRoot ; CHECK: if.split: ; preds = %newFuncRoot
; CHECK: %tmp5 = icmp sgt i32 %arg, 0 ; CHECK: %tmp5 = icmp sgt i32 %arg, 0
; CHECK: %tmp8 = icmp sgt i32 %arg1, 0 ; CHECK: %tmp8 = icmp sgt i32 %arg1, 0
; CHECK: %or.cond = and i1 %tmp5, %tmp8 ; CHECK: %or.cond = and i1 %tmp5, %tmp8
; CHECK: br i1 %or.cond, label %then, label %else ; CHECK: br i1 %or.cond, label %then, label %else
; ;
; CHECK: end.split: ; preds = %then, %else ; CHECK: end.split: ; preds = %then, %else
; CHECK: %tmp.0.ce = phi i32 [ %tmp13, %then ], [ %tmp25, %else ] ; CHECK: %tmp.0.ce = phi i32 [ %tmp13, %then ], [ %tmp25, %else ]
; CHECK: store i32 %tmp.0.ce, i32* %tmp.0.ce.out ; CHECK: store i32 %tmp.0.ce, i32* %tmp.0.ce.out
; CHECK: br label %end.exitStub ; CHECK: br label %end.exitStub
;
; CHECK: end.exitStub: ; preds = %end.split
; CHECK: ret void
; CHECK: } ; CHECK: }
; The second extracted function is the region composed by the blocks ; The second extracted function is the region composed by the blocks
; bb14 and bb20 from bar. ; bb14 and bb20 from bar.
; CHECK: define dso_local i1 @bar.bb14(i32 %arg1, i32 %arg, i32* %tmp25.out) { ; CHECK: define dso_local i1 @bar.bb14(i32 %arg1, i32 %arg, i32* %tmp25.out) {
; CHECK: newFuncRoot: ; CHECK: newFuncRoot:
; CHECK: br label %bb14 ; CHECK: br label %bb14
; ;
; CHECK: bb26.exitStub: ; preds = %bb14
; CHECK: ret i1 true
;
; CHECK: bb30.exitStub: ; preds = %bb20
; CHECK: ret i1 false
;
; CHECK: bb14: ; preds = %newFuncRoot ; CHECK: bb14: ; preds = %newFuncRoot
; CHECK: %tmp0 = and i32 %arg1, %arg ; CHECK: %tmp0 = and i32 %arg1, %arg
; CHECK: %tmp1 = icmp slt i32 %tmp0, 0 ; CHECK: %tmp1 = icmp slt i32 %tmp0, 0
; CHECK: br i1 %tmp1, label %bb20, label %bb26.exitStub ; CHECK: br i1 %tmp1, label %bb20, label %bb26.exitStub
; ;
; CHECK: bb20: ; preds = %bb14 ; CHECK: bb20: ; preds = %bb14
; CHECK: %tmp22 = mul nsw i32 %arg, 3 ; CHECK: %tmp22 = mul nsw i32 %arg, 3
; CHECK: %tmp24 = sdiv i32 %arg1, 6 ; CHECK: %tmp24 = sdiv i32 %arg1, 6
; CHECK: %tmp25 = add nsw i32 %tmp24, %tmp22 ; CHECK: %tmp25 = add nsw i32 %tmp24, %tmp22
; CHECK: store i32 %tmp25, i32* %tmp25.out ; CHECK: store i32 %tmp25, i32* %tmp25.out
; CHECK: br label %bb30.exitStub ; CHECK: br label %bb30.exitStub
;
; CHECK: bb26.exitStub: ; preds = %bb14
; CHECK: ret i1 true
;
; CHECK: bb30.exitStub: ; preds = %bb20
; CHECK: ret i1 false
; CHECK: } ; CHECK: }
define i32 @foo(i32 %arg, i32 %arg1) { define i32 @foo(i32 %arg, i32 %arg1) {
if: if:
%tmp5 = icmp sgt i32 %arg, 0 %tmp5 = icmp sgt i32 %arg, 0
%tmp8 = icmp sgt i32 %arg1, 0 %tmp8 = icmp sgt i32 %arg1, 0
%or.cond = and i1 %tmp5, %tmp8 %or.cond = and i1 %tmp5, %tmp8
br i1 %or.cond, label %then, label %else br i1 %or.cond, label %then, label %else
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