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Show First 20 Lines • Show All 1,713 Lines • ▼ Show 20 Lines	.. table:: AMDGPU DWARF Register Mapping
96-127 Reserved *Reserved for frequently accessed		96-127 Reserved *Reserved for frequently accessed
registers using DWARF 1-byte ULEB.*		registers using DWARF 1-byte ULEB.*
128 STATUS 32 Status Register.		128 STATUS 32 Status Register.
129-511 Reserved *Reserved for future Scalar		129-511 Reserved *Reserved for future Scalar
Architectural Registers.*		Architectural Registers.*
512 VCC_32 32 Vector Condition Code Register		512 VCC_32 32 Vector Condition Code Register
when executing in wavefront 32		when executing in wavefront 32
mode.		mode.
513-1023 Reserved *Reserved for future Vector		513-767 Reserved *Reserved for future Vector
Architectural Registers when		Architectural Registers when
executing in wavefront 32 mode.*		executing in wavefront 32 mode.*
768 VCC_64 64 Vector Condition Code Register		768 VCC_64 64 Vector Condition Code Register
when executing in wavefront 64		when executing in wavefront 64
mode.		mode.
769-1023 Reserved *Reserved for future Vector		769-1023 Reserved *Reserved for future Vector
Architectural Registers when		Architectural Registers when
executing in wavefront 64 mode.*		executing in wavefront 64 mode.*
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[docs, AMDGPU] Fix typo in dwarf register number mappingClosedPublic