[AArch64][GlobalISel] Add regbankselect support for G_LROUND

[paquette]

Summary

Destination is always a GPR, since the result is always an integer.

Source is always a FPR, since the source is always floating point.

[jroelofs]

LGTM

llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

 bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
                                          const MachineRegisterInfo &MRI,
                                          const TargetRegisterInfo &TRI,
                                          unsigned Depth) const {
   switch (MI.getOpcode()) {
   case TargetOpcode::G_FPTOSI:
   case TargetOpcode::G_FPTOUI:
   case TargetOpcode::G_FCMP:
+  case TargetOpcode::G_LROUND:
     return true;
   default:
     break;
   }
   return hasFPConstraints(MI, MRI, TRI, Depth);
 }
 
 bool AArch64RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
if (!isFPIntrinsic(ID))
       break;
     for (const auto &Op : MI.explicit_operands()) {
       if (Op.isReg())
         OpRegBankIdx[Idx] = PMI_FirstFPR;
       ++Idx;
     }
     break;
   }
+  case TargetOpcode::G_LROUND: {
+    // Source is always floating point and destination is always integer.
+    OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
+    break;
+  }
   }
 
   // Finally construct the computed mapping.
   SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
   for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
     if (MI.getOperand(Idx).isReg() && MI.getOperand(Idx).getReg()) {
       auto Mapping = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
       if (!Mapping->isValid())

llvm/test/CodeGen/AArch64/GlobalISel/regbank-lround.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name:            no_cross_bank_copies_needed
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: no_cross_bank_copies_needed
+    ; CHECK: liveins: $d0
+    ; CHECK: %fpr:fpr(s64) = COPY $d0
+    ; CHECK: %lround:gpr(s32) = G_LROUND %fpr(s64)
+    ; CHECK: $s0 = COPY %lround(s32)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %fpr:_(s64) = COPY $d0
+    %lround:_(s32) = G_LROUND %fpr
+    $s0 = COPY %lround:_(s32)
+    RET_ReallyLR implicit $s0
+...
+---
+name:            source_needs_copy
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: source_needs_copy
+    ; CHECK: liveins: $x0
+    ; CHECK: %gpr:gpr(s64) = COPY $x0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
+    ; CHECK: %lround:gpr(s32) = G_LROUND [[COPY]](s64)
+    ; CHECK: $s0 = COPY %lround(s32)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %gpr:_(s64) = COPY $x0
+    %lround:_(s32) = G_LROUND %gpr
+    $s0 = COPY %lround:_(s32)
+    RET_ReallyLR implicit $s0
+...
+---
+name:            load_gets_fpr
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: load_gets_fpr
+    ; CHECK: liveins: $x0
+    ; CHECK: %ptr:gpr(p0) = COPY $x0
+    ; CHECK: %load:fpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
+    ; CHECK: %lround:gpr(s32) = G_LROUND %load(s32)
+    ; CHECK: $s0 = COPY %lround(s32)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %ptr:_(p0) = COPY $x0
+    %load:_(s32) = G_LOAD %ptr(p0) :: (load (s32))
+    %lround:_(s32) = G_LROUND %load
+    $s0 = COPY %lround:_(s32)
+    RET_ReallyLR implicit $s0
+
+...