[GlobalISel] Add IRTranslator support for @llvm.lround.* -> G_LROUND

[paquette]

Summary

Translate the @llvm.lround.* family to G_LROUND via IRTranslator::translateSimpleIntrinsic.

[jroelofs]

LGTM

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

switch (ID) {
     case Intrinsic::vector_reduce_smax:
       return TargetOpcode::G_VECREDUCE_SMAX;
     case Intrinsic::vector_reduce_smin:
       return TargetOpcode::G_VECREDUCE_SMIN;
     case Intrinsic::vector_reduce_umax:
       return TargetOpcode::G_VECREDUCE_UMAX;
     case Intrinsic::vector_reduce_umin:
       return TargetOpcode::G_VECREDUCE_UMIN;
+    case Intrinsic::lround:
+      return TargetOpcode::G_LROUND;
   }
   return Intrinsic::not_intrinsic;
 }
 
 bool IRTranslator::translateSimpleIntrinsic(const CallInst &CI,
                                             Intrinsic::ID ID,
                                             MachineIRBuilder &MIRBuilder) {
 

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

define {i8, i32} @test_freeze_struct({ i8, i32 }* %addr) {
   ; CHECK-NEXT: $w1 = COPY [[FREEZE1]]
   ; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
   %load = load { i8, i32 }, { i8, i32 }* %addr
   %res = freeze {i8, i32} %load
   ret {i8, i32} %res
 }
 
 !0 = !{ i64 0, i64 2 }
+
+declare i64 @llvm.lround.i64.f32(float) nounwind readnone
+define i64 @lround(float %x) {
+  ; CHECK-LABEL: name: lround
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   liveins: $s0
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+  ; CHECK:   [[LROUND:%[0-9]+]]:_(s64) = G_LROUND [[COPY]](s32)
+  ; CHECK:   $x0 = COPY [[LROUND]](s64)
+  ; CHECK:   RET_ReallyLR implicit $x0
+  %lround = tail call i64 @llvm.lround.i64.f32(float %x)
+  ret i64 %lround
+}