[WebAssembly] More convert_low and promote_low codegen

[tlively]

Summary

The convert_low and promote_low instructions can widen the lower two lanes of a
four-lane vector, but we were previously scalarizing patterns that widened lanes
besides the low two lanes. The commit adds a shuffle to move the widened lanes
into the low lane positions so the convert_low and promote_low instructions can
be used instead of scalarizing.

Depends on D108266.

[GMNGeoffrey]

I'm seeing narrowing diagnostic failures from this:

llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp:1840:33: error: non-constant-expression cannot be narrowed from type 'unsigned int' to 'int' in initializer list [-Wc++11-narrowing]
                               {LHSIndex, RHSIndex + 4, -1, -1});
                                ^~~~~~~~
llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp:1840:33: note: insert an explicit cast to silence this issue
                               {LHSIndex, RHSIndex + 4, -1, -1});
                                ^~~~~~~~
                                static_cast<int>( )
llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp:1840:43: error: non-constant-expression cannot be narrowed from type 'unsigned int' to 'int' in initializer list [-Wc++11-narrowing]
                               {LHSIndex, RHSIndex + 4, -1, -1});
                                          ^~~~~~~~~~~~
llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp:1840:43: note: insert an explicit cast to silence this issue
                               {LHSIndex, RHSIndex + 4, -1, -1});
                                          ^~~~~~~~~~~~
                                          static_cast<int>( )

Could you please look into a fix?

[tlively]

Yes, sorry about that. I'll fix that momentarily.

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

WebAssemblyTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
   SDValue NewExtract = DAG.getNode(
       ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(),
       DAG.getBitcast(ExtractedVecT, Extract.getOperand(0)), NewIndex);
   return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), NewExtract,
                      Op.getOperand(1));
 }
 
 static SDValue LowerConvertLow(SDValue Op, SelectionDAG &DAG) {
+  SDLoc DL(Op);
   if (Op.getValueType() != MVT::v2f64)
     return SDValue();
 
   auto GetConvertedLane = [](SDValue Op, unsigned &Opcode, SDValue &SrcVec,
                              unsigned &Index) -> bool {
     switch (Op.getOpcode()) {
     case ISD::SINT_TO_FP:
       Opcode = WebAssemblyISD::CONVERT_LOW_S;
static SDValue LowerConvertLow(SDValue Op, SelectionDAG &DAG) {
   };
 
   unsigned LHSOpcode, RHSOpcode, LHSIndex, RHSIndex;
   SDValue LHSSrcVec, RHSSrcVec;
   if (!GetConvertedLane(Op.getOperand(0), LHSOpcode, LHSSrcVec, LHSIndex) ||
       !GetConvertedLane(Op.getOperand(1), RHSOpcode, RHSSrcVec, RHSIndex))
     return SDValue();
 
-  if (LHSOpcode != RHSOpcode || LHSSrcVec != RHSSrcVec)
-    return SDValue();
-
-  if (LHSIndex != 0 || RHSIndex != 1)
+  if (LHSOpcode != RHSOpcode)
     return SDValue();
 
   MVT ExpectedSrcVT;
   switch (LHSOpcode) {
   case WebAssemblyISD::CONVERT_LOW_S:
   case WebAssemblyISD::CONVERT_LOW_U:
     ExpectedSrcVT = MVT::v4i32;
     break;
   case WebAssemblyISD::PROMOTE_LOW:
     ExpectedSrcVT = MVT::v4f32;
     break;
   }
   if (LHSSrcVec.getValueType() != ExpectedSrcVT)
     return SDValue();
 
-  return DAG.getNode(LHSOpcode, SDLoc(Op), MVT::v2f64, LHSSrcVec);
+  auto Src = LHSSrcVec;
+  if (LHSIndex != 0 || RHSIndex != 1 || LHSSrcVec != RHSSrcVec) {
+    // Shuffle the source vector so that the converted lanes are the low lanes.
+    Src = DAG.getVectorShuffle(ExpectedSrcVT, DL, LHSSrcVec, RHSSrcVec,
+                               {LHSIndex, RHSIndex + 4, -1, -1});
+  }
+  return DAG.getNode(LHSOpcode, DL, MVT::v2f64, Src);
 }
 
 SDValue WebAssemblyTargetLowering::LowerBUILD_VECTOR(SDValue Op,
                                                      SelectionDAG &DAG) const {
   if (auto ConvertLow = LowerConvertLow(Op, DAG))
     return ConvertLow;
 
   SDLoc DL(Op);

llvm/test/CodeGen/WebAssembly/simd-conversions.ll

 ; CHECK:         .functype convert_low_s_v4f64 (i32, v128, v128) -> ()
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    f64x2.convert_low_i32x4_s
 ; CHECK-NEXT:    v128.store 0
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32x4.extract_lane 2
-; CHECK-NEXT:    f64.convert_i32_s
-; CHECK-NEXT:    f64x2.splat
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32x4.extract_lane 3
-; CHECK-NEXT:    f64.convert_i32_s
-; CHECK-NEXT:    f64x2.replace_lane 1
+; CHECK-NEXT:    i8x16.shuffle 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT:    f64x2.convert_low_i32x4_s
 ; CHECK-NEXT:    v128.store 16
 ; CHECK-NEXT:    # fallthrough-return
   %v = shufflevector <8 x i32> %x, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %a = sitofp <4 x i32> %v to <4 x double>
   ret <4 x double> %a
 }
 
 define <4 x double> @convert_low_u_v4f64(<8 x i32> %x) {
 ; CHECK-LABEL: convert_low_u_v4f64:
 ; CHECK:         .functype convert_low_u_v4f64 (i32, v128, v128) -> ()
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    f64x2.convert_low_i32x4_u
 ; CHECK-NEXT:    v128.store 0
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32x4.extract_lane 2
-; CHECK-NEXT:    f64.convert_i32_u
-; CHECK-NEXT:    f64x2.splat
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32x4.extract_lane 3
-; CHECK-NEXT:    f64.convert_i32_u
-; CHECK-NEXT:    f64x2.replace_lane 1
+; CHECK-NEXT:    i8x16.shuffle 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT:    f64x2.convert_low_i32x4_u
 ; CHECK-NEXT:    v128.store 16
 ; CHECK-NEXT:    # fallthrough-return
   %v = shufflevector <8 x i32> %x, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %a = uitofp <4 x i32> %v to <4 x double>
   ret <4 x double> %a
 }
 
 
 define <4 x double> @convert_low_s_v4f64_2(<8 x i32> %x) {
 ; CHECK-LABEL: convert_low_s_v4f64_2:
 ; CHECK:         .functype convert_low_s_v4f64_2 (i32, v128, v128) -> ()
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    f64x2.convert_low_i32x4_s
 ; CHECK-NEXT:    v128.store 0
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32x4.extract_lane 2
-; CHECK-NEXT:    f64.convert_i32_s
-; CHECK-NEXT:    f64x2.splat
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32x4.extract_lane 3
-; CHECK-NEXT:    f64.convert_i32_s
-; CHECK-NEXT:    f64x2.replace_lane 1
+; CHECK-NEXT:    i8x16.shuffle 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT:    f64x2.convert_low_i32x4_s
 ; CHECK-NEXT:    v128.store 16
 ; CHECK-NEXT:    # fallthrough-return
   %v = sitofp <8 x i32> %x to <8 x double>
   %a = shufflevector <8 x double> %v, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x double> %a
 }
 
 define <4 x double> @convert_low_u_v4f64_2(<8 x i32> %x) {
 ; CHECK-LABEL: convert_low_u_v4f64_2:
 ; CHECK:         .functype convert_low_u_v4f64_2 (i32, v128, v128) -> ()
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    f64x2.convert_low_i32x4_u
 ; CHECK-NEXT:    v128.store 0
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32x4.extract_lane 2
-; CHECK-NEXT:    f64.convert_i32_u
-; CHECK-NEXT:    f64x2.splat
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    i32x4.extract_lane 3
-; CHECK-NEXT:    f64.convert_i32_u
-; CHECK-NEXT:    f64x2.replace_lane 1
+; CHECK-NEXT:    i8x16.shuffle 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT:    f64x2.convert_low_i32x4_u
 ; CHECK-NEXT:    v128.store 16
 ; CHECK-NEXT:    # fallthrough-return
   %v = uitofp <8 x i32> %x to <8 x double>
   %a = shufflevector <8 x double> %v, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x double> %a
 }
 
 define <4 x double> @promote_low_v4f64(<8 x float> %x) {
 ; CHECK-LABEL: promote_low_v4f64:
 ; CHECK:         .functype promote_low_v4f64 (i32, v128, v128) -> ()
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    f64x2.promote_low_f32x4
 ; CHECK-NEXT:    v128.store 0
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    f32x4.extract_lane 2
-; CHECK-NEXT:    f64.promote_f32
-; CHECK-NEXT:    f64x2.splat
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    f32x4.extract_lane 3
-; CHECK-NEXT:    f64.promote_f32
-; CHECK-NEXT:    f64x2.replace_lane 1
+; CHECK-NEXT:    i8x16.shuffle 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT:    f64x2.promote_low_f32x4
 ; CHECK-NEXT:    v128.store 16
 ; CHECK-NEXT:    # fallthrough-return
   %v = shufflevector <8 x float> %x, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %a = fpext <4 x float> %v to <4 x double>
   ret <4 x double> %a
 }
 
 define <4 x double> @promote_low_v4f64_2(<8 x float> %x) {
 ; CHECK-LABEL: promote_low_v4f64_2:
 ; CHECK:         .functype promote_low_v4f64_2 (i32, v128, v128) -> ()
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    local.get 1
 ; CHECK-NEXT:    f64x2.promote_low_f32x4
 ; CHECK-NEXT:    v128.store 0
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    f32x4.extract_lane 2
-; CHECK-NEXT:    f64.promote_f32
-; CHECK-NEXT:    f64x2.splat
 ; CHECK-NEXT:    local.get 1
-; CHECK-NEXT:    f32x4.extract_lane 3
-; CHECK-NEXT:    f64.promote_f32
-; CHECK-NEXT:    f64x2.replace_lane 1
+; CHECK-NEXT:    i8x16.shuffle 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT:    f64x2.promote_low_f32x4
 ; CHECK-NEXT:    v128.store 16
 ; CHECK-NEXT:    # fallthrough-return
   %v = fpext <8 x float> %x to <8 x double>
   %a = shufflevector <8 x double> %v, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x double> %a
 }
+
+define <2 x double> @promote_mixed_v2f64(<4 x float> %x, <4 x float> %y) {
+; CHECK-LABEL: promote_mixed_v2f64:
+; CHECK:         .functype promote_mixed_v2f64 (v128, v128) -> (v128)
+; CHECK-NEXT:  # %bb.0:
+; CHECK-NEXT:    local.get 0
+; CHECK-NEXT:    local.get 1
+; CHECK-NEXT:    i8x16.shuffle 8, 9, 10, 11, 28, 29, 30, 31, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT:    f64x2.promote_low_f32x4
+; CHECK-NEXT:    # fallthrough-return
+  %v = shufflevector <4 x float> %x, <4 x float> %y, <2 x i32> <i32 2, i32 7>
+  %a = fpext <2 x float> %v to <2 x double>
+  ret <2 x double> %a
+}