[X86] [AMX] Fix the test case failure caused by D107544.

[yubing]

Summary

The issue can be duplicated when EXPENSIVE_CHECKS is specified for llvm
build. Thank Simon report this issue at
https://bugs.llvm.org/show_bug.cgi?id=51513. We need return correct
value for the changed IR.

[yubing]

Bring back getRowFromCol

[LuoYuanke]

LGTM, thanks.

[RKSimon]

LGTM - cheers

llvm/lib/Target/X86/X86LowerAMXType.cpp

class X86LowerAMXType {
   std::map<Value *, Value *> Col2Row;
 
 public:
   X86LowerAMXType(Function &F) : Func(F) {}
   bool visit();
   void combineLoadBitcast(LoadInst *LD, BitCastInst *Bitcast);
   void combineBitcastStore(BitCastInst *Bitcast, StoreInst *ST);
   bool transformBitcast(BitCastInst *Bitcast);
-  Value *getRowFromCol(Instruction *II, Value *V, unsigned Granularity);
 };
 
-Value *X86LowerAMXType::getRowFromCol(Instruction *II, Value *V,
-                                      unsigned Granularity) {
-  if (Col2Row.count(V))
-    return Col2Row[V];
-  IRBuilder<> Builder(&*II->getParent()->getFirstInsertionPt());
-  if (auto *I = dyn_cast<Instruction>(V)) {
-    BasicBlock::iterator Iter = I->getIterator();
-    ++Iter;
-    Builder.SetInsertPoint(&*Iter);
-  }
-  ConstantInt *Gran = Builder.getInt16(Granularity);
-  Value *RealRow = Builder.CreateUDiv(V, Gran);
-  Col2Row[V] = RealRow;
-  return RealRow;
-}
-
 // %src = load <256 x i32>, <256 x i32>* %addr, align 64
 // %2 = bitcast <256 x i32> %src to x86_amx
 // -->
 // %2 = call x86_amx @llvm.x86.tileloadd64.internal(i16 %row, i16 %col,
 // i8* %addr, i64 %stride64)
 void X86LowerAMXType::combineLoadBitcast(LoadInst *LD, BitCastInst *Bitcast) {
   Value *Row = nullptr, *Col = nullptr;
   Use &U = *(Bitcast->use_begin());
for (auto *Inst : Insts) {
         Change = true;
       }
     }
   };
 
   Convert(Vec2TileInsts, Intrinsic::x86_cast_tile_to_vector);
   Convert(Tile2VecInsts, Intrinsic::x86_cast_vector_to_tile);
 
-  auto EraseInst = [](SmallVectorImpl<Instruction *> &Insts) {
+  auto EraseInst = [&](SmallVectorImpl<Instruction *> &Insts) {
     for (auto *Inst : Insts) {
-      if (Inst->use_empty())
+      if (Inst->use_empty()) {
         Inst->eraseFromParent();
+        Change = true;
+      }
     }
   };
 
   EraseInst(Vec2TileInsts);
   EraseInst(Tile2VecInsts);
 
   // Handle the A->B->A cast, and there is an intervening PHI node.
   for (BasicBlock &BB : Func) {
     for (Instruction &I : BB) {
       if (isAMXCast(&I)) {
-        if (PHINode *PN = dyn_cast<PHINode>(I.getOperand(0)))
+        if (dyn_cast<PHINode>(I.getOperand(0)))
           PhiCastWorkList.push_back(&I);
       }
     }
   }
   for (auto *I : PhiCastWorkList) {
     // We skip the dead Amxcast.
     if (DeadInst.contains(I))
       continue;

 public:
   static char ID;
 
   X86LowerAMXTypeLegacyPass() : FunctionPass(ID) {
     initializeX86LowerAMXTypeLegacyPassPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnFunction(Function &F) override {
+    bool C = false;
     TargetMachine *TM = &getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
     TargetLibraryInfo *TLI =
         &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(F);
     X86LowerAMXCast LAC(F);
-    LAC.combineAMXcast(TLI);
+    C |= LAC.combineAMXcast(TLI);
     // There might be remaining AMXcast after combineAMXcast and they should be
     // handled elegantly.
-    LAC.transformAllAMXCast();
+    C |= LAC.transformAllAMXCast();
 
     X86LowerAMXType LAT(F);
-    bool C = LAT.visit();
+    C |= LAT.visit();
 
     // Prepare for fast register allocation at O0.
     // Todo: May better check the volatile model of AMX code, not just
     // by checking Attribute::OptimizeNone and CodeGenOpt::None.
     if (TM->getOptLevel() == CodeGenOpt::None) {
       // If Front End not use O0 but the Mid/Back end use O0, (e.g.
       // "Clang -O2 -S -emit-llvm t.c" + "llc t.ll") we should make
       // sure the amx data is volatile, that is nessary for AMX fast