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Differential D108210

[AMDGPU] Fix lowering of AMDGPU::G_CTTZ_ZERO_UNDEF to AMDGPU::G_AMDGPU_FFBL_B32
ClosedPublic

Authored by RKSimon on Aug 17 2021, 8:28 AM.

Details

Reviewers
arsenm
foad
hliao
Petar.Avramovic
Commits
rGfb81271e8b44: [AMDGPU] Fix lowering of AMDGPU::G_CTTZ_ZERO_UNDEF to AMDGPU::G_AMDGPU_FFBL_B32
Summary

As mentioned on D107474, there was a copy+paste typo repeating G_CTLZ_ZERO_UNDEF that coverity reported as dead code.

Diff Detail

Event Timeline

RKSimon created this revision.Aug 17 2021, 8:28 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 6 others. · View Herald TranscriptAug 17 2021, 8:28 AM
RKSimon requested review of this revision.Aug 17 2021, 8:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 17 2021, 8:28 AM
Herald added a subscriber: wdng. · View Herald Transcript
Harbormaster completed remote builds in B119911: Diff 366906.Aug 17 2021, 9:02 AM
arsenm accepted this revision.Aug 17 2021, 9:51 AM
This revision is now accepted and ready to land.Aug 17 2021, 9:51 AM
This revision was landed with ongoing or failed builds.Aug 17 2021, 10:10 AM
Closed by commit rGfb81271e8b44: [AMDGPU] Fix lowering of AMDGPU::G_CTTZ_ZERO_UNDEF to AMDGPU::G_AMDGPU_FFBL_B32 (authored by RKSimon). · Explain Why
This revision was automatically updated to reflect the committed changes.
RKSimon added a commit: rGfb81271e8b44: [AMDGPU] Fix lowering of AMDGPU::G_CTTZ_ZERO_UNDEF to AMDGPU::G_AMDGPU_FFBL_B32.
foad mentioned this in D107474: [AMDGPU] Better legalization of ctlz/cttz.Aug 22 2021, 12:44 PM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
8 lines

Diff 366934

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 2,533 Lines • ▼ Show 20 Lines case AMDGPU::G_CTTZ_ZERO_UNDEF: {
// (cttz_zero_undef hi:lo) -> (umin (add (ffbl hi), 32), (ffbl lo)) // (cttz_zero_undef hi:lo) -> (umin (add (ffbl hi), 32), (ffbl lo))
// (ffbh hi:lo) -> (umin (ffbh hi), (uaddsat (ffbh lo), 32)) // (ffbh hi:lo) -> (umin (ffbh hi), (uaddsat (ffbh lo), 32))
// (ffbl hi:lo) -> (umin (uaddsat (ffbh hi), 32), (ffbh lo)) // (ffbl hi:lo) -> (umin (uaddsat (ffbh hi), 32), (ffbh lo))
ApplyRegBankMapping ApplyVALU(*this, MRI, &AMDGPU::VGPRRegBank); ApplyRegBankMapping ApplyVALU(*this, MRI, &AMDGPU::VGPRRegBank);
MachineIRBuilder B(MI, ApplyVALU); MachineIRBuilder B(MI, ApplyVALU);
SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1)); SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1));
unsigned NewOpc = Opc == AMDGPU::G_CTLZ_ZERO_UNDEF unsigned NewOpc = Opc == AMDGPU::G_CTLZ_ZERO_UNDEF
? AMDGPU::G_AMDGPU_FFBH_U32 ? AMDGPU::G_AMDGPU_FFBH_U32
: Opc == AMDGPU::G_CTLZ_ZERO_UNDEF : Opc == AMDGPU::G_CTTZ_ZERO_UNDEF
? AMDGPU::G_AMDGPU_FFBL_B32 ? AMDGPU::G_AMDGPU_FFBL_B32
: Opc; : Opc;
unsigned Idx = NewOpc == AMDGPU::G_AMDGPU_FFBH_U32; unsigned Idx = NewOpc == AMDGPU::G_AMDGPU_FFBH_U32;
auto X = B.buildInstr(NewOpc, {S32}, {SrcRegs[Idx]}); auto X = B.buildInstr(NewOpc, {S32}, {SrcRegs[Idx]});
auto Y = B.buildInstr(NewOpc, {S32}, {SrcRegs[Idx ^ 1]}); auto Y = B.buildInstr(NewOpc, {S32}, {SrcRegs[Idx ^ 1]});
unsigned AddOpc = unsigned AddOpc =
Opc == AMDGPU::G_CTLZ_ZERO_UNDEF || Opc == AMDGPU::G_CTTZ_ZERO_UNDEF Opc == AMDGPU::G_CTLZ_ZERO_UNDEF || Opc == AMDGPU::G_CTTZ_ZERO_UNDEF
? AMDGPU::G_ADD ? AMDGPU::G_ADD
▲ Show 20 Lines • Show All 2,005 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
legalized: true legalized: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: cttz_zero_undef_s64_v ; CHECK-LABEL: name: cttz_zero_undef_s64_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64) ; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:vgpr(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32) ; CHECK: [[AMDGPU_FFBL_B32_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBL_B32 [[UV]](s32)
; CHECK: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:vgpr(s32) = G_CTTZ_ZERO_UNDEF [[UV1]](s32) ; CHECK: [[AMDGPU_FFBL_B32_1:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBL_B32 [[UV1]](s32)
; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 32 ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 32
; CHECK: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[CTTZ_ZERO_UNDEF1]], [[C]] ; CHECK: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[AMDGPU_FFBL_B32_1]], [[C]]
; CHECK: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[CTTZ_ZERO_UNDEF]], [[ADD]] ; CHECK: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[ADD]]
; CHECK: S_ENDPGM 0, implicit [[UMIN]](s32) ; CHECK: S_ENDPGM 0, implicit [[UMIN]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CTTZ_ZERO_UNDEF %0 %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...