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Differential D107777

[AArch64][GlobalISel] Legalize scalar G_SSUBSAT + G_SADDSAT
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Authored by paquette on Aug 9 2021, 11:49 AM.

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Reviewers
aemerson
jroelofs
Commits
rGccfc07904769: [AArch64][GlobalISel] Legalize scalar G_SSUBSAT + G_SADDSAT
Summary

These are lowered, matching SDAG behaviour. (See llvm/test/CodeGen/AArch64/ssub_sat.ll and llvm/test/CodeGen/AArch64/sadd_sat.ll)

These fall back ~159 times on a build of clang with GISel enabled.

Abort is disabled here because we can't clamp these instructions yet. The s88 test requires widening to s128 then clamping back down. I think this is consistent with what SDAG does: https://godbolt.org/z/cn3fWGvqx

Diff Detail

Event Timeline

paquette created this revision.Aug 9 2021, 11:49 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka. · View Herald TranscriptAug 9 2021, 11:49 AM
paquette requested review of this revision.Aug 9 2021, 11:49 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 9 2021, 11:49 AM
Harbormaster completed remote builds in B118727: Diff 365250.Aug 9 2021, 1:03 PM
aemerson added a comment.Aug 9 2021, 3:13 PM

If we have to lower these, would it be better to just do so and then let the simpler, lowered ops be re-legalized if they have odd types?

paquette updated this revision to Diff 366138.EditedAug 12 2021, 3:46 PM

Just lower it

Also add missing update to the legalizer validation test.

Harbormaster completed remote builds in B119354: Diff 366138.Aug 12 2021, 4:53 PM
aemerson accepted this revision.Aug 12 2021, 8:42 PM
This revision is now accepted and ready to land.Aug 12 2021, 8:42 PM
This revision was landed with ongoing or failed builds.Aug 13 2021, 9:12 AM
Closed by commit rGccfc07904769: [AArch64][GlobalISel] Legalize scalar G_SSUBSAT + G_SADDSAT (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rGccfc07904769: [AArch64][GlobalISel] Legalize scalar G_SSUBSAT + G_SADDSAT.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
4 lines
test/
CodeGen/
AArch64/
GlobalISel/
301 lines
301 lines
9 lines

Diff 366138

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Show First 20 Lines • Show All 718 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder(G_CTPOP)
{s64, s64}, {s64, s64},
{s128, s128}, {s128, s128},
{v2s64, v2s64}, {v2s64, v2s64},
{v2s32, v2s32}, {v2s32, v2s32},
{v4s32, v4s32}, {v4s32, v4s32},
{v4s16, v4s16}, {v4s16, v4s16},
{v8s16, v8s16}}); {v8s16, v8s16}});
// TODO: Vector types.
getActionDefinitionsBuilder({G_SADDSAT, G_SSUBSAT})
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  getActionDefinitionsBuilder({G_SADDSAT, G_SSUBSAT})
-      .lowerIf(isScalar(0));
+  getActionDefinitionsBuilder({G_SADDSAT, G_SSUBSAT}).lowerIf(isScalar(0));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - getActionDefinitionsBuilder({G_SADDSAT…
.lowerIf(isScalar(0));
getLegacyLegalizerInfo().computeTables(); getLegacyLegalizerInfo().computeTables();
verify(*ST.getInstrInfo()); verify(*ST.getInstrInfo());
} }
bool AArch64LegalizerInfo::legalizeCustom(LegalizerHelper &Helper, bool AArch64LegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
MachineInstr &MI) const { MachineInstr &MI) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
▲ Show 20 Lines • Show All 557 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=legalizer -verify-machineinstrs -global-isel-abort=0 %s -o - | FileCheck %s
...
---
name: s32
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: s32
; CHECK: liveins: $w0, $w1
; CHECK: %x:_(s32) = COPY $w0
; CHECK: %y:_(s32) = COPY $w1
; CHECK: [[SADDO:%[0-9]+]]:_(s32), [[SADDO1:%[0-9]+]]:_(s1) = G_SADDO %x, %y
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SADDO]], [[C]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
; CHECK: %saddsat:_(s32) = G_SELECT [[SADDO1]](s1), [[ADD]], [[SADDO]]
; CHECK: $w0 = COPY %saddsat(s32)
; CHECK: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%saddsat:_(s32) = G_SADDSAT %x, %y
$w0 = COPY %saddsat(s32)
RET_ReallyLR implicit $w0
...
---
name: s64
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: s64
; CHECK: liveins: $x0, $x1
; CHECK: %x:_(s64) = COPY $x0
; CHECK: %y:_(s64) = COPY $x1
; CHECK: [[SADDO:%[0-9]+]]:_(s64), [[SADDO1:%[0-9]+]]:_(s1) = G_SADDO %x, %y
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SADDO]], [[C]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
; CHECK: %saddsat:_(s64) = G_SELECT [[SADDO1]](s1), [[ADD]], [[SADDO]]
; CHECK: $x0 = COPY %saddsat(s64)
; CHECK: RET_ReallyLR implicit $x0
%x:_(s64) = COPY $x0
%y:_(s64) = COPY $x1
%saddsat:_(s64) = G_SADDSAT %x, %y
$x0 = COPY %saddsat(s64)
RET_ReallyLR implicit $x0
...
---
name: s16
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: s16
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s16) = G_TRUNC %copy_1(s32)
%copy_2:_(s32) = COPY $w1
%y:_(s16) = G_TRUNC %copy_2(s32)
%saddsat:_(s16) = G_SADDSAT %x, %y
%ext:_(s32) = G_ANYEXT %saddsat(s16)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: s1
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: s1
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s1) = G_TRUNC %copy_1(s32)
%copy_2:_(s32) = COPY $w1
%y:_(s1) = G_TRUNC %copy_2(s32)
%saddsat:_(s1) = G_SADDSAT %x, %y
%ext:_(s32) = G_ANYEXT %saddsat(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: s3
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: s3
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 3
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 3
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 3
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 3
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s3) = G_TRUNC %copy_1(s32)
%copy_2:_(s32) = COPY $w1
%y:_(s3) = G_TRUNC %copy_2(s32)
%saddsat:_(s3) = G_SADDSAT %x, %y
%ext:_(s32) = G_ANYEXT %saddsat(s3)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: s36
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: s36
; CHECK: liveins: $x0, $x1
; CHECK: %copy_1:_(s64) = COPY $x0
; CHECK: %copy_2:_(s64) = COPY $x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %copy_1(s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 36
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %copy_2(s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 36
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ADD]](s64)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 36
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s64), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[ADD]](s64)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 36
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 68719476735
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY4]], [[C1]]
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[AND]](s64)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY [[ASHR]](s64)
; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
; CHECK: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[COPY5]], [[COPY6]]
; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY [[ADD1]](s64)
; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY [[ADD]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY7]], [[COPY8]]
; CHECK: %ext:_(s64) = COPY [[SELECT]](s64)
; CHECK: $x0 = COPY %ext(s64)
; CHECK: RET_ReallyLR implicit $x0
%copy_1:_(s64) = COPY $x0
%x:_(s36) = G_TRUNC %copy_1(s64)
%copy_2:_(s64) = COPY $x1
%y:_(s36) = G_TRUNC %copy_2(s64)
%saddsat:_(s36) = G_SADDSAT %x, %y
%ext:_(s64) = G_ANYEXT %saddsat(s36)
$x0 = COPY %ext(s64)
RET_ReallyLR implicit $x0
...
---
name: s88
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: s88
; CHECK: liveins: $q0, $q1, $x0
; CHECK: %copy_1:_(s128) = COPY $q0
; CHECK: %copy_2:_(s128) = COPY $q1
; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %copy_1(s128)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s128), 0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %copy_2(s128)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s128), 0
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[EXTRACT]], [[EXTRACT1]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[UADDO1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 24
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UADDO]](s64)
; CHECK: [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UADDE]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[UV16:%[0-9]+]]:_(s8), [[UV17:%[0-9]+]]:_(s8), [[UV18:%[0-9]+]]:_(s8), [[UV19:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF1]](s32)
; CHECK: [[UV20:%[0-9]+]]:_(s8), [[UV21:%[0-9]+]]:_(s8), [[UV22:%[0-9]+]]:_(s8), [[UV23:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF1]](s32)
; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV4]](s8), [[UV5]](s8), [[UV6]](s8), [[UV7]](s8)
; CHECK: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV8]](s8), [[UV9]](s8), [[UV10]](s8), [[UV11]](s8)
; CHECK: [[MV2:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV12]](s8), [[UV13]](s8), [[UV14]](s8), [[DEF]](s8)
; CHECK: [[MV3:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV16]](s8), [[UV17]](s8), [[UV18]](s8), [[UV20]](s8)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 87
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
; CHECK: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
; CHECK: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV2]](s32), [[MV3]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV4]], [[C3]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[MV5]], [[C3]](s64)
; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV4]], [[C4]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; CHECK: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[SHL]], [[C3]](s64)
; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C4]](s64)
; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL2]]
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[OR]], [[C3]](s64)
; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
; CHECK: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C5]](s64)
; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 -8388608
; CHECK: [[UADDO2:%[0-9]+]]:_(s64), [[UADDO3:%[0-9]+]]:_(s1) = G_UADDO [[ASHR1]], [[C1]]
; CHECK: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC2]](s1), [[UADDO2]], [[MV6]]
; CHECK: $x0 = COPY [[SELECT]](s64)
; CHECK: RET_ReallyLR implicit $x0
%copy_1:_(s128) = COPY $q0
%x:_(s88) = G_TRUNC %copy_1(s128)
%copy_2:_(s128) = COPY $q1
%y:_(s88) = G_TRUNC %copy_2(s128)
%saddsat:_(s88) = G_SADDSAT %x, %y
%trunc:_(s64) = G_TRUNC %saddsat(s88)
$x0 = COPY %trunc(s64)
RET_ReallyLR implicit $x0

llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=legalizer -verify-machineinstrs -global-isel-abort=0 %s -o - | FileCheck %s
...
---
name: s32
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: s32
; CHECK: liveins: $w0, $w1
; CHECK: %x:_(s32) = COPY $w0
; CHECK: %y:_(s32) = COPY $w1
; CHECK: [[SSUBO:%[0-9]+]]:_(s32), [[SSUBO1:%[0-9]+]]:_(s1) = G_SSUBO %x, %y
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SSUBO]], [[C]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
; CHECK: %ssubsat:_(s32) = G_SELECT [[SSUBO1]](s1), [[ADD]], [[SSUBO]]
; CHECK: $w0 = COPY %ssubsat(s32)
; CHECK: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%ssubsat:_(s32) = G_SSUBSAT %x, %y
$w0 = COPY %ssubsat(s32)
RET_ReallyLR implicit $w0
...
---
name: s64
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: s64
; CHECK: liveins: $x0, $x1
; CHECK: %x:_(s64) = COPY $x0
; CHECK: %y:_(s64) = COPY $x1
; CHECK: [[SSUBO:%[0-9]+]]:_(s64), [[SSUBO1:%[0-9]+]]:_(s1) = G_SSUBO %x, %y
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SSUBO]], [[C]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
; CHECK: %ssubsat:_(s64) = G_SELECT [[SSUBO1]](s1), [[ADD]], [[SSUBO]]
; CHECK: $x0 = COPY %ssubsat(s64)
; CHECK: RET_ReallyLR implicit $x0
%x:_(s64) = COPY $x0
%y:_(s64) = COPY $x1
%ssubsat:_(s64) = G_SSUBSAT %x, %y
$x0 = COPY %ssubsat(s64)
RET_ReallyLR implicit $x0
...
---
name: s16
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: s16
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s16) = G_TRUNC %copy_1(s32)
%copy_2:_(s32) = COPY $w1
%y:_(s16) = G_TRUNC %copy_2(s32)
%ssubsat:_(s16) = G_SSUBSAT %x, %y
%ext:_(s32) = G_ANYEXT %ssubsat(s16)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: s1
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: s1
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s1) = G_TRUNC %copy_1(s32)
%copy_2:_(s32) = COPY $w1
%y:_(s1) = G_TRUNC %copy_2(s32)
%ssubsat:_(s1) = G_SSUBSAT %x, %y
%ext:_(s32) = G_ANYEXT %ssubsat(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: s3
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: s3
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 3
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 3
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 3
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 3
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s3) = G_TRUNC %copy_1(s32)
%copy_2:_(s32) = COPY $w1
%y:_(s3) = G_TRUNC %copy_2(s32)
%ssubsat:_(s3) = G_SSUBSAT %x, %y
%ext:_(s32) = G_ANYEXT %ssubsat(s3)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: s36
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: s36
; CHECK: liveins: $x0, $x1
; CHECK: %copy_1:_(s64) = COPY $x0
; CHECK: %copy_2:_(s64) = COPY $x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %copy_1(s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 36
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %copy_2(s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 36
; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SUB]](s64)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 36
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s64), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[SUB]](s64)
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 36
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 68719476735
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY4]], [[C1]]
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[AND]](s64)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY [[ASHR]](s64)
; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY5]], [[COPY6]]
; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY [[ADD]](s64)
; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY [[SUB]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY7]], [[COPY8]]
; CHECK: %ext:_(s64) = COPY [[SELECT]](s64)
; CHECK: $x0 = COPY %ext(s64)
; CHECK: RET_ReallyLR implicit $x0
%copy_1:_(s64) = COPY $x0
%x:_(s36) = G_TRUNC %copy_1(s64)
%copy_2:_(s64) = COPY $x1
%y:_(s36) = G_TRUNC %copy_2(s64)
%ssubsat:_(s36) = G_SSUBSAT %x, %y
%ext:_(s64) = G_ANYEXT %ssubsat(s36)
$x0 = COPY %ext(s64)
RET_ReallyLR implicit $x0
...
---
name: s88
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: s88
; CHECK: liveins: $q0, $q1, $x0
; CHECK: %copy_1:_(s128) = COPY $q0
; CHECK: %copy_2:_(s128) = COPY $q1
; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %copy_1(s128)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s128), 0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %copy_2(s128)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s128), 0
; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
; CHECK: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[EXTRACT]], [[EXTRACT1]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], [[USUBO1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 24
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[USUBO]](s64)
; CHECK: [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[USUBE]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[UV16:%[0-9]+]]:_(s8), [[UV17:%[0-9]+]]:_(s8), [[UV18:%[0-9]+]]:_(s8), [[UV19:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF1]](s32)
; CHECK: [[UV20:%[0-9]+]]:_(s8), [[UV21:%[0-9]+]]:_(s8), [[UV22:%[0-9]+]]:_(s8), [[UV23:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[DEF1]](s32)
; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV4]](s8), [[UV5]](s8), [[UV6]](s8), [[UV7]](s8)
; CHECK: [[MV1:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV8]](s8), [[UV9]](s8), [[UV10]](s8), [[UV11]](s8)
; CHECK: [[MV2:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV12]](s8), [[UV13]](s8), [[UV14]](s8), [[DEF]](s8)
; CHECK: [[MV3:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[UV16]](s8), [[UV17]](s8), [[UV18]](s8), [[UV20]](s8)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 87
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
; CHECK: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
; CHECK: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV2]](s32), [[MV3]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV4]], [[C3]](s64)
; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[MV5]], [[C3]](s64)
; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[MV4]], [[C4]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]]
; CHECK: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[SHL]], [[C3]](s64)
; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C4]](s64)
; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL2]]
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[OR]], [[C3]](s64)
; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 23
; CHECK: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C5]](s64)
; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 -8388608
; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[ASHR1]], [[C1]]
; CHECK: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[MV]](s32), [[MV1]](s32)
; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC2]](s1), [[UADDO]], [[MV6]]
; CHECK: $x0 = COPY [[SELECT]](s64)
; CHECK: RET_ReallyLR implicit $x0
%copy_1:_(s128) = COPY $q0
%x:_(s88) = G_TRUNC %copy_1(s128)
%copy_2:_(s128) = COPY $q1
%y:_(s88) = G_TRUNC %copy_2(s128)
%ssubsat:_(s88) = G_SSUBSAT %x, %y
%trunc:_(s64) = G_TRUNC %ssubsat(s88)
$x0 = COPY %trunc(s64)
RET_ReallyLR implicit $x0

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_SMULH (opcode {{[0-9]+}}): 1 type index, 0 imm indices # DEBUG-NEXT: G_SMULH (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 1, OK # DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_UADDSAT (opcode {{[0-9]+}}): 1 type index, 0 imm indices # DEBUG-NEXT: G_UADDSAT (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_SADDSAT (opcode {{[0-9]+}}): 1 type index, 0 imm indices # DEBUG-NEXT: G_SADDSAT (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_USUBSAT (opcode {{[0-9]+}}): 1 type index, 0 imm indices # DEBUG-NEXT: G_USUBSAT (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_SSUBSAT (opcode {{[0-9]+}}): 1 type index, 0 imm indices # DEBUG-NEXT: G_SSUBSAT (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_USHLSAT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices # DEBUG-NEXT: G_USHLSAT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_SSHLSAT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices # DEBUG-NEXT: G_SSHLSAT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_SMULFIX (opcode {{[0-9]+}}): 1 type index, 1 imm index # DEBUG-NEXT: G_SMULFIX (opcode {{[0-9]+}}): 1 type index, 1 imm index
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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