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Differential D107644

[AArch64] NFC: Remove DecodeVectorRegisterClass from disassembler
ClosedPublic

Authored by c-rhodes on Aug 6 2021, 7:13 AM.

Details

Reviewers
david-arm
tmatheson
ostannard
Commits
rG1a18bb9270ce: [AArch64] NFC: Remove DecodeVectorRegisterClass from disassembler
Summary

The decoder function and table are the same as FPR128, use that instead.

Diff Detail

Event Timeline

c-rhodes created this revision.Aug 6 2021, 7:13 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptAug 6 2021, 7:14 AM
c-rhodes requested review of this revision.Aug 6 2021, 7:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 6 2021, 7:14 AM
david-arm accepted this revision.Aug 6 2021, 7:40 AM

LGTM!

This revision is now accepted and ready to land.Aug 6 2021, 7:40 AM
Harbormaster completed remote builds in B118378: Diff 364789.Aug 6 2021, 8:08 AM
Closed by commit rG1a18bb9270ce: [AArch64] NFC: Remove DecodeVectorRegisterClass from disassembler (authored by c-rhodes). · Explain WhyAug 9 2021, 12:00 AM
This revision was automatically updated to reflect the committed changes.
c-rhodes added a commit: rG1a18bb9270ce: [AArch64] NFC: Remove DecodeVectorRegisterClass from disassembler.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
Disassembler/
27 lines

Diff 364789

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

Show First 20 Lines • Show All 761 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
const void* Decoder) { const void* Decoder) {
if (RegNo > 7) if (RegNo > 7)
return Fail; return Fail;
// Just reuse the PPR decode table // Just reuse the PPR decode table
return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder); return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
} }
static const unsigned VectorDecoderTable[] = {
AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
AArch64::Q30, AArch64::Q31
};
static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Addr,
const void *Decoder) {
if (RegNo > 31)
return Fail;
unsigned Register = VectorDecoderTable[RegNo];
Inst.addOperand(MCOperand::createReg(Register));
return Success;
}
static const unsigned QQDecoderTable[] = { static const unsigned QQDecoderTable[] = {
AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
▲ Show 20 Lines • Show All 971 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned cmode = fieldFromInstruction(insn, 12, 4); unsigned cmode = fieldFromInstruction(insn, 12, 4);
unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
imm |= fieldFromInstruction(insn, 5, 5); imm |= fieldFromInstruction(insn, 5, 5);
if (Inst.getOpcode() == AArch64::MOVID) if (Inst.getOpcode() == AArch64::MOVID)
DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
else else
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
default: default:
break; break;
case AArch64::MOVIv4i16: case AArch64::MOVIv4i16:
case AArch64::MOVIv8i16: case AArch64::MOVIv8i16:
Show All 20 Linesstatic DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
uint64_t Addr, uint64_t Addr,
const void *Decoder) { const void *Decoder) {
unsigned Rd = fieldFromInstruction(insn, 0, 5); unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned cmode = fieldFromInstruction(insn, 12, 4); unsigned cmode = fieldFromInstruction(insn, 12, 4);
unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
imm |= fieldFromInstruction(insn, 5, 5); imm |= fieldFromInstruction(insn, 5, 5);
// Tied operands added twice. // Tied operands added twice.
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
Inst.addOperand(MCOperand::createImm(imm)); Inst.addOperand(MCOperand::createImm(imm));
Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
return Success; return Success;
} }
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
▲ Show 20 Lines • Show All 215 Lines • Show Last 20 Lines