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Differential D107638

[ARM] Add a tail-predication loop predicate register
ClosedPublic

Authored by dmgreen on Aug 6 2021, 4:52 AM.

Details

Reviewers
SjoerdMeijer
samtebbs
NickGuy
ostannard
simon_tatham
Commits
rG9cb8f4d1ad65: [ARM] Add a tail-predication loop predicate register
Summary

The semantics of tail predication loops means that the value of LR as an instruction is executed determines the predicate. In other words:

mov r3, #3
DLSTP lr, r3        // Start tail predication, lr==3
VADD.s32 q0, q1, q2 // Lanes 0,1 and 2 are updated in q0.
mov lr, #1
VADD.s32 q0, q1, q2 // Only first lane is updated.

This means that the value of lr cannot be spilled and re-used in tail predication regions without potentially altering the behaviour of the program. More lanes than required could be stored, for example, and in the case of a gather those lanes might not have been setup, leading to alignment exceptions.

This patch adds a new "lr" predicate operand to MVE instructions in order to keep a reference to the lr that they use as a tail predicate. It will usually hold the zeroreg meaning not predicated, being set to the LR phi value in the MVETPAndVPTOptimisationsPass. This will prevent it from being spilled anywhere that it needs to be set.

A lot of tests needed updating.

Diff Detail

Event Timeline

dmgreen created this revision.Aug 6 2021, 4:52 AM
Herald added subscribers: danielkiss, zzheng, hiraditya and 2 others. · View Herald TranscriptAug 6 2021, 4:52 AM
dmgreen requested review of this revision.Aug 6 2021, 4:52 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 6 2021, 4:52 AM
Harbormaster completed remote builds in B118351: Diff 364751.Aug 6 2021, 5:32 AM
samtebbs added inline comments.Aug 9 2021, 5:50 AM
llvm/lib/CodeGen/MachineVerifier.cpp
1656–1657

What's the purpose of this change?

samtebbs added a comment.Aug 9 2021, 5:53 AM

From looking at the changes to some of the tests that should produce tail-predicated loops, none of them get the $noreg replaced with $lr. Isn't that supposed to happen in the VPT optimisation pass, or am I looking in the wrong place?

dmgreen added a comment.Aug 9 2021, 9:15 AM

From looking at the changes to some of the tests that should produce tail-predicated loops, none of them get the $noreg replaced with $lr. Isn't that supposed to happen in the VPT optimisation pass, or am I looking in the wrong place?

There are a couple of mir tests that I updated to use $lr (like dont-ignore-vctp.mir and subreg-liveness.mir), but most I just used $noreg for to simplify things, in the same way that we still use t2DoLoopStart where most tailpredicated loops would usually use t2DoLoopStartTP. It is the register allocator that this is targetting, so the tests checking the ARMLowOverheadLoops pass needn't change.

The only reproducer I have of the original problem requires a very large test file and downstream scheduling to trigger the same issue.

llvm/lib/CodeGen/MachineVerifier.cpp
1656–1657

The "UnspillableTerminator" we use for t2LoopEndDec and t2DoLoopEndTP need only a single use up to phi elimination in order to be lowered correctly. That is already tested in phi elimination, with this verifier check making sure that the unspillable terminators always have a single use. This is only for virtual regs, not physical regs.

But there is a point, in between phi elimination and when the reg allocator assigns registers (which is only a very short period of time) that we can have multiple uses for a def that is still not (quite yet) a physical reg. So this check makes it slightly more precise, not running into verifier problems where they are not an issue.

samtebbs accepted this revision.Sep 1 2021, 9:14 AM

Your comments make sense 👍 LGTM

This revision is now accepted and ready to land.Sep 1 2021, 9:14 AM
This revision was landed with ongoing or failed builds.Sep 2 2021, 5:43 AM
Closed by commit rG9cb8f4d1ad65: [ARM] Add a tail-predication loop predicate register (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG9cb8f4d1ad65: [ARM] Add a tail-predication loop predicate register.

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Diff 370244

llvm/lib/CodeGen/MachineVerifier.cpp

Show First 20 Lines • Show All 1,647 Lines • ▼ Show 20 Lines if (MI->isInlineAsm())
verifyInlineAsm(MI); verifyInlineAsm(MI);
// Check that unspillable terminators define a reg and have at most one use. // Check that unspillable terminators define a reg and have at most one use.
if (TII->isUnspillableTerminator(MI)) { if (TII->isUnspillableTerminator(MI)) {
if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef()) if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
report("Unspillable Terminator does not define a reg", MI); report("Unspillable Terminator does not define a reg", MI);
Register Def = MI->getOperand(0).getReg(); Register Def = MI->getOperand(0).getReg();
if (Def.isVirtual() && if (Def.isVirtual() &&
!MF->getProperties().hasProperty(
MachineFunctionProperties::Property::NoPHIs) &&
samtebbsUnsubmitted
Not Done
ReplyInline Actions

What's the purpose of this change?

samtebbs: What's the purpose of this change?
dmgreenAuthorUnsubmitted
Done
ReplyInline Actions

The "UnspillableTerminator" we use for t2LoopEndDec and t2DoLoopEndTP need only a single use up to phi elimination in order to be lowered correctly. That is already tested in phi elimination, with this verifier check making sure that the unspillable terminators always have a single use. This is only for virtual regs, not physical regs.

But there is a point, in between phi elimination and when the reg allocator assigns registers (which is only a very short period of time) that we can have multiple uses for a def that is still not (quite yet) a physical reg. So this check makes it slightly more precise, not running into verifier problems where they are not an issue.

dmgreen: The "UnspillableTerminator" we use for t2LoopEndDec and t2DoLoopEndTP need only a single use up…
std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1) std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
report("Unspillable Terminator expected to have at most one use!", MI); report("Unspillable Terminator expected to have at most one use!", MI);
} }
// A fully-formed DBG_VALUE must have a location. Ignore partially formed // A fully-formed DBG_VALUE must have a location. Ignore partially formed
// DBG_VALUEs: these are convenient to use in tests, but should never get // DBG_VALUEs: these are convenient to use in tests, but should never get
// generated. // generated.
if (MI->isDebugValue() && MI->getNumOperands() == 4) if (MI->isDebugValue() && MI->getNumOperands() == 4)
▲ Show 20 Lines • Show All 1,592 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Show First 20 Lines • Show All 861 Lines • ▼ Show 20 Linesvoid ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
MIB.addReg(SrcReg, getKillRegState(KillSrc)) MIB.addReg(SrcReg, getKillRegState(KillSrc))
.add(predOps(ARMCC::AL)) .add(predOps(ARMCC::AL))
.addReg(ARM::CPSR, RegState::Implicit | RegState::Define); .addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
} }
void llvm::addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB) { void llvm::addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB) {
MIB.addImm(ARMVCC::None); MIB.addImm(ARMVCC::None);
MIB.addReg(0); MIB.addReg(0);
MIB.addReg(0); // tp_reg
} }
void llvm::addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, void llvm::addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB,
Register DestReg) { Register DestReg) {
addUnpredicatedMveVpredNOp(MIB); addUnpredicatedMveVpredNOp(MIB);
MIB.addReg(DestReg, RegState::Undef); MIB.addReg(DestReg, RegState::Undef);
} }
void llvm::addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond) { void llvm::addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond) {
MIB.addImm(Cond); MIB.addImm(Cond);
MIB.addReg(ARM::VPR, RegState::Implicit); MIB.addReg(ARM::VPR, RegState::Implicit);
MIB.addReg(0); // tp_reg
} }
void llvm::addPredicatedMveVpredROp(MachineInstrBuilder &MIB, void llvm::addPredicatedMveVpredROp(MachineInstrBuilder &MIB,
unsigned Cond, unsigned Inactive) { unsigned Cond, unsigned Inactive) {
addPredicatedMveVpredNOp(MIB, Cond); addPredicatedMveVpredNOp(MIB, Cond);
MIB.addReg(Inactive); MIB.addReg(Inactive);
} }
▲ Show 20 Lines • Show All 5,669 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

Show First 20 Lines • Show All 1,816 Lines • ▼ Show 20 Lines else if (Alignment >= Align(2) &&
SelectT2AddrModeImm7Offset(N, Offset, NewOffset, 1)) SelectT2AddrModeImm7Offset(N, Offset, NewOffset, 1))
Opcode = isPre ? ARM::MVE_VLDRHU16_pre : ARM::MVE_VLDRHU16_post; Opcode = isPre ? ARM::MVE_VLDRHU16_pre : ARM::MVE_VLDRHU16_post;
else if ((CanChangeType || LoadedVT == MVT::v16i8) && else if ((CanChangeType || LoadedVT == MVT::v16i8) &&
SelectT2AddrModeImm7Offset(N, Offset, NewOffset, 0)) SelectT2AddrModeImm7Offset(N, Offset, NewOffset, 0))
Opcode = isPre ? ARM::MVE_VLDRBU8_pre : ARM::MVE_VLDRBU8_post; Opcode = isPre ? ARM::MVE_VLDRBU8_pre : ARM::MVE_VLDRBU8_post;
else else
return false; return false;
SDValue Ops[] = {Base, NewOffset, SDValue Ops[] = {Base,
CurDAG->getTargetConstant(Pred, SDLoc(N), MVT::i32), PredReg, NewOffset,
CurDAG->getTargetConstant(Pred, SDLoc(N), MVT::i32),
PredReg,
CurDAG->getRegister(0, MVT::i32), // tp_reg
Chain}; Chain};
SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
N->getValueType(0), MVT::Other, Ops); N->getValueType(0), MVT::Other, Ops);
transferMemOperands(N, New); transferMemOperands(N, New);
ReplaceUses(SDValue(N, 0), SDValue(New, 1)); ReplaceUses(SDValue(N, 0), SDValue(New, 1));
ReplaceUses(SDValue(N, 1), SDValue(New, 0)); ReplaceUses(SDValue(N, 1), SDValue(New, 0));
ReplaceUses(SDValue(N, 2), SDValue(New, 2)); ReplaceUses(SDValue(N, 2), SDValue(New, 2));
CurDAG->RemoveDeadNode(N); CurDAG->RemoveDeadNode(N);
▲ Show 20 Lines • Show All 689 Lines • ▼ Show 20 Linesvoid ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
CurDAG->RemoveDeadNode(N); CurDAG->RemoveDeadNode(N);
} }
template <typename SDValueVector> template <typename SDValueVector>
void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
SDValue PredicateMask) { SDValue PredicateMask) {
Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32)); Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32));
Ops.push_back(PredicateMask); Ops.push_back(PredicateMask);
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg
} }
template <typename SDValueVector> template <typename SDValueVector>
void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, void ARMDAGToDAGISel::AddMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
SDValue PredicateMask, SDValue PredicateMask,
SDValue Inactive) { SDValue Inactive) {
Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32)); Ops.push_back(CurDAG->getTargetConstant(ARMVCC::Then, Loc, MVT::i32));
Ops.push_back(PredicateMask); Ops.push_back(PredicateMask);
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg
Ops.push_back(Inactive); Ops.push_back(Inactive);
} }
template <typename SDValueVector> template <typename SDValueVector>
void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc) { void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc) {
Ops.push_back(CurDAG->getTargetConstant(ARMVCC::None, Loc, MVT::i32)); Ops.push_back(CurDAG->getTargetConstant(ARMVCC::None, Loc, MVT::i32));
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); Ops.push_back(CurDAG->getRegister(0, MVT::i32));
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg
} }
template <typename SDValueVector> template <typename SDValueVector>
void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc, void ARMDAGToDAGISel::AddEmptyMVEPredicateToOps(SDValueVector &Ops, SDLoc Loc,
EVT InactiveTy) { EVT InactiveTy) {
Ops.push_back(CurDAG->getTargetConstant(ARMVCC::None, Loc, MVT::i32)); Ops.push_back(CurDAG->getTargetConstant(ARMVCC::None, Loc, MVT::i32));
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); Ops.push_back(CurDAG->getRegister(0, MVT::i32));
Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // tp_reg
Ops.push_back(SDValue( Ops.push_back(SDValue(
CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, Loc, InactiveTy), 0)); CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, Loc, InactiveTy), 0));
} }
void ARMDAGToDAGISel::SelectMVE_WB(SDNode *N, const uint16_t *Opcodes, void ARMDAGToDAGISel::SelectMVE_WB(SDNode *N, const uint16_t *Opcodes,
bool Predicated) { bool Predicated) {
SDLoc Loc(N); SDLoc Loc(N);
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
▲ Show 20 Lines • Show All 3,352 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 11,536 Lines • ▼ Show 20 Lines BuildMI(TpLoopBody, Dl, TII->get(ARM::PHI), PredCounterPhiReg)
.addUse(RemainingElementsReg) .addUse(RemainingElementsReg)
.addMBB(TpLoopBody); .addMBB(TpLoopBody);
// Pass predication counter to VCTP // Pass predication counter to VCTP
Register VccrReg = MRI.createVirtualRegister(&ARM::VCCRRegClass); Register VccrReg = MRI.createVirtualRegister(&ARM::VCCRRegClass);
BuildMI(TpLoopBody, Dl, TII->get(ARM::MVE_VCTP8), VccrReg) BuildMI(TpLoopBody, Dl, TII->get(ARM::MVE_VCTP8), VccrReg)
.addUse(PredCounterPhiReg) .addUse(PredCounterPhiReg)
.addImm(ARMVCC::None) .addImm(ARMVCC::None)
.addReg(0)
.addReg(0); .addReg(0);
BuildMI(TpLoopBody, Dl, TII->get(ARM::t2SUBri), RemainingElementsReg) BuildMI(TpLoopBody, Dl, TII->get(ARM::t2SUBri), RemainingElementsReg)
.addUse(PredCounterPhiReg) .addUse(PredCounterPhiReg)
.addImm(16) .addImm(16)
.add(predOps(ARMCC::AL)) .add(predOps(ARMCC::AL))
.addReg(0); .addReg(0);
// VLDRB (only if memcpy) and VSTRB instructions, predicated using VPR // VLDRB (only if memcpy) and VSTRB instructions, predicated using VPR
Register SrcValueReg; Register SrcValueReg;
if (IsMemcpy) { if (IsMemcpy) {
SrcValueReg = MRI.createVirtualRegister(&ARM::MQPRRegClass); SrcValueReg = MRI.createVirtualRegister(&ARM::MQPRRegClass);
BuildMI(TpLoopBody, Dl, TII->get(ARM::MVE_VLDRBU8_post)) BuildMI(TpLoopBody, Dl, TII->get(ARM::MVE_VLDRBU8_post))
.addDef(CurrSrcReg) .addDef(CurrSrcReg)
.addDef(SrcValueReg) .addDef(SrcValueReg)
.addReg(SrcPhiReg) .addReg(SrcPhiReg)
.addImm(16) .addImm(16)
.addImm(ARMVCC::Then) .addImm(ARMVCC::Then)
.addUse(VccrReg); .addUse(VccrReg)
.addReg(0);
} else } else
SrcValueReg = OpSrcReg; SrcValueReg = OpSrcReg;
BuildMI(TpLoopBody, Dl, TII->get(ARM::MVE_VSTRBU8_post)) BuildMI(TpLoopBody, Dl, TII->get(ARM::MVE_VSTRBU8_post))
.addDef(CurrDestReg) .addDef(CurrDestReg)
.addUse(SrcValueReg) .addUse(SrcValueReg)
.addReg(DestPhiReg) .addReg(DestPhiReg)
.addImm(16) .addImm(16)
.addImm(ARMVCC::Then) .addImm(ARMVCC::Then)
.addUse(VccrReg); .addUse(VccrReg)
.addReg(0);
// Add the pseudoInstrs for decrementing the loop counter and marking the // Add the pseudoInstrs for decrementing the loop counter and marking the
// end:t2DoLoopDec and t2DoLoopEnd // end:t2DoLoopDec and t2DoLoopEnd
BuildMI(TpLoopBody, Dl, TII->get(ARM::t2LoopDec), RemainingLoopIterationsReg) BuildMI(TpLoopBody, Dl, TII->get(ARM::t2LoopDec), RemainingLoopIterationsReg)
.addUse(LoopCounterPhiReg) .addUse(LoopCounterPhiReg)
.addImm(1); .addImm(1);
BuildMI(TpLoopBody, Dl, TII->get(ARM::t2LoopEnd)) BuildMI(TpLoopBody, Dl, TII->get(ARM::t2LoopEnd))
▲ Show 20 Lines • Show All 9,479 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMInstrCDE.td

Show First 20 Lines • Show All 606 Lines • ▼ Show 20 Lines def : Pat<(v16i8 (int_arm_cde_vcx3qa timm:$coproc, (v16i8 MQPR:$acc),
imm_4b:$imm))>; imm_4b:$imm))>;
} }
multiclass VCXPredicatedPat_m<MVEVectorVTInfo VTI> { multiclass VCXPredicatedPat_m<MVEVectorVTInfo VTI> {
def : Pat<(VTI.Vec (int_arm_cde_vcx1q_predicated timm:$coproc, def : Pat<(VTI.Vec (int_arm_cde_vcx1q_predicated timm:$coproc,
(VTI.Vec MQPR:$inactive), timm:$imm, (VTI.Vec MQPR:$inactive), timm:$imm,
(VTI.Pred VCCR:$pred))), (VTI.Pred VCCR:$pred))),
(VTI.Vec (CDE_VCX1_vec p_imm:$coproc, imm_12b:$imm, ARMVCCThen, (VTI.Vec (CDE_VCX1_vec p_imm:$coproc, imm_12b:$imm, ARMVCCThen,
(VTI.Pred VCCR:$pred), (VTI.Pred VCCR:$pred), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
def : Pat<(VTI.Vec (int_arm_cde_vcx1qa_predicated timm:$coproc, def : Pat<(VTI.Vec (int_arm_cde_vcx1qa_predicated timm:$coproc,
(VTI.Vec MQPR:$acc), timm:$imm, (VTI.Vec MQPR:$acc), timm:$imm,
(VTI.Pred VCCR:$pred))), (VTI.Pred VCCR:$pred))),
(VTI.Vec (CDE_VCX1A_vec p_imm:$coproc, (VTI.Vec MQPR:$acc), (VTI.Vec (CDE_VCX1A_vec p_imm:$coproc, (VTI.Vec MQPR:$acc),
imm_12b:$imm, ARMVCCThen, imm_12b:$imm, ARMVCCThen,
(VTI.Pred VCCR:$pred)))>; (VTI.Pred VCCR:$pred), zero_reg))>;
def : Pat<(VTI.Vec (int_arm_cde_vcx2q_predicated timm:$coproc, def : Pat<(VTI.Vec (int_arm_cde_vcx2q_predicated timm:$coproc,
(VTI.Vec MQPR:$inactive), (VTI.Vec MQPR:$inactive),
(v16i8 MQPR:$n), timm:$imm, (v16i8 MQPR:$n), timm:$imm,
(VTI.Pred VCCR:$pred))), (VTI.Pred VCCR:$pred))),
(VTI.Vec (CDE_VCX2_vec p_imm:$coproc, (v16i8 MQPR:$n), (VTI.Vec (CDE_VCX2_vec p_imm:$coproc, (v16i8 MQPR:$n),
imm_7b:$imm, ARMVCCThen, imm_7b:$imm, ARMVCCThen,
(VTI.Pred VCCR:$pred), (VTI.Pred VCCR:$pred), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
def : Pat<(VTI.Vec (int_arm_cde_vcx2qa_predicated timm:$coproc, def : Pat<(VTI.Vec (int_arm_cde_vcx2qa_predicated timm:$coproc,
(VTI.Vec MQPR:$acc), (VTI.Vec MQPR:$acc),
(v16i8 MQPR:$n), timm:$imm, (v16i8 MQPR:$n), timm:$imm,
(VTI.Pred VCCR:$pred))), (VTI.Pred VCCR:$pred))),
(VTI.Vec (CDE_VCX2A_vec p_imm:$coproc, (VTI.Vec MQPR:$acc), (VTI.Vec (CDE_VCX2A_vec p_imm:$coproc, (VTI.Vec MQPR:$acc),
(v16i8 MQPR:$n), timm:$imm, ARMVCCThen, (v16i8 MQPR:$n), timm:$imm, ARMVCCThen,
(VTI.Pred VCCR:$pred)))>; (VTI.Pred VCCR:$pred), zero_reg))>;
def : Pat<(VTI.Vec (int_arm_cde_vcx3q_predicated timm:$coproc, def : Pat<(VTI.Vec (int_arm_cde_vcx3q_predicated timm:$coproc,
(VTI.Vec MQPR:$inactive), (VTI.Vec MQPR:$inactive),
(v16i8 MQPR:$n), (v16i8 MQPR:$m), (v16i8 MQPR:$n), (v16i8 MQPR:$m),
timm:$imm, timm:$imm,
(VTI.Pred VCCR:$pred))), (VTI.Pred VCCR:$pred))),
(VTI.Vec (CDE_VCX3_vec p_imm:$coproc, (v16i8 MQPR:$n), (VTI.Vec (CDE_VCX3_vec p_imm:$coproc, (v16i8 MQPR:$n),
(v16i8 MQPR:$m), (v16i8 MQPR:$m),
imm_4b:$imm, ARMVCCThen, imm_4b:$imm, ARMVCCThen,
(VTI.Pred VCCR:$pred), (VTI.Pred VCCR:$pred), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
def : Pat<(VTI.Vec (int_arm_cde_vcx3qa_predicated timm:$coproc, def : Pat<(VTI.Vec (int_arm_cde_vcx3qa_predicated timm:$coproc,
(VTI.Vec MQPR:$acc), (VTI.Vec MQPR:$acc),
(v16i8 MQPR:$n), (v16i8 MQPR:$m), timm:$imm, (v16i8 MQPR:$n), (v16i8 MQPR:$m), timm:$imm,
(VTI.Pred VCCR:$pred))), (VTI.Pred VCCR:$pred))),
(VTI.Vec (CDE_VCX3A_vec p_imm:$coproc, (VTI.Vec MQPR:$acc), (VTI.Vec (CDE_VCX3A_vec p_imm:$coproc, (VTI.Vec MQPR:$acc),
(v16i8 MQPR:$n), (v16i8 MQPR:$m), (v16i8 MQPR:$n), (v16i8 MQPR:$m),
imm_4b:$imm, ARMVCCThen, imm_4b:$imm, ARMVCCThen,
(VTI.Pred VCCR:$pred)))>; (VTI.Pred VCCR:$pred), zero_reg))>;
} }
let Predicates = [HasCDE, HasMVEInt] in let Predicates = [HasCDE, HasMVEInt] in
foreach VTI = [ MVE_v16i8, MVE_v8i16, MVE_v4i32, MVE_v2i64 ] in foreach VTI = [ MVE_v16i8, MVE_v8i16, MVE_v4i32, MVE_v2i64 ] in
defm : VCXPredicatedPat_m<VTI>; defm : VCXPredicatedPat_m<VTI>;
let Predicates = [HasCDE, HasMVEFloat] in let Predicates = [HasCDE, HasMVEFloat] in
foreach VTI = [ MVE_v8f16, MVE_v4f32 ] in foreach VTI = [ MVE_v8f16, MVE_v4f32 ] in
defm : VCXPredicatedPat_m<VTI>; defm : VCXPredicatedPat_m<VTI>;

llvm/lib/Target/ARM/ARMInstrFormats.td

Show First 20 Lines • Show All 243 Lines • ▼ Show 20 Lines
// is defined to set disabled output lanes to zero rather than leaving // is defined to set disabled output lanes to zero rather than leaving
// them unchanged (vector loads), or because it doesn't output a // them unchanged (vector loads), or because it doesn't output a
// vector register at all (stores, compares). In any of these // vector register at all (stores, compares). In any of these
// situations it's unnecessary to have an extra operand tied to the // situations it's unnecessary to have an extra operand tied to the
// output, and inconvenient to leave it there unused. // output, and inconvenient to leave it there unused.
// Base class for both kinds of vpred. // Base class for both kinds of vpred.
class vpred_ops<dag extra_op, dag extra_mi> : OperandWithDefaultOps<OtherVT, class vpred_ops<dag extra_op, dag extra_mi> : OperandWithDefaultOps<OtherVT,
!con((ops (i32 0), (i32 zero_reg)), extra_op)> { !con((ops (i32 0), (i32 zero_reg), (i32 zero_reg)), extra_op)> {
let PrintMethod = "printVPTPredicateOperand"; let PrintMethod = "printVPTPredicateOperand";
let OperandNamespace = "ARM"; let OperandNamespace = "ARM";
let MIOperandInfo = !con((ops i32imm:$cond, VCCR:$cond_reg), extra_mi); let MIOperandInfo = !con((ops i32imm:$cond, VCCR:$cond_reg, GPRlr:$tp_reg), extra_mi);
// For convenience, we provide a string value that can be appended // For convenience, we provide a string value that can be appended
// to the constraints string. It's empty for vpred_n, and for // to the constraints string. It's empty for vpred_n, and for
// vpred_r it ties the $inactive operand to the output q-register // vpred_r it ties the $inactive operand to the output q-register
// (which by convention will be called $Qd). // (which by convention will be called $Qd).
string vpred_constraint; string vpred_constraint;
} }
▲ Show 20 Lines • Show All 2,515 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 326 Lines • ▼ Show 20 Linesmulticlass MVE_TwoOpPattern<MVEVectorVTInfo VTI, SDPatternOperator Op, Intrinsic PredInt,
// Predicated with select // Predicated with select
if !ne(VTI.Size, 0b11) then { if !ne(VTI.Size, 0b11) then {
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$mask), def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$mask),
(VTI.Vec (Op (VTI.Vec MQPR:$Qm), (VTI.Vec (Op (VTI.Vec MQPR:$Qm),
(VTI.Vec MQPR:$Qn))), (VTI.Vec MQPR:$Qn))),
(VTI.Vec MQPR:$inactive))), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
// Optionally with the select folded through the op // Optionally with the select folded through the op
def : Pat<(VTI.Vec (Op (VTI.Vec MQPR:$Qm), def : Pat<(VTI.Vec (Op (VTI.Vec MQPR:$Qm),
(VTI.Vec (vselect (VTI.Pred VCCR:$mask), (VTI.Vec (vselect (VTI.Pred VCCR:$mask),
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qn),
(VTI.Vec IdentityVec))))), (VTI.Vec IdentityVec))))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$Qm)))>; (VTI.Vec MQPR:$Qm)))>;
} }
// Predicated with intrinsic // Predicated with intrinsic
def : Pat<(VTI.Vec !con((PredInt (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)), def : Pat<(VTI.Vec !con((PredInt (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)),
PredOperands, PredOperands,
(? (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive)))), (? (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive)))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
multiclass MVE_TwoOpPatternDup<MVEVectorVTInfo VTI, SDPatternOperator Op, Intrinsic PredInt, multiclass MVE_TwoOpPatternDup<MVEVectorVTInfo VTI, SDPatternOperator Op, Intrinsic PredInt,
dag PredOperands, Instruction Inst, dag PredOperands, Instruction Inst,
SDPatternOperator IdentityVec = null_frag> { SDPatternOperator IdentityVec = null_frag> {
// Unpredicated // Unpredicated
def : Pat<(VTI.Vec (Op (VTI.Vec MQPR:$Qm), (VTI.Vec (ARMvdup rGPR:$Rn)))), def : Pat<(VTI.Vec (Op (VTI.Vec MQPR:$Qm), (VTI.Vec (ARMvdup rGPR:$Rn)))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn))>; (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn))>;
// Predicated with select // Predicated with select
if !ne(VTI.Size, 0b11) then { if !ne(VTI.Size, 0b11) then {
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$mask), def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$mask),
(VTI.Vec (Op (VTI.Vec MQPR:$Qm), (VTI.Vec (Op (VTI.Vec MQPR:$Qm),
(VTI.Vec (ARMvdup rGPR:$Rn)))), (VTI.Vec (ARMvdup rGPR:$Rn)))),
(VTI.Vec MQPR:$inactive))), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn, (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn,
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
// Optionally with the select folded through the op // Optionally with the select folded through the op
def : Pat<(VTI.Vec (Op (VTI.Vec MQPR:$Qm), def : Pat<(VTI.Vec (Op (VTI.Vec MQPR:$Qm),
(VTI.Vec (vselect (VTI.Pred VCCR:$mask), (VTI.Vec (vselect (VTI.Pred VCCR:$mask),
(ARMvdup rGPR:$Rn), (ARMvdup rGPR:$Rn),
(VTI.Vec IdentityVec))))), (VTI.Vec IdentityVec))))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn, (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn,
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$Qm)))>; (VTI.Vec MQPR:$Qm)))>;
} }
// Predicated with intrinsic // Predicated with intrinsic
def : Pat<(VTI.Vec !con((PredInt (VTI.Vec MQPR:$Qm), (VTI.Vec (ARMvdup rGPR:$Rn))), def : Pat<(VTI.Vec !con((PredInt (VTI.Vec MQPR:$Qm), (VTI.Vec (ARMvdup rGPR:$Rn))),
PredOperands, PredOperands,
(? (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive)))), (? (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive)))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn, (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn,
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
// --------- Start of base classes for the instructions themselves // --------- Start of base classes for the instructions themselves
class MVE_MI<dag oops, dag iops, InstrItinClass itin, string asm, class MVE_MI<dag oops, dag iops, InstrItinClass itin, string asm,
string ops, string cstr, list<dag> pattern> string ops, string cstr, list<dag> pattern>
: Thumb2XI<oops, iops, AddrModeNone, 4, itin, !strconcat(asm, "\t", ops), cstr, : Thumb2XI<oops, iops, AddrModeNone, 4, itin, !strconcat(asm, "\t", ops), cstr,
▲ Show 20 Lines • Show All 249 Lines • ▼ Show 20 Lines let Predicates = [HasMVEInt] in {
def : Pat<(i32 (int_arm_mve_vabav_predicated def : Pat<(i32 (int_arm_mve_vabav_predicated
(i32 VTI.Unsigned), (i32 VTI.Unsigned),
(i32 rGPR:$Rda_src), (i32 rGPR:$Rda_src),
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
(VTI.Pred VCCR:$mask))), (VTI.Pred VCCR:$mask))),
(i32 (Inst (i32 rGPR:$Rda_src), (i32 (Inst (i32 rGPR:$Rda_src),
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
ARMVCCThen, (VTI.Pred VCCR:$mask)))>; ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg))>;
} }
} }
defm MVE_VABAVs8 : MVE_VABAV_m<MVE_v16s8>; defm MVE_VABAVs8 : MVE_VABAV_m<MVE_v16s8>;
defm MVE_VABAVs16 : MVE_VABAV_m<MVE_v8s16>; defm MVE_VABAVs16 : MVE_VABAV_m<MVE_v8s16>;
defm MVE_VABAVs32 : MVE_VABAV_m<MVE_v4s32>; defm MVE_VABAVs32 : MVE_VABAV_m<MVE_v4s32>;
defm MVE_VABAVu8 : MVE_VABAV_m<MVE_v16u8>; defm MVE_VABAVu8 : MVE_VABAV_m<MVE_v16u8>;
defm MVE_VABAVu16 : MVE_VABAV_m<MVE_v8u16>; defm MVE_VABAVu16 : MVE_VABAV_m<MVE_v8u16>;
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesmulticlass MVE_VADDV_A<MVEVectorVTInfo VTI> {
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
if VTI.Unsigned then { if VTI.Unsigned then {
def : Pat<(i32 (vecreduce_add (VTI.Vec MQPR:$vec))), def : Pat<(i32 (vecreduce_add (VTI.Vec MQPR:$vec))),
(i32 (InstN $vec))>; (i32 (InstN $vec))>;
def : Pat<(i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred), def : Pat<(i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec MQPR:$vec), (VTI.Vec MQPR:$vec),
(VTI.Vec ARMimmAllZerosV))))), (VTI.Vec ARMimmAllZerosV))))),
(i32 (InstN $vec, ARMVCCThen, $pred))>; (i32 (InstN $vec, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (ARMVADDVu (VTI.Vec MQPR:$vec))), def : Pat<(i32 (ARMVADDVu (VTI.Vec MQPR:$vec))),
(i32 (InstN $vec))>; (i32 (InstN $vec))>;
def : Pat<(i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))), def : Pat<(i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
(i32 (InstN $vec, ARMVCCThen, $pred))>; (i32 (InstN $vec, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec MQPR:$vec))), def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec MQPR:$vec))),
(i32 tGPREven:$acc))), (i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec))>; (i32 (InstA $acc, $vec))>;
def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred), def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec MQPR:$vec), (VTI.Vec MQPR:$vec),
(VTI.Vec ARMimmAllZerosV))))), (VTI.Vec ARMimmAllZerosV))))),
(i32 tGPREven:$acc))), (i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec, ARMVCCThen, $pred))>; (i32 (InstA $acc, $vec, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (add (i32 (ARMVADDVu (VTI.Vec MQPR:$vec))), def : Pat<(i32 (add (i32 (ARMVADDVu (VTI.Vec MQPR:$vec))),
(i32 tGPREven:$acc))), (i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec))>; (i32 (InstA $acc, $vec))>;
def : Pat<(i32 (add (i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))), def : Pat<(i32 (add (i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
(i32 tGPREven:$acc))), (i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec, ARMVCCThen, $pred))>; (i32 (InstA $acc, $vec, ARMVCCThen, $pred, zero_reg))>;
} else { } else {
def : Pat<(i32 (ARMVADDVs (VTI.Vec MQPR:$vec))), def : Pat<(i32 (ARMVADDVs (VTI.Vec MQPR:$vec))),
(i32 (InstN $vec))>; (i32 (InstN $vec))>;
def : Pat<(i32 (add (i32 (ARMVADDVs (VTI.Vec MQPR:$vec))), def : Pat<(i32 (add (i32 (ARMVADDVs (VTI.Vec MQPR:$vec))),
(i32 tGPREven:$acc))), (i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec))>; (i32 (InstA $acc, $vec))>;
def : Pat<(i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))), def : Pat<(i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
(i32 (InstN $vec, ARMVCCThen, $pred))>; (i32 (InstN $vec, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (add (i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))), def : Pat<(i32 (add (i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
(i32 tGPREven:$acc))), (i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec, ARMVCCThen, $pred))>; (i32 (InstA $acc, $vec, ARMVCCThen, $pred, zero_reg))>;
} }
def : Pat<(i32 (int_arm_mve_addv_predicated (VTI.Vec MQPR:$vec), def : Pat<(i32 (int_arm_mve_addv_predicated (VTI.Vec MQPR:$vec),
(i32 VTI.Unsigned), (i32 VTI.Unsigned),
(VTI.Pred VCCR:$pred))), (VTI.Pred VCCR:$pred))),
(i32 (InstN $vec, ARMVCCThen, $pred))>; (i32 (InstN $vec, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (add (int_arm_mve_addv_predicated (VTI.Vec MQPR:$vec), def : Pat<(i32 (add (int_arm_mve_addv_predicated (VTI.Vec MQPR:$vec),
(i32 VTI.Unsigned), (i32 VTI.Unsigned),
(VTI.Pred VCCR:$pred)), (VTI.Pred VCCR:$pred)),
(i32 tGPREven:$acc))), (i32 tGPREven:$acc))),
(i32 (InstA $acc, $vec, ARMVCCThen, $pred))>; (i32 (InstA $acc, $vec, ARMVCCThen, $pred, zero_reg))>;
} }
} }
defm MVE_VADDVs8 : MVE_VADDV_A<MVE_v16s8>; defm MVE_VADDVs8 : MVE_VADDV_A<MVE_v16s8>;
defm MVE_VADDVs16 : MVE_VADDV_A<MVE_v8s16>; defm MVE_VADDVs16 : MVE_VADDV_A<MVE_v8s16>;
defm MVE_VADDVs32 : MVE_VADDV_A<MVE_v4s32>; defm MVE_VADDVs32 : MVE_VADDV_A<MVE_v4s32>;
defm MVE_VADDVu8 : MVE_VADDV_A<MVE_v16u8>; defm MVE_VADDVu8 : MVE_VADDV_A<MVE_v16u8>;
defm MVE_VADDVu16 : MVE_VADDV_A<MVE_v8u16>; defm MVE_VADDVu16 : MVE_VADDV_A<MVE_v8u16>;
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Linesmulticlass MVE_VADDLV_A<MVEVectorVTInfo VTI> {
defvar ARMVADDLVAp = SDNode<"ARMISD::VADDLVAp" # letter, SDTVecReduceLPA>; defvar ARMVADDLVAp = SDNode<"ARMISD::VADDLVAp" # letter, SDTVecReduceLPA>;
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
def : Pat<(ARMVADDLV (v4i32 MQPR:$vec)), def : Pat<(ARMVADDLV (v4i32 MQPR:$vec)),
(InstN (v4i32 MQPR:$vec))>; (InstN (v4i32 MQPR:$vec))>;
def : Pat<(ARMVADDLVA tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec)), def : Pat<(ARMVADDLVA tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec)),
(InstA tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec))>; (InstA tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec))>;
def : Pat<(ARMVADDLVp (v4i32 MQPR:$vec), (VTI.Pred VCCR:$pred)), def : Pat<(ARMVADDLVp (v4i32 MQPR:$vec), (VTI.Pred VCCR:$pred)),
(InstN (v4i32 MQPR:$vec), ARMVCCThen, (VTI.Pred VCCR:$pred))>; (InstN (v4i32 MQPR:$vec), ARMVCCThen, (VTI.Pred VCCR:$pred), zero_reg)>;
def : Pat<(ARMVADDLVAp tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec), def : Pat<(ARMVADDLVAp tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec),
(VTI.Pred VCCR:$pred)), (VTI.Pred VCCR:$pred)),
(InstA tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec), (InstA tGPREven:$acclo, tGPROdd:$acchi, (v4i32 MQPR:$vec),
ARMVCCThen, (VTI.Pred VCCR:$pred))>; ARMVCCThen, (VTI.Pred VCCR:$pred), zero_reg)>;
} }
} }
defm MVE_VADDLVs32 : MVE_VADDLV_A<MVE_v4s32>; defm MVE_VADDLVs32 : MVE_VADDLV_A<MVE_v4s32>;
defm MVE_VADDLVu32 : MVE_VADDLV_A<MVE_v4u32>; defm MVE_VADDLVu32 : MVE_VADDLV_A<MVE_v4u32>;
class MVE_VMINMAXNMV<string iname, string suffix, bit sz, class MVE_VMINMAXNMV<string iname, string suffix, bit sz,
bit bit_17, bit bit_7, list<dag> pattern=[]> bit bit_17, bit bit_7, list<dag> pattern=[]>
Show All 34 Lines def : Pat<(Scalar (unpred_intr (Scalar ScalarReg:$prev),
(COPY_TO_REGCLASS (Inst (COPY_TO_REGCLASS ScalarReg:$prev, rGPR), (COPY_TO_REGCLASS (Inst (COPY_TO_REGCLASS ScalarReg:$prev, rGPR),
(VTI.Vec MQPR:$vec)), (VTI.Vec MQPR:$vec)),
ScalarReg)>; ScalarReg)>;
def : Pat<(Scalar (pred_intr (Scalar ScalarReg:$prev), def : Pat<(Scalar (pred_intr (Scalar ScalarReg:$prev),
(VTI.Vec MQPR:$vec), (VTI.Vec MQPR:$vec),
(VTI.Pred VCCR:$pred))), (VTI.Pred VCCR:$pred))),
(COPY_TO_REGCLASS (Inst (COPY_TO_REGCLASS ScalarReg:$prev, rGPR), (COPY_TO_REGCLASS (Inst (COPY_TO_REGCLASS ScalarReg:$prev, rGPR),
(VTI.Vec MQPR:$vec), (VTI.Vec MQPR:$vec),
ARMVCCThen, (VTI.Pred VCCR:$pred)), ARMVCCThen, (VTI.Pred VCCR:$pred), zero_reg),
ScalarReg)>; ScalarReg)>;
} }
} }
multiclass MVE_VMINMAXNMV_fty<string iname, bit notAbs, bit isMin, multiclass MVE_VMINMAXNMV_fty<string iname, bit notAbs, bit isMin,
string intrBase> { string intrBase> {
defm f32 : MVE_VMINMAXNMV_p<iname, notAbs, isMin, MVE_v4f32, intrBase, defm f32 : MVE_VMINMAXNMV_p<iname, notAbs, isMin, MVE_v4f32, intrBase,
f32, SPR>; f32, SPR>;
Show All 38 Linesmulticlass MVE_VMINMAXV_p<string iname, bit notAbs, bit isMin,
defvar args = !if(notAbs, !con(base_args, (? (i32 VTI.Unsigned))), defvar args = !if(notAbs, !con(base_args, (? (i32 VTI.Unsigned))),
base_args); base_args);
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
def : Pat<(i32 !con(args, (unpred_intr))), def : Pat<(i32 !con(args, (unpred_intr))),
(i32 (Inst (i32 rGPR:$prev), (VTI.Vec MQPR:$vec)))>; (i32 (Inst (i32 rGPR:$prev), (VTI.Vec MQPR:$vec)))>;
def : Pat<(i32 !con(args, (pred_intr (VTI.Pred VCCR:$pred)))), def : Pat<(i32 !con(args, (pred_intr (VTI.Pred VCCR:$pred)))),
(i32 (Inst (i32 rGPR:$prev), (VTI.Vec MQPR:$vec), (i32 (Inst (i32 rGPR:$prev), (VTI.Vec MQPR:$vec),
ARMVCCThen, (VTI.Pred VCCR:$pred)))>; ARMVCCThen, (VTI.Pred VCCR:$pred), zero_reg))>;
} }
} }
multiclass MVE_VMINMAXV_ty<string iname, bit isMin, string intrBaseName> { multiclass MVE_VMINMAXV_ty<string iname, bit isMin, string intrBaseName> {
defm s8 : MVE_VMINMAXV_p<iname, 1, isMin, MVE_v16s8, intrBaseName>; defm s8 : MVE_VMINMAXV_p<iname, 1, isMin, MVE_v16s8, intrBaseName>;
defm s16: MVE_VMINMAXV_p<iname, 1, isMin, MVE_v8s16, intrBaseName>; defm s16: MVE_VMINMAXV_p<iname, 1, isMin, MVE_v8s16, intrBaseName>;
defm s32: MVE_VMINMAXV_p<iname, 1, isMin, MVE_v4s32, intrBaseName>; defm s32: MVE_VMINMAXV_p<iname, 1, isMin, MVE_v4s32, intrBaseName>;
defm u8 : MVE_VMINMAXV_p<iname, 1, isMin, MVE_v16u8, intrBaseName>; defm u8 : MVE_VMINMAXV_p<iname, 1, isMin, MVE_v16u8, intrBaseName>;
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines def : Pat<(i32 (int_arm_mve_vmldava_predicated
(i32 VTI.Unsigned), (i32 VTI.Unsigned),
(i32 bit_0) /* subtract */, (i32 bit_0) /* subtract */,
(i32 X) /* exchange */, (i32 X) /* exchange */,
(i32 0) /* accumulator */, (i32 0) /* accumulator */,
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
(VTI.Pred VCCR:$mask))), (VTI.Pred VCCR:$mask))),
(i32 (!cast<Instruction>(NAME # x # VTI.Suffix) (i32 (!cast<Instruction>(NAME # x # VTI.Suffix)
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
ARMVCCThen, (VTI.Pred VCCR:$mask)))>; ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg))>;
def : Pat<(i32 (int_arm_mve_vmldava def : Pat<(i32 (int_arm_mve_vmldava
(i32 VTI.Unsigned), (i32 VTI.Unsigned),
(i32 bit_0) /* subtract */, (i32 bit_0) /* subtract */,
(i32 X) /* exchange */, (i32 X) /* exchange */,
(i32 tGPREven:$RdaSrc), (i32 tGPREven:$RdaSrc),
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm))),
(i32 (!cast<Instruction>(NAME # "a" # x # VTI.Suffix) (i32 (!cast<Instruction>(NAME # "a" # x # VTI.Suffix)
(i32 tGPREven:$RdaSrc), (i32 tGPREven:$RdaSrc),
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm)))>; (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm)))>;
def : Pat<(i32 (int_arm_mve_vmldava_predicated def : Pat<(i32 (int_arm_mve_vmldava_predicated
(i32 VTI.Unsigned), (i32 VTI.Unsigned),
(i32 bit_0) /* subtract */, (i32 bit_0) /* subtract */,
(i32 X) /* exchange */, (i32 X) /* exchange */,
(i32 tGPREven:$RdaSrc), (i32 tGPREven:$RdaSrc),
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
(VTI.Pred VCCR:$mask))), (VTI.Pred VCCR:$mask))),
(i32 (!cast<Instruction>(NAME # "a" # x # VTI.Suffix) (i32 (!cast<Instruction>(NAME # "a" # x # VTI.Suffix)
(i32 tGPREven:$RdaSrc), (i32 tGPREven:$RdaSrc),
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
ARMVCCThen, (VTI.Pred VCCR:$mask)))>; ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg))>;
} }
} }
multiclass MVE_VMLAMLSDAV_AX<string iname, MVEVectorVTInfo VTI, bit sz, multiclass MVE_VMLAMLSDAV_AX<string iname, MVEVectorVTInfo VTI, bit sz,
bit bit_28, bit bit_8, bit bit_0> { bit bit_28, bit bit_8, bit bit_0> {
defm "" : MVE_VMLAMLSDAV_A<iname, "", VTI, sz, bit_28, defm "" : MVE_VMLAMLSDAV_A<iname, "", VTI, sz, bit_28,
0b0, bit_8, bit_0>; 0b0, bit_8, bit_0>;
defm "" : MVE_VMLAMLSDAV_A<iname, "x", VTI, sz, bit_28, defm "" : MVE_VMLAMLSDAV_A<iname, "x", VTI, sz, bit_28,
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines def : Pat<(i32 (add (ARMVMLAVs (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)), tGPREven:$Rd)),
(i32 (MVE_VMLADAVas8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>; (i32 (MVE_VMLADAVas8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
def : Pat<(i32 (add (ARMVMLAVu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)), tGPREven:$Rd)), def : Pat<(i32 (add (ARMVMLAVu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)), tGPREven:$Rd)),
(i32 (MVE_VMLADAVau8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>; (i32 (MVE_VMLADAVau8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
// Predicated // Predicated
def : Pat<(i32 (vecreduce_add (vselect (v4i1 VCCR:$pred), def : Pat<(i32 (vecreduce_add (vselect (v4i1 VCCR:$pred),
(mul (v4i32 MQPR:$src1), (v4i32 MQPR:$src2)), (mul (v4i32 MQPR:$src1), (v4i32 MQPR:$src2)),
(v4i32 ARMimmAllZerosV)))), (v4i32 ARMimmAllZerosV)))),
(i32 (MVE_VMLADAVu32 $src1, $src2, ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVu32 $src1, $src2, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (vecreduce_add (vselect (v8i1 VCCR:$pred), def : Pat<(i32 (vecreduce_add (vselect (v8i1 VCCR:$pred),
(mul (v8i16 MQPR:$src1), (v8i16 MQPR:$src2)), (mul (v8i16 MQPR:$src1), (v8i16 MQPR:$src2)),
(v8i16 ARMimmAllZerosV)))), (v8i16 ARMimmAllZerosV)))),
(i32 (MVE_VMLADAVu16 $src1, $src2, ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVu16 $src1, $src2, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (ARMVMLAVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred))), def : Pat<(i32 (ARMVMLAVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred))),
(i32 (MVE_VMLADAVs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (ARMVMLAVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred))), def : Pat<(i32 (ARMVMLAVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred))),
(i32 (MVE_VMLADAVu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (vecreduce_add (vselect (v16i1 VCCR:$pred), def : Pat<(i32 (vecreduce_add (vselect (v16i1 VCCR:$pred),
(mul (v16i8 MQPR:$src1), (v16i8 MQPR:$src2)), (mul (v16i8 MQPR:$src1), (v16i8 MQPR:$src2)),
(v16i8 ARMimmAllZerosV)))), (v16i8 ARMimmAllZerosV)))),
(i32 (MVE_VMLADAVu8 $src1, $src2, ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVu8 $src1, $src2, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (ARMVMLAVps (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred))), def : Pat<(i32 (ARMVMLAVps (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred))),
(i32 (MVE_VMLADAVs8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVs8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (ARMVMLAVpu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred))), def : Pat<(i32 (ARMVMLAVpu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred))),
(i32 (MVE_VMLADAVu8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVu8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v4i1 VCCR:$pred), def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v4i1 VCCR:$pred),
(mul (v4i32 MQPR:$src1), (v4i32 MQPR:$src2)), (mul (v4i32 MQPR:$src1), (v4i32 MQPR:$src2)),
(v4i32 ARMimmAllZerosV)))), (v4i32 ARMimmAllZerosV)))),
(i32 tGPREven:$src3))), (i32 tGPREven:$src3))),
(i32 (MVE_VMLADAVau32 $src3, $src1, $src2, ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVau32 $src3, $src1, $src2, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v8i1 VCCR:$pred), def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v8i1 VCCR:$pred),
(mul (v8i16 MQPR:$src1), (v8i16 MQPR:$src2)), (mul (v8i16 MQPR:$src1), (v8i16 MQPR:$src2)),
(v8i16 ARMimmAllZerosV)))), (v8i16 ARMimmAllZerosV)))),
(i32 tGPREven:$src3))), (i32 tGPREven:$src3))),
(i32 (MVE_VMLADAVau16 $src3, $src1, $src2, ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVau16 $src3, $src1, $src2, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (add (ARMVMLAVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), tGPREven:$Rd)), def : Pat<(i32 (add (ARMVMLAVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), tGPREven:$Rd)),
(i32 (MVE_VMLADAVas16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVas16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (add (ARMVMLAVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), tGPREven:$Rd)), def : Pat<(i32 (add (ARMVMLAVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), tGPREven:$Rd)),
(i32 (MVE_VMLADAVau16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVau16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v16i1 VCCR:$pred), def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v16i1 VCCR:$pred),
(mul (v16i8 MQPR:$src1), (v16i8 MQPR:$src2)), (mul (v16i8 MQPR:$src1), (v16i8 MQPR:$src2)),
(v16i8 ARMimmAllZerosV)))), (v16i8 ARMimmAllZerosV)))),
(i32 tGPREven:$src3))), (i32 tGPREven:$src3))),
(i32 (MVE_VMLADAVau8 $src3, $src1, $src2, ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVau8 $src3, $src1, $src2, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (add (ARMVMLAVps (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred)), tGPREven:$Rd)), def : Pat<(i32 (add (ARMVMLAVps (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred)), tGPREven:$Rd)),
(i32 (MVE_VMLADAVas8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVas8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
def : Pat<(i32 (add (ARMVMLAVpu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred)), tGPREven:$Rd)), def : Pat<(i32 (add (ARMVMLAVpu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred)), tGPREven:$Rd)),
(i32 (MVE_VMLADAVau8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred))>; (i32 (MVE_VMLADAVau8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred, zero_reg))>;
} }
// vmlav aliases vmladav // vmlav aliases vmladav
foreach acc = ["", "a"] in { foreach acc = ["", "a"] in {
foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32"] in { foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32"] in {
def : MVEInstAlias<"vmlav"#acc#"${vp}."#suffix#"\t$RdaDest, $Qn, $Qm", def : MVEInstAlias<"vmlav"#acc#"${vp}."#suffix#"\t$RdaDest, $Qn, $Qm",
(!cast<Instruction>("MVE_VMLADAV"#acc#suffix) (!cast<Instruction>("MVE_VMLADAV"#acc#suffix)
tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>; tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Lines def : Pat<(ARMVMLALVAu tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)),
(MVE_VMLALDAVau32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))>; (MVE_VMLALDAVau32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))>;
def : Pat<(ARMVMLALVAs tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)), def : Pat<(ARMVMLALVAs tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)),
(MVE_VMLALDAVas16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))>; (MVE_VMLALDAVas16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))>;
def : Pat<(ARMVMLALVAu tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)), def : Pat<(ARMVMLALVAu tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)),
(MVE_VMLALDAVau16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))>; (MVE_VMLALDAVau16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))>;
// Predicated // Predicated
def : Pat<(ARMVMLALVps (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)), def : Pat<(ARMVMLALVps (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)),
(MVE_VMLALDAVs32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred)>; (MVE_VMLALDAVs32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
def : Pat<(ARMVMLALVpu (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)), def : Pat<(ARMVMLALVpu (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)),
(MVE_VMLALDAVu32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred)>; (MVE_VMLALDAVu32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
def : Pat<(ARMVMLALVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), def : Pat<(ARMVMLALVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)),
(MVE_VMLALDAVs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred)>; (MVE_VMLALDAVs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
def : Pat<(ARMVMLALVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), def : Pat<(ARMVMLALVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)),
(MVE_VMLALDAVu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred)>; (MVE_VMLALDAVu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
def : Pat<(ARMVMLALVAps tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)), def : Pat<(ARMVMLALVAps tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)),
(MVE_VMLALDAVas32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred)>; (MVE_VMLALDAVas32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
def : Pat<(ARMVMLALVApu tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)), def : Pat<(ARMVMLALVApu tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)),
(MVE_VMLALDAVau32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred)>; (MVE_VMLALDAVau32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
def : Pat<(ARMVMLALVAps tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), def : Pat<(ARMVMLALVAps tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)),
(MVE_VMLALDAVas16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred)>; (MVE_VMLALDAVas16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
def : Pat<(ARMVMLALVApu tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), def : Pat<(ARMVMLALVApu tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)),
(MVE_VMLALDAVau16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred)>; (MVE_VMLALDAVau16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred, zero_reg)>;
} }
// vmlalv aliases vmlaldav // vmlalv aliases vmlaldav
foreach acc = ["", "a"] in { foreach acc = ["", "a"] in {
foreach suffix = ["s16", "s32", "u16", "u32"] in { foreach suffix = ["s16", "s32", "u16", "u32"] in {
def : MVEInstAlias<"vmlalv" # acc # "${vp}." # suffix # def : MVEInstAlias<"vmlalv" # acc # "${vp}." # suffix #
"\t$RdaLoDest, $RdaHiDest, $Qn, $Qm", "\t$RdaLoDest, $RdaHiDest, $Qn, $Qm",
(!cast<Instruction>("MVE_VMLALDAV"#acc#suffix) (!cast<Instruction>("MVE_VMLALDAV"#acc#suffix)
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Linesmulticlass MVE_VREV_basic_patterns<int revbits, list<MVEVectorVTInfo> VTIs,
defvar unpred_op = !cast<SDNode>("ARMvrev" # revbits); defvar unpred_op = !cast<SDNode>("ARMvrev" # revbits);
foreach VTI = VTIs in { foreach VTI = VTIs in {
def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$src))), def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$src))),
(VTI.Vec (Inst (VTI.Vec MQPR:$src)))>; (VTI.Vec (Inst (VTI.Vec MQPR:$src)))>;
def : Pat<(VTI.Vec (int_arm_mve_vrev_predicated (VTI.Vec MQPR:$src), def : Pat<(VTI.Vec (int_arm_mve_vrev_predicated (VTI.Vec MQPR:$src),
revbits, (VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive))), revbits, (VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst (VTI.Vec MQPR:$src), ARMVCCThen, (VTI.Vec (Inst (VTI.Vec MQPR:$src), ARMVCCThen,
(VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive)))>; (VTI.Pred VCCR:$pred), zero_reg, (VTI.Vec MQPR:$inactive)))>;
} }
} }
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
defm: MVE_VREV_basic_patterns<64, [MVE_v4i32, MVE_v4f32], MVE_VREV64_32>; defm: MVE_VREV_basic_patterns<64, [MVE_v4i32, MVE_v4f32], MVE_VREV64_32>;
defm: MVE_VREV_basic_patterns<64, [MVE_v8i16, MVE_v8f16], MVE_VREV64_16>; defm: MVE_VREV_basic_patterns<64, [MVE_v8i16, MVE_v8f16], MVE_VREV64_16>;
defm: MVE_VREV_basic_patterns<64, [MVE_v16i8 ], MVE_VREV64_8>; defm: MVE_VREV_basic_patterns<64, [MVE_v16i8 ], MVE_VREV64_8>;
Show All 16 Lines
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
foreach VTI = [ MVE_v16i8, MVE_v8i16, MVE_v4i32, MVE_v2i64 ] in { foreach VTI = [ MVE_v16i8, MVE_v8i16, MVE_v4i32, MVE_v2i64 ] in {
def : Pat<(VTI.Vec (vnotq (VTI.Vec MQPR:$val1))), def : Pat<(VTI.Vec (vnotq (VTI.Vec MQPR:$val1))),
(VTI.Vec (MVE_VMVN (VTI.Vec MQPR:$val1)))>; (VTI.Vec (MVE_VMVN (VTI.Vec MQPR:$val1)))>;
def : Pat<(VTI.Vec (int_arm_mve_mvn_predicated (VTI.Vec MQPR:$val1), def : Pat<(VTI.Vec (int_arm_mve_mvn_predicated (VTI.Vec MQPR:$val1),
(VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive))), (VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (MVE_VMVN (VTI.Vec MQPR:$val1), ARMVCCThen, (VTI.Vec (MVE_VMVN (VTI.Vec MQPR:$val1), ARMVCCThen,
(VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive)))>; (VTI.Pred VCCR:$pred), zero_reg, (VTI.Vec MQPR:$inactive)))>;
} }
} }
class MVE_bit_ops<string iname, bits<2> bit_21_20, bit bit_28> class MVE_bit_ops<string iname, bits<2> bit_21_20, bit bit_28>
: MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
iname, "", "$Qd, $Qn, $Qm", ""> { iname, "", "$Qd, $Qn, $Qm", ""> {
bits<4> Qn; bits<4> Qn;
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Linesmulticlass MVE_bit_cmode_p<string iname, bit opcode,
defvar UnpredPat = (VTI.Vec (op (VTI.Vec MQPR:$src), timm:$simm)); defvar UnpredPat = (VTI.Vec (op (VTI.Vec MQPR:$src), timm:$simm));
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
def : Pat<UnpredPat, def : Pat<UnpredPat,
(VTI.Vec (Inst (VTI.Vec MQPR:$src), imm_type:$simm))>; (VTI.Vec (Inst (VTI.Vec MQPR:$src), imm_type:$simm))>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred), def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
UnpredPat, (VTI.Vec MQPR:$src))), UnpredPat, (VTI.Vec MQPR:$src))),
(VTI.Vec (Inst (VTI.Vec MQPR:$src), imm_type:$simm, (VTI.Vec (Inst (VTI.Vec MQPR:$src), imm_type:$simm,
ARMVCCThen, (VTI.Pred VCCR:$pred)))>; ARMVCCThen, (VTI.Pred VCCR:$pred), zero_reg))>;
} }
} }
multiclass MVE_VORRimm<MVEVectorVTInfo VTI, Operand imm_type> { multiclass MVE_VORRimm<MVEVectorVTInfo VTI, Operand imm_type> {
defm "": MVE_bit_cmode_p<"vorr", 0, VTI, imm_type, ARMvorrImm>; defm "": MVE_bit_cmode_p<"vorr", 0, VTI, imm_type, ARMvorrImm>;
} }
multiclass MVE_VBICimm<MVEVectorVTInfo VTI, Operand imm_type> { multiclass MVE_VBICimm<MVEVectorVTInfo VTI, Operand imm_type> {
defm "": MVE_bit_cmode_p<"vbic", 1, VTI, imm_type, ARMvbicImm>; defm "": MVE_bit_cmode_p<"vbic", 1, VTI, imm_type, ARMvbicImm>;
▲ Show 20 Lines • Show All 465 Lines • ▼ Show 20 Lines def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
(i32 VTI.Unsigned))), (i32 VTI.Unsigned))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>; (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
// Predicated add-with-divide-by-two // Predicated add-with-divide-by-two
def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
(i32 VTI.Unsigned), (VTI.Pred VCCR:$mask), (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
(VTI.Vec MQPR:$inactive))), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
} }
multiclass MVE_VRHADD<MVEVectorVTInfo VTI> multiclass MVE_VRHADD<MVEVectorVTInfo VTI>
: MVE_VRHADD_m<VTI, int_arm_mve_vrhadd, int_arm_mve_rhadd_predicated>; : MVE_VRHADD_m<VTI, int_arm_mve_vrhadd, int_arm_mve_rhadd_predicated>;
defm MVE_VRHADDs8 : MVE_VRHADD<MVE_v16s8>; defm MVE_VRHADDs8 : MVE_VRHADD<MVE_v16s8>;
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines let Predicates = [HasMVEInt] in {
def : Pat<(VTI.Vec (shift_op (add_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)), (i32 1))), def : Pat<(VTI.Vec (shift_op (add_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)), (i32 1))),
(Inst MQPR:$Qm, MQPR:$Qn)>; (Inst MQPR:$Qm, MQPR:$Qn)>;
// Predicated add-and-divide-by-two // Predicated add-and-divide-by-two
def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (i32 VTI.Unsigned), def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (i32 VTI.Unsigned),
(VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))), (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
} }
multiclass MVE_VHADD<MVEVectorVTInfo VTI, PatFrag add_op, SDNode shift_op> multiclass MVE_VHADD<MVEVectorVTInfo VTI, PatFrag add_op, SDNode shift_op>
: MVE_VHADD_m<VTI, int_arm_mve_vhadd, int_arm_mve_hadd_predicated, add_op, : MVE_VHADD_m<VTI, int_arm_mve_vhadd, int_arm_mve_hadd_predicated, add_op,
shift_op>; shift_op>;
Show All 24 Lines def : Pat<(VTI.Vec (shift_op (sub_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)), (i32 1))),
(Inst MQPR:$Qm, MQPR:$Qn)>; (Inst MQPR:$Qm, MQPR:$Qn)>;
// Predicated subtract-and-divide-by-two // Predicated subtract-and-divide-by-two
def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
(i32 VTI.Unsigned), (VTI.Pred VCCR:$mask), (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
(VTI.Vec MQPR:$inactive))), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
} }
multiclass MVE_VHSUB<MVEVectorVTInfo VTI, PatFrag sub_op, SDNode shift_op> multiclass MVE_VHSUB<MVEVectorVTInfo VTI, PatFrag sub_op, SDNode shift_op>
: MVE_VHSUB_m<VTI, int_arm_mve_vhsub, int_arm_mve_hsub_predicated, sub_op, : MVE_VHSUB_m<VTI, int_arm_mve_vhsub, int_arm_mve_hsub_predicated, sub_op,
shift_op>; shift_op>;
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines def : Pat<(v8f16 (ARMvdup (i32 rGPR:$elem))),
(MVE_VDUP16 rGPR:$elem)>; (MVE_VDUP16 rGPR:$elem)>;
def : Pat<(v4f32 (ARMvdup (i32 rGPR:$elem))), def : Pat<(v4f32 (ARMvdup (i32 rGPR:$elem))),
(MVE_VDUP32 rGPR:$elem)>; (MVE_VDUP32 rGPR:$elem)>;
// Match a vselect with an ARMvdup as a predicated MVE_VDUP // Match a vselect with an ARMvdup as a predicated MVE_VDUP
def : Pat<(v16i8 (vselect (v16i1 VCCR:$pred), def : Pat<(v16i8 (vselect (v16i1 VCCR:$pred),
(v16i8 (ARMvdup (i32 rGPR:$elem))), (v16i8 (ARMvdup (i32 rGPR:$elem))),
(v16i8 MQPR:$inactive))), (v16i8 MQPR:$inactive))),
(MVE_VDUP8 rGPR:$elem, ARMVCCThen, (v16i1 VCCR:$pred), (MVE_VDUP8 rGPR:$elem, ARMVCCThen, (v16i1 VCCR:$pred), zero_reg,
(v16i8 MQPR:$inactive))>; (v16i8 MQPR:$inactive))>;
def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred), def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred),
(v8i16 (ARMvdup (i32 rGPR:$elem))), (v8i16 (ARMvdup (i32 rGPR:$elem))),
(v8i16 MQPR:$inactive))), (v8i16 MQPR:$inactive))),
(MVE_VDUP16 rGPR:$elem, ARMVCCThen, (v8i1 VCCR:$pred), (MVE_VDUP16 rGPR:$elem, ARMVCCThen, (v8i1 VCCR:$pred), zero_reg,
(v8i16 MQPR:$inactive))>; (v8i16 MQPR:$inactive))>;
def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred), def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred),
(v4i32 (ARMvdup (i32 rGPR:$elem))), (v4i32 (ARMvdup (i32 rGPR:$elem))),
(v4i32 MQPR:$inactive))), (v4i32 MQPR:$inactive))),
(MVE_VDUP32 rGPR:$elem, ARMVCCThen, (v4i1 VCCR:$pred), (MVE_VDUP32 rGPR:$elem, ARMVCCThen, (v4i1 VCCR:$pred), zero_reg,
(v4i32 MQPR:$inactive))>; (v4i32 MQPR:$inactive))>;
def : Pat<(v4f32 (vselect (v4i1 VCCR:$pred), def : Pat<(v4f32 (vselect (v4i1 VCCR:$pred),
(v4f32 (ARMvdup (i32 rGPR:$elem))), (v4f32 (ARMvdup (i32 rGPR:$elem))),
(v4f32 MQPR:$inactive))), (v4f32 MQPR:$inactive))),
(MVE_VDUP32 rGPR:$elem, ARMVCCThen, (v4i1 VCCR:$pred), (MVE_VDUP32 rGPR:$elem, ARMVCCThen, (v4i1 VCCR:$pred), zero_reg,
(v4f32 MQPR:$inactive))>; (v4f32 MQPR:$inactive))>;
def : Pat<(v8f16 (vselect (v8i1 VCCR:$pred), def : Pat<(v8f16 (vselect (v8i1 VCCR:$pred),
(v8f16 (ARMvdup (i32 rGPR:$elem))), (v8f16 (ARMvdup (i32 rGPR:$elem))),
(v8f16 MQPR:$inactive))), (v8f16 MQPR:$inactive))),
(MVE_VDUP16 rGPR:$elem, ARMVCCThen, (v8i1 VCCR:$pred), (MVE_VDUP16 rGPR:$elem, ARMVCCThen, (v8i1 VCCR:$pred), zero_reg,
(v8f16 MQPR:$inactive))>; (v8f16 MQPR:$inactive))>;
} }
class MVEIntSingleSrc<string iname, string suffix, bits<2> size, class MVEIntSingleSrc<string iname, string suffix, bits<2> size,
list<dag> pattern=[]> list<dag> pattern=[]>
: MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qm), NoItinerary, : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qm), NoItinerary,
iname, suffix, "$Qd, $Qm", vpred_r, "", pattern> { iname, suffix, "$Qd, $Qm", vpred_r, "", pattern> {
Show All 31 Linesmulticlass MVE_VCLSCLZ_p<string opname, bit opcode, MVEVectorVTInfo VTI,
defvar pred_int = !cast<Intrinsic>("int_arm_mve_"#opname#"_predicated"); defvar pred_int = !cast<Intrinsic>("int_arm_mve_"#opname#"_predicated");
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$val))), def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$val))),
(VTI.Vec (Inst (VTI.Vec MQPR:$val)))>; (VTI.Vec (Inst (VTI.Vec MQPR:$val)))>;
def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$val), (VTI.Pred VCCR:$pred), def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$val), (VTI.Pred VCCR:$pred),
(VTI.Vec MQPR:$inactive))), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst (VTI.Vec MQPR:$val), ARMVCCThen, (VTI.Vec (Inst (VTI.Vec MQPR:$val), ARMVCCThen,
(VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive)))>; (VTI.Pred VCCR:$pred), zero_reg, (VTI.Vec MQPR:$inactive)))>;
} }
} }
defm MVE_VCLSs8 : MVE_VCLSCLZ_p<"cls", 0, MVE_v16s8, int_arm_mve_vcls>; defm MVE_VCLSs8 : MVE_VCLSCLZ_p<"cls", 0, MVE_v16s8, int_arm_mve_vcls>;
defm MVE_VCLSs16 : MVE_VCLSCLZ_p<"cls", 0, MVE_v8s16, int_arm_mve_vcls>; defm MVE_VCLSs16 : MVE_VCLSCLZ_p<"cls", 0, MVE_v8s16, int_arm_mve_vcls>;
defm MVE_VCLSs32 : MVE_VCLSCLZ_p<"cls", 0, MVE_v4s32, int_arm_mve_vcls>; defm MVE_VCLSs32 : MVE_VCLSCLZ_p<"cls", 0, MVE_v4s32, int_arm_mve_vcls>;
defm MVE_VCLZs8 : MVE_VCLSCLZ_p<"clz", 1, MVE_v16i8, ctlz>; defm MVE_VCLZs8 : MVE_VCLSCLZ_p<"clz", 1, MVE_v16i8, ctlz>;
Show All 29 Lines let Predicates = [HasMVEInt] in {
// VQABS and VQNEG have more difficult isel patterns defined elsewhere // VQABS and VQNEG have more difficult isel patterns defined elsewhere
if !not(saturate) then { if !not(saturate) then {
def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$v))), def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$v))),
(VTI.Vec (Inst $v))>; (VTI.Vec (Inst $v))>;
} }
def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$v), (VTI.Pred VCCR:$mask), def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$v), (VTI.Pred VCCR:$mask),
(VTI.Vec MQPR:$inactive))), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst $v, ARMVCCThen, $mask, $inactive))>; (VTI.Vec (Inst $v, ARMVCCThen, $mask, zero_reg, $inactive))>;
} }
} }
foreach VTI = [ MVE_v16s8, MVE_v8s16, MVE_v4s32 ] in { foreach VTI = [ MVE_v16s8, MVE_v8s16, MVE_v4s32 ] in {
defm "MVE_VABS" # VTI.Suffix : MVE_VABSNEG_int_m< defm "MVE_VABS" # VTI.Suffix : MVE_VABSNEG_int_m<
"vabs", 0, 0, abs, int_arm_mve_abs_predicated, VTI>; "vabs", 0, 0, abs, int_arm_mve_abs_predicated, VTI>;
defm "MVE_VQABS" # VTI.Suffix : MVE_VABSNEG_int_m< defm "MVE_VQABS" # VTI.Suffix : MVE_VABSNEG_int_m<
"vqabs", 0, 1, ?, int_arm_mve_qabs_predicated, VTI>; "vqabs", 0, 1, ?, int_arm_mve_qabs_predicated, VTI>;
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines def : Pat<(v4i32 (ARMvmvnImm timm:$simm)),
(v4i32 (MVE_VMVNimmi32 nImmVMOVI32:$simm))>; (v4i32 (MVE_VMVNimmi32 nImmVMOVI32:$simm))>;
def : Pat<(v4f32 (ARMvmovFPImm timm:$simm)), def : Pat<(v4f32 (ARMvmovFPImm timm:$simm)),
(v4f32 (MVE_VMOVimmf32 nImmVMOVF32:$simm))>; (v4f32 (MVE_VMOVimmf32 nImmVMOVF32:$simm))>;
def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred), (ARMvmvnImm timm:$simm), def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred), (ARMvmvnImm timm:$simm),
MQPR:$inactive)), MQPR:$inactive)),
(v8i16 (MVE_VMVNimmi16 nImmSplatI16:$simm, (v8i16 (MVE_VMVNimmi16 nImmSplatI16:$simm,
ARMVCCThen, VCCR:$pred, MQPR:$inactive))>; ARMVCCThen, VCCR:$pred, zero_reg, MQPR:$inactive))>;
def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred), (ARMvmvnImm timm:$simm), def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred), (ARMvmvnImm timm:$simm),
MQPR:$inactive)), MQPR:$inactive)),
(v4i32 (MVE_VMVNimmi32 nImmSplatI32:$simm, (v4i32 (MVE_VMVNimmi32 nImmSplatI32:$simm,
ARMVCCThen, VCCR:$pred, MQPR:$inactive))>; ARMVCCThen, VCCR:$pred, zero_reg, MQPR:$inactive))>;
} }
class MVE_VMINMAXA<string iname, string suffix, bits<2> size, class MVE_VMINMAXA<string iname, string suffix, bits<2> size,
bit bit_12, list<dag> pattern=[]> bit bit_12, list<dag> pattern=[]>
: MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm), : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
NoItinerary, iname, suffix, "$Qd, $Qm", vpred_n, "$Qd = $Qd_src", NoItinerary, iname, suffix, "$Qd, $Qm", vpred_n, "$Qd = $Qd_src",
pattern> { pattern> {
bits<4> Qd; bits<4> Qd;
Show All 24 Lines let Predicates = [HasMVEInt] in {
// Unpredicated v(min|max)a // Unpredicated v(min|max)a
def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qd), (abs (VTI.Vec MQPR:$Qm)))), def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qd), (abs (VTI.Vec MQPR:$Qm)))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm)))>; (VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm)))>;
// Predicated v(min|max)a // Predicated v(min|max)a
def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm), def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm),
(VTI.Pred VCCR:$mask))), (VTI.Pred VCCR:$mask))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm), (VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm),
ARMVCCThen, (VTI.Pred VCCR:$mask)))>; ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg))>;
} }
} }
multiclass MVE_VMINA<MVEVectorVTInfo VTI> multiclass MVE_VMINA<MVEVectorVTInfo VTI>
: MVE_VMINMAXA_m<"vmina", VTI, umin, int_arm_mve_vmina_predicated, 0b1>; : MVE_VMINMAXA_m<"vmina", VTI, umin, int_arm_mve_vmina_predicated, 0b1>;
defm MVE_VMINAs8 : MVE_VMINA<MVE_v16s8>; defm MVE_VMINAs8 : MVE_VMINA<MVE_v16s8>;
defm MVE_VMINAs16 : MVE_VMINA<MVE_v8s16>; defm MVE_VMINAs16 : MVE_VMINA<MVE_v8s16>;
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines def "": MVE_VMOVL<"vmovl" # chr, InVTI.Suffix, OutVTI.Size,
InVTI.Unsigned, top>; InVTI.Unsigned, top>;
defvar Inst = !cast<Instruction>(NAME); defvar Inst = !cast<Instruction>(NAME);
def : Pat<(OutVTI.Vec (int_arm_mve_vmovl_predicated (InVTI.Vec MQPR:$src), def : Pat<(OutVTI.Vec (int_arm_mve_vmovl_predicated (InVTI.Vec MQPR:$src),
(i32 InVTI.Unsigned), (i32 top), (i32 InVTI.Unsigned), (i32 top),
(OutVTI.Pred VCCR:$pred), (OutVTI.Pred VCCR:$pred),
(OutVTI.Vec MQPR:$inactive))), (OutVTI.Vec MQPR:$inactive))),
(OutVTI.Vec (Inst (InVTI.Vec MQPR:$src), ARMVCCThen, (OutVTI.Vec (Inst (InVTI.Vec MQPR:$src), ARMVCCThen,
(OutVTI.Pred VCCR:$pred), (OutVTI.Pred VCCR:$pred), zero_reg,
(OutVTI.Vec MQPR:$inactive)))>; (OutVTI.Vec MQPR:$inactive)))>;
} }
defm MVE_VMOVLs8bh : MVE_VMOVL_m<0, "b", MVE_v8s16, MVE_v16s8>; defm MVE_VMOVLs8bh : MVE_VMOVL_m<0, "b", MVE_v8s16, MVE_v16s8>;
defm MVE_VMOVLs8th : MVE_VMOVL_m<1, "t", MVE_v8s16, MVE_v16s8>; defm MVE_VMOVLs8th : MVE_VMOVL_m<1, "t", MVE_v8s16, MVE_v16s8>;
defm MVE_VMOVLu8bh : MVE_VMOVL_m<0, "b", MVE_v8u16, MVE_v16u8>; defm MVE_VMOVLu8bh : MVE_VMOVL_m<0, "b", MVE_v8u16, MVE_v16u8>;
defm MVE_VMOVLu8th : MVE_VMOVL_m<1, "t", MVE_v8u16, MVE_v16u8>; defm MVE_VMOVLu8th : MVE_VMOVL_m<1, "t", MVE_v8u16, MVE_v16u8>;
defm MVE_VMOVLs16bh : MVE_VMOVL_m<0, "b", MVE_v4s32, MVE_v8s16>; defm MVE_VMOVLs16bh : MVE_VMOVL_m<0, "b", MVE_v4s32, MVE_v8s16>;
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines def : Pat<(VTI.DblVec (unpred_int (VTI.Vec MQPR:$src), (i32 VTI.LaneBits),
(i32 VTI.Unsigned), (i32 top))), (i32 VTI.Unsigned), (i32 top))),
(VTI.DblVec (inst_lw (VTI.Vec MQPR:$src)))>; (VTI.DblVec (inst_lw (VTI.Vec MQPR:$src)))>;
def : Pat<(VTI.DblVec (pred_int (VTI.Vec MQPR:$src), imm:$imm, def : Pat<(VTI.DblVec (pred_int (VTI.Vec MQPR:$src), imm:$imm,
(i32 VTI.Unsigned), (i32 top), (i32 VTI.Unsigned), (i32 top),
(VTI.DblPred VCCR:$mask), (VTI.DblPred VCCR:$mask),
(VTI.DblVec MQPR:$inactive))), (VTI.DblVec MQPR:$inactive))),
(VTI.DblVec (inst_imm (VTI.Vec MQPR:$src), imm:$imm, (VTI.DblVec (inst_imm (VTI.Vec MQPR:$src), imm:$imm,
ARMVCCThen, (VTI.DblPred VCCR:$mask), ARMVCCThen, (VTI.DblPred VCCR:$mask), zero_reg,
(VTI.DblVec MQPR:$inactive)))>; (VTI.DblVec MQPR:$inactive)))>;
def : Pat<(VTI.DblVec (pred_int (VTI.Vec MQPR:$src), (i32 VTI.LaneBits), def : Pat<(VTI.DblVec (pred_int (VTI.Vec MQPR:$src), (i32 VTI.LaneBits),
(i32 VTI.Unsigned), (i32 top), (i32 VTI.Unsigned), (i32 top),
(VTI.DblPred VCCR:$mask), (VTI.DblPred VCCR:$mask),
(VTI.DblVec MQPR:$inactive))), (VTI.DblVec MQPR:$inactive))),
(VTI.DblVec (inst_lw (VTI.Vec MQPR:$src), ARMVCCThen, (VTI.DblVec (inst_lw (VTI.Vec MQPR:$src), ARMVCCThen,
(VTI.DblPred VCCR:$mask), (VTI.DblPred VCCR:$mask), zero_reg,
(VTI.DblVec MQPR:$inactive)))>; (VTI.DblVec MQPR:$inactive)))>;
} }
foreach VTI = [MVE_v16s8, MVE_v8s16, MVE_v16u8, MVE_v8u16] in foreach VTI = [MVE_v16s8, MVE_v8s16, MVE_v16u8, MVE_v8u16] in
foreach top = [0, 1] in foreach top = [0, 1] in
defm : MVE_VSHLL_patterns<VTI, top>; defm : MVE_VSHLL_patterns<VTI, top>;
class MVE_shift_imm_partial<Operand imm, string iname, string suffix> class MVE_shift_imm_partial<Operand imm, string iname, string suffix>
▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines defvar inparams = (? (OutVTI.Vec MQPR:$QdSrc), (InVTI.Vec MQPR:$Qm),
(i32 OutVTI.Unsigned), (i32 InVTI.Unsigned), (i32 top)); (i32 OutVTI.Unsigned), (i32 InVTI.Unsigned), (i32 top));
defvar outparams = (inst (OutVTI.Vec MQPR:$QdSrc), (InVTI.Vec MQPR:$Qm), defvar outparams = (inst (OutVTI.Vec MQPR:$QdSrc), (InVTI.Vec MQPR:$Qm),
(imm:$imm)); (imm:$imm));
def : Pat<(OutVTI.Vec !setdagop(inparams, int_arm_mve_vshrn)), def : Pat<(OutVTI.Vec !setdagop(inparams, int_arm_mve_vshrn)),
(OutVTI.Vec outparams)>; (OutVTI.Vec outparams)>;
def : Pat<(OutVTI.Vec !con(inparams, (int_arm_mve_vshrn_predicated def : Pat<(OutVTI.Vec !con(inparams, (int_arm_mve_vshrn_predicated
(InVTI.Pred VCCR:$pred)))), (InVTI.Pred VCCR:$pred)))),
(OutVTI.Vec !con(outparams, (? ARMVCCThen, VCCR:$pred)))>; (OutVTI.Vec !con(outparams, (? ARMVCCThen, VCCR:$pred, zero_reg)))>;
} }
defm : MVE_VSHRN_patterns<MVE_VSHRNi16bh, MVE_v16s8, MVE_v8s16, 0,0,0>; defm : MVE_VSHRN_patterns<MVE_VSHRNi16bh, MVE_v16s8, MVE_v8s16, 0,0,0>;
defm : MVE_VSHRN_patterns<MVE_VSHRNi16th, MVE_v16s8, MVE_v8s16, 0,0,1>; defm : MVE_VSHRN_patterns<MVE_VSHRNi16th, MVE_v16s8, MVE_v8s16, 0,0,1>;
defm : MVE_VSHRN_patterns<MVE_VSHRNi32bh, MVE_v8s16, MVE_v4s32, 0,0,0>; defm : MVE_VSHRN_patterns<MVE_VSHRNi32bh, MVE_v8s16, MVE_v4s32, 0,0,0>;
defm : MVE_VSHRN_patterns<MVE_VSHRNi32th, MVE_v8s16, MVE_v4s32, 0,0,1>; defm : MVE_VSHRN_patterns<MVE_VSHRNi32th, MVE_v8s16, MVE_v4s32, 0,0,1>;
defm : MVE_VSHRN_patterns<MVE_VSHRNi16bh, MVE_v16u8, MVE_v8u16, 0,0,0>; defm : MVE_VSHRN_patterns<MVE_VSHRNi16bh, MVE_v16u8, MVE_v8u16, 0,0,0>;
defm : MVE_VSHRN_patterns<MVE_VSHRNi16th, MVE_v16u8, MVE_v8u16, 0,0,1>; defm : MVE_VSHRN_patterns<MVE_VSHRNi16th, MVE_v16u8, MVE_v8u16, 0,0,1>;
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines def : Pat<(VTI.Vec (int_arm_mve_vshl_vector
(i32 q), (i32 r), (i32 VTI.Unsigned))), (i32 q), (i32 r), (i32 VTI.Unsigned))),
(VTI.Vec (Inst (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh)))>; (VTI.Vec (Inst (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh)))>;
def : Pat<(VTI.Vec (int_arm_mve_vshl_vector_predicated def : Pat<(VTI.Vec (int_arm_mve_vshl_vector_predicated
(VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh), (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh),
(i32 q), (i32 r), (i32 VTI.Unsigned), (i32 q), (i32 r), (i32 VTI.Unsigned),
(VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))), (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh), (VTI.Vec (Inst (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
multiclass mve_shift_by_vec_multi<string iname, bit bit_4, bit bit_8> { multiclass mve_shift_by_vec_multi<string iname, bit bit_4, bit bit_8> {
defm s8 : MVE_shift_by_vec_p<iname, MVE_v16s8, bit_4, bit_8>; defm s8 : MVE_shift_by_vec_p<iname, MVE_v16s8, bit_4, bit_8>;
defm s16 : MVE_shift_by_vec_p<iname, MVE_v8s16, bit_4, bit_8>; defm s16 : MVE_shift_by_vec_p<iname, MVE_v8s16, bit_4, bit_8>;
defm s32 : MVE_shift_by_vec_p<iname, MVE_v4s32, bit_4, bit_8>; defm s32 : MVE_shift_by_vec_p<iname, MVE_v4s32, bit_4, bit_8>;
defm u8 : MVE_shift_by_vec_p<iname, MVE_v16u8, bit_4, bit_8>; defm u8 : MVE_shift_by_vec_p<iname, MVE_v16u8, bit_4, bit_8>;
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Linesmulticlass MVE_VSxI_patterns<MVE_VSxI_imm inst, string name,
defvar outparams = (inst (VTI.Vec MQPR:$QdSrc), (VTI.Vec MQPR:$Qm), defvar outparams = (inst (VTI.Vec MQPR:$QdSrc), (VTI.Vec MQPR:$Qm),
(inst.immediateType:$imm)); (inst.immediateType:$imm));
defvar unpred_int = !cast<Intrinsic>("int_arm_mve_" # name); defvar unpred_int = !cast<Intrinsic>("int_arm_mve_" # name);
defvar pred_int = !cast<Intrinsic>("int_arm_mve_" # name # "_predicated"); defvar pred_int = !cast<Intrinsic>("int_arm_mve_" # name # "_predicated");
def : Pat<(VTI.Vec !setdagop(inparams, unpred_int)), def : Pat<(VTI.Vec !setdagop(inparams, unpred_int)),
(VTI.Vec outparams)>; (VTI.Vec outparams)>;
def : Pat<(VTI.Vec !con(inparams, (pred_int (VTI.Pred VCCR:$pred)))), def : Pat<(VTI.Vec !con(inparams, (pred_int (VTI.Pred VCCR:$pred)))),
(VTI.Vec !con(outparams, (? ARMVCCThen, VCCR:$pred)))>; (VTI.Vec !con(outparams, (? ARMVCCThen, VCCR:$pred, zero_reg)))>;
} }
defm : MVE_VSxI_patterns<MVE_VSLIimm8, "vsli", MVE_v16i8>; defm : MVE_VSxI_patterns<MVE_VSLIimm8, "vsli", MVE_v16i8>;
defm : MVE_VSxI_patterns<MVE_VSLIimm16, "vsli", MVE_v8i16>; defm : MVE_VSxI_patterns<MVE_VSLIimm16, "vsli", MVE_v8i16>;
defm : MVE_VSxI_patterns<MVE_VSLIimm32, "vsli", MVE_v4i32>; defm : MVE_VSxI_patterns<MVE_VSLIimm32, "vsli", MVE_v4i32>;
defm : MVE_VSxI_patterns<MVE_VSRIimm8, "vsri", MVE_v16i8>; defm : MVE_VSxI_patterns<MVE_VSRIimm8, "vsri", MVE_v16i8>;
defm : MVE_VSxI_patterns<MVE_VSRIimm16, "vsri", MVE_v8i16>; defm : MVE_VSxI_patterns<MVE_VSRIimm16, "vsri", MVE_v8i16>;
defm : MVE_VSxI_patterns<MVE_VSRIimm32, "vsri", MVE_v4i32>; defm : MVE_VSxI_patterns<MVE_VSRIimm32, "vsri", MVE_v4i32>;
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Linesmulticlass MVE_shift_imm_patterns<MVE_shift_with_imm inst> {
def : Pat<(inst.VTI.Vec !con((inst.pred_int (inst.VTI.Vec MQPR:$src), def : Pat<(inst.VTI.Vec !con((inst.pred_int (inst.VTI.Vec MQPR:$src),
inst.immediateType:$imm), inst.immediateType:$imm),
inst.unsignedFlag, inst.unsignedFlag,
(? (inst.VTI.Pred VCCR:$mask), (? (inst.VTI.Pred VCCR:$mask),
(inst.VTI.Vec MQPR:$inactive)))), (inst.VTI.Vec MQPR:$inactive)))),
(inst.VTI.Vec (inst (inst.VTI.Vec MQPR:$src), (inst.VTI.Vec (inst (inst.VTI.Vec MQPR:$src),
inst.immediateType:$imm, inst.immediateType:$imm,
ARMVCCThen, (inst.VTI.Pred VCCR:$mask), ARMVCCThen, (inst.VTI.Pred VCCR:$mask), zero_reg,
(inst.VTI.Vec MQPR:$inactive)))>; (inst.VTI.Vec MQPR:$inactive)))>;
} }
defm : MVE_shift_imm_patterns<MVE_VQSHLimms8>; defm : MVE_shift_imm_patterns<MVE_VQSHLimms8>;
defm : MVE_shift_imm_patterns<MVE_VQSHLimmu8>; defm : MVE_shift_imm_patterns<MVE_VQSHLimmu8>;
defm : MVE_shift_imm_patterns<MVE_VQSHLimms16>; defm : MVE_shift_imm_patterns<MVE_VQSHLimms16>;
defm : MVE_shift_imm_patterns<MVE_VQSHLimmu16>; defm : MVE_shift_imm_patterns<MVE_VQSHLimmu16>;
defm : MVE_shift_imm_patterns<MVE_VQSHLimms32>; defm : MVE_shift_imm_patterns<MVE_VQSHLimms32>;
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Linesmulticlass MVE_immediate_shift_patterns_inner<
def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$src), imm_operand_type:$imm)), def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$src), imm_operand_type:$imm)),
(VTI.Vec (inst (VTI.Vec MQPR:$src), imm_operand_type:$imm))>; (VTI.Vec (inst (VTI.Vec MQPR:$src), imm_operand_type:$imm))>;
def : Pat<(VTI.Vec !con((pred_int (VTI.Vec MQPR:$src), imm_operand_type:$imm), def : Pat<(VTI.Vec !con((pred_int (VTI.Vec MQPR:$src), imm_operand_type:$imm),
!dag(pred_int, unsignedFlag, ?), !dag(pred_int, unsignedFlag, ?),
(pred_int (VTI.Pred VCCR:$mask), (pred_int (VTI.Pred VCCR:$mask),
(VTI.Vec MQPR:$inactive)))), (VTI.Vec MQPR:$inactive)))),
(VTI.Vec (inst (VTI.Vec MQPR:$src), imm_operand_type:$imm, (VTI.Vec (inst (VTI.Vec MQPR:$src), imm_operand_type:$imm,
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
multiclass MVE_immediate_shift_patterns<MVEVectorVTInfo VTI, multiclass MVE_immediate_shift_patterns<MVEVectorVTInfo VTI,
Operand imm_operand_type> { Operand imm_operand_type> {
defm : MVE_immediate_shift_patterns_inner<VTI, imm_operand_type, defm : MVE_immediate_shift_patterns_inner<VTI, imm_operand_type,
ARMvshlImm, int_arm_mve_shl_imm_predicated, ARMvshlImm, int_arm_mve_shl_imm_predicated,
!cast<Instruction>("MVE_VSHL_immi" # VTI.BitsSuffix)>; !cast<Instruction>("MVE_VSHL_immi" # VTI.BitsSuffix)>;
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Linesmulticlass MVE_VRINT_m<MVEVectorVTInfo VTI, string suffix, bits<3> opcode,
defvar pred_int = !cast<Intrinsic>("int_arm_mve_vrint"#suffix#"_predicated"); defvar pred_int = !cast<Intrinsic>("int_arm_mve_vrint"#suffix#"_predicated");
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$val))), def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$val))),
(VTI.Vec (Inst (VTI.Vec MQPR:$val)))>; (VTI.Vec (Inst (VTI.Vec MQPR:$val)))>;
def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$val), (VTI.Pred VCCR:$pred), def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$val), (VTI.Pred VCCR:$pred),
(VTI.Vec MQPR:$inactive))), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst (VTI.Vec MQPR:$val), ARMVCCThen, (VTI.Vec (Inst (VTI.Vec MQPR:$val), ARMVCCThen,
(VTI.Pred VCCR:$pred), (VTI.Vec MQPR:$inactive)))>; (VTI.Pred VCCR:$pred), zero_reg, (VTI.Vec MQPR:$inactive)))>;
} }
} }
multiclass MVE_VRINT_ops<MVEVectorVTInfo VTI> { multiclass MVE_VRINT_ops<MVEVectorVTInfo VTI> {
defm N : MVE_VRINT_m<VTI, "n", 0b000, int_arm_mve_vrintn>; defm N : MVE_VRINT_m<VTI, "n", 0b000, int_arm_mve_vrintn>;
defm X : MVE_VRINT_m<VTI, "x", 0b001, frint>; defm X : MVE_VRINT_m<VTI, "x", 0b001, frint>;
defm A : MVE_VRINT_m<VTI, "a", 0b010, fround>; defm A : MVE_VRINT_m<VTI, "a", 0b010, fround>;
defm Z : MVE_VRINT_m<VTI, "z", 0b011, ftrunc>; defm Z : MVE_VRINT_m<VTI, "z", 0b011, ftrunc>;
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines def : Pat<(VTI.Vec (int_arm_mve_vcmlaq
imm:$rot))>; imm:$rot))>;
def : Pat<(VTI.Vec (int_arm_mve_vcmlaq_predicated def : Pat<(VTI.Vec (int_arm_mve_vcmlaq_predicated
imm:$rot, (VTI.Vec MQPR:$Qd_src), imm:$rot, (VTI.Vec MQPR:$Qd_src),
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
(VTI.Pred VCCR:$mask))), (VTI.Pred VCCR:$mask))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src), (VTI.Vec MQPR:$Qn), (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src), (VTI.Vec MQPR:$Qn),
(VTI.Vec MQPR:$Qm), imm:$rot, (VTI.Vec MQPR:$Qm), imm:$rot,
ARMVCCThen, (VTI.Pred VCCR:$mask)))>; ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg))>;
} }
} }
defm MVE_VCMLAf16 : MVE_VCMLA_m<MVE_v8f16, 0b0>; defm MVE_VCMLAf16 : MVE_VCMLA_m<MVE_v8f16, 0b0>;
defm MVE_VCMLAf32 : MVE_VCMLA_m<MVE_v4f32, 0b1>; defm MVE_VCMLAf32 : MVE_VCMLA_m<MVE_v4f32, 0b1>;
class MVE_VADDSUBFMA_fp<string iname, string suffix, bit size, bit bit_4, class MVE_VADDSUBFMA_fp<string iname, string suffix, bit size, bit bit_4,
Show All 31 Linesmulticlass MVE_VFMA_fp_multi<string iname, bit fms, MVEVectorVTInfo VTI> {
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
if fms then { if fms then {
def : Pat<(VTI.Vec (fma (fneg m1), m2, add)), def : Pat<(VTI.Vec (fma (fneg m1), m2, add)),
(Inst $add, $m1, $m2)>; (Inst $add, $m1, $m2)>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred), def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma (fneg m1), m2, add)), (VTI.Vec (fma (fneg m1), m2, add)),
add)), add)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>; (Inst $add, $m1, $m2, ARMVCCThen, $pred, zero_reg)>;
def : Pat<(VTI.Vec (pred_int (fneg m1), m2, add, pred)), def : Pat<(VTI.Vec (pred_int (fneg m1), m2, add, pred)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>; (Inst $add, $m1, $m2, ARMVCCThen, $pred, zero_reg)>;
def : Pat<(VTI.Vec (pred_int m1, (fneg m2), add, pred)), def : Pat<(VTI.Vec (pred_int m1, (fneg m2), add, pred)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>; (Inst $add, $m1, $m2, ARMVCCThen, $pred, zero_reg)>;
} else { } else {
def : Pat<(VTI.Vec (fma m1, m2, add)), def : Pat<(VTI.Vec (fma m1, m2, add)),
(Inst $add, $m1, $m2)>; (Inst $add, $m1, $m2)>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred), def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma m1, m2, add)), (VTI.Vec (fma m1, m2, add)),
add)), add)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>; (Inst $add, $m1, $m2, ARMVCCThen, $pred, zero_reg)>;
def : Pat<(VTI.Vec (pred_int m1, m2, add, pred)), def : Pat<(VTI.Vec (pred_int m1, m2, add, pred)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>; (Inst $add, $m1, $m2, ARMVCCThen, $pred, zero_reg)>;
} }
} }
} }
defm MVE_VFMAf32 : MVE_VFMA_fp_multi<"vfma", 0, MVE_v4f32>; defm MVE_VFMAf32 : MVE_VFMA_fp_multi<"vfma", 0, MVE_v4f32>;
defm MVE_VFMAf16 : MVE_VFMA_fp_multi<"vfma", 0, MVE_v8f16>; defm MVE_VFMAf16 : MVE_VFMA_fp_multi<"vfma", 0, MVE_v8f16>;
defm MVE_VFMSf32 : MVE_VFMA_fp_multi<"vfms", 1, MVE_v4f32>; defm MVE_VFMSf32 : MVE_VFMA_fp_multi<"vfms", 1, MVE_v4f32>;
defm MVE_VFMSf16 : MVE_VFMA_fp_multi<"vfms", 1, MVE_v8f16>; defm MVE_VFMSf16 : MVE_VFMA_fp_multi<"vfms", 1, MVE_v8f16>;
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines def : Pat<(VTI.Vec (int_arm_mve_vcaddq (i32 1),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
imm:$rot))>; imm:$rot))>;
def : Pat<(VTI.Vec (int_arm_mve_vcaddq_predicated (i32 1), def : Pat<(VTI.Vec (int_arm_mve_vcaddq_predicated (i32 1),
imm:$rot, (VTI.Vec MQPR:$inactive), imm:$rot, (VTI.Vec MQPR:$inactive),
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
(VTI.Pred VCCR:$mask))), (VTI.Pred VCCR:$mask))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
imm:$rot, ARMVCCThen, (VTI.Pred VCCR:$mask), imm:$rot, ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
} }
defm MVE_VCADDf16 : MVE_VCADD_m<MVE_v8f16, 0b0>; defm MVE_VCADDf16 : MVE_VCADD_m<MVE_v8f16, 0b0>;
defm MVE_VCADDf32 : MVE_VCADD_m<MVE_v4f32, 0b1, "@earlyclobber $Qd">; defm MVE_VCADDf32 : MVE_VCADD_m<MVE_v4f32, 0b1, "@earlyclobber $Qd">;
Show All 25 Linesmulticlass MVE_VABDT_fp_m<MVEVectorVTInfo VTI,
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
(i32 0))), (i32 0))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>; (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
(i32 0), (VTI.Pred VCCR:$mask), (i32 0), (VTI.Pred VCCR:$mask),
(VTI.Vec MQPR:$inactive))), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
} }
multiclass MVE_VABD_fp_m<MVEVectorVTInfo VTI> multiclass MVE_VABD_fp_m<MVEVectorVTInfo VTI>
: MVE_VABDT_fp_m<VTI, int_arm_mve_vabd, int_arm_mve_abd_predicated>; : MVE_VABDT_fp_m<VTI, int_arm_mve_vabd, int_arm_mve_abd_predicated>;
defm MVE_VABDf32 : MVE_VABD_fp_m<MVE_v4f32>; defm MVE_VABDf32 : MVE_VABD_fp_m<MVE_v4f32>;
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines def : Pat<(DestVTI.Vec (int_arm_mve_vcvt_fix
(i32 U), (SrcVTI.Vec MQPR:$Qm), imm:$scale)), (i32 U), (SrcVTI.Vec MQPR:$Qm), imm:$scale)),
(DestVTI.Vec (Inst (SrcVTI.Vec MQPR:$Qm), imm:$scale))>; (DestVTI.Vec (Inst (SrcVTI.Vec MQPR:$Qm), imm:$scale))>;
def : Pat<(DestVTI.Vec (int_arm_mve_vcvt_fix_predicated (i32 U), def : Pat<(DestVTI.Vec (int_arm_mve_vcvt_fix_predicated (i32 U),
(DestVTI.Vec MQPR:$inactive), (DestVTI.Vec MQPR:$inactive),
(SrcVTI.Vec MQPR:$Qm), (SrcVTI.Vec MQPR:$Qm),
imm:$scale, imm:$scale,
(DestVTI.Pred VCCR:$mask))), (DestVTI.Pred VCCR:$mask))),
(DestVTI.Vec (Inst (SrcVTI.Vec MQPR:$Qm), imm:$scale, (DestVTI.Vec (Inst (SrcVTI.Vec MQPR:$Qm), imm:$scale,
ARMVCCThen, (DestVTI.Pred VCCR:$mask), ARMVCCThen, (DestVTI.Pred VCCR:$mask), zero_reg,
(DestVTI.Vec MQPR:$inactive)))>; (DestVTI.Vec MQPR:$inactive)))>;
} }
} }
multiclass MVE_VCVT_fix_f32_m<bit U, bit op, multiclass MVE_VCVT_fix_f32_m<bit U, bit op,
MVEVectorVTInfo DestVTI, MVEVectorVTInfo SrcVTI> { MVEVectorVTInfo DestVTI, MVEVectorVTInfo SrcVTI> {
def "" : MVE_VCVT_fix_f32<DestVTI.Suffix#"."#SrcVTI.Suffix, U, op>; def "" : MVE_VCVT_fix_f32<DestVTI.Suffix#"."#SrcVTI.Suffix, U, op>;
defm : MVE_VCVT_fix_patterns<!cast<Instruction>(NAME), U, DestVTI, SrcVTI>; defm : MVE_VCVT_fix_patterns<!cast<Instruction>(NAME), U, DestVTI, SrcVTI>;
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Linesmulticlass MVE_VCVT_fp_int_anpm_inner<MVEVectorVTInfo Int, MVEVectorVTInfo Flt,
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
def : Pat<(Int.Vec (UnpredIntr (i32 Int.Unsigned), (Flt.Vec MQPR:$in))), def : Pat<(Int.Vec (UnpredIntr (i32 Int.Unsigned), (Flt.Vec MQPR:$in))),
(Int.Vec (Inst (Flt.Vec MQPR:$in)))>; (Int.Vec (Inst (Flt.Vec MQPR:$in)))>;
def : Pat<(Int.Vec (PredIntr (i32 Int.Unsigned), (Int.Vec MQPR:$inactive), def : Pat<(Int.Vec (PredIntr (i32 Int.Unsigned), (Int.Vec MQPR:$inactive),
(Flt.Vec MQPR:$in), (Flt.Pred VCCR:$pred))), (Flt.Vec MQPR:$in), (Flt.Pred VCCR:$pred))),
(Int.Vec (Inst (Flt.Vec MQPR:$in), ARMVCCThen, (Int.Vec (Inst (Flt.Vec MQPR:$in), ARMVCCThen,
(Flt.Pred VCCR:$pred), (Int.Vec MQPR:$inactive)))>; (Flt.Pred VCCR:$pred), zero_reg, (Int.Vec MQPR:$inactive)))>;
} }
} }
multiclass MVE_VCVT_fp_int_anpm_outer<MVEVectorVTInfo Int, multiclass MVE_VCVT_fp_int_anpm_outer<MVEVectorVTInfo Int,
MVEVectorVTInfo Flt> { MVEVectorVTInfo Flt> {
defm a : MVE_VCVT_fp_int_anpm_inner<Int, Flt, "a", 0b00>; defm a : MVE_VCVT_fp_int_anpm_inner<Int, Flt, "a", 0b00>;
defm n : MVE_VCVT_fp_int_anpm_inner<Int, Flt, "n", 0b01>; defm n : MVE_VCVT_fp_int_anpm_inner<Int, Flt, "n", 0b01>;
defm p : MVE_VCVT_fp_int_anpm_inner<Int, Flt, "p", 0b10>; defm p : MVE_VCVT_fp_int_anpm_inner<Int, Flt, "p", 0b10>;
Show All 39 Linesmulticlass MVE_VCVT_fp_int_m<MVEVectorVTInfo Dest, MVEVectorVTInfo Src,
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
def : Pat<(Dest.Vec (unpred_op (Src.Vec MQPR:$src))), def : Pat<(Dest.Vec (unpred_op (Src.Vec MQPR:$src))),
(Dest.Vec (Inst (Src.Vec MQPR:$src)))>; (Dest.Vec (Inst (Src.Vec MQPR:$src)))>;
def : Pat<(Dest.Vec (int_arm_mve_vcvt_fp_int_predicated def : Pat<(Dest.Vec (int_arm_mve_vcvt_fp_int_predicated
(Src.Vec MQPR:$src), (i32 Unsigned), (Src.Vec MQPR:$src), (i32 Unsigned),
(Src.Pred VCCR:$mask), (Dest.Vec MQPR:$inactive))), (Src.Pred VCCR:$mask), (Dest.Vec MQPR:$inactive))),
(Dest.Vec (Inst (Src.Vec MQPR:$src), ARMVCCThen, (Dest.Vec (Inst (Src.Vec MQPR:$src), ARMVCCThen,
(Src.Pred VCCR:$mask), (Src.Pred VCCR:$mask), zero_reg,
(Dest.Vec MQPR:$inactive)))>; (Dest.Vec MQPR:$inactive)))>;
} }
} }
// The unsuffixed VCVT for float->int implicitly rounds toward zero, // The unsuffixed VCVT for float->int implicitly rounds toward zero,
// which I reflect here in the llvm instruction names // which I reflect here in the llvm instruction names
defm MVE_VCVTs16f16z : MVE_VCVT_fp_int_m<MVE_v8s16, MVE_v8f16, fp_to_sint>; defm MVE_VCVTs16f16z : MVE_VCVT_fp_int_m<MVE_v8s16, MVE_v8f16, fp_to_sint>;
defm MVE_VCVTu16f16z : MVE_VCVT_fp_int_m<MVE_v8u16, MVE_v8f16, fp_to_uint>; defm MVE_VCVTu16f16z : MVE_VCVT_fp_int_m<MVE_v8u16, MVE_v8f16, fp_to_uint>;
defm MVE_VCVTs32f32z : MVE_VCVT_fp_int_m<MVE_v4s32, MVE_v4f32, fp_to_sint>; defm MVE_VCVTs32f32z : MVE_VCVT_fp_int_m<MVE_v4s32, MVE_v4f32, fp_to_sint>;
Show All 39 Linesmulticlass MVE_VABSNEG_fp_m<string iname, SDNode unpred_op, Intrinsic pred_int,
def "" : MVE_VABSNEG_fp<iname, VTI.Suffix, VTI.Size, opcode>; def "" : MVE_VABSNEG_fp<iname, VTI.Suffix, VTI.Size, opcode>;
defvar Inst = !cast<Instruction>(NAME); defvar Inst = !cast<Instruction>(NAME);
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$v))), def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$v))),
(VTI.Vec (Inst $v))>; (VTI.Vec (Inst $v))>;
def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$v), (VTI.Pred VCCR:$mask), def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$v), (VTI.Pred VCCR:$mask),
(VTI.Vec MQPR:$inactive))), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst $v, ARMVCCThen, $mask, $inactive))>; (VTI.Vec (Inst $v, ARMVCCThen, $mask, zero_reg, $inactive))>;
} }
} }
defm MVE_VABSf16 : MVE_VABSNEG_fp_m<"vabs", fabs, int_arm_mve_abs_predicated, defm MVE_VABSf16 : MVE_VABSNEG_fp_m<"vabs", fabs, int_arm_mve_abs_predicated,
MVE_v8f16, 0>; MVE_v8f16, 0>;
defm MVE_VABSf32 : MVE_VABSNEG_fp_m<"vabs", fabs, int_arm_mve_abs_predicated, defm MVE_VABSf32 : MVE_VABSNEG_fp_m<"vabs", fabs, int_arm_mve_abs_predicated,
MVE_v4f32, 0>; MVE_v4f32, 0>;
defm MVE_VNEGf16 : MVE_VABSNEG_fp_m<"vneg", fneg, int_arm_mve_neg_predicated, defm MVE_VNEGf16 : MVE_VABSNEG_fp_m<"vneg", fneg, int_arm_mve_neg_predicated,
Show All 36 Lines let Predicates = [HasMVEInt] in {
def : Pat<(VTI.Vec (unpred_op (fabs (VTI.Vec MQPR:$Qd)), def : Pat<(VTI.Vec (unpred_op (fabs (VTI.Vec MQPR:$Qd)),
(fabs (VTI.Vec MQPR:$Qm)))), (fabs (VTI.Vec MQPR:$Qm)))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm)))>; (VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm)))>;
// Predicated v(max|min)nma // Predicated v(max|min)nma
def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm), def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm),
(VTI.Pred VCCR:$mask))), (VTI.Pred VCCR:$mask))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm), (VTI.Vec (Inst (VTI.Vec MQPR:$Qd), (VTI.Vec MQPR:$Qm),
ARMVCCThen, (VTI.Pred VCCR:$mask)))>; ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg))>;
} }
} }
multiclass MVE_VMAXNMA<MVEVectorVTInfo VTI, bit bit_12> multiclass MVE_VMAXNMA<MVEVectorVTInfo VTI, bit bit_12>
: MVE_VMAXMINNMA_m<"vmaxnma", VTI, fmaxnum, int_arm_mve_vmaxnma_predicated, bit_12>; : MVE_VMAXMINNMA_m<"vmaxnma", VTI, fmaxnum, int_arm_mve_vmaxnma_predicated, bit_12>;
defm MVE_VMAXNMAf32 : MVE_VMAXNMA<MVE_v4f32, 0b0>; defm MVE_VMAXNMAf32 : MVE_VMAXNMA<MVE_v4f32, 0b0>;
defm MVE_VMAXNMAf16 : MVE_VMAXNMA<MVE_v8f16, 0b0>; defm MVE_VMAXNMAf16 : MVE_VMAXNMA<MVE_v8f16, 0b0>;
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Linesmulticlass unpred_vcmp_z<string suffix, PatLeaf fc> {
def i8 : Pat<(v16i1 (ARMvcmpz (v16i8 MQPR:$v1), fc)), def i8 : Pat<(v16i1 (ARMvcmpz (v16i8 MQPR:$v1), fc)),
(v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), ZR, fc))>; (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), ZR, fc))>;
def i16 : Pat<(v8i1 (ARMvcmpz (v8i16 MQPR:$v1), fc)), def i16 : Pat<(v8i1 (ARMvcmpz (v8i16 MQPR:$v1), fc)),
(v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), ZR, fc))>; (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), ZR, fc))>;
def i32 : Pat<(v4i1 (ARMvcmpz (v4i32 MQPR:$v1), fc)), def i32 : Pat<(v4i1 (ARMvcmpz (v4i32 MQPR:$v1), fc)),
(v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), ZR, fc))>; (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), ZR, fc))>;
def : Pat<(v16i1 (and (v16i1 VCCR:$p1), (v16i1 (ARMvcmpz (v16i8 MQPR:$v1), fc)))), def : Pat<(v16i1 (and (v16i1 VCCR:$p1), (v16i1 (ARMvcmpz (v16i8 MQPR:$v1), fc)))),
(v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>; (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmpz (v8i16 MQPR:$v1), fc)))), def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmpz (v8i16 MQPR:$v1), fc)))),
(v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>; (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmpz (v4i32 MQPR:$v1), fc)))), def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmpz (v4i32 MQPR:$v1), fc)))),
(v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>; (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
} }
multiclass unpred_vcmp_r<string suffix, PatLeaf fc> { multiclass unpred_vcmp_r<string suffix, PatLeaf fc> {
def i8 : Pat<(v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc)), def i8 : Pat<(v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc)),
(v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8") (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc))>; (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8") (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc))>;
def i16 : Pat<(v8i1 (ARMvcmp (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc)), def i16 : Pat<(v8i1 (ARMvcmp (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc)),
(v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16") (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc))>; (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16") (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc))>;
def i32 : Pat<(v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc)), def i32 : Pat<(v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc)),
(v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32") (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc))>; (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32") (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc))>;
def i8r : Pat<(v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 (ARMvdup rGPR:$v2)), fc)), def i8r : Pat<(v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 (ARMvdup rGPR:$v2)), fc)),
(v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), (i32 rGPR:$v2), fc))>; (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), (i32 rGPR:$v2), fc))>;
def i16r : Pat<(v8i1 (ARMvcmp (v8i16 MQPR:$v1), (v8i16 (ARMvdup rGPR:$v2)), fc)), def i16r : Pat<(v8i1 (ARMvcmp (v8i16 MQPR:$v1), (v8i16 (ARMvdup rGPR:$v2)), fc)),
(v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), (i32 rGPR:$v2), fc))>; (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), (i32 rGPR:$v2), fc))>;
def i32r : Pat<(v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 (ARMvdup rGPR:$v2)), fc)), def i32r : Pat<(v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 (ARMvdup rGPR:$v2)), fc)),
(v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), (i32 rGPR:$v2), fc))>; (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), (i32 rGPR:$v2), fc))>;
def : Pat<(v16i1 (and (v16i1 VCCR:$p1), (v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc)))), def : Pat<(v16i1 (and (v16i1 VCCR:$p1), (v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc)))),
(v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8") (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1))>; (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8") (v16i8 MQPR:$v1), (v16i8 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmp (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc)))), def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmp (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc)))),
(v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16") (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1))>; (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16") (v8i16 MQPR:$v1), (v8i16 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc)))), def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc)))),
(v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32") (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1))>; (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32") (v4i32 MQPR:$v1), (v4i32 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
def : Pat<(v16i1 (and (v16i1 VCCR:$p1), (v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 (ARMvdup rGPR:$v2)), fc)))), def : Pat<(v16i1 (and (v16i1 VCCR:$p1), (v16i1 (ARMvcmp (v16i8 MQPR:$v1), (v16i8 (ARMvdup rGPR:$v2)), fc)))),
(v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1))>; (v16i1 (!cast<Instruction>("MVE_VCMP"#suffix#"8r") (v16i8 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmp (v8i16 MQPR:$v1), (v8i16 (ARMvdup rGPR:$v2)), fc)))), def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmp (v8i16 MQPR:$v1), (v8i16 (ARMvdup rGPR:$v2)), fc)))),
(v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1))>; (v8i1 (!cast<Instruction>("MVE_VCMP"#suffix#"16r") (v8i16 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 (ARMvdup rGPR:$v2)), fc)))), def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4i32 MQPR:$v1), (v4i32 (ARMvdup rGPR:$v2)), fc)))),
(v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1))>; (v4i1 (!cast<Instruction>("MVE_VCMP"#suffix#"32r") (v4i32 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
} }
multiclass unpred_vcmpf_z<PatLeaf fc> { multiclass unpred_vcmpf_z<PatLeaf fc> {
def f16 : Pat<(v8i1 (ARMvcmpz (v8f16 MQPR:$v1), fc)), def f16 : Pat<(v8i1 (ARMvcmpz (v8f16 MQPR:$v1), fc)),
(v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc))>; (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc))>;
def f32 : Pat<(v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)), def f32 : Pat<(v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)),
(v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc))>; (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc))>;
def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmpz (v8f16 MQPR:$v1), fc)))), def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmpz (v8f16 MQPR:$v1), fc)))),
(v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>; (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)))), def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmpz (v4f32 MQPR:$v1), fc)))),
(v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1))>; (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
} }
multiclass unpred_vcmpf_r<PatLeaf fc> { multiclass unpred_vcmpf_r<PatLeaf fc> {
def : Pat<(v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc)), def : Pat<(v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc)),
(v8i1 (MVE_VCMPf16 (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc))>; (v8i1 (MVE_VCMPf16 (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc))>;
def : Pat<(v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc)), def : Pat<(v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc)),
(v4i1 (MVE_VCMPf32 (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc))>; (v4i1 (MVE_VCMPf32 (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc))>;
def : Pat<(v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 (ARMvdup rGPR:$v2)), fc)), def : Pat<(v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 (ARMvdup rGPR:$v2)), fc)),
(v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), (i32 rGPR:$v2), fc))>; (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), (i32 rGPR:$v2), fc))>;
def : Pat<(v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 (ARMvdup rGPR:$v2)), fc)), def : Pat<(v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 (ARMvdup rGPR:$v2)), fc)),
(v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), (i32 rGPR:$v2), fc))>; (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), (i32 rGPR:$v2), fc))>;
def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc)))), def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc)))),
(v8i1 (MVE_VCMPf16 (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1))>; (v8i1 (MVE_VCMPf16 (v8f16 MQPR:$v1), (v8f16 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc)))), def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc)))),
(v4i1 (MVE_VCMPf32 (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1))>; (v4i1 (MVE_VCMPf32 (v4f32 MQPR:$v1), (v4f32 MQPR:$v2), fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 (ARMvdup rGPR:$v2)), fc)))), def : Pat<(v8i1 (and (v8i1 VCCR:$p1), (v8i1 (ARMvcmp (v8f16 MQPR:$v1), (v8f16 (ARMvdup rGPR:$v2)), fc)))),
(v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1))>; (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 (ARMvdup rGPR:$v2)), fc)))), def : Pat<(v4i1 (and (v4i1 VCCR:$p1), (v4i1 (ARMvcmp (v4f32 MQPR:$v1), (v4f32 (ARMvdup rGPR:$v2)), fc)))),
(v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1))>; (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), (i32 rGPR:$v2), fc, ARMVCCThen, VCCR:$p1, zero_reg))>;
} }
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
defm MVE_VCEQZ : unpred_vcmp_z<"i", ARMCCeq>; defm MVE_VCEQZ : unpred_vcmp_z<"i", ARMCCeq>;
defm MVE_VCNEZ : unpred_vcmp_z<"i", ARMCCne>; defm MVE_VCNEZ : unpred_vcmp_z<"i", ARMCCne>;
defm MVE_VCGEZ : unpred_vcmp_z<"s", ARMCCge>; defm MVE_VCGEZ : unpred_vcmp_z<"s", ARMCCge>;
defm MVE_VCLTZ : unpred_vcmp_z<"s", ARMCClt>; defm MVE_VCLTZ : unpred_vcmp_z<"s", ARMCClt>;
defm MVE_VCGTZ : unpred_vcmp_z<"s", ARMCCgt>; defm MVE_VCGTZ : unpred_vcmp_z<"s", ARMCCgt>;
▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines def : Pat<(VTI.Vec !con((unpred_intr (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b),
(VTI.Vec MQPR:$c)), ConstParams)), (VTI.Vec MQPR:$c)), ConstParams)),
(VTI.Vec (Inst (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b), (VTI.Vec (Inst (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b),
(VTI.Vec MQPR:$c)))>; (VTI.Vec MQPR:$c)))>;
def : Pat<(VTI.Vec !con((pred_intr (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b), def : Pat<(VTI.Vec !con((pred_intr (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b),
(VTI.Vec MQPR:$c)), ConstParams, (VTI.Vec MQPR:$c)), ConstParams,
(? (VTI.Pred VCCR:$pred)))), (? (VTI.Pred VCCR:$pred)))),
(VTI.Vec (Inst (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b), (VTI.Vec (Inst (VTI.Vec MQPR:$a), (VTI.Vec MQPR:$b),
(VTI.Vec MQPR:$c), (VTI.Vec MQPR:$c),
ARMVCCThen, (VTI.Pred VCCR:$pred)))>; ARMVCCThen, (VTI.Pred VCCR:$pred), zero_reg))>;
} }
multiclass MVE_VQxDMLxDH_multi<string iname, bit exch, multiclass MVE_VQxDMLxDH_multi<string iname, bit exch,
bit round, bit subtract> { bit round, bit subtract> {
defm s8 : MVE_VQxDMLxDH_p<iname, exch, round, subtract, MVE_v16s8>; defm s8 : MVE_VQxDMLxDH_p<iname, exch, round, subtract, MVE_v16s8>;
defm s16 : MVE_VQxDMLxDH_p<iname, exch, round, subtract, MVE_v8s16>; defm s16 : MVE_VQxDMLxDH_p<iname, exch, round, subtract, MVE_v8s16>;
defm s32 : MVE_VQxDMLxDH_p<iname, exch, round, subtract, MVE_v4s32>; defm s32 : MVE_VQxDMLxDH_p<iname, exch, round, subtract, MVE_v4s32>;
} }
Show All 37 Lines def : Pat<(VTI.Vec (int_arm_mve_vcmulq
(VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
imm:$rot))>; imm:$rot))>;
def : Pat<(VTI.Vec (int_arm_mve_vcmulq_predicated def : Pat<(VTI.Vec (int_arm_mve_vcmulq_predicated
imm:$rot, (VTI.Vec MQPR:$inactive), imm:$rot, (VTI.Vec MQPR:$inactive),
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
(VTI.Pred VCCR:$mask))), (VTI.Pred VCCR:$mask))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
imm:$rot, ARMVCCThen, (VTI.Pred VCCR:$mask), imm:$rot, ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
} }
defm MVE_VCMULf16 : MVE_VCMUL_m<"vcmul", MVE_v8f16, 0b0>; defm MVE_VCMULf16 : MVE_VCMUL_m<"vcmul", MVE_v8f16, 0b0>;
defm MVE_VCMULf32 : MVE_VCMUL_m<"vcmul", MVE_v4f32, 0b1, "@earlyclobber $Qd">; defm MVE_VCMULf32 : MVE_VCMUL_m<"vcmul", MVE_v4f32, 0b1, "@earlyclobber $Qd">;
Show All 35 Lines def : Pat<(VTI.DblVec !con((unpred_op (VTI.Vec MQPR:$Qm),
(VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>; (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
// Predicated multiply // Predicated multiply
def : Pat<(VTI.DblVec !con((pred_int (VTI.Vec MQPR:$Qm), def : Pat<(VTI.DblVec !con((pred_int (VTI.Vec MQPR:$Qm),
(VTI.Vec MQPR:$Qn)), (VTI.Vec MQPR:$Qn)),
uflag, (? (i32 Top), (VTI.DblPred VCCR:$mask), uflag, (? (i32 Top), (VTI.DblPred VCCR:$mask),
(VTI.DblVec MQPR:$inactive)))), (VTI.DblVec MQPR:$inactive)))),
(VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
ARMVCCThen, (VTI.DblPred VCCR:$mask), ARMVCCThen, (VTI.DblPred VCCR:$mask), zero_reg,
(VTI.DblVec MQPR:$inactive)))>; (VTI.DblVec MQPR:$inactive)))>;
} }
} }
// For polynomial multiplies, the size bits take the unused value 0b11, and // For polynomial multiplies, the size bits take the unused value 0b11, and
// the unsigned bit switches to encoding the size. // the unsigned bit switches to encoding the size.
defm MVE_VMULLBs8 : MVE_VMULL_m<MVE_v16s8, int_arm_mve_vmull, defm MVE_VMULLBs8 : MVE_VMULL_m<MVE_v16s8, int_arm_mve_vmull,
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines if !eq(round, 0b0) then {
defm : MVE_TwoOpPattern<VTI, mulh, PredInt, (? (i32 VTI.Unsigned)), defm : MVE_TwoOpPattern<VTI, mulh, PredInt, (? (i32 VTI.Unsigned)),
!cast<Instruction>(NAME)>; !cast<Instruction>(NAME)>;
} else { } else {
// Predicated multiply returning high bits // Predicated multiply returning high bits
def : Pat<(VTI.Vec (PredInt (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), def : Pat<(VTI.Vec (PredInt (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
(i32 VTI.Unsigned), (VTI.Pred VCCR:$mask), (i32 VTI.Unsigned), (VTI.Pred VCCR:$mask),
(VTI.Vec MQPR:$inactive))), (VTI.Vec MQPR:$inactive))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
// Unpredicated intrinsic // Unpredicated intrinsic
def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
(i32 VTI.Unsigned))), (i32 VTI.Unsigned))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>; (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
} }
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Linesmulticlass MVE_VMOVN_p<Instruction Inst, bit top,
// Match the IR intrinsic for a predicated VMOVN. This regards the Qm input // Match the IR intrinsic for a predicated VMOVN. This regards the Qm input
// as having wider lanes that we're narrowing, instead of already-narrow // as having wider lanes that we're narrowing, instead of already-narrow
// lanes that we're taking every other one of. // lanes that we're taking every other one of.
def : Pat<(VTI.Vec (int_arm_mve_vmovn_predicated (VTI.Vec MQPR:$Qd_src), def : Pat<(VTI.Vec (int_arm_mve_vmovn_predicated (VTI.Vec MQPR:$Qd_src),
(InVTI.Vec MQPR:$Qm), (i32 top), (InVTI.Vec MQPR:$Qm), (i32 top),
(InVTI.Pred VCCR:$pred))), (InVTI.Pred VCCR:$pred))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src), (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src),
(InVTI.Vec MQPR:$Qm), (InVTI.Vec MQPR:$Qm),
ARMVCCThen, (InVTI.Pred VCCR:$pred)))>; ARMVCCThen, (InVTI.Pred VCCR:$pred), zero_reg))>;
} }
defm : MVE_VMOVN_p<MVE_VMOVNi32bh, 0, MVE_v8i16, MVE_v4i32>; defm : MVE_VMOVN_p<MVE_VMOVNi32bh, 0, MVE_v8i16, MVE_v4i32>;
defm : MVE_VMOVN_p<MVE_VMOVNi32th, 1, MVE_v8i16, MVE_v4i32>; defm : MVE_VMOVN_p<MVE_VMOVNi32th, 1, MVE_v8i16, MVE_v4i32>;
defm : MVE_VMOVN_p<MVE_VMOVNi16bh, 0, MVE_v16i8, MVE_v8i16>; defm : MVE_VMOVN_p<MVE_VMOVNi16bh, 0, MVE_v16i8, MVE_v8i16>;
defm : MVE_VMOVN_p<MVE_VMOVNi16th, 1, MVE_v16i8, MVE_v8i16>; defm : MVE_VMOVN_p<MVE_VMOVNi16th, 1, MVE_v16i8, MVE_v8i16>;
multiclass MVE_VQMOVN_p<Instruction Inst, bit outU, bit inU, bit top, multiclass MVE_VQMOVN_p<Instruction Inst, bit outU, bit inU, bit top,
MVEVectorVTInfo VTI, MVEVectorVTInfo InVTI> { MVEVectorVTInfo VTI, MVEVectorVTInfo InVTI> {
def : Pat<(VTI.Vec (int_arm_mve_vqmovn (VTI.Vec MQPR:$Qd_src), def : Pat<(VTI.Vec (int_arm_mve_vqmovn (VTI.Vec MQPR:$Qd_src),
(InVTI.Vec MQPR:$Qm), (InVTI.Vec MQPR:$Qm),
(i32 outU), (i32 inU), (i32 top))), (i32 outU), (i32 inU), (i32 top))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src), (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src),
(InVTI.Vec MQPR:$Qm)))>; (InVTI.Vec MQPR:$Qm)))>;
def : Pat<(VTI.Vec (int_arm_mve_vqmovn_predicated (VTI.Vec MQPR:$Qd_src), def : Pat<(VTI.Vec (int_arm_mve_vqmovn_predicated (VTI.Vec MQPR:$Qd_src),
(InVTI.Vec MQPR:$Qm), (InVTI.Vec MQPR:$Qm),
(i32 outU), (i32 inU), (i32 top), (i32 outU), (i32 inU), (i32 top),
(InVTI.Pred VCCR:$pred))), (InVTI.Pred VCCR:$pred))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src), (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src),
(InVTI.Vec MQPR:$Qm), (InVTI.Vec MQPR:$Qm),
ARMVCCThen, (InVTI.Pred VCCR:$pred)))>; ARMVCCThen, (InVTI.Pred VCCR:$pred), zero_reg))>;
} }
defm : MVE_VQMOVN_p<MVE_VQMOVNs32bh, 0, 0, 0, MVE_v8i16, MVE_v4i32>; defm : MVE_VQMOVN_p<MVE_VQMOVNs32bh, 0, 0, 0, MVE_v8i16, MVE_v4i32>;
defm : MVE_VQMOVN_p<MVE_VQMOVNs32th, 0, 0, 1, MVE_v8i16, MVE_v4i32>; defm : MVE_VQMOVN_p<MVE_VQMOVNs32th, 0, 0, 1, MVE_v8i16, MVE_v4i32>;
defm : MVE_VQMOVN_p<MVE_VQMOVNs16bh, 0, 0, 0, MVE_v16i8, MVE_v8i16>; defm : MVE_VQMOVN_p<MVE_VQMOVNs16bh, 0, 0, 0, MVE_v16i8, MVE_v8i16>;
defm : MVE_VQMOVN_p<MVE_VQMOVNs16th, 0, 0, 1, MVE_v16i8, MVE_v8i16>; defm : MVE_VQMOVN_p<MVE_VQMOVNs16th, 0, 0, 1, MVE_v16i8, MVE_v8i16>;
defm : MVE_VQMOVN_p<MVE_VQMOVNu32bh, 1, 1, 0, MVE_v8i16, MVE_v4i32>; defm : MVE_VQMOVN_p<MVE_VQMOVNu32bh, 1, 1, 0, MVE_v8i16, MVE_v4i32>;
defm : MVE_VQMOVN_p<MVE_VQMOVNu32th, 1, 1, 1, MVE_v8i16, MVE_v4i32>; defm : MVE_VQMOVN_p<MVE_VQMOVNu32th, 1, 1, 1, MVE_v8i16, MVE_v4i32>;
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Linesmulticlass MVE_VCVT_f2h_m<string iname, int half> {
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
def : Pat<(v8f16 (int_arm_mve_vcvt_narrow def : Pat<(v8f16 (int_arm_mve_vcvt_narrow
(v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half))), (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half))),
(v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm)))>; (v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm)))>;
def : Pat<(v8f16 (int_arm_mve_vcvt_narrow_predicated def : Pat<(v8f16 (int_arm_mve_vcvt_narrow_predicated
(v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half), (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half),
(v4i1 VCCR:$mask))), (v4i1 VCCR:$mask))),
(v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm),
ARMVCCThen, (v4i1 VCCR:$mask)))>; ARMVCCThen, (v4i1 VCCR:$mask), zero_reg))>;
def : Pat<(v8f16 (MVEvcvtn (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half))), def : Pat<(v8f16 (MVEvcvtn (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm), (i32 half))),
(v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm)))>; (v8f16 (Inst (v8f16 MQPR:$Qd_src), (v4f32 MQPR:$Qm)))>;
} }
} }
multiclass MVE_VCVT_h2f_m<string iname, int half> { multiclass MVE_VCVT_h2f_m<string iname, int half> {
def "": MVE_VCVT_ff<iname, "f32.f16", 0b1, half, (ins), vpred_r, "">; def "": MVE_VCVT_ff<iname, "f32.f16", 0b1, half, (ins), vpred_r, "">;
defvar Inst = !cast<Instruction>(NAME); defvar Inst = !cast<Instruction>(NAME);
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
def : Pat<(v4f32 (int_arm_mve_vcvt_widen (v8f16 MQPR:$Qm), (i32 half))), def : Pat<(v4f32 (int_arm_mve_vcvt_widen (v8f16 MQPR:$Qm), (i32 half))),
(v4f32 (Inst (v8f16 MQPR:$Qm)))>; (v4f32 (Inst (v8f16 MQPR:$Qm)))>;
def : Pat<(v4f32 (int_arm_mve_vcvt_widen_predicated def : Pat<(v4f32 (int_arm_mve_vcvt_widen_predicated
(v4f32 MQPR:$inactive), (v8f16 MQPR:$Qm), (i32 half), (v4f32 MQPR:$inactive), (v8f16 MQPR:$Qm), (i32 half),
(v4i1 VCCR:$mask))), (v4i1 VCCR:$mask))),
(v4f32 (Inst (v8f16 MQPR:$Qm), ARMVCCThen, (v4f32 (Inst (v8f16 MQPR:$Qm), ARMVCCThen,
(v4i1 VCCR:$mask), (v4f32 MQPR:$inactive)))>; (v4i1 VCCR:$mask), zero_reg, (v4f32 MQPR:$inactive)))>;
def : Pat<(v4f32 (MVEvcvtl (v8f16 MQPR:$Qm), (i32 half))), def : Pat<(v4f32 (MVEvcvtl (v8f16 MQPR:$Qm), (i32 half))),
(v4f32 (Inst (v8f16 MQPR:$Qm)))>; (v4f32 (Inst (v8f16 MQPR:$Qm)))>;
} }
} }
defm MVE_VCVTf16f32bh : MVE_VCVT_f2h_m<"vcvtb", 0b0>; defm MVE_VCVTf16f32bh : MVE_VCVT_f2h_m<"vcvtb", 0b0>;
defm MVE_VCVTf16f32th : MVE_VCVT_f2h_m<"vcvtt", 0b1>; defm MVE_VCVTf16f32th : MVE_VCVT_f2h_m<"vcvtt", 0b1>;
Show All 29 Lines def : Pat<(VTI.Vec (int_arm_mve_vcaddq halve,
(VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
imm:$rot))>; imm:$rot))>;
def : Pat<(VTI.Vec (int_arm_mve_vcaddq_predicated halve, def : Pat<(VTI.Vec (int_arm_mve_vcaddq_predicated halve,
imm:$rot, (VTI.Vec MQPR:$inactive), imm:$rot, (VTI.Vec MQPR:$inactive),
(VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
(VTI.Pred VCCR:$mask))), (VTI.Pred VCCR:$mask))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm),
imm:$rot, ARMVCCThen, (VTI.Pred VCCR:$mask), imm:$rot, ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
} }
defm MVE_VCADDi8 : MVE_VxCADD_m<"vcadd", MVE_v16i8, 0b1>; defm MVE_VCADDi8 : MVE_VxCADD_m<"vcadd", MVE_v16i8, 0b1>;
defm MVE_VCADDi16 : MVE_VxCADD_m<"vcadd", MVE_v8i16, 0b1>; defm MVE_VCADDi16 : MVE_VxCADD_m<"vcadd", MVE_v8i16, 0b1>;
defm MVE_VCADDi32 : MVE_VxCADD_m<"vcadd", MVE_v4i32, 0b1, "@earlyclobber $Qd">; defm MVE_VCADDi32 : MVE_VxCADD_m<"vcadd", MVE_v4i32, 0b1, "@earlyclobber $Qd">;
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines def : Pat<(VTI.DblVec (int_arm_mve_vqdmull (VTI.Vec MQPR:$Qm),
(VTI.Vec MQPR:$Qn), (i32 T))), (VTI.Vec MQPR:$Qn), (i32 T))),
(VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>; (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
// Predicated saturating multiply // Predicated saturating multiply
def : Pat<(VTI.DblVec (int_arm_mve_vqdmull_predicated def : Pat<(VTI.DblVec (int_arm_mve_vqdmull_predicated
(VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
(i32 T), (VTI.DblPred VCCR:$mask), (i32 T), (VTI.DblPred VCCR:$mask),
(VTI.DblVec MQPR:$inactive))), (VTI.DblVec MQPR:$inactive))),
(VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
ARMVCCThen, (VTI.DblPred VCCR:$mask), ARMVCCThen, (VTI.DblPred VCCR:$mask), zero_reg,
(VTI.DblVec MQPR:$inactive)))>; (VTI.DblVec MQPR:$inactive)))>;
} }
} }
multiclass MVE_VQDMULL_halves<MVEVectorVTInfo VTI, bit size, string cstr=""> { multiclass MVE_VQDMULL_halves<MVEVectorVTInfo VTI, bit size, string cstr=""> {
defm bh : MVE_VQDMULL_m<"vqdmullb", VTI, size, 0b0, cstr>; defm bh : MVE_VQDMULL_m<"vqdmullb", VTI, size, 0b0, cstr>;
defm th : MVE_VQDMULL_m<"vqdmullt", VTI, size, 0b1, cstr>; defm th : MVE_VQDMULL_m<"vqdmullt", VTI, size, 0b1, cstr>;
} }
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines def : Pat<(VTI.Vec !con((unpred_op (VTI.Vec MQPR:$Qm),
(VTI.Vec (inst (VTI.Vec MQPR:$Qm), (i32 rGPR:$val)))>; (VTI.Vec (inst (VTI.Vec MQPR:$Qm), (i32 rGPR:$val)))>;
// Predicated version // Predicated version
def : Pat<(VTI.Vec !con((pred_op (VTI.Vec MQPR:$Qm), def : Pat<(VTI.Vec !con((pred_op (VTI.Vec MQPR:$Qm),
(VTI.Vec (ARMvdup rGPR:$val))), (VTI.Vec (ARMvdup rGPR:$val))),
PredSign, PredSign,
(pred_op (VTI.Pred VCCR:$mask), (pred_op (VTI.Pred VCCR:$mask),
(VTI.Vec MQPR:$inactive)))), (VTI.Vec MQPR:$inactive)))),
(VTI.Vec (inst (VTI.Vec MQPR:$Qm), (i32 rGPR:$val), (VTI.Vec (inst (VTI.Vec MQPR:$Qm), (i32 rGPR:$val),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
} }
class MVE_VADDSUB_qr<string iname, string suffix, bits<2> size, class MVE_VADDSUB_qr<string iname, string suffix, bits<2> size,
bit bit_5, bit bit_12, bit bit_16, bit bit_28> bit bit_5, bit bit_12, bit bit_16, bit bit_28>
: MVE_qDest_rSrc<iname, suffix, ""> { : MVE_qDest_rSrc<iname, suffix, ""> {
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines let Predicates = [HasMVEInt] in {
// Predicated saturating multiply // Predicated saturating multiply
def : Pat<(VTI.DblVec (int_arm_mve_vqdmull_predicated def : Pat<(VTI.DblVec (int_arm_mve_vqdmull_predicated
(VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qm),
(VTI.Vec (ARMvdup rGPR:$val)), (VTI.Vec (ARMvdup rGPR:$val)),
(i32 T), (i32 T),
(VTI.DblPred VCCR:$mask), (VTI.DblPred VCCR:$mask),
(VTI.DblVec MQPR:$inactive))), (VTI.DblVec MQPR:$inactive))),
(VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (i32 rGPR:$val), (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (i32 rGPR:$val),
ARMVCCThen, (VTI.DblPred VCCR:$mask), ARMVCCThen, (VTI.DblPred VCCR:$mask), zero_reg,
(VTI.DblVec MQPR:$inactive)))>; (VTI.DblVec MQPR:$inactive)))>;
} }
} }
multiclass MVE_VQDMULL_qr_halves<MVEVectorVTInfo VTI, bit size, string cstr=""> { multiclass MVE_VQDMULL_qr_halves<MVEVectorVTInfo VTI, bit size, string cstr=""> {
defm bh : MVE_VQDMULL_qr_m<"vqdmullb", VTI, size, 0b0, cstr>; defm bh : MVE_VQDMULL_qr_m<"vqdmullb", VTI, size, 0b0, cstr>;
defm th : MVE_VQDMULL_qr_m<"vqdmullt", VTI, size, 0b1, cstr>; defm th : MVE_VQDMULL_qr_m<"vqdmullt", VTI, size, 0b1, cstr>;
} }
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines def : Pat<(VTI.Vec (int_arm_mve_vshl_scalar
(i32 q), (i32 r), (i32 VTI.Unsigned))), (i32 q), (i32 r), (i32 VTI.Unsigned))),
(VTI.Vec (Inst (VTI.Vec MQPR:$in), (i32 rGPR:$sh)))>; (VTI.Vec (Inst (VTI.Vec MQPR:$in), (i32 rGPR:$sh)))>;
def : Pat<(VTI.Vec (int_arm_mve_vshl_scalar_predicated def : Pat<(VTI.Vec (int_arm_mve_vshl_scalar_predicated
(VTI.Vec MQPR:$in), (i32 rGPR:$sh), (VTI.Vec MQPR:$in), (i32 rGPR:$sh),
(i32 q), (i32 r), (i32 VTI.Unsigned), (i32 q), (i32 r), (i32 VTI.Unsigned),
(VTI.Pred VCCR:$mask))), (VTI.Pred VCCR:$mask))),
(VTI.Vec (Inst (VTI.Vec MQPR:$in), (i32 rGPR:$sh), (VTI.Vec (Inst (VTI.Vec MQPR:$in), (i32 rGPR:$sh),
ARMVCCThen, (VTI.Pred VCCR:$mask)))>; ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg))>;
} }
multiclass MVE_VxSHL_qr_types<string iname, bit bit_7, bit bit_17> { multiclass MVE_VxSHL_qr_types<string iname, bit bit_7, bit bit_17> {
defm s8 : MVE_VxSHL_qr_p<iname, MVE_v16s8, bit_7, bit_17>; defm s8 : MVE_VxSHL_qr_p<iname, MVE_v16s8, bit_7, bit_17>;
defm s16 : MVE_VxSHL_qr_p<iname, MVE_v8s16, bit_7, bit_17>; defm s16 : MVE_VxSHL_qr_p<iname, MVE_v8s16, bit_7, bit_17>;
defm s32 : MVE_VxSHL_qr_p<iname, MVE_v4s32, bit_7, bit_17>; defm s32 : MVE_VxSHL_qr_p<iname, MVE_v4s32, bit_7, bit_17>;
defm u8 : MVE_VxSHL_qr_p<iname, MVE_v16u8, bit_7, bit_17>; defm u8 : MVE_VxSHL_qr_p<iname, MVE_v16u8, bit_7, bit_17>;
defm u16 : MVE_VxSHL_qr_p<iname, MVE_v8u16, bit_7, bit_17>; defm u16 : MVE_VxSHL_qr_p<iname, MVE_v8u16, bit_7, bit_17>;
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesmulticlass MVE_VBRSR_pat_m<MVEVectorVTInfo VTI, Instruction Inst> {
def : Pat<(VTI.Vec (int_arm_mve_vbrsr (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm))), def : Pat<(VTI.Vec (int_arm_mve_vbrsr (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm)))>; (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm)))>;
// Predicated // Predicated
def : Pat<(VTI.Vec (int_arm_mve_vbrsr_predicated def : Pat<(VTI.Vec (int_arm_mve_vbrsr_predicated
(VTI.Vec MQPR:$inactive), (VTI.Vec MQPR:$inactive),
(VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm), (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm),
(VTI.Pred VCCR:$mask))), (VTI.Pred VCCR:$mask))),
(VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm), (VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask), zero_reg,
(VTI.Vec MQPR:$inactive)))>; (VTI.Vec MQPR:$inactive)))>;
} }
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
def : Pat<(v16i8 ( bitreverse (v16i8 MQPR:$val1))), def : Pat<(v16i8 ( bitreverse (v16i8 MQPR:$val1))),
(v16i8 ( MVE_VBRSR8 (v16i8 MQPR:$val1), (t2MOVi (i32 8)) ))>; (v16i8 ( MVE_VBRSR8 (v16i8 MQPR:$val1), (t2MOVi (i32 8)) ))>;
def : Pat<(v4i32 ( bitreverse (v4i32 MQPR:$val1))), def : Pat<(v4i32 ( bitreverse (v4i32 MQPR:$val1))),
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines if scalar_addend then {
def : Pat<(VTI.Vec (add (mul v1, v2), vs)), def : Pat<(VTI.Vec (add (mul v1, v2), vs)),
(VTI.Vec (Inst v1, v2, s))>; (VTI.Vec (Inst v1, v2, s))>;
} else { } else {
def : Pat<(VTI.Vec (add (mul v2, vs), v1)), def : Pat<(VTI.Vec (add (mul v2, vs), v1)),
(VTI.Vec (Inst v1, v2, s))>; (VTI.Vec (Inst v1, v2, s))>;
} }
def : Pat<(VTI.Vec (pred_int v1, v2, s, pred)), def : Pat<(VTI.Vec (pred_int v1, v2, s, pred)),
(VTI.Vec (Inst v1, v2, s, ARMVCCThen, pred))>; (VTI.Vec (Inst v1, v2, s, ARMVCCThen, pred, zero_reg))>;
} }
} }
defm MVE_VMLA_qr_s8 : MVE_VMLA_qr_multi<"vmla", MVE_v16s8, 0b0>; defm MVE_VMLA_qr_s8 : MVE_VMLA_qr_multi<"vmla", MVE_v16s8, 0b0>;
defm MVE_VMLA_qr_s16 : MVE_VMLA_qr_multi<"vmla", MVE_v8s16, 0b0>; defm MVE_VMLA_qr_s16 : MVE_VMLA_qr_multi<"vmla", MVE_v8s16, 0b0>;
defm MVE_VMLA_qr_s32 : MVE_VMLA_qr_multi<"vmla", MVE_v4s32, 0b0>; defm MVE_VMLA_qr_s32 : MVE_VMLA_qr_multi<"vmla", MVE_v4s32, 0b0>;
defm MVE_VMLA_qr_u8 : MVE_VMLA_qr_multi<"vmla", MVE_v16u8, 0b0>; defm MVE_VMLA_qr_u8 : MVE_VMLA_qr_multi<"vmla", MVE_v16u8, 0b0>;
defm MVE_VMLA_qr_u16 : MVE_VMLA_qr_multi<"vmla", MVE_v8u16, 0b0>; defm MVE_VMLA_qr_u16 : MVE_VMLA_qr_multi<"vmla", MVE_v8u16, 0b0>;
Show All 19 Linesmulticlass MVE_VFMA_qr_multi<string iname, MVEVectorVTInfo VTI,
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
if scalar_addend then { if scalar_addend then {
def : Pat<(VTI.Vec (fma v1, v2, vs)), def : Pat<(VTI.Vec (fma v1, v2, vs)),
(VTI.Vec (Inst v1, v2, is))>; (VTI.Vec (Inst v1, v2, is))>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred), def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma v1, v2, vs)), (VTI.Vec (fma v1, v2, vs)),
v1)), v1)),
(VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred))>; (VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(VTI.Vec (pred_int v1, v2, vs, pred)), def : Pat<(VTI.Vec (pred_int v1, v2, vs, pred)),
(VTI.Vec (Inst v1, v2, is, ARMVCCThen, pred))>; (VTI.Vec (Inst v1, v2, is, ARMVCCThen, pred, zero_reg))>;
} else { } else {
def : Pat<(VTI.Vec (fma v1, vs, v2)), def : Pat<(VTI.Vec (fma v1, vs, v2)),
(VTI.Vec (Inst v2, v1, is))>; (VTI.Vec (Inst v2, v1, is))>;
def : Pat<(VTI.Vec (fma vs, v1, v2)), def : Pat<(VTI.Vec (fma vs, v1, v2)),
(VTI.Vec (Inst v2, v1, is))>; (VTI.Vec (Inst v2, v1, is))>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred), def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma vs, v2, v1)), (VTI.Vec (fma vs, v2, v1)),
v1)), v1)),
(VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred))>; (VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred), def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma v2, vs, v1)), (VTI.Vec (fma v2, vs, v1)),
v1)), v1)),
(VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred))>; (VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred, zero_reg))>;
def : Pat<(VTI.Vec (pred_int v1, vs, v2, pred)), def : Pat<(VTI.Vec (pred_int v1, vs, v2, pred)),
(VTI.Vec (Inst v2, v1, is, ARMVCCThen, pred))>; (VTI.Vec (Inst v2, v1, is, ARMVCCThen, pred, zero_reg))>;
def : Pat<(VTI.Vec (pred_int vs, v1, v2, pred)), def : Pat<(VTI.Vec (pred_int vs, v1, v2, pred)),
(VTI.Vec (Inst v2, v1, is, ARMVCCThen, pred))>; (VTI.Vec (Inst v2, v1, is, ARMVCCThen, pred, zero_reg))>;
} }
} }
} }
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
defm MVE_VFMA_qr_f16 : MVE_VFMA_qr_multi<"vfma", MVE_v8f16, 0>; defm MVE_VFMA_qr_f16 : MVE_VFMA_qr_multi<"vfma", MVE_v8f16, 0>;
defm MVE_VFMA_qr_f32 : MVE_VFMA_qr_multi<"vfma", MVE_v4f32, 0>; defm MVE_VFMA_qr_f32 : MVE_VFMA_qr_multi<"vfma", MVE_v4f32, 0>;
defm MVE_VFMA_qr_Sf16 : MVE_VFMA_qr_multi<"vfmas", MVE_v8f16, 1>; defm MVE_VFMA_qr_Sf16 : MVE_VFMA_qr_multi<"vfmas", MVE_v8f16, 1>;
Show All 23 Lines let Predicates = [HasMVEInt] in {
def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2), def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
(i32 rGPR:$s))), (i32 rGPR:$s))),
(VTI.Vec (Inst (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2), (VTI.Vec (Inst (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
(i32 rGPR:$s)))>; (i32 rGPR:$s)))>;
def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2), def : Pat<(VTI.Vec (pred_int (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
(i32 rGPR:$s), (VTI.Pred VCCR:$pred))), (i32 rGPR:$s), (VTI.Pred VCCR:$pred))),
(VTI.Vec (Inst (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2), (VTI.Vec (Inst (VTI.Vec MQPR:$v1), (VTI.Vec MQPR:$v2),
(i32 rGPR:$s), ARMVCCThen, (i32 rGPR:$s), ARMVCCThen,
(VTI.Pred VCCR:$pred)))>; (VTI.Pred VCCR:$pred), zero_reg))>;
} }
} }
multiclass MVE_VQDMLAH_qr_types<string iname, bit bit_5, bit bit_12> { multiclass MVE_VQDMLAH_qr_types<string iname, bit bit_5, bit bit_12> {
defm s8 : MVE_VQDMLAH_qr_multi<iname, MVE_v16s8, bit_5, bit_12>; defm s8 : MVE_VQDMLAH_qr_multi<iname, MVE_v16s8, bit_5, bit_12>;
defm s16 : MVE_VQDMLAH_qr_multi<iname, MVE_v8s16, bit_5, bit_12>; defm s16 : MVE_VQDMLAH_qr_multi<iname, MVE_v8s16, bit_5, bit_12>;
defm s32 : MVE_VQDMLAH_qr_multi<iname, MVE_v4s32, bit_5, bit_12>; defm s32 : MVE_VQDMLAH_qr_multi<iname, MVE_v4s32, bit_5, bit_12>;
} }
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
multiclass MVE_VCTP<MVEVectorVTInfo VTI, Intrinsic intr> { multiclass MVE_VCTP<MVEVectorVTInfo VTI, Intrinsic intr> {
def "": MVE_VCTPInst<VTI.BitsSuffix, VTI.Size>; def "": MVE_VCTPInst<VTI.BitsSuffix, VTI.Size>;
defvar Inst = !cast<Instruction>(NAME); defvar Inst = !cast<Instruction>(NAME);
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
def : Pat<(intr rGPR:$Rn), def : Pat<(intr rGPR:$Rn),
(VTI.Pred (Inst rGPR:$Rn))>; (VTI.Pred (Inst rGPR:$Rn))>;
def : Pat<(and (intr rGPR:$Rn), (VTI.Pred VCCR:$mask)), def : Pat<(and (intr rGPR:$Rn), (VTI.Pred VCCR:$mask)),
(VTI.Pred (Inst rGPR:$Rn, ARMVCCThen, VCCR:$mask))>; (VTI.Pred (Inst rGPR:$Rn, ARMVCCThen, VCCR:$mask, zero_reg))>;
} }
} }
defm MVE_VCTP8 : MVE_VCTP<MVE_v16i8, int_arm_mve_vctp8>; defm MVE_VCTP8 : MVE_VCTP<MVE_v16i8, int_arm_mve_vctp8>;
defm MVE_VCTP16 : MVE_VCTP<MVE_v8i16, int_arm_mve_vctp16>; defm MVE_VCTP16 : MVE_VCTP<MVE_v8i16, int_arm_mve_vctp16>;
defm MVE_VCTP32 : MVE_VCTP<MVE_v4i32, int_arm_mve_vctp32>; defm MVE_VCTP32 : MVE_VCTP<MVE_v4i32, int_arm_mve_vctp32>;
defm MVE_VCTP64 : MVE_VCTP<MVE_v2i64, int_arm_mve_vctp64>; defm MVE_VCTP64 : MVE_VCTP<MVE_v2i64, int_arm_mve_vctp64>;
▲ Show 20 Lines • Show All 515 Lines • ▼ Show 20 Linesmulticlass MVE_VLDR_rq_w<MVE_memsz memsz, list<MVEVectorVTInfo> VTIs> {
foreach VTI = VTIs in foreach VTI = VTIs in
foreach UnsignedFlag = !if(!eq(VTI.Size, memsz.encoding), foreach UnsignedFlag = !if(!eq(VTI.Size, memsz.encoding),
[0,1], [VTI.Unsigned]) in { [0,1], [VTI.Unsigned]) in {
def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, 0, UnsignedFlag)), def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, 0, UnsignedFlag)),
(VTI.Vec (InstU GPR:$base, MQPR:$offsets))>; (VTI.Vec (InstU GPR:$base, MQPR:$offsets))>;
def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, memsz.shift, UnsignedFlag)), def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, memsz.shift, UnsignedFlag)),
(VTI.Vec (Inst GPR:$base, MQPR:$offsets))>; (VTI.Vec (Inst GPR:$base, MQPR:$offsets))>;
def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, 0, UnsignedFlag, (VTI.Pred VCCR:$pred))), def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, 0, UnsignedFlag, (VTI.Pred VCCR:$pred))),
(VTI.Vec (InstU GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred))>; (VTI.Vec (InstU GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred, zero_reg))>;
def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, memsz.shift, UnsignedFlag, (VTI.Pred VCCR:$pred))), def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), memsz.TypeBits, memsz.shift, UnsignedFlag, (VTI.Pred VCCR:$pred))),
(VTI.Vec (Inst GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred))>; (VTI.Vec (Inst GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred, zero_reg))>;
} }
} }
multiclass MVE_VLDR_rq_b<list<MVEVectorVTInfo> VTIs> { multiclass MVE_VLDR_rq_b<list<MVEVectorVTInfo> VTIs> {
def "": MVE_VLDRSTR_rq_b<MVE_ld, MVE_memB, "vldrb", def "": MVE_VLDRSTR_rq_b<MVE_ld, MVE_memB, "vldrb",
VTIs[0].Suffix, VTIs[0].Unsigned, VTIs[0].Size>; VTIs[0].Suffix, VTIs[0].Unsigned, VTIs[0].Size>;
defvar Inst = !cast<Instruction>(NAME); defvar Inst = !cast<Instruction>(NAME);
foreach VTI = VTIs in { foreach VTI = VTIs in {
def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), 8, 0, VTI.Unsigned)), def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), 8, 0, VTI.Unsigned)),
(VTI.Vec (Inst GPR:$base, MQPR:$offsets))>; (VTI.Vec (Inst GPR:$base, MQPR:$offsets))>;
def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), 8, 0, VTI.Unsigned, (VTI.Pred VCCR:$pred))), def : Pat<(VTI.Vec (int_arm_mve_vldr_gather_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), 8, 0, VTI.Unsigned, (VTI.Pred VCCR:$pred))),
(VTI.Vec (Inst GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred))>; (VTI.Vec (Inst GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred, zero_reg))>;
} }
} }
multiclass MVE_VSTR_rq_w<MVE_memsz memsz, list<MVEVectorVTInfo> VTIs> { multiclass MVE_VSTR_rq_w<MVE_memsz memsz, list<MVEVectorVTInfo> VTIs> {
defm "": MVE_VLDRSTR_rq_w<MVE_st, memsz, "vstr" # memsz.MnemonicLetter, defm "": MVE_VLDRSTR_rq_w<MVE_st, memsz, "vstr" # memsz.MnemonicLetter,
VTIs[0].BitsSuffix, 0, VTIs[0].Size>; VTIs[0].BitsSuffix, 0, VTIs[0].Size>;
defvar Inst = !cast<Instruction>(NAME); defvar Inst = !cast<Instruction>(NAME);
defvar InstU = !cast<Instruction>(NAME # "_u"); defvar InstU = !cast<Instruction>(NAME # "_u");
foreach VTI = VTIs in { foreach VTI = VTIs in {
def : Pat<(int_arm_mve_vstr_scatter_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, 0), def : Pat<(int_arm_mve_vstr_scatter_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, 0),
(InstU MQPR:$data, GPR:$base, MQPR:$offsets)>; (InstU MQPR:$data, GPR:$base, MQPR:$offsets)>;
def : Pat<(int_arm_mve_vstr_scatter_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, memsz.shift), def : Pat<(int_arm_mve_vstr_scatter_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, memsz.shift),
(Inst MQPR:$data, GPR:$base, MQPR:$offsets)>; (Inst MQPR:$data, GPR:$base, MQPR:$offsets)>;
def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, 0, (VTI.Pred VCCR:$pred)), def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, 0, (VTI.Pred VCCR:$pred)),
(InstU MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred)>; (InstU MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred, zero_reg)>;
def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, memsz.shift, (VTI.Pred VCCR:$pred)), def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), memsz.TypeBits, memsz.shift, (VTI.Pred VCCR:$pred)),
(Inst MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred)>; (Inst MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred, zero_reg)>;
} }
} }
multiclass MVE_VSTR_rq_b<list<MVEVectorVTInfo> VTIs> { multiclass MVE_VSTR_rq_b<list<MVEVectorVTInfo> VTIs> {
def "": MVE_VLDRSTR_rq_b<MVE_st, MVE_memB, "vstrb", def "": MVE_VLDRSTR_rq_b<MVE_st, MVE_memB, "vstrb",
VTIs[0].BitsSuffix, 0, VTIs[0].Size>; VTIs[0].BitsSuffix, 0, VTIs[0].Size>;
defvar Inst = !cast<Instruction>(NAME); defvar Inst = !cast<Instruction>(NAME);
foreach VTI = VTIs in { foreach VTI = VTIs in {
def : Pat<(int_arm_mve_vstr_scatter_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), 8, 0), def : Pat<(int_arm_mve_vstr_scatter_offset GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), 8, 0),
(Inst MQPR:$data, GPR:$base, MQPR:$offsets)>; (Inst MQPR:$data, GPR:$base, MQPR:$offsets)>;
def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), 8, 0, (VTI.Pred VCCR:$pred)), def : Pat<(int_arm_mve_vstr_scatter_offset_predicated GPR:$base, (VTIs[0].Vec MQPR:$offsets), (VTI.Vec MQPR:$data), 8, 0, (VTI.Pred VCCR:$pred)),
(Inst MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred)>; (Inst MQPR:$data, GPR:$base, MQPR:$offsets, ARMVCCThen, VCCR:$pred, zero_reg)>;
} }
} }
// Actually define all the loads and stores in this family. // Actually define all the loads and stores in this family.
defm MVE_VLDRBU8_rq : MVE_VLDR_rq_b<[MVE_v16u8,MVE_v16s8]>; defm MVE_VLDRBU8_rq : MVE_VLDR_rq_b<[MVE_v16u8,MVE_v16s8]>;
defm MVE_VLDRBU16_rq: MVE_VLDR_rq_b<[MVE_v8u16]>; defm MVE_VLDRBU16_rq: MVE_VLDR_rq_b<[MVE_v8u16]>;
defm MVE_VLDRBS16_rq: MVE_VLDR_rq_b<[MVE_v8s16]>; defm MVE_VLDRBS16_rq: MVE_VLDR_rq_b<[MVE_v8s16]>;
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Linesmulticlass MVE_VLDR_qi<MVE_memsz memsz, MVEVectorVTInfo AVTI,
foreach DVTI = DVTIs in { foreach DVTI = DVTIs in {
def : Pat<(DVTI.Vec (int_arm_mve_vldr_gather_base def : Pat<(DVTI.Vec (int_arm_mve_vldr_gather_base
(AVTI.Vec MQPR:$addr), (i32 imm:$offset))), (AVTI.Vec MQPR:$addr), (i32 imm:$offset))),
(DVTI.Vec (Inst (AVTI.Vec MQPR:$addr), (i32 imm:$offset)))>; (DVTI.Vec (Inst (AVTI.Vec MQPR:$addr), (i32 imm:$offset)))>;
def : Pat<(DVTI.Vec (int_arm_mve_vldr_gather_base_predicated def : Pat<(DVTI.Vec (int_arm_mve_vldr_gather_base_predicated
(AVTI.Vec MQPR:$addr), (i32 imm:$offset), (AVTI.Pred VCCR:$pred))), (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (AVTI.Pred VCCR:$pred))),
(DVTI.Vec (Inst (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec (Inst (AVTI.Vec MQPR:$addr), (i32 imm:$offset),
ARMVCCThen, VCCR:$pred))>; ARMVCCThen, VCCR:$pred, zero_reg))>;
} }
} }
multiclass MVE_VSTR_qi<MVE_memsz memsz, MVEVectorVTInfo AVTI, multiclass MVE_VSTR_qi<MVE_memsz memsz, MVEVectorVTInfo AVTI,
list<MVEVectorVTInfo> DVTIs> { list<MVEVectorVTInfo> DVTIs> {
defm "" : MVE_VLDRSTR_qi_m<MVE_st, memsz, "vstr" # memsz.MnemonicLetter, defm "" : MVE_VLDRSTR_qi_m<MVE_st, memsz, "vstr" # memsz.MnemonicLetter,
!cast<string>(memsz.TypeBits)>; !cast<string>(memsz.TypeBits)>;
defvar Inst = !cast<Instruction>(NAME); defvar Inst = !cast<Instruction>(NAME);
defvar InstPre = !cast<Instruction>(NAME # "_pre"); defvar InstPre = !cast<Instruction>(NAME # "_pre");
foreach DVTI = DVTIs in { foreach DVTI = DVTIs in {
def : Pat<(int_arm_mve_vstr_scatter_base def : Pat<(int_arm_mve_vstr_scatter_base
(AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data)), (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data)),
(Inst (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr), (Inst (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr),
(i32 imm:$offset))>; (i32 imm:$offset))>;
def : Pat<(int_arm_mve_vstr_scatter_base_predicated def : Pat<(int_arm_mve_vstr_scatter_base_predicated
(AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data), (AVTI.Pred VCCR:$pred)), (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data), (AVTI.Pred VCCR:$pred)),
(Inst (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr), (Inst (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr),
(i32 imm:$offset), ARMVCCThen, VCCR:$pred)>; (i32 imm:$offset), ARMVCCThen, VCCR:$pred, zero_reg)>;
def : Pat<(AVTI.Vec (int_arm_mve_vstr_scatter_base_wb def : Pat<(AVTI.Vec (int_arm_mve_vstr_scatter_base_wb
(AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data))), (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data))),
(AVTI.Vec (InstPre (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr), (AVTI.Vec (InstPre (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr),
(i32 imm:$offset)))>; (i32 imm:$offset)))>;
def : Pat<(AVTI.Vec (int_arm_mve_vstr_scatter_base_wb_predicated def : Pat<(AVTI.Vec (int_arm_mve_vstr_scatter_base_wb_predicated
(AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data), (AVTI.Pred VCCR:$pred))), (AVTI.Vec MQPR:$addr), (i32 imm:$offset), (DVTI.Vec MQPR:$data), (AVTI.Pred VCCR:$pred))),
(AVTI.Vec (InstPre (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr), (AVTI.Vec (InstPre (DVTI.Vec MQPR:$data), (AVTI.Vec MQPR:$addr),
(i32 imm:$offset), ARMVCCThen, VCCR:$pred))>; (i32 imm:$offset), ARMVCCThen, VCCR:$pred, zero_reg))>;
} }
} }
// Actual instruction definitions. // Actual instruction definitions.
defm MVE_VLDRWU32_qi: MVE_VLDR_qi<MVE_memW, MVE_v4i32, [MVE_v4i32,MVE_v4f32]>; defm MVE_VLDRWU32_qi: MVE_VLDR_qi<MVE_memW, MVE_v4i32, [MVE_v4i32,MVE_v4f32]>;
defm MVE_VLDRDU64_qi: MVE_VLDR_qi<MVE_memD, MVE_v2i64, [MVE_v2i64,MVE_v2f64]>; defm MVE_VLDRDU64_qi: MVE_VLDR_qi<MVE_memD, MVE_v2i64, [MVE_v2i64,MVE_v2f64]>;
defm MVE_VSTRW32_qi: MVE_VSTR_qi<MVE_memW, MVE_v4i32, [MVE_v4i32,MVE_v4f32]>; defm MVE_VSTRW32_qi: MVE_VSTR_qi<MVE_memW, MVE_v4i32, [MVE_v4i32,MVE_v4f32]>;
defm MVE_VSTRD64_qi: MVE_VSTR_qi<MVE_memD, MVE_v2i64, [MVE_v2i64,MVE_v2f64]>; defm MVE_VSTRD64_qi: MVE_VSTR_qi<MVE_memD, MVE_v2i64, [MVE_v2i64,MVE_v2f64]>;
▲ Show 20 Lines • Show All 238 Lines • ▼ Show 20 Lines
foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32", foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32",
"i8", "i16", "i32", "f16", "f32"] in "i8", "i16", "i32", "f16", "f32"] in
def : MVEInstAlias<"vpsel${vp}." # suffix # "\t$Qd, $Qn, $Qm", def : MVEInstAlias<"vpsel${vp}." # suffix # "\t$Qd, $Qn, $Qm",
(MVE_VPSEL MQPR:$Qd, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>; (MVE_VPSEL MQPR:$Qd, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
def : Pat<(v16i8 (vselect (v16i1 VCCR:$pred), (v16i8 MQPR:$v1), (v16i8 MQPR:$v2))), def : Pat<(v16i8 (vselect (v16i1 VCCR:$pred), (v16i8 MQPR:$v1), (v16i8 MQPR:$v2))),
(v16i8 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred))>; (v16i8 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred), (v8i16 MQPR:$v1), (v8i16 MQPR:$v2))), def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred), (v8i16 MQPR:$v1), (v8i16 MQPR:$v2))),
(v8i16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred))>; (v8i16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred), (v4i32 MQPR:$v1), (v4i32 MQPR:$v2))), def : Pat<(v4i32 (vselect (v4i1 VCCR:$pred), (v4i32 MQPR:$v1), (v4i32 MQPR:$v2))),
(v4i32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred))>; (v4i32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v8f16 (vselect (v8i1 VCCR:$pred), (v8f16 MQPR:$v1), (v8f16 MQPR:$v2))), def : Pat<(v8f16 (vselect (v8i1 VCCR:$pred), (v8f16 MQPR:$v1), (v8f16 MQPR:$v2))),
(v8f16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred))>; (v8f16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v4f32 (vselect (v4i1 VCCR:$pred), (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))), def : Pat<(v4f32 (vselect (v4i1 VCCR:$pred), (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))),
(v4f32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred))>; (v4f32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v16i8 (vselect (v16i8 MQPR:$pred), (v16i8 MQPR:$v1), (v16i8 MQPR:$v2))), def : Pat<(v16i8 (vselect (v16i8 MQPR:$pred), (v16i8 MQPR:$v1), (v16i8 MQPR:$v2))),
(v16i8 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, (v16i8 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone,
(MVE_VCMPi8 (v16i8 MQPR:$pred), (MVE_VMOVimmi8 0), ARMCCne)))>; (MVE_VCMPi8 (v16i8 MQPR:$pred), (MVE_VMOVimmi8 0), ARMCCne), zero_reg))>;
def : Pat<(v8i16 (vselect (v8i16 MQPR:$pred), (v8i16 MQPR:$v1), (v8i16 MQPR:$v2))), def : Pat<(v8i16 (vselect (v8i16 MQPR:$pred), (v8i16 MQPR:$v1), (v8i16 MQPR:$v2))),
(v8i16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, (v8i16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone,
(MVE_VCMPi16 (v8i16 MQPR:$pred), (MVE_VMOVimmi16 0), ARMCCne)))>; (MVE_VCMPi16 (v8i16 MQPR:$pred), (MVE_VMOVimmi16 0), ARMCCne), zero_reg))>;
def : Pat<(v4i32 (vselect (v4i32 MQPR:$pred), (v4i32 MQPR:$v1), (v4i32 MQPR:$v2))), def : Pat<(v4i32 (vselect (v4i32 MQPR:$pred), (v4i32 MQPR:$v1), (v4i32 MQPR:$v2))),
(v4i32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, (v4i32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone,
(MVE_VCMPi32 (v4i32 MQPR:$pred), (MVE_VMOVimmi32 0), ARMCCne)))>; (MVE_VCMPi32 (v4i32 MQPR:$pred), (MVE_VMOVimmi32 0), ARMCCne), zero_reg))>;
def : Pat<(v8f16 (vselect (v8i16 MQPR:$pred), (v8f16 MQPR:$v1), (v8f16 MQPR:$v2))), def : Pat<(v8f16 (vselect (v8i16 MQPR:$pred), (v8f16 MQPR:$v1), (v8f16 MQPR:$v2))),
(v8f16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, (v8f16 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone,
(MVE_VCMPi16 (v8i16 MQPR:$pred), (MVE_VMOVimmi16 0), ARMCCne)))>; (MVE_VCMPi16 (v8i16 MQPR:$pred), (MVE_VMOVimmi16 0), ARMCCne), zero_reg))>;
def : Pat<(v4f32 (vselect (v4i32 MQPR:$pred), (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))), def : Pat<(v4f32 (vselect (v4i32 MQPR:$pred), (v4f32 MQPR:$v1), (v4f32 MQPR:$v2))),
(v4f32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone, (v4f32 (MVE_VPSEL MQPR:$v1, MQPR:$v2, ARMVCCNone,
(MVE_VCMPi32 (v4i32 MQPR:$pred), (MVE_VMOVimmi32 0), ARMCCne)))>; (MVE_VCMPi32 (v4i32 MQPR:$pred), (MVE_VMOVimmi32 0), ARMCCne), zero_reg))>;
// Pred <-> Int // Pred <-> Int
def : Pat<(v16i8 (zext (v16i1 VCCR:$pred))), def : Pat<(v16i8 (zext (v16i1 VCCR:$pred))),
(v16i8 (MVE_VPSEL (MVE_VMOVimmi8 1), (MVE_VMOVimmi8 0), ARMVCCNone, VCCR:$pred))>; (v16i8 (MVE_VPSEL (MVE_VMOVimmi8 1), (MVE_VMOVimmi8 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v8i16 (zext (v8i1 VCCR:$pred))), def : Pat<(v8i16 (zext (v8i1 VCCR:$pred))),
(v8i16 (MVE_VPSEL (MVE_VMOVimmi16 1), (MVE_VMOVimmi16 0), ARMVCCNone, VCCR:$pred))>; (v8i16 (MVE_VPSEL (MVE_VMOVimmi16 1), (MVE_VMOVimmi16 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v4i32 (zext (v4i1 VCCR:$pred))), def : Pat<(v4i32 (zext (v4i1 VCCR:$pred))),
(v4i32 (MVE_VPSEL (MVE_VMOVimmi32 1), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred))>; (v4i32 (MVE_VPSEL (MVE_VMOVimmi32 1), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v16i8 (sext (v16i1 VCCR:$pred))), def : Pat<(v16i8 (sext (v16i1 VCCR:$pred))),
(v16i8 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi8 0), ARMVCCNone, VCCR:$pred))>; (v16i8 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi8 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v8i16 (sext (v8i1 VCCR:$pred))), def : Pat<(v8i16 (sext (v8i1 VCCR:$pred))),
(v8i16 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi16 0), ARMVCCNone, VCCR:$pred))>; (v8i16 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi16 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v4i32 (sext (v4i1 VCCR:$pred))), def : Pat<(v4i32 (sext (v4i1 VCCR:$pred))),
(v4i32 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred))>; (v4i32 (MVE_VPSEL (MVE_VMOVimmi8 255), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v16i8 (anyext (v16i1 VCCR:$pred))), def : Pat<(v16i8 (anyext (v16i1 VCCR:$pred))),
(v16i8 (MVE_VPSEL (MVE_VMOVimmi8 1), (MVE_VMOVimmi8 0), ARMVCCNone, VCCR:$pred))>; (v16i8 (MVE_VPSEL (MVE_VMOVimmi8 1), (MVE_VMOVimmi8 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v8i16 (anyext (v8i1 VCCR:$pred))), def : Pat<(v8i16 (anyext (v8i1 VCCR:$pred))),
(v8i16 (MVE_VPSEL (MVE_VMOVimmi16 1), (MVE_VMOVimmi16 0), ARMVCCNone, VCCR:$pred))>; (v8i16 (MVE_VPSEL (MVE_VMOVimmi16 1), (MVE_VMOVimmi16 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v4i32 (anyext (v4i1 VCCR:$pred))), def : Pat<(v4i32 (anyext (v4i1 VCCR:$pred))),
(v4i32 (MVE_VPSEL (MVE_VMOVimmi32 1), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred))>; (v4i32 (MVE_VPSEL (MVE_VMOVimmi32 1), (MVE_VMOVimmi32 0), ARMVCCNone, VCCR:$pred, zero_reg))>;
} }
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
// Pred <-> Float // Pred <-> Float
// 112 is 1.0 in float // 112 is 1.0 in float
def : Pat<(v4f32 (uint_to_fp (v4i1 VCCR:$pred))), def : Pat<(v4f32 (uint_to_fp (v4i1 VCCR:$pred))),
(v4f32 (MVE_VPSEL (v4f32 (MVE_VMOVimmf32 112)), (v4f32 (MVE_VMOVimmi32 0)), ARMVCCNone, VCCR:$pred))>; (v4f32 (MVE_VPSEL (v4f32 (MVE_VMOVimmf32 112)), (v4f32 (MVE_VMOVimmi32 0)), ARMVCCNone, VCCR:$pred, zero_reg))>;
// 2620 in 1.0 in half // 2620 in 1.0 in half
def : Pat<(v8f16 (uint_to_fp (v8i1 VCCR:$pred))), def : Pat<(v8f16 (uint_to_fp (v8i1 VCCR:$pred))),
(v8f16 (MVE_VPSEL (v8f16 (MVE_VMOVimmi16 2620)), (v8f16 (MVE_VMOVimmi16 0)), ARMVCCNone, VCCR:$pred))>; (v8f16 (MVE_VPSEL (v8f16 (MVE_VMOVimmi16 2620)), (v8f16 (MVE_VMOVimmi16 0)), ARMVCCNone, VCCR:$pred, zero_reg))>;
// 240 is -1.0 in float // 240 is -1.0 in float
def : Pat<(v4f32 (sint_to_fp (v4i1 VCCR:$pred))), def : Pat<(v4f32 (sint_to_fp (v4i1 VCCR:$pred))),
(v4f32 (MVE_VPSEL (v4f32 (MVE_VMOVimmf32 240)), (v4f32 (MVE_VMOVimmi32 0)), ARMVCCNone, VCCR:$pred))>; (v4f32 (MVE_VPSEL (v4f32 (MVE_VMOVimmf32 240)), (v4f32 (MVE_VMOVimmi32 0)), ARMVCCNone, VCCR:$pred, zero_reg))>;
// 2748 is -1.0 in half // 2748 is -1.0 in half
def : Pat<(v8f16 (sint_to_fp (v8i1 VCCR:$pred))), def : Pat<(v8f16 (sint_to_fp (v8i1 VCCR:$pred))),
(v8f16 (MVE_VPSEL (v8f16 (MVE_VMOVimmi16 2748)), (v8f16 (MVE_VMOVimmi16 0)), ARMVCCNone, VCCR:$pred))>; (v8f16 (MVE_VPSEL (v8f16 (MVE_VMOVimmi16 2748)), (v8f16 (MVE_VMOVimmi16 0)), ARMVCCNone, VCCR:$pred, zero_reg))>;
def : Pat<(v4i1 (fp_to_uint (v4f32 MQPR:$v1))), def : Pat<(v4i1 (fp_to_uint (v4f32 MQPR:$v1))),
(v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, ARMCCne))>; (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, ARMCCne))>;
def : Pat<(v8i1 (fp_to_uint (v8f16 MQPR:$v1))), def : Pat<(v8i1 (fp_to_uint (v8f16 MQPR:$v1))),
(v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, ARMCCne))>; (v8i1 (MVE_VCMPf16r (v8f16 MQPR:$v1), ZR, ARMCCne))>;
def : Pat<(v4i1 (fp_to_sint (v4f32 MQPR:$v1))), def : Pat<(v4i1 (fp_to_sint (v4f32 MQPR:$v1))),
(v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, ARMCCne))>; (v4i1 (MVE_VCMPf32r (v4f32 MQPR:$v1), ZR, ARMCCne))>;
def : Pat<(v8i1 (fp_to_sint (v8f16 MQPR:$v1))), def : Pat<(v8i1 (fp_to_sint (v8f16 MQPR:$v1))),
▲ Show 20 Lines • Show All 340 Lines • ▼ Show 20 Lines
class MVE_vector_store_typed<ValueType Ty, Instruction RegImmInst, class MVE_vector_store_typed<ValueType Ty, Instruction RegImmInst,
PatFrag StoreKind, int shift> PatFrag StoreKind, int shift>
: Pat<(StoreKind (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr), : Pat<(StoreKind (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr),
(RegImmInst (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr)>; (RegImmInst (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr)>;
class MVE_vector_maskedstore_typed<ValueType Ty, Instruction RegImmInst, class MVE_vector_maskedstore_typed<ValueType Ty, Instruction RegImmInst,
PatFrag StoreKind, int shift> PatFrag StoreKind, int shift>
: Pat<(StoreKind (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr, VCCR:$pred), : Pat<(StoreKind (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr, VCCR:$pred),
(RegImmInst (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr, ARMVCCThen, VCCR:$pred)>; (RegImmInst (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg)>;
multiclass MVE_vector_store<Instruction RegImmInst, PatFrag StoreKind, multiclass MVE_vector_store<Instruction RegImmInst, PatFrag StoreKind,
int shift> { int shift> {
def : MVE_vector_store_typed<v16i8, RegImmInst, StoreKind, shift>; def : MVE_vector_store_typed<v16i8, RegImmInst, StoreKind, shift>;
def : MVE_vector_store_typed<v8i16, RegImmInst, StoreKind, shift>; def : MVE_vector_store_typed<v8i16, RegImmInst, StoreKind, shift>;
def : MVE_vector_store_typed<v8f16, RegImmInst, StoreKind, shift>; def : MVE_vector_store_typed<v8f16, RegImmInst, StoreKind, shift>;
def : MVE_vector_store_typed<v4i32, RegImmInst, StoreKind, shift>; def : MVE_vector_store_typed<v4i32, RegImmInst, StoreKind, shift>;
def : MVE_vector_store_typed<v4f32, RegImmInst, StoreKind, shift>; def : MVE_vector_store_typed<v4f32, RegImmInst, StoreKind, shift>;
def : MVE_vector_store_typed<v2i64, RegImmInst, StoreKind, shift>; def : MVE_vector_store_typed<v2i64, RegImmInst, StoreKind, shift>;
def : MVE_vector_store_typed<v2f64, RegImmInst, StoreKind, shift>; def : MVE_vector_store_typed<v2f64, RegImmInst, StoreKind, shift>;
} }
class MVE_vector_load_typed<ValueType Ty, Instruction RegImmInst, class MVE_vector_load_typed<ValueType Ty, Instruction RegImmInst,
PatFrag LoadKind, int shift> PatFrag LoadKind, int shift>
: Pat<(Ty (LoadKind t2addrmode_imm7<shift>:$addr)), : Pat<(Ty (LoadKind t2addrmode_imm7<shift>:$addr)),
(Ty (RegImmInst t2addrmode_imm7<shift>:$addr))>; (Ty (RegImmInst t2addrmode_imm7<shift>:$addr))>;
class MVE_vector_maskedload_typed<ValueType Ty, Instruction RegImmInst, class MVE_vector_maskedload_typed<ValueType Ty, Instruction RegImmInst,
PatFrag LoadKind, int shift> PatFrag LoadKind, int shift>
: Pat<(Ty (LoadKind t2addrmode_imm7<shift>:$addr, VCCR:$pred, (Ty (ARMvmovImm (i32 0))))), : Pat<(Ty (LoadKind t2addrmode_imm7<shift>:$addr, VCCR:$pred, (Ty (ARMvmovImm (i32 0))))),
(Ty (RegImmInst t2addrmode_imm7<shift>:$addr, ARMVCCThen, VCCR:$pred))>; (Ty (RegImmInst t2addrmode_imm7<shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg))>;
multiclass MVE_vector_load<Instruction RegImmInst, PatFrag LoadKind, multiclass MVE_vector_load<Instruction RegImmInst, PatFrag LoadKind,
int shift> { int shift> {
def : MVE_vector_load_typed<v16i8, RegImmInst, LoadKind, shift>; def : MVE_vector_load_typed<v16i8, RegImmInst, LoadKind, shift>;
def : MVE_vector_load_typed<v8i16, RegImmInst, LoadKind, shift>; def : MVE_vector_load_typed<v8i16, RegImmInst, LoadKind, shift>;
def : MVE_vector_load_typed<v8f16, RegImmInst, LoadKind, shift>; def : MVE_vector_load_typed<v8f16, RegImmInst, LoadKind, shift>;
def : MVE_vector_load_typed<v4i32, RegImmInst, LoadKind, shift>; def : MVE_vector_load_typed<v4i32, RegImmInst, LoadKind, shift>;
def : MVE_vector_load_typed<v4f32, RegImmInst, LoadKind, shift>; def : MVE_vector_load_typed<v4f32, RegImmInst, LoadKind, shift>;
def : MVE_vector_load_typed<v2i64, RegImmInst, LoadKind, shift>; def : MVE_vector_load_typed<v2i64, RegImmInst, LoadKind, shift>;
def : MVE_vector_load_typed<v2f64, RegImmInst, LoadKind, shift>; def : MVE_vector_load_typed<v2f64, RegImmInst, LoadKind, shift>;
} }
class MVE_vector_offset_store_typed<ValueType Ty, Instruction Opcode, class MVE_vector_offset_store_typed<ValueType Ty, Instruction Opcode,
PatFrag StoreKind, int shift> PatFrag StoreKind, int shift>
: Pat<(StoreKind (Ty MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<shift>:$addr), : Pat<(StoreKind (Ty MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<shift>:$addr),
(Opcode MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<shift>:$addr)>; (Opcode MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<shift>:$addr)>;
class MVE_vector_offset_maskedstore_typed<ValueType Ty, Instruction Opcode, class MVE_vector_offset_maskedstore_typed<ValueType Ty, Instruction Opcode,
PatFrag StoreKind, int shift> PatFrag StoreKind, int shift>
: Pat<(StoreKind (Ty MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<shift>:$addr, VCCR:$pred), : Pat<(StoreKind (Ty MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<shift>:$addr, VCCR:$pred),
(Opcode MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<shift>:$addr, ARMVCCThen, VCCR:$pred)>; (Opcode MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg)>;
multiclass MVE_vector_offset_store<Instruction RegImmInst, PatFrag StoreKind, multiclass MVE_vector_offset_store<Instruction RegImmInst, PatFrag StoreKind,
int shift> { int shift> {
def : MVE_vector_offset_store_typed<v16i8, RegImmInst, StoreKind, shift>; def : MVE_vector_offset_store_typed<v16i8, RegImmInst, StoreKind, shift>;
def : MVE_vector_offset_store_typed<v8i16, RegImmInst, StoreKind, shift>; def : MVE_vector_offset_store_typed<v8i16, RegImmInst, StoreKind, shift>;
def : MVE_vector_offset_store_typed<v8f16, RegImmInst, StoreKind, shift>; def : MVE_vector_offset_store_typed<v8f16, RegImmInst, StoreKind, shift>;
def : MVE_vector_offset_store_typed<v4i32, RegImmInst, StoreKind, shift>; def : MVE_vector_offset_store_typed<v4i32, RegImmInst, StoreKind, shift>;
def : MVE_vector_offset_store_typed<v4f32, RegImmInst, StoreKind, shift>; def : MVE_vector_offset_store_typed<v4f32, RegImmInst, StoreKind, shift>;
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines def : Pat<(!cast<PatFrag>("aligned_truncst"#Amble) (VT MQPR:$val), taddrmode_imm7<Shift>:$addr),
(!cast<Instruction>(StoreInst) MQPR:$val, taddrmode_imm7<Shift>:$addr)>; (!cast<Instruction>(StoreInst) MQPR:$val, taddrmode_imm7<Shift>:$addr)>;
def : Pat<(!cast<PatFrag>("aligned_post_truncst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr), def : Pat<(!cast<PatFrag>("aligned_post_truncst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr),
(!cast<Instruction>(StoreInst#"_post") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr)>; (!cast<Instruction>(StoreInst#"_post") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr)>;
def : Pat<(!cast<PatFrag>("aligned_pre_truncst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr), def : Pat<(!cast<PatFrag>("aligned_pre_truncst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr),
(!cast<Instruction>(StoreInst#"_pre") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr)>; (!cast<Instruction>(StoreInst#"_pre") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr)>;
// Masked trunc stores // Masked trunc stores
def : Pat<(!cast<PatFrag>("aligned_truncmaskedst"#Amble) (VT MQPR:$val), taddrmode_imm7<Shift>:$addr, VCCR:$pred), def : Pat<(!cast<PatFrag>("aligned_truncmaskedst"#Amble) (VT MQPR:$val), taddrmode_imm7<Shift>:$addr, VCCR:$pred),
(!cast<Instruction>(StoreInst) MQPR:$val, taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred)>; (!cast<Instruction>(StoreInst) MQPR:$val, taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg)>;
def : Pat<(!cast<PatFrag>("aligned_post_truncmaskedst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, VCCR:$pred), def : Pat<(!cast<PatFrag>("aligned_post_truncmaskedst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, VCCR:$pred),
(!cast<Instruction>(StoreInst#"_post") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, ARMVCCThen, VCCR:$pred)>; (!cast<Instruction>(StoreInst#"_post") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg)>;
def : Pat<(!cast<PatFrag>("aligned_pre_truncmaskedst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, VCCR:$pred), def : Pat<(!cast<PatFrag>("aligned_pre_truncmaskedst"#Amble) (VT MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, VCCR:$pred),
(!cast<Instruction>(StoreInst#"_pre") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, ARMVCCThen, VCCR:$pred)>; (!cast<Instruction>(StoreInst#"_pre") MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<Shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg)>;
// Ext loads // Ext loads
def : Pat<(VT (!cast<PatFrag>("aligned_extload"#Amble) taddrmode_imm7<Shift>:$addr)), def : Pat<(VT (!cast<PatFrag>("aligned_extload"#Amble) taddrmode_imm7<Shift>:$addr)),
(VT (LoadUInst taddrmode_imm7<Shift>:$addr))>; (VT (LoadUInst taddrmode_imm7<Shift>:$addr))>;
def : Pat<(VT (!cast<PatFrag>("aligned_sextload"#Amble) taddrmode_imm7<Shift>:$addr)), def : Pat<(VT (!cast<PatFrag>("aligned_sextload"#Amble) taddrmode_imm7<Shift>:$addr)),
(VT (LoadSInst taddrmode_imm7<Shift>:$addr))>; (VT (LoadSInst taddrmode_imm7<Shift>:$addr))>;
def : Pat<(VT (!cast<PatFrag>("aligned_zextload"#Amble) taddrmode_imm7<Shift>:$addr)), def : Pat<(VT (!cast<PatFrag>("aligned_zextload"#Amble) taddrmode_imm7<Shift>:$addr)),
(VT (LoadUInst taddrmode_imm7<Shift>:$addr))>; (VT (LoadUInst taddrmode_imm7<Shift>:$addr))>;
// Masked ext loads // Masked ext loads
def : Pat<(VT (!cast<PatFrag>("aligned_extmaskedload"#Amble) taddrmode_imm7<Shift>:$addr, VCCR:$pred, (VT (ARMvmovImm (i32 0))))), def : Pat<(VT (!cast<PatFrag>("aligned_extmaskedload"#Amble) taddrmode_imm7<Shift>:$addr, VCCR:$pred, (VT (ARMvmovImm (i32 0))))),
(VT (LoadUInst taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred))>; (VT (LoadUInst taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg))>;
def : Pat<(VT (!cast<PatFrag>("aligned_sextmaskedload"#Amble) taddrmode_imm7<Shift>:$addr, VCCR:$pred, (VT (ARMvmovImm (i32 0))))), def : Pat<(VT (!cast<PatFrag>("aligned_sextmaskedload"#Amble) taddrmode_imm7<Shift>:$addr, VCCR:$pred, (VT (ARMvmovImm (i32 0))))),
(VT (LoadSInst taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred))>; (VT (LoadSInst taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg))>;
def : Pat<(VT (!cast<PatFrag>("aligned_zextmaskedload"#Amble) taddrmode_imm7<Shift>:$addr, VCCR:$pred, (VT (ARMvmovImm (i32 0))))), def : Pat<(VT (!cast<PatFrag>("aligned_zextmaskedload"#Amble) taddrmode_imm7<Shift>:$addr, VCCR:$pred, (VT (ARMvmovImm (i32 0))))),
(VT (LoadUInst taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred))>; (VT (LoadUInst taddrmode_imm7<Shift>:$addr, ARMVCCThen, VCCR:$pred, zero_reg))>;
} }
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
defm : MVEExtLoadStore<MVE_VLDRBS16, MVE_VLDRBU16, "MVE_VSTRB16", "vi8", v8i16, 0>; defm : MVEExtLoadStore<MVE_VLDRBS16, MVE_VLDRBU16, "MVE_VSTRB16", "vi8", v8i16, 0>;
defm : MVEExtLoadStore<MVE_VLDRBS32, MVE_VLDRBU32, "MVE_VSTRB32", "vi8", v4i32, 0>; defm : MVEExtLoadStore<MVE_VLDRBS32, MVE_VLDRBU32, "MVE_VSTRB32", "vi8", v4i32, 0>;
defm : MVEExtLoadStore<MVE_VLDRHS32, MVE_VLDRHU32, "MVE_VSTRH32", "vi16", v4i32, 1>; defm : MVEExtLoadStore<MVE_VLDRHS32, MVE_VLDRHU32, "MVE_VSTRH32", "vi16", v4i32, 1>;
} }
▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Show First 20 Lines • Show All 2,805 Lines • ▼ Show 20 Lines case ARMII::AddrModeT2_i7s4:
// Any MVE load/store // Any MVE load/store
return BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID) return BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID)
.addReg(NewReg, RegState::Define) .addReg(NewReg, RegState::Define)
.add(MI->getOperand(0)) .add(MI->getOperand(0))
.add(MI->getOperand(1)) .add(MI->getOperand(1))
.addImm(Offset) .addImm(Offset)
.add(MI->getOperand(3)) .add(MI->getOperand(3))
.add(MI->getOperand(4)) .add(MI->getOperand(4))
.add(MI->getOperand(5))
.cloneMemRefs(*MI); .cloneMemRefs(*MI);
case ARMII::AddrModeT2_i8: case ARMII::AddrModeT2_i8:
if (MI->mayLoad()) { if (MI->mayLoad()) {
return BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID) return BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID)
.add(MI->getOperand(0)) .add(MI->getOperand(0))
.addReg(NewReg, RegState::Define) .addReg(NewReg, RegState::Define)
.add(MI->getOperand(1)) .add(MI->getOperand(1))
.addImm(Offset) .addImm(Offset)
▲ Show 20 Lines • Show All 201 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

Show First 20 Lines • Show All 874 Lines • ▼ Show 20 Linesstatic bool producesFalseLanesZero(MachineInstr &MI,
}; };
bool AllowScalars = isHorizontalReduction(MI); bool AllowScalars = isHorizontalReduction(MI);
for (auto &MO : MI.operands()) { for (auto &MO : MI.operands()) {
if (!MO.isReg() || !MO.getReg()) if (!MO.isReg() || !MO.getReg())
continue; continue;
if (!isRegInClass(MO, QPRs) && AllowScalars) if (!isRegInClass(MO, QPRs) && AllowScalars)
continue; continue;
// Skip the lr predicate reg
int PIdx = llvm::findFirstVPTPredOperandIdx(MI);
if (PIdx != -1 && (int)MI.getOperandNo(&MO) == PIdx + 2)
continue;
// Check that this instruction will produce zeros in its false lanes: // Check that this instruction will produce zeros in its false lanes:
// - If it only consumes false lanes zero or constant 0 (vmov #0) // - If it only consumes false lanes zero or constant 0 (vmov #0)
// - If it's predicated, it only matters that it's def register already has // - If it's predicated, it only matters that it's def register already has
// false lane zeros, so we can ignore the uses. // false lane zeros, so we can ignore the uses.
SmallPtrSet<MachineInstr *, 2> Defs; SmallPtrSet<MachineInstr *, 2> Defs;
RDA.getGlobalReachingDefs(&MI, MO.getReg(), Defs); RDA.getGlobalReachingDefs(&MI, MO.getReg(), Defs);
for (auto *Def : Defs) { for (auto *Def : Defs) {
▲ Show 20 Lines • Show All 910 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,472 Lines • ▼ Show 20 Lines
void addCondCodeOperands(MCInst &Inst, unsigned N) const { void addCondCodeOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!"); assert(N == 2 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
Inst.addOperand(MCOperand::createReg(RegNum)); Inst.addOperand(MCOperand::createReg(RegNum));
} }
void addVPTPredNOperands(MCInst &Inst, unsigned N) const { void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
assert(N == 2 && "Invalid number of operands!"); assert(N == 3 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred()))); Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0; unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
Inst.addOperand(MCOperand::createReg(RegNum)); Inst.addOperand(MCOperand::createReg(RegNum));
Inst.addOperand(MCOperand::createReg(0));
} }
void addVPTPredROperands(MCInst &Inst, unsigned N) const { void addVPTPredROperands(MCInst &Inst, unsigned N) const {
assert(N == 3 && "Invalid number of operands!"); assert(N == 4 && "Invalid number of operands!");
addVPTPredNOperands(Inst, N-1); addVPTPredNOperands(Inst, N-1);
unsigned RegNum; unsigned RegNum;
if (getVPTPred() == ARMVCC::None) { if (getVPTPred() == ARMVCC::None) {
RegNum = 0; RegNum = 0;
} else { } else {
unsigned NextOpIndex = Inst.getNumOperands(); unsigned NextOpIndex = Inst.getNumOperands();
const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()]; const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()];
int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO); int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
▲ Show 20 Lines • Show All 9,971 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Show First 20 Lines • Show All 848 Lines • ▼ Show 20 LinesARMDisassembler::AddThumbPredicate(MCInst &MI) const {
for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
} }
if (isVectorPredicable(MI.getOpcode())) { if (isVectorPredicable(MI.getOpcode())) {
VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
++VCCI; ++VCCI;
if (VCC == ARMVCC::None) if (VCC == ARMVCC::None)
MI.insert(VCCI, MCOperand::createReg(0)); VCCI = MI.insert(VCCI, MCOperand::createReg(0));
else else
MI.insert(VCCI, MCOperand::createReg(ARM::P0)); VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0));
++VCCI;
VCCI = MI.insert(VCCI, MCOperand::createReg(0));
++VCCI;
if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint(
VCCPos + 2, MCOI::TIED_TO); VCCPos + 3, MCOI::TIED_TO);
assert(TiedOp >= 0 && assert(TiedOp >= 0 &&
"Inactive register in vpred_r is not tied to an output!"); "Inactive register in vpred_r is not tied to an output!");
// Copy the operand to ensure it's not invalidated when MI grows. // Copy the operand to ensure it's not invalidated when MI grows.
MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp)));
} }
} else if (VCC != ARMVCC::None) { } else if (VCC != ARMVCC::None) {
Check(S, SoftFail); Check(S, SoftFail);
} }
▲ Show 20 Lines • Show All 5,819 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp

Show All 34 Lines
#define DEBUG_TYPE "arm-mve-vpt-opts" #define DEBUG_TYPE "arm-mve-vpt-opts"
static cl::opt<bool> static cl::opt<bool>
MergeEndDec("arm-enable-merge-loopenddec", cl::Hidden, MergeEndDec("arm-enable-merge-loopenddec", cl::Hidden,
cl::desc("Enable merging Loop End and Dec instructions."), cl::desc("Enable merging Loop End and Dec instructions."),
cl::init(true)); cl::init(true));
static cl::opt<bool>
SetLRPredicate("arm-set-lr-predicate", cl::Hidden,
cl::desc("Enable setting lr as a predicate in tail predication regions."),
cl::init(true));
namespace { namespace {
class MVETPAndVPTOptimisations : public MachineFunctionPass { class MVETPAndVPTOptimisations : public MachineFunctionPass {
public: public:
static char ID; static char ID;
const Thumb2InstrInfo *TII; const Thumb2InstrInfo *TII;
MachineRegisterInfo *MRI; MachineRegisterInfo *MRI;
MVETPAndVPTOptimisations() : MachineFunctionPass(ID) {} MVETPAndVPTOptimisations() : MachineFunctionPass(ID) {}
▲ Show 20 Lines • Show All 378 Lines • ▼ Show 20 Linesbool MVETPAndVPTOptimisations::ConvertTailPredLoop(MachineLoop *ML,
MachineInstr *LoopEnd, *LoopPhi, *LoopStart, *LoopDec; MachineInstr *LoopEnd, *LoopPhi, *LoopStart, *LoopDec;
if (!findLoopComponents(ML, MRI, LoopStart, LoopPhi, LoopDec, LoopEnd)) if (!findLoopComponents(ML, MRI, LoopStart, LoopPhi, LoopDec, LoopEnd))
return false; return false;
if (LoopDec != LoopEnd || (LoopStart->getOpcode() != ARM::t2DoLoopStart && if (LoopDec != LoopEnd || (LoopStart->getOpcode() != ARM::t2DoLoopStart &&
LoopStart->getOpcode() != ARM::t2WhileLoopStartLR)) LoopStart->getOpcode() != ARM::t2WhileLoopStartLR))
return false; return false;
SmallVector<MachineInstr *, 4> VCTPs; SmallVector<MachineInstr *, 4> VCTPs;
for (MachineBasicBlock *BB : ML->blocks()) SmallVector<MachineInstr *, 4> MVEInstrs;
for (MachineBasicBlock *BB : ML->blocks()) {
for (MachineInstr &MI : *BB) for (MachineInstr &MI : *BB)
if (isVCTP(&MI)) if (isVCTP(&MI))
VCTPs.push_back(&MI); VCTPs.push_back(&MI);
else if (findFirstVPTPredOperandIdx(MI) != -1)
MVEInstrs.push_back(&MI);
}
if (VCTPs.empty()) { if (VCTPs.empty()) {
LLVM_DEBUG(dbgs() << " no VCTPs\n"); LLVM_DEBUG(dbgs() << " no VCTPs\n");
return false; return false;
} }
// Check all VCTPs are the same. // Check all VCTPs are the same.
MachineInstr *FirstVCTP = *VCTPs.begin(); MachineInstr *FirstVCTP = *VCTPs.begin();
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines MachineInstrBuilder MI =
.addReg(CountReg); .addReg(CountReg);
if (NewOpc == ARM::t2WhileLoopStartTP) if (NewOpc == ARM::t2WhileLoopStartTP)
MI.add(LoopStart->getOperand(2)); MI.add(LoopStart->getOperand(2));
LLVM_DEBUG(dbgs() << "Replacing " << *LoopStart << " with " LLVM_DEBUG(dbgs() << "Replacing " << *LoopStart << " with "
<< *MI.getInstr()); << *MI.getInstr());
MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass); MRI->constrainRegClass(CountReg, &ARM::rGPRRegClass);
LoopStart->eraseFromParent(); LoopStart->eraseFromParent();
if (SetLRPredicate) {
// Each instruction in the loop needs to be using LR as the predicate from
// the Phi as the predicate.
Register LR = LoopPhi->getOperand(0).getReg();
for (MachineInstr *MI : MVEInstrs) {
int Idx = findFirstVPTPredOperandIdx(*MI);
MI->getOperand(Idx + 2).setReg(LR);
}
}
return true; return true;
} }
// Returns true if Opcode is any VCMP Opcode. // Returns true if Opcode is any VCMP Opcode.
static bool IsVCMP(unsigned Opcode) { return VCMPOpcodeToVPT(Opcode) != 0; } static bool IsVCMP(unsigned Opcode) { return VCMPOpcodeToVPT(Opcode) != 0; }
// Returns true if a VCMP with this Opcode can have its operands swapped. // Returns true if a VCMP with this Opcode can have its operands swapped.
// There is 2 kind of VCMP that can't have their operands swapped: Float VCMPs, // There is 2 kind of VCMP that can't have their operands swapped: Float VCMPs,
▲ Show 20 Lines • Show All 465 Lines • ▼ Show 20 Lines for (MachineInstr &MI : MBB.instrs()) {
MachineInstrBuilder MIBuilder = MachineInstrBuilder MIBuilder =
BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(ARM::MVE_VORR)) BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(ARM::MVE_VORR))
.add(MI.getOperand(0)) .add(MI.getOperand(0))
.add(MI.getOperand(1)) .add(MI.getOperand(1))
.add(MI.getOperand(1)) .add(MI.getOperand(1))
.addImm(ARMVCC::Then) .addImm(ARMVCC::Then)
.add(MI.getOperand(4)) .add(MI.getOperand(4))
.add(MI.getOperand(5))
.add(MI.getOperand(2)); .add(MI.getOperand(2));
// Silence unused variable warning in release builds. // Silence unused variable warning in release builds.
(void)MIBuilder; (void)MIBuilder;
LLVM_DEBUG(dbgs() << "Replacing VPSEL: "; MI.dump(); LLVM_DEBUG(dbgs() << "Replacing VPSEL: "; MI.dump();
dbgs() << " with VMOVT: "; MIBuilder.getInstr()->dump()); dbgs() << " with VMOVT: "; MIBuilder.getInstr()->dump());
DeadInstructions.push_back(&MI); DeadInstructions.push_back(&MI);
} }
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/machine-outliner-unoutlinable.mir

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
name: dont_outline_mve name: dont_outline_mve
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: dont_outline_mve ; CHECK-LABEL: name: dont_outline_mve
; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION ; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION
bb.0: bb.0:
liveins: $r3, $r4, $q0, $q3, $q4, $q5 liveins: $r3, $r4, $q0, $q3, $q4, $q5
$q5 = MVE_VDUP32 $r3, 0, $noreg, $q5 $q5 = MVE_VDUP32 $r3, 0, $noreg, $noreg, $q5
$q4 = MVE_VDUP32 $r4, 0, $noreg, $q4 $q4 = MVE_VDUP32 $r4, 0, $noreg, $noreg, $q4
$q0 = MVE_VADDf32 $q4, $q5, 0, $noreg, $q0 $q0 = MVE_VADDf32 $q4, $q5, 0, $noreg, $noreg, $q0
$lr = t2DoLoopStart $r4 $lr = t2DoLoopStart $r4
$r0 = MVE_VMOV_from_lane_32 renamable $q0, 1, 14, $noreg $r0 = MVE_VMOV_from_lane_32 renamable $q0, 1, 14, $noreg
tBL 14, $noreg, @z tBL 14, $noreg, @z
bb.1: bb.1:
liveins: $r3, $r4, $q0, $q3, $q4, $q5 liveins: $r3, $r4, $q0, $q3, $q4, $q5
$q5 = MVE_VDUP32 $r3, 0, $noreg, $q5 $q5 = MVE_VDUP32 $r3, 0, $noreg, $noreg, $q5
$q4 = MVE_VDUP32 $r4, 0, $noreg, $q4 $q4 = MVE_VDUP32 $r4, 0, $noreg, $noreg, $q4
$q0 = MVE_VADDf32 $q4, $q5, 0, $noreg, $q0 $q0 = MVE_VADDf32 $q4, $q5, 0, $noreg, $noreg, $q0
$lr = t2DoLoopStart $r4 $lr = t2DoLoopStart $r4
$r0 = MVE_VMOV_from_lane_32 renamable $q0, 1, 14, $noreg $r0 = MVE_VMOV_from_lane_32 renamable $q0, 1, 14, $noreg
tBL 14, $noreg, @z tBL 14, $noreg, @z
bb.2: bb.2:
tBX_RET 14, $noreg tBX_RET 14, $noreg

llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14 /* CC::al */, $noreg ; CHECK: renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2WLS renamable $r7, %bb.3 ; CHECK: dead $lr = t2WLS renamable $r7, %bb.3
; CHECK: bb.1.for.body.lr.ph: ; CHECK: bb.1.for.body.lr.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $r12
; CHECK: $r6, $r5 = t2LDRDi8 $sp, 40, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.4, align 8), (load (s32) from %fixed-stack.5) ; CHECK: $r6, $r5 = t2LDRDi8 $sp, 40, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.4, align 8), (load (s32) from %fixed-stack.5)
; CHECK: $r4 = tMOVr killed $r7, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r7, 14 /* CC::al */, $noreg
; CHECK: $r7, $r8 = t2LDRDi8 $sp, 24, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8), (load (s32) from %fixed-stack.1) ; CHECK: $r7, $r8 = t2LDRDi8 $sp, 24, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8), (load (s32) from %fixed-stack.1)
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14 /* CC::al */, $noreg
; CHECK: bb.2.for.body: ; CHECK: bb.2.for.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12 ; CHECK: liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load (s128) from %ir.input_2_cast, align 4) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_2_cast, align 4)
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load (s128) from %ir.input_1_cast, align 4) ; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_1_cast, align 4)
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3 ; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2
; CHECK: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, $noreg, undef renamable $q2
; CHECK: renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg ; CHECK: renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg, $noreg
; CHECK: early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep2) ; CHECK: early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep2)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0 ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x40000000), %bb.3(0x40000000) successors: %bb.1(0x40000000), %bb.3(0x40000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $lr
Show All 14 Linesbody: |
bb.1.for.body.lr.ph: bb.1.for.body.lr.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $r12 liveins: $r0, $r1, $r2, $r3, $r7, $r12
$r6, $r5 = t2LDRDi8 $sp, 40, 14, $noreg :: (load (s32) from %fixed-stack.2, align 8), (load (s32) from %fixed-stack.1) $r6, $r5 = t2LDRDi8 $sp, 40, 14, $noreg :: (load (s32) from %fixed-stack.2, align 8), (load (s32) from %fixed-stack.1)
$r4 = tMOVr killed $r7, 14, $noreg $r4 = tMOVr killed $r7, 14, $noreg
$r7, $r8 = t2LDRDi8 $sp, 24, 14, $noreg :: (load (s32) from %fixed-stack.6, align 8), (load (s32) from %fixed-stack.5) $r7, $r8 = t2LDRDi8 $sp, 24, 14, $noreg :: (load (s32) from %fixed-stack.6, align 8), (load (s32) from %fixed-stack.5)
renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0
renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q1
renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14, $noreg renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14, $noreg
bb.2.for.body: bb.2.for.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12 liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load (s128) from %ir.input_2_cast, align 4) renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_2_cast, align 4)
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load (s128) from %ir.input_1_cast, align 4) renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_1_cast, align 4)
renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2
renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3 renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3
$lr = tMOVr $r4, 14, $noreg $lr = tMOVr $r4, 14, $noreg
renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14, $noreg renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14, $noreg
renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, $noreg, undef renamable $q2
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2 renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2
renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, undef renamable $q2 renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, $noreg, undef renamable $q2
renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg, $noreg
early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14, $noreg :: (store (s32) into %ir.scevgep2) early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14, $noreg :: (store (s32) into %ir.scevgep2)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
$r0, dead $cpsr = tMOVi8 0, 14, $noreg $r0, dead $cpsr = tMOVi8 0, 14, $noreg
$sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0 $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/begin-vpt-without-inst.mir

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: tCBZ $r0, %bb.3 ; CHECK: tCBZ $r0, %bb.3
; CHECK: bb.1.vector.ph.preheader: ; CHECK: bb.1.vector.ph.preheader:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0 ; CHECK: liveins: $r0
; CHECK: renamable $r1 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r1 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 3, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 3, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q1 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load (s128) from constant-pool, align 8) ; CHECK: renamable $q1 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)
; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @arr, 14 /* CC::al */, $noreg ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @arr, 14 /* CC::al */, $noreg
; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @arr, 14 /* CC::al */, $noreg ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @arr, 14 /* CC::al */, $noreg
; CHECK: renamable $vpr = MVE_VCMPu32 killed renamable $q0, killed renamable $q1, 8, 0, $noreg ; CHECK: renamable $vpr = MVE_VCMPu32 killed renamable $q0, killed renamable $q1, 8, 0, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 2, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 2, 0, $noreg, $noreg, undef renamable $q0
; CHECK: bb.2.vector.ph: ; CHECK: bb.2.vector.ph:
; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000) ; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000)
; CHECK: liveins: $vpr, $q0, $r0, $r1 ; CHECK: liveins: $vpr, $q0, $r0, $r1
; CHECK: renamable $r0, $cpsr = tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, $cpsr = tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: MVE_VSTRWU32 renamable $q0, renamable $r1, 0, 1, renamable $vpr :: (store (s128) into `<4 x i32>* bitcast ([0 x i32]* @arr to <4 x i32>*)`, align 4) ; CHECK: MVE_VSTRWU32 renamable $q0, renamable $r1, 0, 1, renamable $vpr, $noreg :: (store (s128) into `<4 x i32>* bitcast ([0 x i32]* @arr to <4 x i32>*)`, align 4)
; CHECK: tBcc %bb.2, 3 /* CC::lo */, killed $cpsr ; CHECK: tBcc %bb.2, 3 /* CC::lo */, killed $cpsr
; CHECK: bb.3.for.end5: ; CHECK: bb.3.for.end5:
; CHECK: tBX_RET 14 /* CC::al */, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
; CHECK: bb.4 (align 8): ; CHECK: bb.4 (align 8):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0 liveins: $r0
tCBZ $r0, %bb.3 tCBZ $r0, %bb.3
bb.1.vector.ph.preheader: bb.1.vector.ph.preheader:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0 liveins: $r0
renamable $r1 = tLEApcrel %const.0, 14 /* CC::al */, $noreg renamable $r1 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 3, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 3, 0, $noreg, $noreg, undef renamable $q0
renamable $q1 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load (s128) from constant-pool, align 8) renamable $q1 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)
$r1 = t2MOVi16 target-flags(arm-lo16) @arr, 14 /* CC::al */, $noreg $r1 = t2MOVi16 target-flags(arm-lo16) @arr, 14 /* CC::al */, $noreg
$r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @arr, 14 /* CC::al */, $noreg $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @arr, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCMPu32 killed renamable $q0, killed renamable $q1, 8, 0, $noreg renamable $vpr = MVE_VCMPu32 killed renamable $q0, killed renamable $q1, 8, 0, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 2, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 2, 0, $noreg, $noreg, undef renamable $q0
bb.2.vector.ph: bb.2.vector.ph:
successors: %bb.3(0x04000000), %bb.2(0x7c000000) successors: %bb.3(0x04000000), %bb.2(0x7c000000)
liveins: $vpr, $q0, $r0, $r1 liveins: $vpr, $q0, $r0, $r1
renamable $r0, $cpsr = tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg renamable $r0, $cpsr = tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 renamable $q0, renamable $r1, 0, 1, renamable $vpr :: (store (s128) into `<4 x i32>* bitcast ([0 x i32]* @arr to <4 x i32>*)`, align 4) MVE_VSTRWU32 renamable $q0, renamable $r1, 0, 1, renamable $vpr, $noreg :: (store (s128) into `<4 x i32>* bitcast ([0 x i32]* @arr to <4 x i32>*)`, align 4)
tBcc %bb.2, 3 /* CC::lo */, killed $cpsr tBcc %bb.2, 3 /* CC::lo */, killed $cpsr
bb.3.for.end5: bb.3.for.end5:
tBX_RET 14 /* CC::al */, $noreg tBX_RET 14 /* CC::al */, $noreg
bb.4 (align 8): bb.4 (align 8):
CONSTPOOL_ENTRY 0, %const.0, 16 CONSTPOOL_ENTRY 0, %const.0, 16
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/cmplx_cong.mir

Show All 40 Linesbody: |
; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg
; CHECK: $r4 = t2MOVi16 target-flags(arm-lo16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg ; CHECK: $r4 = t2MOVi16 target-flags(arm-lo16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg
; CHECK: $r4 = t2MOVTi16 killed $r4, target-flags(arm-hi16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg ; CHECK: $r4 = t2MOVTi16 killed $r4, target-flags(arm-hi16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nnan ninf nsz MVE_VLDRWU32 killed renamable $r4, 0, 0, $noreg ; CHECK: renamable $q0 = nnan ninf nsz MVE_VLDRWU32 killed renamable $r4, 0, 0, $noreg, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.1 (align 4): ; CHECK: bb.1 (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg, $noreg
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg, $noreg
; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0: bb.0:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r4, $lr liveins: $r0, $r1, $r2, $r4, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r4, -8 frame-setup CFI_INSTRUCTION offset $r4, -8
renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 /* CC::al */, $noreg
tCMPi8 renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
$r12 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate $r12 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg
$r4 = t2MOVi16 target-flags(arm-lo16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg $r4 = t2MOVi16 target-flags(arm-lo16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
$r4 = t2MOVTi16 killed $r4, target-flags(arm-hi16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg $r4 = t2MOVTi16 killed $r4, target-flags(arm-hi16) @arm_cmplx_conj_f32_mve.cmplx_conj_sign, 14 /* CC::al */, $noreg
renamable $q0 = nnan ninf nsz MVE_VLDRWU32 killed renamable $r4, 0, 0, $noreg renamable $q0 = nnan ninf nsz MVE_VLDRWU32 killed renamable $r4, 0, 0, $noreg, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.1 (align 4): bb.1 (align 4):
successors: %bb.1(0x7c000000), %bb.2(0x04000000) successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r3 liveins: $lr, $q0, $r0, $r1, $r3
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg
renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q1
MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr, $noreg
renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14 /* CC::al */, $noreg tB %bb.2, 14 /* CC::al */, $noreg
bb.2: bb.2:
tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/count_dominates_start.mir

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Linesbody: |
; CHECK: [[t2DoLoopStartTP:%[0-9]+]]:gprlr = t2DoLoopStartTP [[COPY4]], [[COPY6]] ; CHECK: [[t2DoLoopStartTP:%[0-9]+]]:gprlr = t2DoLoopStartTP [[COPY4]], [[COPY6]]
; CHECK: bb.3.vector.body: ; CHECK: bb.3.vector.body:
; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.2, %10, %bb.3 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.2, %10, %bb.3
; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.2, %9, %bb.3 ; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.2, %9, %bb.3
; CHECK: [[PHI2:%[0-9]+]]:tgpreven = PHI [[COPY5]], %bb.2, %8, %bb.3 ; CHECK: [[PHI2:%[0-9]+]]:tgpreven = PHI [[COPY5]], %bb.2, %8, %bb.3
; CHECK: [[PHI3:%[0-9]+]]:gprlr = PHI [[t2DoLoopStartTP]], %bb.2, %33, %bb.3 ; CHECK: [[PHI3:%[0-9]+]]:gprlr = PHI [[t2DoLoopStartTP]], %bb.2, %33, %bb.3
; CHECK: [[PHI4:%[0-9]+]]:rgpr = PHI [[COPY6]], %bb.2, %7, %bb.3 ; CHECK: [[PHI4:%[0-9]+]]:rgpr = PHI [[COPY6]], %bb.2, %7, %bb.3
; CHECK: [[MVE_VCTP16_:%[0-9]+]]:vccr = MVE_VCTP16 [[PHI4]], 0, $noreg ; CHECK: [[MVE_VCTP16_:%[0-9]+]]:vccr = MVE_VCTP16 [[PHI4]], 0, $noreg, $noreg
; CHECK: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[PHI4]], 8, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[PHI4]], 8, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[COPY7:%[0-9]+]]:gpr = COPY [[t2SUBri1]] ; CHECK: [[COPY7:%[0-9]+]]:gpr = COPY [[t2SUBri1]]
; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI]], 16, 1, [[MVE_VCTP16_]] :: (load (s128) from %ir.lsr.iv35, align 2) ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI]], 16, 1, [[MVE_VCTP16_]], [[PHI3]] :: (load (s128) from %ir.lsr.iv35, align 2)
; CHECK: [[MVE_VLDRHU16_post2:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post3:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI1]], 16, 1, [[MVE_VCTP16_]] :: (load (s128) from %ir.lsr.iv12, align 2) ; CHECK: [[MVE_VLDRHU16_post2:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post3:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI1]], 16, 1, [[MVE_VCTP16_]], [[PHI3]] :: (load (s128) from %ir.lsr.iv12, align 2)
; CHECK: [[MVE_VMLADAVas16_:%[0-9]+]]:tgpreven = MVE_VMLADAVas16 [[PHI2]], killed [[MVE_VLDRHU16_post3]], killed [[MVE_VLDRHU16_post1]], 1, [[MVE_VCTP16_]] ; CHECK: [[MVE_VMLADAVas16_:%[0-9]+]]:tgpreven = MVE_VMLADAVas16 [[PHI2]], killed [[MVE_VLDRHU16_post3]], killed [[MVE_VLDRHU16_post1]], 1, [[MVE_VCTP16_]], [[PHI3]]
; CHECK: [[COPY8:%[0-9]+]]:gpr = COPY [[MVE_VMLADAVas16_]] ; CHECK: [[COPY8:%[0-9]+]]:gpr = COPY [[MVE_VMLADAVas16_]]
; CHECK: [[COPY9:%[0-9]+]]:gpr = COPY [[MVE_VLDRHU16_post2]] ; CHECK: [[COPY9:%[0-9]+]]:gpr = COPY [[MVE_VLDRHU16_post2]]
; CHECK: [[COPY10:%[0-9]+]]:gpr = COPY [[MVE_VLDRHU16_post]] ; CHECK: [[COPY10:%[0-9]+]]:gpr = COPY [[MVE_VLDRHU16_post]]
; CHECK: [[t2LoopEndDec:%[0-9]+]]:gprlr = t2LoopEndDec [[PHI3]], %bb.3, implicit-def $cpsr ; CHECK: [[t2LoopEndDec:%[0-9]+]]:gprlr = t2LoopEndDec [[PHI3]], %bb.3, implicit-def $cpsr
; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.4.for.cond.cleanup: ; CHECK: bb.4.for.cond.cleanup:
; CHECK: [[PHI5:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.1, [[COPY8]], %bb.3 ; CHECK: [[PHI5:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.1, [[COPY8]], %bb.3
; CHECK: $r0 = COPY [[PHI5]] ; CHECK: $r0 = COPY [[PHI5]]
Show All 33 Linesbody: |
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
%2:rgpr = PHI %13, %bb.1, %10, %bb.2 %2:rgpr = PHI %13, %bb.1, %10, %bb.2
%3:rgpr = PHI %14, %bb.1, %9, %bb.2 %3:rgpr = PHI %14, %bb.1, %9, %bb.2
%4:tgpreven = PHI %23, %bb.1, %8, %bb.2 %4:tgpreven = PHI %23, %bb.1, %8, %bb.2
%5:gprlr = PHI %1, %bb.1, %11, %bb.2 %5:gprlr = PHI %1, %bb.1, %11, %bb.2
%6:rgpr = PHI %35, %bb.1, %7, %bb.2 %6:rgpr = PHI %35, %bb.1, %7, %bb.2
%26:vccr = MVE_VCTP16 %6, 0, $noreg %26:vccr = MVE_VCTP16 %6, 0, $noreg, $noreg
%27:rgpr = t2SUBri %6, 8, 14 /* CC::al */, $noreg, $noreg %27:rgpr = t2SUBri %6, 8, 14 /* CC::al */, $noreg, $noreg
%7:gpr = COPY %27 %7:gpr = COPY %27
%28:rgpr, %29:mqpr = MVE_VLDRHU16_post %2, 16, 1, %26 :: (load (s128) from %ir.lsr.iv35, align 2) %28:rgpr, %29:mqpr = MVE_VLDRHU16_post %2, 16, 1, %26, $noreg :: (load (s128) from %ir.lsr.iv35, align 2)
%30:rgpr, %31:mqpr = MVE_VLDRHU16_post %3, 16, 1, %26 :: (load (s128) from %ir.lsr.iv12, align 2) %30:rgpr, %31:mqpr = MVE_VLDRHU16_post %3, 16, 1, %26, $noreg :: (load (s128) from %ir.lsr.iv12, align 2)
%32:tgpreven = MVE_VMLADAVas16 %4, killed %31, killed %29, 1, %26 %32:tgpreven = MVE_VMLADAVas16 %4, killed %31, killed %29, 1, %26, $noreg
%8:gpr = COPY %32 %8:gpr = COPY %32
%9:gpr = COPY %30 %9:gpr = COPY %30
%10:gpr = COPY %28 %10:gpr = COPY %28
%33:gprlr = t2LoopDec %5, 1 %33:gprlr = t2LoopDec %5, 1
%11:gpr = COPY %33 %11:gpr = COPY %33
t2LoopEnd %33, %bb.2, implicit-def dead $cpsr t2LoopEnd %33, %bb.2, implicit-def dead $cpsr
t2B %bb.3, 14 /* CC::al */, $noreg t2B %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
%12:gpr = PHI %16, %bb.4, %8, %bb.2 %12:gpr = PHI %16, %bb.4, %8, %bb.2
$r0 = COPY %12 $r0 = COPY %12
tBX_RET 14 /* CC::al */, $noreg, implicit $r0 tBX_RET 14 /* CC::al */, $noreg, implicit $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) ; CHECK: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: bb.2.loop.body: ; CHECK: bb.2.loop.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r4 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.b, align 2) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 2)
; CHECK: renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 1, renamable $vpr :: (load (s128) from %ir.addr.a, align 2) ; CHECK: renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 2)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VCLZs8 killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VCLZs8 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg ; CHECK: renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.addr.c, align 2) ; CHECK: renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 2)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
Show All 12 Lines bb.1.loop.ph:
renamable $lr = t2DoLoopStart killed renamable $lr renamable $lr = t2DoLoopStart killed renamable $lr
$r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg
bb.2.loop.body: bb.2.loop.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3, $r4 liveins: $r0, $r1, $r2, $r3, $r4
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.b, align 2) renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 2)
renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 1, renamable $vpr :: (load (s128) from %ir.addr.a, align 2) renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 2)
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VCLZs8 killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VCLZs8 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r1, 14 /* CC::al */, $noreg $r0 = tMOVr $r1, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.addr.c, align 2) renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 2)
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
... ...
--- ---
Show All 40 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r4 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4
; CHECK: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) ; CHECK: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: bb.2.loop.body: ; CHECK: bb.2.loop.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r12
; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.b, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.a, align 4) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q1 = MVE_VCLZs16 killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VCLZs16 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg ; CHECK: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.addr.c, align 4) ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $r4 ; CHECK: liveins: $r4
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def dead $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def dead $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
Show All 13 Lines bb.1.loop.ph:
renamable $lr = t2DoLoopStart killed renamable $lr renamable $lr = t2DoLoopStart killed renamable $lr
$r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg
bb.2.loop.body: bb.2.loop.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
$lr = tMOVr $r12, 14 /* CC::al */, $noreg $lr = tMOVr $r12, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.b, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.a, align 4) renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
renamable $q1 = MVE_VCLZs16 killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VCLZs16 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.addr.c, align 4) renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
... ...
--- ---
Show All 40 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r4 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4
; CHECK: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) ; CHECK: renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: bb.2.loop.body: ; CHECK: bb.2.loop.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r12
; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.a, align 4) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)
; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.b, align 4) ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q1 = MVE_VCLZs32 killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VCLZs32 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VQSHRUNs32th killed renamable $q0, killed renamable $q1, 3, 0, $noreg ; CHECK: renamable $q0 = MVE_VQSHRUNs32th killed renamable $q0, killed renamable $q1, 3, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.addr.c, align 4) ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $r4 ; CHECK: liveins: $r4
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def dead $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def dead $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
Show All 13 Lines bb.1.loop.ph:
renamable $lr = t2DoLoopStart killed renamable $lr renamable $lr = t2DoLoopStart killed renamable $lr
$r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg
bb.2.loop.body: bb.2.loop.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
$lr = tMOVr $r12, 14 /* CC::al */, $noreg $lr = tMOVr $r12, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.a, align 4) renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)
renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.b, align 4) renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
renamable $q1 = MVE_VCLZs32 killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VCLZs32 killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q0 = MVE_VQSHRUNs32th killed renamable $q0, killed renamable $q1, 3, 0, $noreg renamable $q0 = MVE_VQSHRUNs32th killed renamable $q0, killed renamable $q1, 3, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.addr.c, align 4) renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir

Show First 20 Lines • Show All 139 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r4 = t2BICri killed renamable $r4, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r4 = t2BICri killed renamable $r4, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s16) from %ir.mask.gep9) ; CHECK: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s16) from %ir.mask.gep9)
; CHECK: renamable $r12 = t2SUBri killed renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: $vpr = VMSR_P0 $r5, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 $r5, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: bb.2.bb9: ; CHECK: bb.2.bb9:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv24, align 4) ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
; CHECK: renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv1, align 4) ; CHECK: renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load (s128) from %ir.scevgep2, align 8) ; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep2, align 8)
; CHECK: MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr ; CHECK: MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr
; CHECK: MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.bb27: ; CHECK: bb.3.bb27:
; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
bb.0.bb: bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
Show All 18 Lines bb.1.bb3:
renamable $r4 = t2BICri killed renamable $r4, 3, 14, $noreg, $noreg renamable $r4 = t2BICri killed renamable $r4, 3, 14, $noreg, $noreg
renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load (s16) from %ir.mask.gep9) renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load (s16) from %ir.mask.gep9)
renamable $r12 = t2SUBri killed renamable $r4, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r4, 4, 14, $noreg, $noreg
renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg
$vpr = VMSR_P0 $r5, 14, $noreg $vpr = VMSR_P0 $r5, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg
VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0) VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0)
renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, $noreg, undef renamable $q0
$r3 = tMOVr $r0, 14, $noreg $r3 = tMOVr $r0, 14, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.bb9: bb.2.bb9:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12
renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0) renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0)
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv24, align 4) renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv1, align 4) renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load (s128) from %ir.scevgep2, align 8) renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep2, align 8)
MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr
MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1, align 4) MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r3, 14, $noreg $r0 = tMOVr $r3, 14, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.bb27: bb.3.bb27:
$sp = tADDspi $sp, 1, 14, $noreg $sp = tADDspi $sp, 1, 14, $noreg
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir

Show First 20 Lines • Show All 96 Lines • ▼ Show 20 Linesbody: |
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load (s128) from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.1.do.body (align 4): ; CHECK: bb.1.do.body (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg, $lr
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $lr, undef renamable $q1
; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg, $lr
; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.do.end: ; CHECK: bb.2.do.end:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 16): ; CHECK: bb.3 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
Show All 9 Lines bb.0.entry:
tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
$r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
renamable $r2 = tLEApcrel %const.0, 14, $noreg renamable $r2 = tLEApcrel %const.0, 14, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load (s128) from constant-pool) renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.1.do.body (align 4): bb.1.do.body (align 4):
successors: %bb.1(0x7c000000), %bb.2(0x04000000) successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r3 liveins: $lr, $q0, $r0, $r1, $r3
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $lr
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $lr
renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $lr, undef renamable $q1
MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr, $lr
renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14, $noreg tB %bb.2, 14, $noreg
bb.2.do.end: bb.2.do.end:
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
bb.3 (align 16): bb.3 (align 16):
CONSTPOOL_ENTRY 0, %const.0, 16 CONSTPOOL_ENTRY 0, %const.0, 16
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir

Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $lr :: (load (s128) from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $lr :: (load (s128) from %ir.lsr.iv1416, align 4)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $lr :: (store (s128) into %ir.lsr.iv1719, align 4)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
Show All 17 Lines bb.1.vector.ph:
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $lr :: (load (s128) from %ir.lsr.iv13, align 4)
renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $lr :: (load (s128) from %ir.lsr.iv1416, align 4)
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1719, align 4) renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $lr :: (store (s128) into %ir.lsr.iv1719, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir

Show First 20 Lines • Show All 406 Lines • ▼ Show 20 Lines bb.0.entry:
tCMPi8 renamable $r4, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r4, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 10, 8, implicit-def $itstate t2IT 10, 8, implicit-def $itstate
renamable $r1 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate renamable $r1 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate
renamable $r1, dead $cpsr = tSUBrr renamable $r4, killed renamable $r1, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBrr renamable $r4, killed renamable $r1, 14 /* CC::al */, $noreg
renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3 = tLDRi killed renamable $r0, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.NumFilters) renamable $r3 = tLDRi killed renamable $r0, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.NumFilters)
$r0 = tMOVr $r4, 14 /* CC::al */, $noreg $r0 = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
$r1 = tMOVr $r5, 14 /* CC::al */, $noreg $r1 = tMOVr $r5, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.1.do.body (align 4): bb.1.do.body (align 4):
successors: %bb.1(0x7c000000), %bb.2(0x04000000) successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r11 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r11
renamable $vpr = MVE_VCTP32 renamable $r0, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r0, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.pInT.033, align 4) renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pInT.033, align 4)
renamable $q0 = MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, undef renamable $q0 renamable $q0 = MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, undef renamable $q0
renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14 /* CC::al */, $noreg tB %bb.2, 14 /* CC::al */, $noreg
bb.2.do.end: bb.2.do.end:
successors: %bb.3(0x40000000), %bb.7(0x40000000) successors: %bb.3(0x40000000), %bb.7(0x40000000)
liveins: $q0, $r2, $r3, $r4, $r5, $r11 liveins: $q0, $r2, $r3, $r4, $r5, $r11
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines bb.4.for.body (align 4):
liveins: $r0, $r1, $r2, $r4, $r5, $r6, $r10, $r11, $r12 liveins: $r0, $r1, $r2, $r4, $r5, $r6, $r10, $r11, $r12
renamable $r3 = t2MUL renamable $r0, renamable $r4, 14 /* CC::al */, $noreg renamable $r3 = t2MUL renamable $r0, renamable $r4, 14 /* CC::al */, $noreg
renamable $r7, dead $cpsr = nuw nsw tADDi3 renamable $r0, 1, 14 /* CC::al */, $noreg renamable $r7, dead $cpsr = nuw nsw tADDi3 renamable $r0, 1, 14 /* CC::al */, $noreg
renamable $r8 = nuw nsw t2ADDri renamable $r0, 2, 14 /* CC::al */, $noreg, $noreg renamable $r8 = nuw nsw t2ADDri renamable $r0, 2, 14 /* CC::al */, $noreg, $noreg
tSTRspi renamable $r7, $sp, 9, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) tSTRspi renamable $r7, $sp, 9, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
renamable $r9 = t2ADDri renamable $r0, 3, 14 /* CC::al */, $noreg, $noreg renamable $r9 = t2ADDri renamable $r0, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r7, dead $cpsr = tMUL renamable $r4, killed renamable $r7, 14 /* CC::al */, $noreg renamable $r7, dead $cpsr = tMUL renamable $r4, killed renamable $r7, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r5, 0, 0, $noreg :: (load (s128) from %ir.39, align 4) renamable $q0 = MVE_VLDRWU32 killed renamable $r5, 0, 0, $noreg, $noreg :: (load (s128) from %ir.39, align 4)
renamable $r3 = t2ADDrs renamable $r11, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2ADDrs renamable $r11, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg
renamable $r5 = t2MUL renamable $r8, renamable $r4, 14 /* CC::al */, $noreg renamable $r5 = t2MUL renamable $r8, renamable $r4, 14 /* CC::al */, $noreg
renamable $r4 = t2MUL renamable $r9, killed renamable $r4, 14 /* CC::al */, $noreg renamable $r4 = t2MUL renamable $r9, killed renamable $r4, 14 /* CC::al */, $noreg
renamable $r7 = t2ADDrs renamable $r11, killed renamable $r7, 18, 14 /* CC::al */, $noreg, $noreg renamable $r7 = t2ADDrs renamable $r11, killed renamable $r7, 18, 14 /* CC::al */, $noreg, $noreg
renamable $r5 = t2ADDrs renamable $r11, killed renamable $r5, 18, 14 /* CC::al */, $noreg, $noreg renamable $r5 = t2ADDrs renamable $r11, killed renamable $r5, 18, 14 /* CC::al */, $noreg, $noreg
renamable $r4 = t2ADDrs killed renamable $r11, killed renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg renamable $r4 = t2ADDrs killed renamable $r11, killed renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
renamable $q1 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from %ir.41, align 4) renamable $q1 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %ir.41, align 4)
renamable $q3 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q3 renamable $q3 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q3
renamable $q1 = MVE_VLDRWU32 killed renamable $r7, 0, 0, $noreg :: (load (s128) from %ir.44, align 4) renamable $q1 = MVE_VLDRWU32 killed renamable $r7, 0, 0, $noreg, $noreg :: (load (s128) from %ir.44, align 4)
renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q2 renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q2
renamable $q1 = MVE_VLDRWU32 killed renamable $r5, 0, 0, $noreg :: (load (s128) from %ir.47, align 4) renamable $q1 = MVE_VLDRWU32 killed renamable $r5, 0, 0, $noreg, $noreg :: (load (s128) from %ir.47, align 4)
renamable $q1 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
renamable $q4 = MVE_VLDRWU32 killed renamable $r4, 0, 0, $noreg :: (load (s128) from %ir.50, align 4) renamable $q4 = MVE_VLDRWU32 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s128) from %ir.50, align 4)
renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q4, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VMULf32 killed renamable $q4, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %stack.7) renamable $lr = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %stack.7)
$r3 = tMOVr $r10, 14 /* CC::al */, $noreg $r3 = tMOVr $r10, 14 /* CC::al */, $noreg
$r5 = tMOVr $r1, 14 /* CC::al */, $noreg $r5 = tMOVr $r1, 14 /* CC::al */, $noreg
$r4 = tMOVr $r12, 14 /* CC::al */, $noreg $r4 = tMOVr $r12, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
$r7 = tMOVr $r6, 14 /* CC::al */, $noreg $r7 = tMOVr $r6, 14 /* CC::al */, $noreg
renamable $r11 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load (s32) from %stack.5) renamable $r11 = t2LDRi12 $sp, 16, 14 /* CC::al */, $noreg :: (load (s32) from %stack.5)
bb.5.do.body24 (align 4): bb.5.do.body24 (align 4):
successors: %bb.5(0x7c000000), %bb.6(0x04000000) successors: %bb.5(0x7c000000), %bb.6(0x04000000)
liveins: $lr, $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 liveins: $lr, $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $r11, renamable $q4 = MVE_VLDRWU32_post killed renamable $r11, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv4, align 4) renamable $r11, renamable $q4 = MVE_VLDRWU32_post killed renamable $r11, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv4, align 4)
renamable $r7, renamable $q5 = MVE_VLDRWU32_post killed renamable $r7, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv911, align 4) renamable $r7, renamable $q5 = MVE_VLDRWU32_post killed renamable $r7, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv911, align 4)
renamable $q3 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q3, renamable $q4, killed renamable $q5, 0, $noreg renamable $q3 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q3, renamable $q4, killed renamable $q5, 0, $noreg, $noreg
renamable $r4, renamable $q5 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv1618, align 4) renamable $r4, renamable $q5 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1618, align 4)
renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q2, renamable $q4, killed renamable $q5, 0, $noreg renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q2, renamable $q4, killed renamable $q5, 0, $noreg, $noreg
renamable $r5, renamable $q5 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv2325, align 4) renamable $r5, renamable $q5 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv2325, align 4)
renamable $q1 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q1, renamable $q4, killed renamable $q5, 0, $noreg renamable $q1 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q1, renamable $q4, killed renamable $q5, 0, $noreg, $noreg
renamable $r3, renamable $q5 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv3032, align 4) renamable $r3, renamable $q5 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv3032, align 4)
renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q4, killed renamable $q5, 0, $noreg renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q4, killed renamable $q5, 0, $noreg, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr
tB %bb.6, 14 /* CC::al */, $noreg tB %bb.6, 14 /* CC::al */, $noreg
bb.6.do.end33: bb.6.do.end33:
successors: %bb.4(0x7c000000), %bb.7(0x04000000) successors: %bb.4(0x7c000000), %bb.7(0x04000000)
liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r6, $r8, $r9, $r10, $r12 liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r6, $r8, $r9, $r10, $r12
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines bb.8.for.body56.preheader:
renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
bb.9.for.body56 (align 4): bb.9.for.body56 (align 4):
successors: %bb.13(0x80000000) successors: %bb.13(0x80000000)
liveins: $r0, $r2, $r3, $r4, $r5, $r11, $r12 liveins: $r0, $r2, $r3, $r4, $r5, $r11, $r12
renamable $r1 = t2MUL renamable $r0, renamable $r4, 14 /* CC::al */, $noreg renamable $r1 = t2MUL renamable $r0, renamable $r4, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r1 = t2ADDrs renamable $r11, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg renamable $r1 = t2ADDrs renamable $r11, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg
$r6 = tMOVr $r4, 14 /* CC::al */, $noreg $r6 = tMOVr $r4, 14 /* CC::al */, $noreg
$r7 = tMOVr $r5, 14 /* CC::al */, $noreg $r7 = tMOVr $r5, 14 /* CC::al */, $noreg
$lr = tMOVr $r3, 14 /* CC::al */, $noreg $lr = tMOVr $r3, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $r3 $lr = t2DoLoopStart renamable $r3
bb.13: bb.13:
successors: %bb.10(0x80000000) successors: %bb.10(0x80000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r11, $r12 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r11, $r12
bb.10.do.body59 (align 4): bb.10.do.body59 (align 4):
successors: %bb.10(0x7c000000), %bb.11(0x04000000) successors: %bb.10(0x7c000000), %bb.11(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r11, $r12 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r11, $r12
renamable $vpr = MVE_VCTP32 renamable $r6, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r6, 0, $noreg, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $r7, renamable $q1 = MVE_VLDRWU32_post killed renamable $r7, 16, 1, renamable $vpr :: (load (s128) from %ir.pInT.21, align 4) renamable $r7, renamable $q1 = MVE_VLDRWU32_post killed renamable $r7, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pInT.21, align 4)
renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.pCos0.12, align 4) renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pCos0.12, align 4)
renamable $q0 = MVE_VFMAf32 killed renamable $q0, killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr renamable $q0 = MVE_VFMAf32 killed renamable $q0, killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg
renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 4, 14 /* CC::al */, $noreg renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.10, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.10, implicit-def dead $cpsr
tB %bb.11, 14 /* CC::al */, $noreg tB %bb.11, 14 /* CC::al */, $noreg
bb.11.do.end66: bb.11.do.end66:
successors: %bb.12(0x04000000), %bb.9(0x7c000000) successors: %bb.12(0x04000000), %bb.9(0x7c000000)
liveins: $q0, $r0, $r2, $r3, $r4, $r5, $r11, $r12 liveins: $q0, $r0, $r2, $r3, $r4, $r5, $r11, $r12
Show All 17 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Linesbody: |
; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: $r0 = VMOVRS killed $s3, 14 /* CC::al */, $noreg, implicit killed $q0 ; CHECK: $r0 = VMOVRS killed $s3, 14 /* CC::al */, $noreg, implicit killed $q0
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r3 = tMOVr killed $r12, 14, $noreg $r3 = tMOVr killed $r12, 14, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2, $r3 liveins: $q0, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
$lr = tMOVr $r3, 14, $noreg $lr = tMOVr $r3, 14, $noreg
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0 liveins: $q0
$r0 = VMOVRS killed $s3, 14, $noreg, implicit $q0 $r0 = VMOVRS killed $s3, 14, $noreg, implicit $q0
tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
Show All 14 Lines bb.1.vector.ph:
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14, $noreg
renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1719, align 4) renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir

Show First 20 Lines • Show All 118 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 5, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 5, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
Show All 14 Lines bb.1.vector.ph:
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 5, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 5, 14, $noreg
renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1719, align 4) renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
Show All 14 Lines bb.1.vector.ph:
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14, $noreg
renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1719, align 4) renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17.d, align 2) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)
; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820.c, align 2) ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.cast.e, align 4) ; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.cast.e, align 4)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
Show All 10 Lines bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg
renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg
renamable $r5 = tLDRspi $sp, 4, 14, $noreg :: (load (s32) from %fixed-stack.1, align 8) renamable $r5 = tLDRspi $sp, 4, 14, $noreg :: (load (s32) from %fixed-stack.1, align 8)
renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
$r4 = tMOVr killed $lr, 14, $noreg $r4 = tMOVr killed $lr, 14, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17.d, align 2) renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)
renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820.c, align 2) renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
$lr = tMOVr $r4, 14, $noreg $lr = tMOVr $r4, 14, $noreg
renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.cast.e, align 4) renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.cast.e, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17.d, align 2) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)
; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820.c, align 2) ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, killed renamable $vpr, $noreg
; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.cast.e, align 4) ; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.cast.e, align 4)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
Show All 10 Lines bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg
renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg
renamable $r5 = tLDRspi $sp, 4, 14, $noreg :: (load (s32) from %fixed-stack.1, align 8) renamable $r5 = tLDRspi $sp, 4, 14, $noreg :: (load (s32) from %fixed-stack.1, align 8)
renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
$r4 = tMOVr killed $lr, 14, $noreg $r4 = tMOVr killed $lr, 14, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17.d, align 2) renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)
renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820.c, align 2) renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
$lr = tMOVr $r4, 14, $noreg $lr = tMOVr $r4, 14, $noreg
renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $vpr = MVE_VPNOT renamable $vpr, 0, killed renamable $vpr renamable $vpr = MVE_VPNOT renamable $vpr, 0, killed renamable $vpr, $noreg
renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.cast.e, align 4) renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.cast.e, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17.d, align 2) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)
; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820.c, align 2) ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, renamable $vpr, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, renamable $vpr, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, renamable $vpr, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, renamable $vpr, $noreg, undef renamable $q0
; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, renamable $vpr :: (store (s128) into %ir.lsr.cast.e, align 4) ; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, renamable $vpr, $noreg :: (store (s128) into %ir.lsr.cast.e, align 4)
; CHECK: dead renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: dead renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
Show All 10 Lines bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg
renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg
renamable $r5 = tLDRspi $sp, 4, 14, $noreg :: (load (s32) from %fixed-stack.1, align 8) renamable $r5 = tLDRspi $sp, 4, 14, $noreg :: (load (s32) from %fixed-stack.1, align 8)
renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
$r4 = tMOVr killed $lr, 14, $noreg $r4 = tMOVr killed $lr, 14, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17.d, align 2) renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)
renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820.c, align 2) renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
$lr = tMOVr $r4, 14, $noreg $lr = tMOVr $r4, 14, $noreg
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, renamable $vpr, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, renamable $vpr, $noreg, undef renamable $q1
renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, renamable $vpr, undef renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, renamable $vpr, $noreg, undef renamable $q0
renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, renamable $vpr :: (store (s128) into %ir.lsr.cast.e, align 4) renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, renamable $vpr, $noreg :: (store (s128) into %ir.lsr.cast.e, align 4)
renamable $vpr = MVE_VPNOT renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT renamable $vpr, 0, $noreg, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir

Show First 20 Lines • Show All 139 Lines • ▼ Show 20 Linesbody: |
; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r5 ; CHECK: dead $lr = t2DLS renamable $r5
; CHECK: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17.d, align 2) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)
; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820.c, align 2) ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.4(0x30000000), %bb.1(0x50000000) successors: %bb.4(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
Show All 9 Linesbody: |
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg
renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg
renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $r5 $lr = t2DoLoopStart renamable $r5
$r4 = tMOVr killed $r5, 14, $noreg $r4 = tMOVr killed $r5, 14, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17.d, align 2) renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)
renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820.c, align 2) renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
$lr = tMOVr $r4, 14, $noreg $lr = tMOVr $r4, 14, $noreg
renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg
renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0 liveins: $q0
renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
bb.4: bb.4:
renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Linesbody: |
; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr ; CHECK: tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r5 ; CHECK: dead $lr = t2DLS renamable $r5
; CHECK: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r5, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17.d, align 2) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)
; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820.c, align 2) ; CHECK: renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
; CHECK: renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, $noreg, undef renamable $q2
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.4(0x30000000), %bb.1(0x50000000) successors: %bb.4(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr
Show All 9 Linesbody: |
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg
renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg
renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $r5 $lr = t2DoLoopStart renamable $r5
$r4 = tMOVr killed $r5, 14, $noreg $r4 = tMOVr killed $r5, 14, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17.d, align 2) renamable $r3, renamable $q1 = MVE_VLDRHS32_post killed renamable $r3, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17.d, align 2)
renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820.c, align 2) renamable $r2, renamable $q2 = MVE_VLDRHS32_post killed renamable $r2, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820.c, align 2)
renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, undef renamable $q2 renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, $noreg, undef renamable $q2
$lr = tMOVr $r4, 14, $noreg $lr = tMOVr $r4, 14, $noreg
renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg
renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0 liveins: $q0
renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
bb.4: bb.4:
renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/invariant-qreg.mir

Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
; CHECK: tCBZ $r2, %bb.3 ; CHECK: tCBZ $r2, %bb.3
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $q0, $r0, $r1, $r2 ; CHECK: liveins: $q0, $r0, $r1, $r2
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $r0, $r1 ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $q2 = nsw MVE_VMULi32 renamable $q0, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q1, killed renamable $r1, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.store, align 4) ; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q1, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.store, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0 ; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
tCBZ $r2, %bb.3 tCBZ $r2, %bb.3
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $q0, $r0, $r1, $r2 liveins: $q0, $r0, $r1, $r2
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $q1, $r0, $r1, $r2, $r3 liveins: $q0, $q1, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
$lr = tMOVr $r3, 14 /* CC::al */, $noreg $lr = tMOVr $r3, 14 /* CC::al */, $noreg
renamable $q2 = nsw MVE_VMULi32 renamable $q0, killed renamable $q2, 0, $noreg, undef renamable $q2 renamable $q2 = nsw MVE_VMULi32 renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r1 = MVE_VSTRWU32_post renamable $q1, killed renamable $r1, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.store, align 4) renamable $r1 = MVE_VSTRWU32_post renamable $q1, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.store, align 4)
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
liveins: $q0 liveins: $q0
renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg
renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit $q0 renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit $q0
Show All 40 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r2 ; CHECK: liveins: $r0, $r2
; CHECK: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg ; CHECK: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
; CHECK: dead $lr = t2DLS renamable $r3 ; CHECK: dead $lr = t2DLS renamable $r3
; CHECK: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2 ; CHECK: liveins: $q0, $r0, $r1, $r2
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
; CHECK: $lr = tMOVr $r1, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r12 = MVE_VMLADAVu32 renamable $q0, killed renamable $q1, 0, $noreg ; CHECK: renamable $r12 = MVE_VMLADAVu32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $r12 ; CHECK: liveins: $r12
; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
Show All 13 Lines bb.1.vector.ph:
liveins: $r0, $r2 liveins: $r0, $r2
renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
$lr = t2DoLoopStart renamable $r3 $lr = t2DoLoopStart renamable $r3
$r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2 liveins: $q0, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
$lr = tMOVr $r1, 14 /* CC::al */, $noreg $lr = tMOVr $r1, 14 /* CC::al */, $noreg
renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r12 = MVE_VMLADAVu32 renamable $q0, killed renamable $q1, 0, $noreg renamable $r12 = MVE_VMLADAVu32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
liveins: $r12 liveins: $r12
$r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r2 ; CHECK: liveins: $r0, $r2
; CHECK: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg ; CHECK: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
; CHECK: dead $lr = t2DLS renamable $r3 ; CHECK: dead $lr = t2DLS renamable $r3
; CHECK: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2 ; CHECK: liveins: $q0, $r0, $r1, $r2
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: $lr = tMOVr $r1, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $r12 ; CHECK: liveins: $r12
; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
Show All 13 Lines bb.1.vector.ph:
liveins: $r0, $r2 liveins: $r0, $r2
renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
$lr = t2DoLoopStart renamable $r3 $lr = t2DoLoopStart renamable $r3
$r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2 liveins: $q0, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
$lr = tMOVr $r1, 14 /* CC::al */, $noreg $lr = tMOVr $r1, 14 /* CC::al */, $noreg
renamable $q1 = nsw MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $r12 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg renamable $r12 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
liveins: $r12 liveins: $r12
$r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.4: bb.4:
renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
$r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir

Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Linesbody: |
; CHECK: t2STRi12 killed renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.iter.addr) ; CHECK: t2STRi12 killed renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.iter.addr)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12
; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: bb.1.do.body: ; CHECK: bb.1.do.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: $lr = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4)
; CHECK: renamable $q0 = MVE_VMULf32 killed renamable $q0, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMULf32 killed renamable $q0, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 0, killed $noreg :: (store (s128) into %ir.pDst.addr.01, align 4) ; CHECK: renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.pDst.addr.01, align 4)
; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.do.end: ; CHECK: bb.2.do.end:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
Show All 13 Lines bb.0.entry:
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
$r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg
bb.1.do.body: bb.1.do.body:
successors: %bb.1(0x7c000000), %bb.2(0x04000000) successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $r0, $r1, $r2, $r12 liveins: $r0, $r1, $r2, $r12
$lr = tMOVr $r2, 14 /* CC::al */, $noreg $lr = tMOVr $r2, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg
renamable $r12 = nsw t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nsw t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.pSrc.addr.02, align 4) renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q0 = MVE_VMULf32 killed renamable $q0, renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMULf32 killed renamable $q0, renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr :: (store (s128) into %ir.pDst.addr.01, align 4) renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.pDst.addr.01, align 4)
t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14 /* CC::al */, $noreg tB %bb.2, 14 /* CC::al */, $noreg
bb.2.do.end: bb.2.do.end:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
... ...
--- ---
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesbody: |
; CHECK: t2STRi12 killed renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.iter.addr) ; CHECK: t2STRi12 killed renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.iter.addr)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12
; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: bb.1.do.body: ; CHECK: bb.1.do.body:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: $lr = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4)
; CHECK: renamable $q0 = MVE_VMULf32 killed renamable $q0, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMULf32 killed renamable $q0, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 0, killed $noreg :: (store (s128) into %ir.pDst.addr.01, align 4) ; CHECK: renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.pDst.addr.01, align 4)
; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.do.end: ; CHECK: bb.2.do.end:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
Show All 13 Lines bb.0.entry:
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
$r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg
bb.1.do.body: bb.1.do.body:
successors: %bb.1(0x7c000000), %bb.2(0x04000000) successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $r0, $r1, $r2, $r12 liveins: $r0, $r1, $r2, $r12
$lr = tMOVr $r2, 14 /* CC::al */, $noreg $lr = tMOVr $r2, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg
renamable $r12 = nsw t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nsw t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.pSrc.addr.02, align 4) renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.02, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q0 = MVE_VMULf32 killed renamable $q0, renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMULf32 killed renamable $q0, renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr :: (store (s128) into %ir.pDst.addr.01, align 4) renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.pDst.addr.01, align 4)
t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14 /* CC::al */, $noreg tB %bb.2, 14 /* CC::al */, $noreg
bb.2.do.end: bb.2.do.end:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Linesbody: |
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: $r1 = t2ADDri renamable $r0, 3, 11 /* CC::lt */, $noreg, $noreg, implicit $itstate ; CHECK: $r1 = t2ADDri renamable $r0, 3, 11 /* CC::lt */, $noreg, $noreg, implicit $itstate
; CHECK: $r3 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, $cpsr, $noreg, implicit renamable $r12, implicit $itstate ; CHECK: $r3 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
; CHECK: $r12 = t2LSLri renamable $r3, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate ; CHECK: $r12 = t2LSLri renamable $r3, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead renamable $r12 = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: dead renamable $r12 = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: dead renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load (s128) from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.1.do.body (align 4): ; CHECK: bb.1.do.body (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg, $noreg
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg, $noreg
; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.do.end: ; CHECK: bb.2.do.end:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 16): ; CHECK: bb.3 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
Show All 11 Lines bb.0.entry:
$r1 = t2ADDri renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate $r1 = t2ADDri renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate
$r3 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate $r3 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
$r12 = t2LSLri renamable $r3, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate $r12 = t2LSLri renamable $r3, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
renamable $r2 = tLEApcrel %const.0, 14, $noreg renamable $r2 = tLEApcrel %const.0, 14, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load (s128) from constant-pool) renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.1.do.body (align 4): bb.1.do.body (align 4):
successors: %bb.1(0x7c000000), %bb.2(0x04000000) successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r3 liveins: $lr, $q0, $r0, $r1, $r3
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg
renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q1
MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr, $noreg
renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14, $noreg tB %bb.2, 14, $noreg
bb.2.do.end: bb.2.do.end:
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
bb.3 (align 16): bb.3 (align 16):
CONSTPOOL_ENTRY 0, %const.0, 16 CONSTPOOL_ENTRY 0, %const.0, 16
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Linesbody: |
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load (s128) from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.1.do.body (align 4): ; CHECK: bb.1.do.body (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg, $noreg
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg, $noreg
; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.do.end: ; CHECK: bb.2.do.end:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 16): ; CHECK: bb.3 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
Show All 10 Lines bb.0.entry:
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
$r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
$r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
renamable $r2 = tLEApcrel %const.0, 14, $noreg renamable $r2 = tLEApcrel %const.0, 14, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load (s128) from constant-pool) renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.1.do.body (align 4): bb.1.do.body (align 4):
successors: %bb.1(0x7c000000), %bb.2(0x04000000) successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r3 liveins: $lr, $q0, $r0, $r1, $r3
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg
renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q1
MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr, $noreg
renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14, $noreg tB %bb.2, 14, $noreg
bb.2.do.end: bb.2.do.end:
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
bb.3 (align 16): bb.3 (align 16):
CONSTPOOL_ENTRY 0, %const.0, 16 CONSTPOOL_ENTRY 0, %const.0, 16
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: $r12 = tMOVr renamable $r1, 11 /* CC::lt */, killed $cpsr, implicit killed renamable $r12, implicit killed $itstate ; CHECK: $r12 = tMOVr renamable $r1, 11 /* CC::lt */, killed $cpsr, implicit killed renamable $r12, implicit killed $itstate
; CHECK: renamable $r3 = t2SUBrr renamable $r1, killed renamable $r12, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2SUBrr renamable $r1, killed renamable $r12, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg
; CHECK: $r12 = tMOVr $r1, 14 /* CC::al */, $noreg ; CHECK: $r12 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $r4 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r4 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4
; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r3, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r3, 0, 0, $noreg, $noreg
; CHECK: renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4
; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg
; CHECK: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg
; CHECK: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0 ; CHECK: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0
; CHECK: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg ; CHECK: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg ; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS killed $r4 ; CHECK: $lr = t2DLS killed $r4
; CHECK: renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: bb.5: ; CHECK: bb.5:
; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $s4 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $s4
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
; CHECK: $r4 = VMOVRS $s4, 14 /* CC::al */, $noreg ; CHECK: $r4 = VMOVRS $s4, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $q2 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr ; CHECK: renamable $q2 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg
; CHECK: renamable $q2 = nnan ninf nsz MVE_VSUB_qr_f32 killed renamable $q2, killed renamable $r4, 1, renamable $vpr, undef renamable $q2 ; CHECK: renamable $q2 = nnan ninf nsz MVE_VSUB_qr_f32 killed renamable $q2, killed renamable $r4, 1, renamable $vpr, $noreg, undef renamable $q2
; CHECK: renamable $q0 = nnan ninf nsz MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr ; CHECK: renamable $q0 = nnan ninf nsz MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5
; CHECK: bb.6: ; CHECK: bb.6:
; CHECK: liveins: $q0, $r1, $r2 ; CHECK: liveins: $q0, $r1, $r2
; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg
Show All 38 Lines bb.2:
tCMPi8 renamable $r1, 4, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r1, 4, 14, $noreg, implicit-def $cpsr
renamable $lr = nuw nsw t2ADDrs renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
$r12 = tMOVr renamable $r1, 11, killed $cpsr, implicit killed renamable $r12, implicit killed $itstate $r12 = tMOVr renamable $r1, 11, killed $cpsr, implicit killed renamable $r12, implicit killed $itstate
renamable $r3 = t2SUBrr renamable $r1, killed renamable $r12, 14, $noreg, $noreg renamable $r3 = t2SUBrr renamable $r1, killed renamable $r12, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14, $noreg renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14, $noreg
$r12 = tMOVr $r1, 14, $noreg $r12 = tMOVr $r1, 14, $noreg
renamable $r4 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg renamable $r4 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
$r3 = tMOVr $r0, 14, $noreg $r3 = tMOVr $r0, 14, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.3: bb.3:
successors: %bb.3(0x7c000000), %bb.4(0x04000000) successors: %bb.3(0x7c000000), %bb.4(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r12 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r12
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r3, 0, 1, renamable $vpr renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r3, 0, 1, renamable $vpr, $noreg
renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0 renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0
renamable $r12 = nsw t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = nsw t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14, $noreg renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14, $noreg
t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
tB %bb.4, 14, $noreg tB %bb.4, 14, $noreg
bb.4: bb.4:
successors: %bb.5(0x80000000) successors: %bb.5(0x80000000)
liveins: $q0, $r0, $r1, $r2, $r4 liveins: $q0, $r0, $r1, $r2, $r4
renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg
$lr = tMOVr $r4, 14, $noreg $lr = tMOVr $r4, 14, $noreg
$r3 = tMOVr $r1, 14, $noreg $r3 = tMOVr $r1, 14, $noreg
renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg
renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit $q0 renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit $q0
$s2 = VMOVSR $r1, 14, $noreg $s2 = VMOVSR $r1, 14, $noreg
renamable $s2 = VUITOS killed renamable $s2, 14, $noreg renamable $s2 = VUITOS killed renamable $s2, 14, $noreg
$lr = t2DoLoopStart killed $r4 $lr = t2DoLoopStart killed $r4
renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
bb.5: bb.5:
successors: %bb.5(0x7c000000), %bb.6(0x04000000) successors: %bb.5(0x7c000000), %bb.6(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $s4 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $s4
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
$r4 = VMOVRS $s4, 14, $noreg $r4 = VMOVRS $s4, 14, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $q2 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr renamable $q2 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg
renamable $q2 = nnan ninf nsz MVE_VSUB_qr_f32 killed renamable $q2, killed renamable $r4, 1, renamable $vpr, undef renamable $q2 renamable $q2 = nnan ninf nsz MVE_VSUB_qr_f32 killed renamable $q2, killed renamable $r4, 1, renamable $vpr, $noreg, undef renamable $q2
renamable $q0 = nnan ninf nsz MVE_VFMAf32 killed renamable $q0, killed renamable $q2, renamable $q2, 1, killed renamable $vpr renamable $q0 = nnan ninf nsz MVE_VFMAf32 killed renamable $q0, killed renamable $q2, renamable $q2, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr
tB %bb.6, 14, $noreg tB %bb.6, 14, $noreg
bb.6: bb.6:
liveins: $q0, $r1, $r2 liveins: $q0, $r1, $r2
Show All 15 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Linesbody: |
; CHECK: tCMPi8 renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: $r12 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, $cpsr, $noreg, implicit killed renamable $r12, implicit $itstate ; CHECK: $r12 = t2LSLri renamable $r2, 1, 11 /* CC::lt */, $cpsr, $noreg, implicit killed renamable $r12, implicit $itstate
; CHECK: $r0 = t2ADDri killed renamable $r0, 42, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r0, implicit killed $itstate ; CHECK: $r0 = t2ADDri killed renamable $r0, 42, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $r0, implicit killed $itstate
; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead renamable $r12 = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: dead renamable $r12 = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: dead renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load (s128) from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.1.do.body (align 4): ; CHECK: bb.1.do.body (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg, $noreg
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg, $noreg
; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.do.end: ; CHECK: bb.2.do.end:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 16): ; CHECK: bb.3 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
Show All 10 Lines bb.0.entry:
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
$r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate
$r0 = t2ADDri renamable $r0, 42, 11, killed $cpsr, $noreg, implicit killed renamable $r0, implicit killed $itstate $r0 = t2ADDri renamable $r0, 42, 11, killed $cpsr, $noreg, implicit killed renamable $r0, implicit killed $itstate
renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg
renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg
renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
renamable $r2 = tLEApcrel %const.0, 14, $noreg renamable $r2 = tLEApcrel %const.0, 14, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load (s128) from constant-pool) renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.1.do.body (align 4): bb.1.do.body (align 4):
successors: %bb.1(0x7c000000), %bb.2(0x04000000) successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r3 liveins: $lr, $q0, $r0, $r1, $r3
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg
renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q1
MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 1, killed renamable $vpr, $noreg
renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg
renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14, $noreg tB %bb.2, 14, $noreg
bb.2.do.end: bb.2.do.end:
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
bb.3 (align 16): bb.3 (align 16):
CONSTPOOL_ENTRY 0, %const.0, 16 CONSTPOOL_ENTRY 0, %const.0, 16
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp-reordered.mir

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24
; CHECK: frame-setup CFI_INSTRUCTION offset $d9, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $d9, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $d8, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $d8, -24
; CHECK: tCBZ $r2, %bb.3 ; CHECK: tCBZ $r2, %bb.3
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q3 ; CHECK: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r3 ; CHECK: dead $lr = t2DLS renamable $r3
; CHECK: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
; CHECK: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4 ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, $noreg ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, $noreg, $noreg
; CHECK: MVE_VPST 1, implicit $vpr ; CHECK: MVE_VPST 1, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv35, align 4) ; CHECK: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv12, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9 ; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
; CHECK: bb.4 (align 16): ; CHECK: bb.4 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
Show All 9 Lines bb.0.entry:
frame-setup CFI_INSTRUCTION offset $d8, -24 frame-setup CFI_INSTRUCTION offset $d8, -24
tCBZ $r2, %bb.3 tCBZ $r2, %bb.3
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q3 renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $r3 $lr = t2DoLoopStart renamable $r3
$r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg
renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4 liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, $noreg renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 0, $noreg, $noreg
MVE_VPST 1, implicit $vpr MVE_VPST 1, implicit $vpr
renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv35, align 4) renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)
renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv12, align 4) renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)
renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
$sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9 $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.4 (align 16): bb.4 (align 16):
CONSTPOOL_ENTRY 0, %const.0, 16 CONSTPOOL_ENTRY 0, %const.0, 16
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp.mir

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24
; CHECK: frame-setup CFI_INSTRUCTION offset $d9, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $d9, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $d8, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $d8, -24
; CHECK: tCBZ $r2, %bb.3 ; CHECK: tCBZ $r2, %bb.3
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q3 ; CHECK: renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r3 ; CHECK: dead $lr = t2DLS renamable $r3
; CHECK: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
; CHECK: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4 ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 1, implicit $vpr ; CHECK: MVE_VPST 1, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr, $noreg
; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv35, align 4) ; CHECK: renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv12, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9 ; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
; CHECK: bb.4 (align 16): ; CHECK: bb.4 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
Show All 9 Lines bb.0.entry:
frame-setup CFI_INSTRUCTION offset $d8, -24 frame-setup CFI_INSTRUCTION offset $d8, -24
tCBZ $r2, %bb.3 tCBZ $r2, %bb.3
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q2
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q3 renamable $q3 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q3
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $r3 $lr = t2DoLoopStart renamable $r3
$r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg $r4 = tMOVr killed $r3, 14 /* CC::al */, $noreg
renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4 liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r4
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
MVE_VPST 1, implicit $vpr MVE_VPST 1, implicit $vpr
renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q2, 2, 1, killed renamable $vpr, $noreg
renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv35, align 4) renamable $r1, renamable $q4 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)
renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv12, align 4) renamable $r0 = MVE_VSTRWU32_post killed renamable $q4, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)
renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q3, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
$sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9 $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.4 (align 16): bb.4 (align 16):
CONSTPOOL_ENTRY 0, %const.0, 16 CONSTPOOL_ENTRY 0, %const.0, 16
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-vcmp.mir

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Linesbody: |
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: frame-destroy tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: frame-destroy tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
; CHECK: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1 ; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1
; CHECK: MVE_VPTv4u32 4, renamable $q1, renamable $q0, 8, implicit-def $vpr ; CHECK: MVE_VPTv4u32 4, renamable $q1, renamable $q0, 8, implicit-def $vpr
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv35, align 4) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q3, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv12, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q3, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.4 (align 16): ; CHECK: bb.4 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
$r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 0, 8, implicit-def $itstate t2IT 0, 8, implicit-def $itstate
frame-destroy tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate frame-destroy tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tLSRri renamable $r2, 1, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q0, 8, 1, killed renamable $vpr, $noreg
renamable $r1, renamable $q3 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv35, align 4) renamable $r1, renamable $q3 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv35, align 4)
renamable $r0 = MVE_VSTRWU32_post killed renamable $q3, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv12, align 4) renamable $r0 = MVE_VSTRWU32_post killed renamable $q3, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv12, align 4)
renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.4 (align 16): bb.4 (align 16):
CONSTPOOL_ENTRY 0, %const.0, 16 CONSTPOOL_ENTRY 0, %const.0, 16
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK: renamable $r12 = t2ADDri $sp, 8, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri $sp, 8, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
; CHECK: tCBZ $r3, %bb.3 ; CHECK: tCBZ $r3, %bb.3
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2 ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r2 = MVE_VSTRWU32_post renamable $q1, killed renamable $r2, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.store, align 4) ; CHECK: renamable $r2 = MVE_VSTRWU32_post renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.store, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0 ; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit killed $q0
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r4, -8 frame-setup CFI_INSTRUCTION offset $r4, -8
renamable $r12 = t2ADDri $sp, 8, 14, $noreg, $noreg renamable $r12 = t2ADDri $sp, 8, 14, $noreg, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
tCBZ $r3, %bb.3 tCBZ $r3, %bb.3
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $q0, $r0, $r1, $r2, $r3 liveins: $q0, $r0, $r1, $r2, $r3
renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg
renamable $lr = t2MOVi 1, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg
renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $r4 = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg renamable $r4 = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $r4 $lr = t2DoLoopStart renamable $r4
$r12 = tMOVr killed $r4, 14, $noreg $r12 = tMOVr killed $r4, 14, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r12 liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r12
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
$lr = tMOVr $r12, 14, $noreg $lr = tMOVr $r12, 14, $noreg
renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
renamable $r12 = nsw t2SUBri killed $r12, 1, 14, $noreg, $noreg renamable $r12 = nsw t2SUBri killed $r12, 1, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r2 = MVE_VSTRWU32_post renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.store, align 4) renamable $r2 = MVE_VSTRWU32_post renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.store, align 4)
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.exit: bb.3.exit:
liveins: $q0 liveins: $q0
renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14, $noreg renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14, $noreg
renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14, $noreg, implicit $q0 renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14, $noreg, implicit $q0
tPOP_RET 14, $noreg, def $r4, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 tPOP_RET 14, $noreg, def $r4, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Linesbody: |
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) ; CHECK: renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 ; CHECK: $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q1, $r0, $r1, $r2 ; CHECK: liveins: $lr, $q1, $r0, $r1, $r2
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv12, align 4) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv12, align 4)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1315, align 4) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4)
; CHECK: renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr ; CHECK: renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q1 ; CHECK: liveins: $q1
; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg
; CHECK: renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit killed $q1 ; CHECK: renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit killed $q1
; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg
; CHECK: $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr ; CHECK: $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0
Show All 19 Lines bb.1.vector.ph:
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
$s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q1, $r0, $r1, $r2 liveins: $lr, $q1, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv12, align 4) renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv12, align 4)
renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1315, align 4) renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4)
renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q1 liveins: $q1
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg
renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1 renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $r3, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) ; CHECK: renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r2, dead $cpsr = tLSRri killed renamable $r2, 2, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tLSRri killed renamable $r2, 2, 14 /* CC::al */, $noreg
; CHECK: $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 ; CHECK: $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q1, $r0, $r1, $r2 ; CHECK: liveins: $lr, $q1, $r0, $r1, $r2
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
; CHECK: renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr ; CHECK: renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q1 ; CHECK: liveins: $q1
; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg
; CHECK: renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit killed $q1 ; CHECK: renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit killed $q1
; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg
; CHECK: $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr ; CHECK: $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0
Show All 21 Lines bb.1.vector.ph:
renamable $r3, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool)
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
renamable $r2, dead $cpsr = tLSRri killed renamable $r2, 2, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tLSRri killed renamable $r2, 2, 14 /* CC::al */, $noreg
$s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q1, $r0, $r1, $r2 liveins: $lr, $q1, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q1 liveins: $q1
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg
renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1 renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg
$sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0
bb.4 (align 4): bb.4 (align 4):
CONSTPOOL_ENTRY 0, %const.0, 4 CONSTPOOL_ENTRY 0, %const.0, 4
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir

Show First 20 Lines • Show All 266 Lines • ▼ Show 20 Linesbody: |
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r4, $r5, $r7, $r8, $r10, $r12 ; CHECK: liveins: $r4, $r5, $r7, $r8, $r10, $r12
; CHECK: renamable $r0 = t2ADDri $r10, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r0 = t2ADDri $r10, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = tMOVr $r10, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r10, 14 /* CC::al */, $noreg
; CHECK: renamable $r0 = t2BICri killed renamable $r0, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r0 = t2BICri killed renamable $r0, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2LSLri $r10, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2LSLri $r10, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.5.for.cond4.preheader.us: ; CHECK: bb.5.for.cond4.preheader.us:
; CHECK: successors: %bb.6(0x80000000) ; CHECK: successors: %bb.6(0x80000000)
; CHECK: liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 ; CHECK: liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
; CHECK: renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.arrayidx12.us) ; CHECK: renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.arrayidx12.us)
; CHECK: $q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1 ; CHECK: $q1 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q1
; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14 /* CC::al */, $noreg ; CHECK: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14 /* CC::al */, $noreg
; CHECK: $r6 = tMOVr $r5, 14 /* CC::al */, $noreg ; CHECK: $r6 = tMOVr $r5, 14 /* CC::al */, $noreg
; CHECK: $r1 = tMOVr $r8, 14 /* CC::al */, $noreg ; CHECK: $r1 = tMOVr $r8, 14 /* CC::al */, $noreg
; CHECK: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS renamable $r0 ; CHECK: $lr = t2DLS renamable $r0
; CHECK: bb.6.vector.body: ; CHECK: bb.6.vector.body:
; CHECK: successors: %bb.6(0x7c000000), %bb.7(0x04000000) ; CHECK: successors: %bb.6(0x7c000000), %bb.7(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12 ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
; CHECK: $q2 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q2 ; CHECK: $q2 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q2
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1012, align 2) ; CHECK: renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1012, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv46, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv46, align 2)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.6 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.6
; CHECK: bb.7.middle.block: ; CHECK: bb.7.middle.block:
; CHECK: successors: %bb.8(0x04000000), %bb.5(0x7c000000) ; CHECK: successors: %bb.8(0x04000000), %bb.5(0x7c000000)
; CHECK: liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 ; CHECK: liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg, $noreg
; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr ; CHECK: renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr, $noreg
; CHECK: $lr = tMOVr $r10, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r10, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg ; CHECK: renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg
; CHECK: t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.27) ; CHECK: t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.27)
; CHECK: renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14 /* CC::al */, $noreg
; CHECK: tCMPhir renamable $r7, $r10, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPhir renamable $r7, $r10, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.5, 1 /* CC::ne */, killed $cpsr ; CHECK: tBcc %bb.5, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.8.for.end16: ; CHECK: bb.8.for.end16:
; CHECK: successors: %bb.9(0x50000000), %bb.13(0x30000000) ; CHECK: successors: %bb.9(0x50000000), %bb.13(0x30000000)
; CHECK: liveins: $lr, $r4, $r12 ; CHECK: liveins: $lr, $r4, $r12
; CHECK: t2CMPri renamable $lr, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: t2CMPri renamable $lr, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines bb.4.for.cond4.preheader.us.preheader:
liveins: $r4, $r5, $r7, $r8, $r10, $r12 liveins: $r4, $r5, $r7, $r8, $r10, $r12
renamable $r0 = t2ADDri $r10, 3, 14, $noreg, $noreg renamable $r0 = t2ADDri $r10, 3, 14, $noreg, $noreg
$lr = tMOVr $r10, 14, $noreg $lr = tMOVr $r10, 14, $noreg
renamable $r0 = t2BICri killed renamable $r0, 3, 14, $noreg, $noreg renamable $r0 = t2BICri killed renamable $r0, 3, 14, $noreg, $noreg
renamable $r3 = t2LSLri $r10, 1, 14, $noreg, $noreg renamable $r3 = t2LSLri $r10, 1, 14, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14, $noreg renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14, $noreg
renamable $r0, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r0, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, $noreg, undef renamable $q0
renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14, $noreg, $noreg renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14, $noreg, $noreg
renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14, $noreg renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14, $noreg
renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14, $noreg, $noreg renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14, $noreg, $noreg
bb.5.for.cond4.preheader.us: bb.5.for.cond4.preheader.us:
successors: %bb.6(0x80000000) successors: %bb.6(0x80000000)
liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14, $noreg :: (load (s32) from %ir.arrayidx12.us) renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14, $noreg :: (load (s32) from %ir.arrayidx12.us)
$q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1 $q1 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q1
$r2 = tMOVr killed $lr, 14, $noreg $r2 = tMOVr killed $lr, 14, $noreg
renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14, $noreg renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14, $noreg
$r6 = tMOVr $r5, 14, $noreg $r6 = tMOVr $r5, 14, $noreg
$r1 = tMOVr $r8, 14, $noreg $r1 = tMOVr $r8, 14, $noreg
$lr = tMOVr $r0, 14, $noreg $lr = tMOVr $r0, 14, $noreg
$lr = t2DoLoopStart renamable $r0 $lr = t2DoLoopStart renamable $r0
bb.6.vector.body: bb.6.vector.body:
successors: %bb.6(0x7c000000), %bb.7(0x04000000) successors: %bb.6(0x7c000000), %bb.7(0x04000000)
liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12 liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
$q2 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q2 $q2 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q2
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1012, align 2) renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1012, align 2)
renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv46, align 2) renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv46, align 2)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, $noreg, undef renamable $q1
t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
tB %bb.7, 14, $noreg tB %bb.7, 14, $noreg
bb.7.middle.block: bb.7.middle.block:
successors: %bb.8(0x04000000), %bb.5(0x7c000000) successors: %bb.8(0x04000000), %bb.5(0x7c000000)
liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg, $noreg
renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14, $noreg renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14, $noreg
renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr, $noreg
$lr = tMOVr $r10, 14, $noreg $lr = tMOVr $r10, 14, $noreg
renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg
t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14, $noreg :: (store (s32) into %ir.27) t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14, $noreg :: (store (s32) into %ir.27)
renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14, $noreg renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14, $noreg
tCMPhir renamable $r7, $r10, 14, $noreg, implicit-def $cpsr tCMPhir renamable $r7, $r10, 14, $noreg, implicit-def $cpsr
tBcc %bb.5, 1, killed $cpsr tBcc %bb.5, 1, killed $cpsr
bb.8.for.end16: bb.8.for.end16:
successors: %bb.9(0x50000000), %bb.13(0x30000000) successors: %bb.9(0x50000000), %bb.13(0x30000000)
liveins: $lr, $r4, $r12 liveins: $lr, $r4, $r12
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Linesbody: |
; CHECK-LABEL: name: arm_var_f32_mve ; CHECK-LABEL: name: arm_var_f32_mve
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: $r4 = tMOVr $lr, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr $lr, 14 /* CC::al */, $noreg
; CHECK: bb.1.do.body.i: ; CHECK: bb.1.do.body.i:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r4, $r12 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r4, $r12
; CHECK: renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg :: (load (s128) from %ir.pSrc.addr.0.i2, align 4) ; CHECK: renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.pSrc.addr.0.i2, align 4)
; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.arm_mean_f32_mve.exit: ; CHECK: bb.2.arm_mean_f32_mve.exit:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4
; CHECK: $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg ; CHECK: $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg
; CHECK: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: dead $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0 ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0
; CHECK: $lr = t2DLS killed $r4 ; CHECK: $lr = t2DLS killed $r4
; CHECK: renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg ; CHECK: renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg
; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: bb.3.do.body: ; CHECK: bb.3.do.body:
; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.pSrc.addr.01, align 4) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.01, align 4)
; CHECK: renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2 ; CHECK: renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2
; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, killed renamable $q2, 1, killed renamable $vpr, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3
; CHECK: bb.4.do.end: ; CHECK: bb.4.do.end:
; CHECK: liveins: $q0, $r1, $r2 ; CHECK: liveins: $q0, $r1, $r2
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0 ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0
; CHECK: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg ; CHECK: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg
; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg ; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult) ; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult)
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r4, $lr liveins: $r0, $r1, $r2, $r4, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r4, -8 frame-setup CFI_INSTRUCTION offset $r4, -8
$r3 = tMOVr $r1, 14 /* CC::al */, $noreg $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 10, 8, implicit-def $itstate t2IT 10, 8, implicit-def $itstate
renamable $r3 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate renamable $r3 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate
renamable $r12 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBrr renamable $r1, killed renamable $r3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tSUBrr renamable $r1, killed renamable $r3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r12, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r12, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
$r3 = tMOVr $r1, 14 /* CC::al */, $noreg $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
$r12 = tMOVr $r0, 14 /* CC::al */, $noreg $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
$r4 = tMOVr $lr, 14 /* CC::al */, $noreg $r4 = tMOVr $lr, 14 /* CC::al */, $noreg
bb.1.do.body.i: bb.1.do.body.i:
successors: %bb.1(0x7c000000), %bb.2(0x04000000) successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r12 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r12
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 1, renamable $vpr :: (load (s128) from %ir.pSrc.addr.0.i2, align 4) renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.0.i2, align 4)
renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0 renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14 /* CC::al */, $noreg tB %bb.2, 14 /* CC::al */, $noreg
bb.2.arm_mean_f32_mve.exit: bb.2.arm_mean_f32_mve.exit:
successors: %bb.3(0x80000000) successors: %bb.3(0x80000000)
liveins: $q0, $r0, $r1, $r2, $r4 liveins: $q0, $r0, $r1, $r2, $r4
$s4 = VMOVSR $r1, 14 /* CC::al */, $noreg $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0
$lr = t2DoLoopStart killed $r4 $lr = t2DoLoopStart killed $r4
renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg
renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1
$r3 = tMOVr $r1, 14 /* CC::al */, $noreg $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
bb.3.do.body: bb.3.do.body:
successors: %bb.3(0x7c000000), %bb.4(0x04000000) successors: %bb.3(0x7c000000), %bb.4(0x04000000)
liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3 liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.pSrc.addr.01, align 4) renamable $r0, renamable $q2 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.pSrc.addr.01, align 4)
renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2 renamable $q2 = nnan ninf nsz arcp contract afn reassoc MVE_VSUBf32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2
renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, renamable $q2, 1, killed renamable $vpr renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VFMAf32 killed renamable $q0, killed renamable $q2, renamable $q2, 1, killed renamable $vpr, $noreg
t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
tB %bb.4, 14 /* CC::al */, $noreg tB %bb.4, 14 /* CC::al */, $noreg
bb.4.do.end: bb.4.do.end:
liveins: $q0, $r1, $r2 liveins: $q0, $r1, $r2
renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0
$s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg
renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult) VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult)
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir

Show First 20 Lines • Show All 113 Lines • ▼ Show 20 Linesbody: |
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r12 = t2LSRri killed renamable $r3, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r3, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load (s32) from %ir.scevgep45, align 1) ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s32) from %ir.scevgep45, align 1)
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load (s32) from %ir.scevgep23, align 1) ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s32) from %ir.scevgep23, align 1)
; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.iv1, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
Show All 20 Lines bb.1.vector.ph:
$lr = t2DoLoopStart renamable $r5 $lr = t2DoLoopStart renamable $r5
$lr = tMOVr killed $r5, 14, $noreg $lr = tMOVr killed $r5, 14, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r12 liveins: $lr, $r0, $r1, $r2, $r3, $r12
renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load (s32) from %ir.scevgep45, align 1) renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep45, align 1)
renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load (s32) from %ir.scevgep23, align 1) renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep23, align 1)
renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1, align 4) renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r4, def $pc tPOP_RET 14, $noreg, def $r4, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load (s32) from %ir.scevgep45, align 1) ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep45, align 1)
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load (s32) from %ir.scevgep23, align 1) ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep23, align 1)
; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
Show All 20 Lines bb.1.vector.ph:
renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
renamable $r12 = t2LSRri killed renamable $r12, 1, 14, $noreg, $noreg renamable $r12 = t2LSRri killed renamable $r12, 1, 14, $noreg, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r12 liveins: $lr, $r0, $r1, $r2, $r3, $r12
renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load (s32) from %ir.scevgep45, align 1) renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep45, align 1)
renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load (s32) from %ir.scevgep23, align 1) renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep23, align 1)
renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1, align 4) renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r4, def $pc tPOP_RET 14, $noreg, def $r4, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load (s32) from %ir.scevgep45, align 1) ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep45, align 1)
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load (s32) from %ir.scevgep23, align 1) ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep23, align 1)
; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
Show All 20 Lines bb.1.vector.ph:
renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
renamable $r12 = t2LSRri killed renamable $r12, 1, 14, $noreg, $noreg renamable $r12 = t2LSRri killed renamable $r12, 1, 14, $noreg, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r12 liveins: $lr, $r0, $r1, $r2, $r3, $r12
renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load (s32) from %ir.scevgep45, align 1) renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep45, align 1)
renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load (s32) from %ir.scevgep23, align 1) renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s32) from %ir.scevgep23, align 1)
renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1, align 4) renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r4, def $pc tPOP_RET 14, $noreg, def $r4, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.2 (%ir-block.32): ; CHECK: bb.2 (%ir-block.32):
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: liveins: $r0, $r1, $r3 ; CHECK: liveins: $r0, $r1, $r3
; CHECK: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.3 (%ir-block.33): ; CHECK: bb.3 (%ir-block.33):
; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg
; CHECK: $r0 = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3
; CHECK: bb.4 (%ir-block.64): ; CHECK: bb.4 (%ir-block.64):
; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10 ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
; CHECK: bb.5 (%ir-block.23): ; CHECK: bb.5 (%ir-block.23):
; CHECK: successors: %bb.6(0x40000000), %bb.7(0x40000000) ; CHECK: successors: %bb.6(0x40000000), %bb.7(0x40000000)
; CHECK: liveins: $r0, $r1, $r3 ; CHECK: liveins: $r0, $r1, $r3
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines bb.2 (%ir-block.32):
renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg
$r2 = tMOVr $r0, 14, $noreg $r2 = tMOVr $r0, 14, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.3 (%ir-block.33): bb.3 (%ir-block.33):
successors: %bb.3(0x7c000000), %bb.4(0x04000000) successors: %bb.3(0x7c000000), %bb.4(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg
renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r2, 14, $noreg $r0 = tMOVr $r2, 14, $noreg
t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
tB %bb.4, 14, $noreg tB %bb.4, 14, $noreg
bb.4 (%ir-block.64): bb.4 (%ir-block.64):
$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10 $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10
tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.1 (%ir-block.17): ; CHECK: bb.1 (%ir-block.17):
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2 (%ir-block.18): ; CHECK: bb.2 (%ir-block.18):
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r3
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg, $noreg
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg
; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3 (%ir-block.34): ; CHECK: bb.3 (%ir-block.34):
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0 (%ir-block.4): bb.0 (%ir-block.4):
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $lr liveins: $r0, $r1, $r2, $r3, $lr
Show All 25 Lines bb.1 (%ir-block.17):
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
$r3 = tMOVr $r0, 14, $noreg $r3 = tMOVr $r0, 14, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2 (%ir-block.18): bb.2 (%ir-block.18):
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg
renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r3, 14, $noreg $r0 = tMOVr $r3, 14, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3 (%ir-block.34): bb.3 (%ir-block.34):
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir

Show First 20 Lines • Show All 366 Lines • ▼ Show 20 Linesbody: |
; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg ; CHECK: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8
; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4) ; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4)
; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4) ; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4)
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.iv6870, align 4) ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv6870, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond4.preheader: ; CHECK: bb.3.for.cond4.preheader:
; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: tCBZ $r3, %bb.6 ; CHECK: tCBZ $r3, %bb.6
; CHECK: bb.4.vector.ph39: ; CHECK: bb.4.vector.ph39:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.5.vector.body38: ; CHECK: bb.5.vector.body38:
; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r12 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r12
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv55, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv55, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4)
; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4) ; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_post killed renamable $r12, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4)
; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store (s128) into %ir.lsr.iv5961, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5961, align 4)
; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
; CHECK: bb.6.for.cond.cleanup6: ; CHECK: bb.6.for.cond.cleanup6:
; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.6(0x30000000), %bb.1(0x50000000) successors: %bb.6(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8
Show All 26 Lines bb.1.vector.ph:
renamable $lr = nuw nsw t2ADDrs killed renamable $r6, renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r6, renamable $r12, 19, 14, $noreg, $noreg
$r6 = tMOVr $r1, 14, $noreg $r6 = tMOVr $r1, 14, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r12 liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r12
renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv6264, align 4) renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4)
renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv6567, align 4) renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4)
renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14, $noreg renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14, $noreg
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv6870, align 4) renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv6870, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond4.preheader: bb.3.for.cond4.preheader:
successors: %bb.6(0x30000000), %bb.4(0x50000000) successors: %bb.6(0x30000000), %bb.4(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
tCBZ $r3, %bb.6 tCBZ $r3, %bb.6
bb.4.vector.ph39: bb.4.vector.ph39:
successors: %bb.5(0x80000000) successors: %bb.5(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
renamable $r6, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r6, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r6, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r6, killed renamable $r12, 19, 14, $noreg, $noreg
$r12 = tMOVr $r0, 14, $noreg $r12 = tMOVr $r0, 14, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.5.vector.body38: bb.5.vector.body38:
successors: %bb.5(0x7c000000), %bb.6(0x04000000) successors: %bb.5(0x7c000000), %bb.6(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r12 liveins: $lr, $r0, $r1, $r2, $r3, $r12
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv55, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv55, align 4)
renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv5658, align 4) renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4)
renamable $r12, renamable $q2 = MVE_VLDRWU32_post killed renamable $r12, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv5961, align 4) renamable $r12, renamable $q2 = MVE_VLDRWU32_post killed renamable $r12, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4)
renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv5961, align 4) MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv5961, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r12, 14, $noreg $r0 = tMOVr $r12, 14, $noreg
t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr
tB %bb.6, 14, $noreg tB %bb.6, 14, $noreg
bb.6.for.cond.cleanup6: bb.6.for.cond.cleanup6:
$r8, $sp = t2LDR_POST $sp, 4, 14, $noreg $r8, $sp = t2LDR_POST $sp, 4, 14, $noreg
tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r4, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg
; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $r5 = tMOVr $r1, 14 /* CC::al */, $noreg ; CHECK: $r5 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8
; CHECK: renamable $r5, renamable $q0 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4) ; CHECK: renamable $r5, renamable $q0 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4)
; CHECK: renamable $r6, renamable $q1 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4) ; CHECK: renamable $r6, renamable $q1 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4)
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.iv6870, align 4) ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv6870, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond4.preheader: ; CHECK: bb.3.for.cond4.preheader:
; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: tCBZ $r3, %bb.6 ; CHECK: tCBZ $r3, %bb.6
; CHECK: bb.4.vector.ph39: ; CHECK: bb.4.vector.ph39:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $r4 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.5.vector.body38: ; CHECK: bb.5.vector.body38:
; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv55, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv55, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4)
; CHECK: renamable $r4, renamable $q2 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4) ; CHECK: renamable $r4, renamable $q2 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4)
; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store (s128) into %ir.lsr.iv5961, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5961, align 4)
; CHECK: $r0 = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
; CHECK: bb.6.for.cond.cleanup6: ; CHECK: bb.6.for.cond.cleanup6:
; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8
Show All 28 Lines bb.1.vector.ph:
renamable $lr = nuw nsw t2ADDrs renamable $r12, killed renamable $r6, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs renamable $r12, killed renamable $r6, 19, 14, $noreg, $noreg
$r6 = tMOVr $r2, 14, $noreg $r6 = tMOVr $r2, 14, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r12 liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r12
renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r5, renamable $q0 = MVE_VLDRWU32_post killed renamable $r5, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv6264, align 4) renamable $r5, renamable $q0 = MVE_VLDRWU32_post killed renamable $r5, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv6264, align 4)
renamable $r6, renamable $q1 = MVE_VLDRWU32_post killed renamable $r6, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv6567, align 4) renamable $r6, renamable $q1 = MVE_VLDRWU32_post killed renamable $r6, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv6567, align 4)
renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14, $noreg renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14, $noreg
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv6870, align 4) renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv6870, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond4.preheader: bb.3.for.cond4.preheader:
successors: %bb.6(0x30000000), %bb.4(0x50000000) successors: %bb.6(0x30000000), %bb.4(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
Show All 9 Lines bb.4.vector.ph39:
renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 4, 14, $noreg renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 4, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r12, killed renamable $r6, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r12, killed renamable $r6, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.5.vector.body38: bb.5.vector.body38:
successors: %bb.5(0x7c000000), %bb.6(0x04000000) successors: %bb.5(0x7c000000), %bb.6(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r4 liveins: $lr, $r0, $r1, $r2, $r3, $r4
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv55, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv55, align 4)
renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv5658, align 4) renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv5658, align 4)
renamable $r4, renamable $q2 = MVE_VLDRWU32_post killed renamable $r4, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv5961, align 4) renamable $r4, renamable $q2 = MVE_VLDRWU32_post killed renamable $r4, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv5961, align 4)
renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv5961, align 4) MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv5961, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r4, 14, $noreg $r0 = tMOVr $r4, 14, $noreg
t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr
tB %bb.6, 14, $noreg tB %bb.6, 14, $noreg
bb.6.for.cond.cleanup6: bb.6.for.cond.cleanup6:
$r8, $sp = t2LDR_POST $sp, 4, 14, $noreg $r8, $sp = t2LDR_POST $sp, 4, 14, $noreg
tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Linesbody: |
; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: $r5 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg ; CHECK: $r6 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r6, $r8
; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv117119, align 4) ; CHECK: renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv117119, align 4)
; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv120122, align 4) ; CHECK: renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv120122, align 4)
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.iv123125, align 4) ; CHECK: renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv123125, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond4.preheader: ; CHECK: bb.3.for.cond4.preheader:
; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr ; CHECK: tBcc %bb.6, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.4.vector.ph66: ; CHECK: bb.4.vector.ph66:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r5, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r5, dead $cpsr = tLSRri renamable $r3, 1, 14 /* CC::al */, $noreg
; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $r9 = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: $r9 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: $r6 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r6 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r5 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r5
; CHECK: bb.5.vector.body65: ; CHECK: bb.5.vector.body65:
; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r9, $r10 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r6, $r9, $r10
; CHECK: renamable $r4, renamable $q0 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv108110, align 4) ; CHECK: renamable $r4, renamable $q0 = MVE_VLDRWU32_post killed renamable $r4, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv108110, align 4)
; CHECK: renamable $r9, renamable $q1 = MVE_VLDRWU32_post killed renamable $r9, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv111113, align 4) ; CHECK: renamable $r9, renamable $q1 = MVE_VLDRWU32_post killed renamable $r9, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv111113, align 4)
; CHECK: renamable $r6, renamable $q2 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv114116, align 4) ; CHECK: renamable $r6, renamable $q2 = MVE_VLDRWU32_post killed renamable $r6, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv114116, align 4)
; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 0, killed $noreg :: (store (s128) into %ir.lsr.iv114116, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv114116, align 4)
; CHECK: $r10 = tMOVr $r6, 14 /* CC::al */, $noreg ; CHECK: $r10 = tMOVr $r6, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
; CHECK: bb.6.for.cond15.preheader: ; CHECK: bb.6.for.cond15.preheader:
; CHECK: successors: %bb.9(0x30000000), %bb.7(0x50000000) ; CHECK: successors: %bb.9(0x30000000), %bb.7(0x50000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: tCBZ $r3, %bb.9 ; CHECK: tCBZ $r3, %bb.9
; CHECK: bb.7.vector.ph85: ; CHECK: bb.7.vector.ph85:
; CHECK: successors: %bb.8(0x80000000) ; CHECK: successors: %bb.8(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $r5 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r5 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.8.vector.body84: ; CHECK: bb.8.vector.body84:
; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000) ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r5 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r5
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv101, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv101, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv102104, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv102104, align 4)
; CHECK: renamable $r5, renamable $q2 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv105107, align 4) ; CHECK: renamable $r5, renamable $q2 = MVE_VLDRWU32_post killed renamable $r5, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv105107, align 4)
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store (s128) into %ir.lsr.iv105107, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv105107, align 4)
; CHECK: $r0 = tMOVr $r5, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r5, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.8 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.8
; CHECK: bb.9.for.cond.cleanup17: ; CHECK: bb.9.for.cond.cleanup17:
; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10 ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.9(0x30000000), %bb.1(0x50000000) successors: %bb.9(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10
Show All 28 Lines bb.1.vector.ph:
renamable $lr = nuw nsw t2ADDrs killed renamable $r6, renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r6, renamable $r12, 19, 14, $noreg, $noreg
$r6 = tMOVr $r1, 14, $noreg $r6 = tMOVr $r1, 14, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r12 liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r12
renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv117119, align 4) renamable $r6, renamable $q0 = MVE_VLDRWU32_post killed renamable $r6, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv117119, align 4)
renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv120122, align 4) renamable $r5, renamable $q1 = MVE_VLDRWU32_post killed renamable $r5, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv120122, align 4)
renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14, $noreg renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14, $noreg
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv123125, align 4) renamable $r8 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r8, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv123125, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond4.preheader: bb.3.for.cond4.preheader:
successors: %bb.6(0x30000000), %bb.4(0x50000000) successors: %bb.6(0x30000000), %bb.4(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
Show All 17 Lines bb.4.vector.ph66:
renamable $lr = nuw nsw t2ADDrs renamable $r8, killed renamable $r6, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs renamable $r8, killed renamable $r6, 19, 14, $noreg, $noreg
$r6 = tMOVr $r0, 14, $noreg $r6 = tMOVr $r0, 14, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.5.vector.body65: bb.5.vector.body65:
successors: %bb.5(0x7c000000), %bb.6(0x04000000) successors: %bb.5(0x7c000000), %bb.6(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r12 liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r12
renamable $vpr = MVE_VCTP32 renamable $r5, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r5, 0, $noreg, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $r4, renamable $q0 = MVE_VLDRWU32_post killed renamable $r4, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv108110, align 4) renamable $r4, renamable $q0 = MVE_VLDRWU32_post killed renamable $r4, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv108110, align 4)
renamable $r9, renamable $q1 = MVE_VLDRWU32_post killed renamable $r9, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv111113, align 4) renamable $r9, renamable $q1 = MVE_VLDRWU32_post killed renamable $r9, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv111113, align 4)
renamable $r6, renamable $q2 = MVE_VLDRWU32_post killed renamable $r6, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv114116, align 4) renamable $r6, renamable $q2 = MVE_VLDRWU32_post killed renamable $r6, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv114116, align 4)
renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $r5, dead $cpsr = tSUBi8 killed renamable $r5, 4, 14, $noreg renamable $r5, dead $cpsr = tSUBi8 killed renamable $r5, 4, 14, $noreg
renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv114116, align 4) MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv114116, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r10 = tMOVr $r6, 14, $noreg $r10 = tMOVr $r6, 14, $noreg
t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr
tB %bb.6, 14, $noreg tB %bb.6, 14, $noreg
bb.6.for.cond15.preheader: bb.6.for.cond15.preheader:
successors: %bb.9(0x30000000), %bb.7(0x50000000) successors: %bb.9(0x30000000), %bb.7(0x50000000)
liveins: $r0, $r1, $r2, $r3, $r8, $r12 liveins: $r0, $r1, $r2, $r3, $r8, $r12
tCBZ $r3, %bb.9 tCBZ $r3, %bb.9
bb.7.vector.ph85: bb.7.vector.ph85:
successors: %bb.8(0x80000000) successors: %bb.8(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r8, $r12 liveins: $r0, $r1, $r2, $r3, $r8, $r12
renamable $lr = nuw nsw t2ADDrs killed renamable $r8, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r8, killed renamable $r12, 19, 14, $noreg, $noreg
$r5 = tMOVr $r0, 14, $noreg $r5 = tMOVr $r0, 14, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.8.vector.body84: bb.8.vector.body84:
successors: %bb.8(0x7c000000), %bb.9(0x04000000) successors: %bb.8(0x7c000000), %bb.9(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r5 liveins: $lr, $r0, $r1, $r2, $r3, $r5
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv101, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv101, align 4)
renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv102104, align 4) renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv102104, align 4)
renamable $r5, renamable $q2 = MVE_VLDRWU32_post killed renamable $r5, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv105107, align 4) renamable $r5, renamable $q2 = MVE_VLDRWU32_post killed renamable $r5, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv105107, align 4)
renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv105107, align 4) MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv105107, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r5, 14, $noreg $r0 = tMOVr $r5, 14, $noreg
t2LoopEnd renamable $lr, %bb.8, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.8, implicit-def dead $cpsr
tB %bb.9, 14, $noreg tB %bb.9, 14, $noreg
bb.9.for.cond.cleanup17: bb.9.for.cond.cleanup17:
$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10 $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10
tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Linesbody: |
; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r3 = tMOVr killed $r12, 14, $noreg $r3 = tMOVr killed $r12, 14, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2, $r3 liveins: $q0, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
$lr = tMOVr $r3, 14, $noreg $lr = tMOVr $r3, 14, $noreg
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0 liveins: $q0
renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir

Show First 20 Lines • Show All 118 Lines • ▼ Show 20 Linesbody: |
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $r3 = t2ADDri renamable $r2, 15, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2ADDri renamable $r2, 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2LSRri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2LSRri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q1
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv2022, align 1) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv2022, align 1)
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, $noreg :: (load (s128) from %ir.lsr.iv19, align 1) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, $noreg, $noreg :: (load (s128) from %ir.lsr.iv19, align 1)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = MVE_VADDi8 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADDi8 killed renamable $q2, renamable $q1, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0, $q1, $r3 ; CHECK: liveins: $q0, $q1, $r3
; CHECK: renamable $vpr = MVE_VCTP8 killed renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP8 killed renamable $r3, 0, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
; CHECK: renamable $r0 = MVE_VADDVu8no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu8no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: renamable $r0 = tUXTB killed renamable $r0, 14 /* CC::al */, $noreg ; CHECK: renamable $r0 = tUXTB killed renamable $r0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 2, implicit-def $itstate t2IT 0, 2, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
renamable $r0 = tUXTB killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tUXTB killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate
tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
$r7 = frame-setup tMOVr $sp, 14, $noreg $r7 = frame-setup tMOVr $sp, 14, $noreg
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
renamable $r3 = t2ADDri renamable $r2, 15, 14, $noreg, $noreg renamable $r3 = t2ADDri renamable $r2, 15, 14, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2BICri killed renamable $r3, 15, 14, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 15, 14, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14, $noreg, $noreg
renamable $r3 = t2LSRri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r3 = t2LSRri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14, $noreg, $noreg renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3 liveins: $lr, $q0, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
$q1 = MVE_VORR killed $q0, $q0, 0, $noreg, undef $q1 $q1 = MVE_VORR killed $q0, $q0, 0, $noreg, $noreg, undef $q1
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv2022, align 1) renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv2022, align 1)
renamable $r0, renamable $q2 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, $noreg :: (load (s128) from %ir.lsr.iv19, align 1) renamable $r0, renamable $q2 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, $noreg, $noreg :: (load (s128) from %ir.lsr.iv19, align 1)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14, $noreg
renamable $q2 = MVE_VADDi8 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VADDi8 killed renamable $q2, renamable $q1, 0, $noreg, $noreg, undef renamable $q2
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q0 = MVE_VADDi8 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi8 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0, $q1, $r3 liveins: $q0, $q1, $r3
renamable $vpr = MVE_VCTP8 killed renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP8 killed renamable $r3, 0, $noreg, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
renamable $r0 = MVE_VADDVu8no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu8no_acc killed renamable $q0, 0, $noreg, $noreg
$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr
renamable $r0 = tUXTB killed renamable $r0, 14, $noreg renamable $r0 = tUXTB killed renamable $r0, 14, $noreg
tBX_RET 14, $noreg, implicit killed $r0 tBX_RET 14, $noreg, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r12 = t2ADDri renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 15, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv15, align 1) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv15, align 1)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv1618, align 1) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1618, align 1)
; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg :: (store (s128) into %ir.lsr.iv1921, align 1) ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg, $noreg :: (store (s128) into %ir.lsr.iv1921, align 1)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $lr liveins: $r0, $r1, $r2, $r3, $lr
frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp
Show All 16 Lines bb.1.vector.ph:
renamable $r12 = t2SUBri killed renamable $r12, 16, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 16, 14, $noreg, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv15, align 1) renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv15, align 1)
renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1618, align 1) renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1618, align 1)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg :: (store (s128) into %ir.lsr.iv1921, align 1) renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg, $noreg :: (store (s128) into %ir.lsr.iv1921, align 1)
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-invariant.mir

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCBZ $r2, %bb.3 ; CHECK: tCBZ $r2, %bb.3
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r2 ; CHECK: liveins: $r0, $r2
; CHECK: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg ; CHECK: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.4(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.4(0x04000000)
; CHECK: liveins: $lr, $q0, $r0 ; CHECK: liveins: $lr, $q0, $r0
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, killed $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, undef renamable $q1
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: tB %bb.4, 14 /* CC::al */, $noreg ; CHECK: tB %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: bb.4.exit: ; CHECK: bb.4.exit:
; CHECK: liveins: $q1 ; CHECK: liveins: $q1
; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, implicit killed $q1 ; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, implicit killed $q1
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
bb.0.entry: bb.0.entry:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r2, $r7, $lr liveins: $r0, $r2, $r7, $lr
Show All 9 Lines bb.1.vector.ph:
liveins: $r0, $r2 liveins: $r0, $r2
renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
$lr = t2DoLoopStart renamable $r3 $lr = t2DoLoopStart renamable $r3
$r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.4(0x04000000) successors: %bb.2(0x7c000000), %bb.4(0x04000000)
liveins: $q0, $r0, $r1, $r2 liveins: $q0, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
$lr = tMOVr $r1, 14 /* CC::al */, $noreg $lr = tMOVr $r1, 14 /* CC::al */, $noreg
renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 1, killed renamable $vpr, undef renamable $q1 renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, undef renamable $q1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.4, 14 /* CC::al */, $noreg tB %bb.4, 14 /* CC::al */, $noreg
bb.3: bb.3:
successors: %bb.4(0x80000000) successors: %bb.4(0x80000000)
renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
bb.4.exit: bb.4.exit:
liveins: $q1 liveins: $q1
renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg
renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, implicit $q1 renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, implicit $q1
tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3 tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $lr = MVE_WLSTP_16 killed renamable $r2, %bb.4 ; CHECK: $lr = MVE_WLSTP_16 killed renamable $r2, %bb.4
; CHECK: bb.1.for.body.preheader: ; CHECK: bb.1.for.body.preheader:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.2.for.body: ; CHECK: bb.2.for.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r3
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 0, $noreg :: (load (s64) from %ir.input_2_cast, align 1) ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.input_2_cast, align 1)
; CHECK: renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 0, $noreg :: (load (s64) from %ir.input_1_cast, align 1) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.input_1_cast, align 1)
; CHECK: renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, killed $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, killed $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4.for.cond.cleanup: ; CHECK: bb.4.for.cond.cleanup:
; CHECK: liveins: $lr ; CHECK: liveins: $lr
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x40000000), %bb.4(0x40000000) successors: %bb.1(0x40000000), %bb.4(0x40000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg
renamable $lr = t2LSRri killed renamable $r3, 3, 14, $noreg, $noreg renamable $lr = t2LSRri killed renamable $r3, 3, 14, $noreg, $noreg
$lr = t2WhileLoopStartLR renamable $lr, %bb.4, implicit-def dead $cpsr $lr = t2WhileLoopStartLR renamable $lr, %bb.4, implicit-def dead $cpsr
tB %bb.1, 14, $noreg tB %bb.1, 14, $noreg
bb.1.for.body.preheader: bb.1.for.body.preheader:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
bb.2.for.body: bb.2.for.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2, $r3, $lr liveins: $q0, $r0, $r1, $r2, $r3, $lr
renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed $r3, 1, 14, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
MVE_VPST 1, implicit $vpr MVE_VPST 1, implicit $vpr
renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.input_2_cast, align 1) renamable $r1, renamable $q1 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.input_2_cast, align 1)
renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.input_1_cast, align 1) renamable $r0, renamable $q2 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.input_1_cast, align 1)
renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 1, renamable $vpr, undef renamable $q1 renamable $q1 = MVE_VADDi16 killed renamable $q2, killed renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q1
renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 1, killed renamable $vpr, undef renamable $q0 renamable $q0 = MVE_VADDi16 killed renamable $q1, killed renamable $q0, 1, killed renamable $vpr, $noreg, undef renamable $q0
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0 liveins: $q0
renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg
tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
bb.4.for.cond.cleanup: bb.4.for.cond.cleanup:
liveins: $lr liveins: $lr
$r0, dead $cpsr = tMOVi8 0, 14, $noreg $r0, dead $cpsr = tMOVi8 0, 14, $noreg
tBX_RET 14, $noreg, implicit killed $r0 tBX_RET 14, $noreg, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir

Show First 20 Lines • Show All 327 Lines • ▼ Show 20 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.vector.body (align 4): ; CHECK: bb.2.vector.body (align 4):
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg :: (load (s32) from %ir.lsr.iv13, align 1) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv13, align 1)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg :: (load (s32) from %ir.lsr.iv1416, align 1) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv1416, align 1)
; CHECK: renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x50000000) successors: %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
Show All 9 Lines bb.1.vector.ph:
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
$r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body (align 4): bb.2.vector.body (align 4):
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2 liveins: $lr, $q0, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load (s32) from %ir.lsr.iv13, align 1) renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s32) from %ir.lsr.iv13, align 1)
renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load (s32) from %ir.lsr.iv1416, align 1) renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s32) from %ir.lsr.iv1416, align 1)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0 liveins: $q0
renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
... ...
--- ---
name: add_var_i8 name: add_var_i8
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
registers: [] registers: []
Show All 29 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.vector.body (align 4): ; CHECK: bb.2.vector.body (align 4):
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg :: (load (s32) from %ir.lsr.iv14, align 1) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv14, align 1)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg :: (load (s32) from %ir.lsr.iv1517, align 1) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s32) from %ir.lsr.iv1517, align 1)
; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, killed renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x50000000) successors: %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
Show All 9 Lines bb.1.vector.ph:
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
$r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body (align 4): bb.2.vector.body (align 4):
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2 liveins: $lr, $q0, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load (s32) from %ir.lsr.iv14, align 1) renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s32) from %ir.lsr.iv14, align 1)
renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load (s32) from %ir.lsr.iv1517, align 1) renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s32) from %ir.lsr.iv1517, align 1)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0 liveins: $q0
renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
... ...
--- ---
name: mul_var_i16 name: mul_var_i16
alignment: 2 alignment: 2
exposesReturnsTwice: false exposesReturnsTwice: false
tracksRegLiveness: true tracksRegLiveness: true
Show All 30 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.vector.body (align 4): ; CHECK: bb.2.vector.body (align 4):
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load (s64) from %ir.lsr.iv13, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv13, align 2)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg :: (load (s64) from %ir.lsr.iv1416, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1416, align 2)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x50000000) successors: %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
Show All 9 Lines bb.1.vector.ph:
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
$r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body (align 4): bb.2.vector.body (align 4):
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2 liveins: $lr, $q0, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv13, align 2) renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv13, align 2)
renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1416, align 2) renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1416, align 2)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0 liveins: $q0
renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
... ...
--- ---
name: add_var_i16 name: add_var_i16
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
registers: [] registers: []
Show All 29 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.vector.body (align 4): ; CHECK: bb.2.vector.body (align 4):
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load (s64) from %ir.lsr.iv14, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv14, align 2)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg :: (load (s64) from %ir.lsr.iv1517, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.lsr.iv1517, align 2)
; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, killed renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x50000000) successors: %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
Show All 9 Lines bb.1.vector.ph:
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
$r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body (align 4): bb.2.vector.body (align 4):
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2 liveins: $lr, $q0, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv14, align 2) renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv14, align 2)
renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1517, align 2) renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1517, align 2)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0 liveins: $q0
renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
... ...
--- ---
name: mul_var_i32 name: mul_var_i32
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
registers: [] registers: []
Show All 29 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.vector.body (align 4): ; CHECK: bb.2.vector.body (align 4):
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv12, align 4) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv12, align 4)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4)
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, $noreg, killed renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x50000000) successors: %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
Show All 9 Lines bb.1.vector.ph:
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
$r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body (align 4): bb.2.vector.body (align 4):
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2 liveins: $lr, $q0, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv12, align 4) renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv12, align 4)
renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1315, align 4) renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1315, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, renamable $q0
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0 liveins: $q0
renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
... ...
--- ---
name: add_var_i32 name: add_var_i32
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
registers: [] registers: []
Show All 29 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.vector.body (align 4): ; CHECK: bb.2.vector.body (align 4):
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1 ; CHECK: liveins: $lr, $q0, $r0, $r1
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, killed renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, $noreg, killed renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0 ; CHECK: liveins: $q0
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x50000000) successors: %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
Show All 9 Lines bb.1.vector.ph:
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
$r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body (align 4): bb.2.vector.body (align 4):
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2 liveins: $lr, $q0, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0 liveins: $q0
renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir

Show First 20 Lines • Show All 177 Lines • ▼ Show 20 Linesbody: |
; CHECK: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg ; CHECK: dead $lr = tMOVr renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: bb.4.vector.body: ; CHECK: bb.4.vector.body:
; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000) ; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg :: (load (s128) from %ir.scevgep18, align 4) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep18, align 4)
; CHECK: $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg :: (store (s128) into %ir.scevgep13, align 4) ; CHECK: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg, $noreg :: (store (s128) into %ir.scevgep13, align 4)
; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr ; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
; CHECK: tB %bb.5, 14 /* CC::al */, $noreg ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg
; CHECK: bb.5.middle.block: ; CHECK: bb.5.middle.block:
; CHECK: successors: %bb.7(0x80000000) ; CHECK: successors: %bb.7(0x80000000)
; CHECK: liveins: $r2, $r3, $r4, $r7, $r12 ; CHECK: liveins: $r2, $r3, $r4, $r7, $r12
; CHECK: tCMPr killed renamable $r4, killed renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPr killed renamable $r4, killed renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines bb.3.vector.ph:
$r5 = tMOVr killed $r3, 14, $noreg $r5 = tMOVr killed $r3, 14, $noreg
renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14, $noreg, $noreg renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14, $noreg
bb.4.vector.body: bb.4.vector.body:
successors: %bb.4(0x7c000000), %bb.5(0x04000000) successors: %bb.4(0x7c000000), %bb.5(0x04000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12 liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12
renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg :: (load (s128) from %ir.scevgep18, align 4) renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep18, align 4)
$lr = tMOVr killed $r5, 14, $noreg $lr = tMOVr killed $r5, 14, $noreg
renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg :: (store (s128) into %ir.scevgep13, align 4) renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg, $noreg :: (store (s128) into %ir.scevgep13, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r5 = tMOVr $lr, 14, $noreg $r5 = tMOVr $lr, 14, $noreg
t2LoopEnd killed renamable $lr, %bb.4, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.4, implicit-def dead $cpsr
tB %bb.5, 14, $noreg tB %bb.5, 14, $noreg
bb.5.middle.block: bb.5.middle.block:
successors: %bb.7(0x80000000) successors: %bb.7(0x80000000)
liveins: $r2, $r3, $r4, $r7, $r12 liveins: $r2, $r3, $r4, $r7, $r12
Show All 40 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) ; CHECK: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
; CHECK: dead $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: dead $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg ; CHECK: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg
; CHECK: bb.2.loop.body: ; CHECK: bb.2.loop.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r12
; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.addr.b, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.b, align 4)
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg :: (load (s128) from %ir.addr.a, align 4) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.a, align 4)
; CHECK: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg ; CHECK: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg
; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg :: (store (s128) into %ir.addr.c, align 4) ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.addr.c, align 4)
; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
Show All 11 Lines bb.1.loop.ph:
renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
$lr = t2DoLoopStart renamable $r4 $lr = t2DoLoopStart renamable $r4
$r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg
bb.2.loop.body: bb.2.loop.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
$lr = tMOVr $r12, 14 /* CC::al */, $noreg $lr = tMOVr $r12, 14 /* CC::al */, $noreg
renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.b, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.a, align 4) renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.addr.c, align 4) renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
... ...
--- ---
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r12 = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) ; CHECK: renamable $r12 = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
; CHECK: dead $lr = MVE_DLSTP_16 killed renamable $r3 ; CHECK: dead $lr = MVE_DLSTP_16 killed renamable $r3
; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.2.loop.body: ; CHECK: bb.2.loop.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r4 ; CHECK: liveins: $r0, $r1, $r2, $r4
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.addr.b, align 2) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.b, align 2)
; CHECK: renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 0, $noreg :: (load (s128) from %ir.addr.a, align 2) ; CHECK: renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 0, $noreg, $noreg :: (load (s128) from %ir.addr.a, align 2)
; CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg ; CHECK: renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg
; CHECK: renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg :: (store (s128) into %ir.addr.c, align 2) ; CHECK: renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.addr.c, align 2)
; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
Show All 11 Lines bb.1.loop.ph:
renamable $r12 = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) renamable $r12 = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg
bb.2.loop.body: bb.2.loop.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3, $r4 liveins: $r0, $r1, $r2, $r3, $r4
renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.b, align 2) renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 2)
renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 1, renamable $vpr :: (load (s128) from %ir.addr.a, align 2) renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 2)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r1, 14 /* CC::al */, $noreg $r0 = tMOVr $r1, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.addr.c, align 2) renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 2)
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir

Show First 20 Lines • Show All 189 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r12
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg, debug-location !28 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg, debug-location !28
; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg, debug-location !28 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg, debug-location !28
; CHECK: renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, debug-location !28 ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, debug-location !28
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, undef renamable $q0, debug-location !28 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, $noreg, undef renamable $q0, debug-location !28
; CHECK: renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14 /* CC::al */, $noreg, debug-location !28 ; CHECK: renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14 /* CC::al */, $noreg, debug-location !28
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg, debug-location !28 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg, debug-location !28
; CHECK: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !28 ; CHECK: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14 /* CC::al */, $noreg, debug-location !28
; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg, debug-location !28 ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14 /* CC::al */, $noreg, $noreg, debug-location !28
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, debug-location !30 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg, debug-location !30
; CHECK: DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !30 ; CHECK: DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !30
; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q1
; CHECK: MVE_VPST 8, implicit $vpr, debug-location !30 ; CHECK: MVE_VPST 8, implicit $vpr, debug-location !30
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, debug-location !30 :: (load (s64) from %ir.lsr.iv14, align 2) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg, debug-location !30 :: (load (s64) from %ir.lsr.iv14, align 2)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg, debug-location !30 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg, debug-location !30
; CHECK: renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !30 ; CHECK: renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !30
; CHECK: renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !32 ; CHECK: renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !32
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2, debug-location !29 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2, debug-location !29
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: liveins: $q0, $q1, $r0, $r3 ; CHECK: liveins: $q0, $q1, $r0, $r3
; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, debug-location !30 ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg, debug-location !30
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, debug-location !32 ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg, debug-location !32
; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, debug-location !28 ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg, debug-location !28
; CHECK: bb.4.for.cond.cleanup: ; CHECK: bb.4.for.cond.cleanup:
; CHECK: liveins: $r0, $r12 ; CHECK: liveins: $r0, $r12
; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23 ; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
; CHECK: t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !33 :: (store (s32) into %ir.a) ; CHECK: t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14 /* CC::al */, $noreg, debug-location !33 :: (store (s32) into %ir.a)
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !34 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !34
bb.0.entry: bb.0.entry:
successors: %bb.4(0x30000000), %bb.1(0x50000000) successors: %bb.4(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r4, $r6, $lr liveins: $r0, $r1, $r2, $r4, $r6, $lr
Show All 21 Lines bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r12 liveins: $r0, $r1, $r2, $r12
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg, debug-location !32 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg, debug-location !32
renamable $lr = t2MOVi 1, 14, $noreg, $noreg renamable $lr = t2MOVi 1, 14, $noreg, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg, debug-location !32 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg, debug-location !32
renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg, debug-location !32 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg, debug-location !32
renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, undef renamable $q0, debug-location !32 renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, $noreg, undef renamable $q0, debug-location !32
renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14, $noreg, debug-location !32 renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14, $noreg, debug-location !32
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14, $noreg, $noreg, debug-location !32 renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14, $noreg, $noreg, debug-location !32
renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14, $noreg, debug-location !32 renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14, $noreg, debug-location !32
renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14, $noreg, $noreg, debug-location !32 renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14, $noreg, $noreg, debug-location !32
$lr = t2DoLoopStart renamable $lr, debug-location !32 $lr = t2DoLoopStart renamable $lr, debug-location !32
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3 liveins: $lr, $q0, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, debug-location !34 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg, debug-location !34
DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !34 DBG_VALUE $vpr, $noreg, !17, !DIExpression(), debug-location !34
$q1 = MVE_VORR killed $q0, $q0, 0, $noreg, undef $q1 $q1 = MVE_VORR killed $q0, $q0, 0, $noreg, $noreg, undef $q1
MVE_VPST 8, implicit $vpr, debug-location !34 MVE_VPST 8, implicit $vpr, debug-location !34
renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, debug-location !34 :: (load (s64) from %ir.lsr.iv14, align 2) renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg, debug-location !34 :: (load (s64) from %ir.lsr.iv14, align 2)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg, debug-location !34 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg, debug-location !34
renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !34 renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !34
renamable $lr = t2LoopDec killed renamable $lr, 1, debug-location !33 renamable $lr = t2LoopDec killed renamable $lr, 1, debug-location !33
renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !38 renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0, debug-location !38
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr, debug-location !33 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr, debug-location !33
tB %bb.3, 14, $noreg, debug-location !33 tB %bb.3, 14, $noreg, debug-location !33
bb.3.middle.block: bb.3.middle.block:
successors: %bb.4(0x80000000) successors: %bb.4(0x80000000)
liveins: $q0, $q1, $r0, $r3 liveins: $q0, $q1, $r0, $r3
renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, debug-location !34 renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg, debug-location !34
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, debug-location !38 renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg, debug-location !38
renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, debug-location !32 renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg, debug-location !32
bb.4.for.cond.cleanup: bb.4.for.cond.cleanup:
liveins: $r0, $r12 liveins: $r0, $r12
DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23 DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23
t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14, $noreg, debug-location !42 :: (store (s32) into %ir.a) t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14, $noreg, debug-location !42 :: (store (s32) into %ir.a)
tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !43 tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !43
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir

Show First 20 Lines • Show All 201 Lines • ▼ Show 20 Linesbody: |
; CHECK: tCBZ renamable $r1, %bb.4, debug-location !31 ; CHECK: tCBZ renamable $r1, %bb.4, debug-location !31
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29 ; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29 ; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29 ; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29 ; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
; CHECK: renamable $q0 = MVE_VMOVimmi32 1152, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 1152, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1, debug-location !31 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1, debug-location !31
; CHECK: bb.2.vector.body (align 4): ; CHECK: bb.2.vector.body (align 4):
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r2 ; CHECK: liveins: $lr, $q0, $r0, $r2
; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29 ; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29 ; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, debug-location !32 :: (load (s128) from %ir.lsr.iv12, align 4, !tbaa !34) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg, debug-location !32 :: (load (s128) from %ir.lsr.iv12, align 4, !tbaa !34)
; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29 ; CHECK: DBG_VALUE $r0, $noreg, !24, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr, debug-location !40 ; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr, debug-location !40
; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, killed renamable $q0, debug-location !40 ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q0, debug-location !40
; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29 ; CHECK: DBG_VALUE $r1, $noreg, !25, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $q0, $r2 ; CHECK: liveins: $q0, $r2
; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29 ; CHECK: DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29 ; CHECK: DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
; CHECK: renamable $s4 = nnan ninf nsz VFP_VMAXNMS renamable $s2, renamable $s3, debug-location !31 ; CHECK: renamable $s4 = nnan ninf nsz VFP_VMAXNMS renamable $s2, renamable $s3, debug-location !31
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines bb.1.vector.ph:
DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29 DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29 DBG_VALUE $r1, $noreg, !25, !DIExpression(), debug-location !29
DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29 DBG_VALUE $r0, $noreg, !24, !DIExpression(), debug-location !29
renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg, debug-location !31 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg, debug-location !31
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg, debug-location !31 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg, debug-location !31
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg, debug-location !31 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg, debug-location !31
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg, debug-location !31 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg, debug-location !31
renamable $q0 = MVE_VMOVimmi32 1152, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 1152, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2DoLoopStartTP killed renamable $r3, renamable $r1, debug-location !31 renamable $lr = t2DoLoopStartTP killed renamable $r3, renamable $r1, debug-location !31
bb.2.vector.body (align 4): bb.2.vector.body (align 4):
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2 liveins: $lr, $q0, $r0, $r1, $r2
DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29 DBG_VALUE float 0x3810000000000000, $noreg, !27, !DIExpression(), debug-location !29
DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29 DBG_VALUE $r2, $noreg, !26, !DIExpression(), debug-location !29
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
MVE_VPST 2, implicit $vpr, debug-location !32 MVE_VPST 2, implicit $vpr, debug-location !32
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, debug-location !32 :: (load (s128) from %ir.lsr.iv12, align 4, !tbaa !34) renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg, debug-location !32 :: (load (s128) from %ir.lsr.iv12, align 4, !tbaa !34)
DBG_VALUE $r0, $noreg, !24, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29 DBG_VALUE $r0, $noreg, !24, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr, debug-location !40 renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr, $noreg, debug-location !40
renamable $q0 = MVE_VORR killed renamable $q1, renamable $q1, 1, killed renamable $vpr, killed renamable $q0, debug-location !40 renamable $q0 = MVE_VORR killed renamable $q1, renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q0, debug-location !40
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
DBG_VALUE $r1, $noreg, !25, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29 DBG_VALUE $r1, $noreg, !25, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location !29
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.middle.block: bb.3.middle.block:
successors: %bb.5(0x80000000) successors: %bb.5(0x80000000)
liveins: $q0, $r2 liveins: $q0, $r2
Show All 30 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Linesbody: |
; CHECK: $r0 = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 10, 8, implicit-def $itstate ; CHECK: t2IT 10, 8, implicit-def $itstate
; CHECK: renamable $r0 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r0, implicit killed $itstate ; CHECK: renamable $r0 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r0, implicit killed $itstate
; CHECK: renamable $r0, dead $cpsr = tSUBrr renamable $r2, killed renamable $r0, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBrr renamable $r2, killed renamable $r0, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r0 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r0, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r0 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r0, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = t2DLS killed renamable $r0 ; CHECK: $lr = t2DLS killed renamable $r0
; CHECK: bb.2.while.body (align 4): ; CHECK: bb.2.while.body (align 4):
; CHECK: successors: %bb.2(0x7c000000), %bb.4(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.4(0x04000000)
; CHECK: liveins: $lr, $q0, $r1, $r2 ; CHECK: liveins: $lr, $q0, $r1, $r2
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load (s128) from %ir.y.addr.0161, align 4) ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr, $lr :: (load (s128) from %ir.y.addr.0161, align 4)
; CHECK: renamable $q0 = MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: tB %bb.4, 14 /* CC::al */, $noreg ; CHECK: tB %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0
; CHECK: bb.4.while.end: ; CHECK: bb.4.while.end:
; CHECK: liveins: $d0 ; CHECK: liveins: $d0
; CHECK: renamable $r0, renamable $r1 = VMOVRRD killed renamable $d0, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, renamable $r1 = VMOVRRD killed renamable $d0, 14 /* CC::al */, $noreg
; CHECK: renamable $r0 = nsw tADDhirr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg ; CHECK: renamable $r0 = nsw tADDhirr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x50000000), %bb.3(0x30000000) successors: %bb.1(0x50000000), %bb.3(0x30000000)
liveins: $r1, $r2, $r7, $lr liveins: $r1, $r2, $r7, $lr
Show All 12 Lines bb.1.while.body.preheader:
$r0 = tMOVr $r2, 14 /* CC::al */, $noreg $r0 = tMOVr $r2, 14 /* CC::al */, $noreg
tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 10, 8, implicit-def $itstate t2IT 10, 8, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r0, implicit killed $itstate renamable $r0 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r0, implicit killed $itstate
renamable $r0, dead $cpsr = tSUBrr renamable $r2, killed renamable $r0, 14 /* CC::al */, $noreg renamable $r0, dead $cpsr = tSUBrr renamable $r2, killed renamable $r0, 14 /* CC::al */, $noreg
renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 3, 14 /* CC::al */, $noreg renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 3, 14 /* CC::al */, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r0 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r0, 19, 14 /* CC::al */, $noreg, $noreg renamable $r0 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r0, 19, 14 /* CC::al */, $noreg, $noreg
renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2DoLoopStartTP killed renamable $r0, renamable $r2 renamable $lr = t2DoLoopStartTP killed renamable $r0, renamable $r2
bb.2.while.body (align 4): bb.2.while.body (align 4):
successors: %bb.2(0x7c000000), %bb.4(0x04000000) successors: %bb.2(0x7c000000), %bb.4(0x04000000)
liveins: $lr, $q0:0x000000000000003C, $r1, $r2 liveins: $lr, $q0:0x000000000000003C, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load (s128) from %ir.y.addr.0161, align 4) renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr, $lr :: (load (s128) from %ir.y.addr.0161, align 4)
renamable $q0 = MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.4, 14 /* CC::al */, $noreg tB %bb.4, 14 /* CC::al */, $noreg
bb.3: bb.3:
successors: %bb.4(0x80000000) successors: %bb.4(0x80000000)
renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0
bb.4.while.end: bb.4.while.end:
liveins: $q0:0x000000000000000C liveins: $q0:0x000000000000000C
renamable $r0, renamable $r1 = VMOVRRD killed renamable $d0, 14 /* CC::al */, $noreg renamable $r0, renamable $r1 = VMOVRRD killed renamable $d0, 14 /* CC::al */, $noreg
renamable $r0 = nsw tADDhirr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg renamable $r0 = nsw tADDhirr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Linesbody: |
; CHECK: $r12 = t2MOVi16 32768, 14 /* CC::al */, $noreg ; CHECK: $r12 = t2MOVi16 32768, 14 /* CC::al */, $noreg
; CHECK: $r12 = t2MOVTi16 killed $r12, 65535, 14 /* CC::al */, $noreg ; CHECK: $r12 = t2MOVTi16 killed $r12, 65535, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2DLS renamable $r3 ; CHECK: dead $lr = t2DLS renamable $r3
; CHECK: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r5, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r5, $r12
; CHECK: $r3 = tMOVr $r12, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r3 = MVE_VMAXVs16 killed renamable $r3, killed renamable $q0, 0, $noreg ; CHECK: renamable $r3 = MVE_VMAXVs16 killed renamable $r3, killed renamable $q0, 0, $noreg, $noreg
; CHECK: $lr = tMOVr $r5, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r5, 14 /* CC::al */, $noreg
; CHECK: early-clobber renamable $r1 = t2STRH_POST killed renamable $r3, killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.lsr.iv.2) ; CHECK: early-clobber renamable $r1 = t2STRH_POST killed renamable $r3, killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.lsr.iv.2)
; CHECK: renamable $r5, dead $cpsr = nsw tSUBi8 killed $r5, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r5, dead $cpsr = nsw tSUBi8 killed $r5, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r5, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r5, def $pc
bb.0.entry: bb.0.entry:
Show All 22 Lines bb.1.vector.ph:
$lr = t2DoLoopStart renamable $r3 $lr = t2DoLoopStart renamable $r3
$r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r5, $r12 liveins: $r0, $r1, $r2, $r5, $r12
$r3 = tMOVr $r12, 14 /* CC::al */, $noreg $r3 = tMOVr $r12, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)
renamable $r3 = MVE_VMAXVs16 killed renamable $r3, killed renamable $q0, 0, $noreg renamable $r3 = MVE_VMAXVs16 killed renamable $r3, killed renamable $q0, 0, $noreg, $noreg
$lr = tMOVr $r5, 14 /* CC::al */, $noreg $lr = tMOVr $r5, 14 /* CC::al */, $noreg
early-clobber renamable $r1 = t2STRH_POST killed renamable $r3, killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.lsr.iv.2) early-clobber renamable $r1 = t2STRH_POST killed renamable $r3, killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (store (s16) into %ir.lsr.iv.2)
renamable $r5, dead $cpsr = nsw tSUBi8 killed $r5, 1, 14 /* CC::al */, $noreg renamable $r5, dead $cpsr = nsw tSUBi8 killed $r5, 1, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
tPOP_RET 14 /* CC::al */, $noreg, def $r5, def $pc tPOP_RET 14 /* CC::al */, $noreg, def $r5, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir

Show First 20 Lines • Show All 282 Lines • ▼ Show 20 Linesbody: |
; CHECK: tB %bb.8, 14 /* CC::al */, $noreg ; CHECK: tB %bb.8, 14 /* CC::al */, $noreg
; CHECK: bb.4.vector.ph: ; CHECK: bb.4.vector.ph:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $lr = MVE_DLSTP_8 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_8 killed renamable $r3
; CHECK: bb.5.vector.body: ; CHECK: bb.5.vector.body:
; CHECK: successors: %bb.5(0x7c000000), %bb.11(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.11(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv46, align 1) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv46, align 1)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv4749, align 1) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv4749, align 1)
; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.iv5052, align 1) ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5052, align 1)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
; CHECK: tB %bb.11, 14 /* CC::al */, $noreg ; CHECK: tB %bb.11, 14 /* CC::al */, $noreg
; CHECK: bb.6.for.body.preheader.new: ; CHECK: bb.6.for.body.preheader.new:
; CHECK: successors: %bb.7(0x80000000) ; CHECK: successors: %bb.7(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines bb.4.vector.ph:
renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 16, 14, $noreg renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 16, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r6, 35, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r6, 35, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.5.vector.body: bb.5.vector.body:
successors: %bb.5(0x7c000000), %bb.11(0x04000000) successors: %bb.5(0x7c000000), %bb.11(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv46, align 1) renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv46, align 1)
renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv4749, align 1) renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv4749, align 1)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv5052, align 1) renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv5052, align 1)
t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr
tB %bb.11, 14, $noreg tB %bb.11, 14, $noreg
bb.6.for.body.preheader.new: bb.6.for.body.preheader.new:
successors: %bb.7(0x80000000) successors: %bb.7(0x80000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r12 liveins: $lr, $r0, $r1, $r2, $r3, $r12
renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-retaining.mir

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) ; CHECK: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
; CHECK: dead $lr = t2DLS renamable $r4 ; CHECK: dead $lr = t2DLS renamable $r4
; CHECK: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg ; CHECK: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg
; CHECK: bb.2.loop.body: ; CHECK: bb.2.loop.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.a, align 4) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)
; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.b, align 4) ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)
; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VMVN killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMVN killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VQSHRNbhs32 killed renamable $q0, killed renamable $q1, 15, 0, $noreg ; CHECK: renamable $q0 = MVE_VQSHRNbhs32 killed renamable $q0, killed renamable $q1, 15, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.addr.c, align 4) ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
Show All 11 Lines bb.1.loop.ph:
renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
$lr = t2DoLoopStart renamable $r4 $lr = t2DoLoopStart renamable $r4
$r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg
bb.2.loop.body: bb.2.loop.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
$lr = tMOVr $r12, 14 /* CC::al */, $noreg $lr = tMOVr $r12, 14 /* CC::al */, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.a, align 4) renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)
renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.b, align 4) renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)
renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
renamable $q1 = MVE_VMVN killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VMVN killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q0 = MVE_VQSHRNbhs32 killed renamable $q0, killed renamable $q1, 15, 0, $noreg renamable $q0 = MVE_VQSHRNbhs32 killed renamable $q0, killed renamable $q1, 15, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.addr.c, align 4) renamable $r2 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
... ...
--- ---
Show All 40 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) ; CHECK: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
; CHECK: dead $lr = t2DLS renamable $r4 ; CHECK: dead $lr = t2DLS renamable $r4
; CHECK: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg ; CHECK: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg
; CHECK: bb.2.loop.body: ; CHECK: bb.2.loop.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.b, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.a, align 4) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)
; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VORN renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VORN renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg ; CHECK: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.addr.c, align 4) ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
Show All 11 Lines bb.1.loop.ph:
renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
$lr = t2DoLoopStart renamable $r4 $lr = t2DoLoopStart renamable $r4
$r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg
bb.2.loop.body: bb.2.loop.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.b, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.addr.a, align 4) renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)
$lr = tMOVr $r12, 14 /* CC::al */, $noreg $lr = tMOVr $r12, 14 /* CC::al */, $noreg
renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VORN renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VORN renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr :: (store (s128) into %ir.addr.c, align 4) renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir

Show First 20 Lines • Show All 854 Lines • ▼ Show 20 Linesbody: |
; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
Show All 16 Lines bb.1.vector.ph:
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3 liveins: $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
$lr = tMOVr $r3, 14 /* CC::al */, $noreg $lr = tMOVr $r3, 14 /* CC::al */, $noreg
early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
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; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: $lr = MVE_DLSTP_16 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_16 killed renamable $r2
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg :: (load (s128) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
Show All 16 Lines bb.1.vector.ph:
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3 liveins: $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)
renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg, $noreg
$lr = tMOVr $r3, 14 /* CC::al */, $noreg $lr = tMOVr $r3, 14 /* CC::al */, $noreg
early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
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; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: $lr = MVE_DLSTP_8 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_8 killed renamable $r2
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 0, killed $noreg :: (load (s128) from %ir.lsr.iv17, align 1) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)
; CHECK: renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
Show All 16 Lines bb.1.vector.ph:
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3 liveins: $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 1) renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)
renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg, $noreg
$lr = tMOVr $r3, 14 /* CC::al */, $noreg $lr = tMOVr $r3, 14 /* CC::al */, $noreg
early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
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; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r2 ; CHECK: liveins: $lr, $r0, $r2
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $r2 ; CHECK: liveins: $r2
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
Show All 20 Lines bb.1.vector.ph:
$lr = t2DoLoopStart renamable $r2 $lr = t2DoLoopStart renamable $r2
$r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3 liveins: $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
$lr = tMOVr $r3, 14 /* CC::al */, $noreg $lr = tMOVr $r3, 14 /* CC::al */, $noreg
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
liveins: $r2 liveins: $r2
$r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
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; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r12 ; CHECK: dead $lr = t2DLS renamable $r12
; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
Show All 18 Lines bb.1.vector.ph:
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3 liveins: $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
$lr = tMOVr $r3, 14 /* CC::al */, $noreg $lr = tMOVr $r3, 14 /* CC::al */, $noreg
renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r2 ; CHECK: dead $lr = t2DLS renamable $r2
; CHECK: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $r2 ; CHECK: liveins: $r2
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
Show All 20 Lines bb.1.vector.ph:
$lr = t2DoLoopStart renamable $r2 $lr = t2DoLoopStart renamable $r2
$r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3 liveins: $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
$lr = tMOVr $r3, 14 /* CC::al */, $noreg $lr = tMOVr $r3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
liveins: $r2 liveins: $r2
$r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
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; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r12 ; CHECK: dead $lr = t2DLS renamable $r12
; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
Show All 18 Lines bb.1.vector.ph:
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3 liveins: $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
$lr = tMOVr $r3, 14 /* CC::al */, $noreg $lr = tMOVr $r3, 14 /* CC::al */, $noreg
renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
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; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r2 ; CHECK: dead $lr = t2DLS renamable $r2
; CHECK: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $r2 ; CHECK: liveins: $r2
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
Show All 20 Lines bb.1.vector.ph:
$lr = t2DoLoopStart renamable $r2 $lr = t2DoLoopStart renamable $r2
$r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3 liveins: $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
$lr = tMOVr $r3, 14 /* CC::al */, $noreg $lr = tMOVr $r3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
liveins: $r2 liveins: $r2
$r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
; CHECK: dead $lr = t2DLS renamable $r12 ; CHECK: dead $lr = t2DLS renamable $r12
; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 1) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1)
; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
Show All 14 Lines bb.1.vector.ph:
liveins: $r0, $r1, $r2, $r4, $lr liveins: $r0, $r1, $r2, $r4, $lr
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2, $r4 liveins: $q0, $r0, $r1, $r2, $r4
renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 1) renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1)
renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0)
; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2DLS renamable $r2 ; CHECK: dead $lr = t2DLS renamable $r2
; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 1) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1)
; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg ; CHECK: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $r3 ; CHECK: liveins: $r3
; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0
Show All 25 Lines bb.1.vector.ph:
renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $r2 $lr = t2DoLoopStart renamable $r2
$r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r3, $r4 liveins: $q0, $r0, $r1, $r3, $r4
renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 1) renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 1)
renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
; CHECK: dead $lr = t2DLS renamable $r12 ; CHECK: dead $lr = t2DLS renamable $r12
; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)
; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
Show All 13 Lines bb.1.vector.ph:
liveins: $r0, $r1, $r2, $r4, $lr liveins: $r0, $r1, $r2, $r4, $lr
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2, $r4 liveins: $q0, $r0, $r1, $r2, $r4
renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)
renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0)
; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2DLS renamable $r2 ; CHECK: dead $lr = t2DLS renamable $r2
; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)
; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg ; CHECK: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $r3 ; CHECK: liveins: $r3
; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0
Show All 25 Lines bb.1.vector.ph:
renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $r2 $lr = t2DoLoopStart renamable $r2
$r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r3, $r4 liveins: $q0, $r0, $r1, $r3, $r4
renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 2)
renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg, $noreg
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
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; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
; CHECK: dead $lr = t2DLS renamable $r12 ; CHECK: dead $lr = t2DLS renamable $r12
; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4
; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 1) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)
; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
Show All 13 Lines bb.1.vector.ph:
liveins: $r0, $r1, $r2, $r4, $lr liveins: $r0, $r1, $r2, $r4, $lr
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2, $r4 liveins: $q0, $r0, $r1, $r2, $r4
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 1) renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)
renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0)
; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2DLS renamable $r2 ; CHECK: dead $lr = t2DLS renamable $r2
; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4
; CHECK: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 1) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)
; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg ; CHECK: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $r3 ; CHECK: liveins: $r3
; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0
Show All 25 Lines bb.1.vector.ph:
renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $r2 $lr = t2DoLoopStart renamable $r2
$r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r3, $r4 liveins: $q0, $r0, $r1, $r3, $r4
renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 1) renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)
renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesbody: |
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
; CHECK: dead $lr = t2DLS renamable $r12 ; CHECK: dead $lr = t2DLS renamable $r12
; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4
; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 1) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)
; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
Show All 13 Lines bb.1.vector.ph:
liveins: $r0, $r1, $r2, $r4, $lr liveins: $r0, $r1, $r2, $r4, $lr
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from %fixed-stack.0, align 8) renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r2, $r4 liveins: $q0, $r0, $r1, $r2, $r4
renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 1) renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)
renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr) early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.store.addr)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0) ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s64) from %fixed-stack.0)
; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2DLS renamable $r2 ; CHECK: dead $lr = t2DLS renamable $r2
; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4
; CHECK: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 1) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)
; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg ; CHECK: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg
; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.exit: ; CHECK: bb.3.exit:
; CHECK: liveins: $r3 ; CHECK: liveins: $r3
; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0
Show All 25 Lines bb.1.vector.ph:
renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $r2 $lr = t2DoLoopStart renamable $r2
$r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q0, $r0, $r1, $r3, $r4 liveins: $q0, $r0, $r1, $r3, $r4
renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv17, align 1) renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv17, align 1)
renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
$lr = tMOVr $r4, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg
renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg, $noreg
renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.exit: bb.3.exit:
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.1.while.body.preheader: ; CHECK: bb.1.while.body.preheader:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.while.body: ; CHECK: bb.2.while.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r12 ; CHECK: liveins: $lr, $r0, $r1, $r12
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 0, $noreg :: (load (s64) from %ir.tmp3, align 2) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 0, $noreg, $noreg :: (load (s64) from %ir.tmp3, align 2)
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 0, killed $noreg :: (load (s64) from %ir.tmp1, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 0, killed $noreg, $noreg :: (load (s64) from %ir.tmp1, align 2)
; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.while.end: ; CHECK: bb.3.while.end:
; CHECK: liveins: $r12 ; CHECK: liveins: $r12
; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
Show All 23 Lines bb.1.while.body.preheader:
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.while.body: bb.2.while.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r12 liveins: $lr, $r0, $r1, $r2, $r12
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, renamable $vpr :: (load (s64) from %ir.tmp3, align 2) renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.tmp3, align 2)
renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load (s64) from %ir.tmp1, align 2) renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.tmp1, align 2)
renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.while.end: bb.3.while.end:
liveins: $r12 liveins: $r12
$r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.1.while.body.preheader: ; CHECK: bb.1.while.body.preheader:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_16 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_16 killed renamable $r2
; CHECK: bb.2.while.body: ; CHECK: bb.2.while.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r3
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.tmp3, align 2) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.tmp3, align 2)
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg :: (load (s128) from %ir.tmp1, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg, $noreg :: (load (s128) from %ir.tmp1, align 2)
; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.while.end: ; CHECK: bb.3.while.end:
; CHECK: liveins: $r3 ; CHECK: liveins: $r3
; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
Show All 24 Lines bb.1.while.body.preheader:
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.while.body: bb.2.while.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.tmp3, align 2) renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2)
renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.tmp1, align 2) renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2)
renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.while.end: bb.3.while.end:
liveins: $r3 liveins: $r3
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.2.while.body: ; CHECK: bb.2.while.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.tmp3, align 2) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2)
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.tmp1, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2)
; CHECK: renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.while.end: ; CHECK: bb.3.while.end:
; CHECK: liveins: $r2 ; CHECK: liveins: $r2
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
Show All 23 Lines bb.1.while.body.preheader:
renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.while.body: bb.2.while.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.tmp3, align 2) renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2)
renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.tmp1, align 2) renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2)
renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q2
renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q0
renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.while.end: bb.3.while.end:
liveins: $r2 liveins: $r2
$r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r2 ; CHECK: dead $lr = t2DLS renamable $r2
; CHECK: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.2.while.body: ; CHECK: bb.2.while.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.tmp3, align 2) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2)
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.tmp1, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2)
; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.while.end: ; CHECK: bb.3.while.end:
; CHECK: liveins: $r2 ; CHECK: liveins: $r2
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
Show All 24 Lines bb.1.while.body.preheader:
$lr = t2DoLoopStart renamable $r2 $lr = t2DoLoopStart renamable $r2
$r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
bb.2.while.body: bb.2.while.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $r0, $r1, $r2, $r3, $r12 liveins: $r0, $r1, $r2, $r3, $r12
renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.tmp3, align 2) renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.tmp3, align 2)
renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load (s128) from %ir.tmp1, align 2) renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.tmp1, align 2)
$lr = tMOVr $r12, 14 /* CC::al */, $noreg $lr = tMOVr $r12, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.while.end: bb.3.while.end:
liveins: $r2 liveins: $r2
$r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.4: bb.4:
renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
$r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination-across-blocks.mir

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines - id: 0
alignment: 4 alignment: 4
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: combine_previous ; CHECK-LABEL: name: combine_previous
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK: bb.1 (align 4): ; CHECK: bb.1 (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0 ; CHECK: liveins: $lr, $q0, $r0
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q0 ; CHECK: renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, $noreg, killed renamable $q0
; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr ; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 4): ; CHECK: bb.3 (align 4):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
bb.0: bb.0:
successors: %bb.6(0x80000000) successors: %bb.6(0x80000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.6 (align 4): bb.6 (align 4):
successors: %bb.6(0x7c000000), %bb.8(0x04000000) successors: %bb.6(0x7c000000), %bb.8(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2 liveins: $lr, $q0, $r0, $r1, $r2
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, renamable $q0 renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, $noreg, renamable $q0
renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VORR killed renamable $q1, renamable $q1, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = MVE_VORR killed renamable $q1, renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q0
t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
tB %bb.8, 14 /* CC::al */, $noreg tB %bb.8, 14 /* CC::al */, $noreg
bb.8: bb.8:
liveins: $r2, $r12, $q0 liveins: $r2, $r12, $q0
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.9 (align 4): bb.9 (align 4):
Show All 32 Lines - id: 0
alignment: 4 alignment: 4
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: combine_middle ; CHECK-LABEL: name: combine_middle
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q2, $r0, $r1 ; CHECK: liveins: $q2, $r0, $r1
; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK: bb.1 (align 4): ; CHECK: bb.1 (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $q2, $r0 ; CHECK: liveins: $lr, $q0, $q2, $r0
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg
; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q2 ; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, $noreg, killed renamable $q2
; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr ; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2 ; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q2
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, killed renamable $q1 ; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, $noreg, killed renamable $q1
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 4): ; CHECK: bb.3 (align 4):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
bb.0: bb.0:
successors: %bb.6(0x80000000) successors: %bb.6(0x80000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.6 (align 4): bb.6 (align 4):
successors: %bb.6(0x7c000000), %bb.8(0x04000000) successors: %bb.6(0x7c000000), %bb.8(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $q2 liveins: $lr, $q0, $r0, $r1, $r2, $q2
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2 renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q2
renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2 renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q2
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1 renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, renamable $q1
t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
tB %bb.8, 14 /* CC::al */, $noreg tB %bb.8, 14 /* CC::al */, $noreg
bb.8: bb.8:
liveins: $r2, $r12, $q0 liveins: $r2, $r12, $q0
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.9 (align 4): bb.9 (align 4):
Show All 32 Lines - id: 0
alignment: 4 alignment: 4
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: combine_last ; CHECK-LABEL: name: combine_last
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q2, $r0, $r1 ; CHECK: liveins: $q2, $r0, $r1
; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK: bb.1 (align 4): ; CHECK: bb.1 (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $q2, $r0 ; CHECK: liveins: $lr, $q0, $q2, $r0
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg
; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr ; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, killed renamable $vpr, killed renamable $q2 ; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q2
; CHECK: MVE_VPTv4f32 8, renamable $q2, renamable $q1, 12, implicit-def $vpr ; CHECK: MVE_VPTv4f32 8, renamable $q2, renamable $q1, 12, implicit-def $vpr
; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, killed renamable $q1 ; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, $noreg, killed renamable $q1
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 4): ; CHECK: bb.3 (align 4):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
bb.0: bb.0:
successors: %bb.6(0x80000000) successors: %bb.6(0x80000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.6 (align 4): bb.6 (align 4):
successors: %bb.6(0x7c000000), %bb.8(0x04000000) successors: %bb.6(0x7c000000), %bb.8(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $q2 liveins: $lr, $q0, $r0, $r1, $r2, $q2
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr, $noreg
renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2 renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q2
renamable $vpr = MVE_VCMPf32 renamable $q2, renamable $q1, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPf32 renamable $q2, renamable $q1, 12, 1, killed renamable $vpr, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1 renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, renamable $q1
t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
tB %bb.8, 14 /* CC::al */, $noreg tB %bb.8, 14 /* CC::al */, $noreg
bb.8: bb.8:
liveins: $r2, $r12, $q0 liveins: $r2, $r12, $q0
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.9 (align 4): bb.9 (align 4):
Show All 32 Lines - id: 0
alignment: 4 alignment: 4
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: combine_kill_flags ; CHECK-LABEL: name: combine_kill_flags
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q2, $r0, $r1 ; CHECK: liveins: $q2, $r0, $r1
; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK: bb.1 (align 4): ; CHECK: bb.1 (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $q2, $r0 ; CHECK: liveins: $lr, $q0, $q2, $r0
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg
; CHECK: renamable $q2 = MVE_VORR killed renamable $q2, renamable $q1, 0, $noreg, killed renamable $q2 ; CHECK: renamable $q2 = MVE_VORR killed renamable $q2, renamable $q1, 0, $noreg, $noreg, killed renamable $q2
; CHECK: MVE_VPTv4f32 8, renamable $q0, killed renamable $q1, 12, implicit-def $vpr ; CHECK: MVE_VPTv4f32 8, renamable $q0, killed renamable $q1, 12, implicit-def $vpr
; CHECK: renamable $q0 = MVE_VORR killed renamable $q0, killed renamable $q0, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = MVE_VORR killed renamable $q0, killed renamable $q0, 1, killed renamable $vpr, $noreg, killed renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 4): ; CHECK: bb.3 (align 4):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
bb.0: bb.0:
successors: %bb.6(0x80000000) successors: %bb.6(0x80000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.6 (align 4): bb.6 (align 4):
successors: %bb.6(0x7c000000), %bb.8(0x04000000) successors: %bb.6(0x7c000000), %bb.8(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $q2 liveins: $lr, $q0, $r0, $r1, $r2, $q2
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
renamable $vpr = MVE_VCMPf32 renamable $q0, renamable $q1, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPf32 renamable $q0, renamable $q1, 12, 1, killed renamable $vpr, $noreg
renamable $q2 = MVE_VORR renamable $q2, killed renamable $q1, 0, $noreg, killed renamable $q2 renamable $q2 = MVE_VORR renamable $q2, killed renamable $q1, 0, $noreg, $noreg, killed renamable $q2
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VORR renamable $q0, renamable $q0, 1, renamable $vpr, killed renamable $q0 renamable $q0 = MVE_VORR renamable $q0, renamable $q0, 1, renamable $vpr, $noreg, killed renamable $q0
t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
tB %bb.8, 14 /* CC::al */, $noreg tB %bb.8, 14 /* CC::al */, $noreg
bb.8: bb.8:
liveins: $r2, $r12, $q0 liveins: $r2, $r12, $q0
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.9 (align 4): bb.9 (align 4):
Show All 32 Lines - id: 0
alignment: 4 alignment: 4
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: no_combination_diff_reg_value ; CHECK-LABEL: name: no_combination_diff_reg_value
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $r0, $r1 ; CHECK: liveins: $r0, $r1
; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK: bb.1 (align 4): ; CHECK: bb.1 (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0 ; CHECK: liveins: $lr, $q0, $r0
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg
; CHECK: renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 0, $noreg, killed renamable $q1 ; CHECK: renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 0, $noreg, $noreg, killed renamable $q1
; CHECK: renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 0, killed $noreg ; CHECK: renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 0, killed $noreg, $noreg
; CHECK: renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q0 ; CHECK: renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, $noreg, killed renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 4): ; CHECK: bb.3 (align 4):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
bb.0: bb.0:
successors: %bb.6(0x80000000) successors: %bb.6(0x80000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.6 (align 4): bb.6 (align 4):
successors: %bb.6(0x7c000000), %bb.8(0x04000000) successors: %bb.6(0x7c000000), %bb.8(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2 liveins: $lr, $q0, $r0, $r1, $r2
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1 renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, renamable $q1
renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr, $noreg
renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q0 renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, $noreg, killed renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VORR killed renamable $q1, renamable $q1, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = MVE_VORR killed renamable $q1, renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q0
t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
tB %bb.8, 14 /* CC::al */, $noreg tB %bb.8, 14 /* CC::al */, $noreg
bb.8: bb.8:
liveins: $r2, $r12, $q0 liveins: $r2, $r12, $q0
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.9 (align 4): bb.9 (align 4):
Show All 32 Lines - id: 0
alignment: 4 alignment: 4
isTargetSpecific: false isTargetSpecific: false
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
; CHECK-LABEL: name: no_combination_vcmp_already_merged ; CHECK-LABEL: name: no_combination_vcmp_already_merged
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q2, $r0, $r1 ; CHECK: liveins: $q2, $r0, $r1
; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK: bb.1 (align 4): ; CHECK: bb.1 (align 4):
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $q2, $r0 ; CHECK: liveins: $lr, $q0, $q2, $r0
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg
; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr ; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2 ; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q2
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, killed renamable $q1 ; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, $noreg, killed renamable $q1
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.3 (align 4): ; CHECK: bb.3 (align 4):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
bb.0: bb.0:
successors: %bb.6(0x80000000) successors: %bb.6(0x80000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.6 (align 4): bb.6 (align 4):
successors: %bb.6(0x7c000000), %bb.8(0x04000000) successors: %bb.6(0x7c000000), %bb.8(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $q2 liveins: $lr, $q0, $r0, $r1, $r2, $q2
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr, $noreg
renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2 renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q2
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1 renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, renamable $q1
t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
tB %bb.8, 14 /* CC::al */, $noreg tB %bb.8, 14 /* CC::al */, $noreg
bb.8: bb.8:
liveins: $r2, $r12, $q0 liveins: $r2, $r12, $q0
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.9 (align 4): bb.9 (align 4):
CONSTPOOL_ENTRY 0, %const.0, 4 CONSTPOOL_ENTRY 0, %const.0, 4
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r12 ; CHECK: dead $lr = t2DLS renamable $r12
; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q1, $r0, $r1, $r2, $r3 ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0, $q1, $r2 ; CHECK: liveins: $q0, $q1, $r2
; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r3 = tMOVr killed $r12, 14, $noreg $r3 = tMOVr killed $r12, 14, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q1, $r0, $r1, $r2, $r3 liveins: $q1, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
$q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q0
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
$lr = tMOVr $r3, 14, $noreg $lr = tMOVr $r3, 14, $noreg
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0, $q1, $r2 liveins: $q0, $q1, $r2
renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14, $noreg renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14, $noreg
renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir

Show First 20 Lines • Show All 121 Lines • ▼ Show 20 Linesbody: |
; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.bb9: ; CHECK: bb.2.bb9:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r3
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv24, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
; CHECK: MVE_VPTv4i32r 8, renamable $q0, $zr, 1, implicit-def $vpr ; CHECK: MVE_VPTv4i32r 8, renamable $q0, $zr, 1, implicit-def $vpr
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1, align 4) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.bb27: ; CHECK: bb.3.bb27:
; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.bb: bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $lr liveins: $r0, $r1, $r2, $r3, $lr
Show All 22 Lines bb.1.bb3:
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.bb9: bb.2.bb9:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0) renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0)
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load (s128) from %ir.lsr.iv24, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $vpr = MVE_VCMPi32r renamable $q0, $zr, 1, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi32r renamable $q0, $zr, 1, 1, killed renamable $vpr, $noreg
renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1, align 4) renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1, align 4) MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r3, 14, $noreg $r0 = tMOVr $r3, 14, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.bb27: bb.3.bb27:
$sp = tADDspi $sp, 1, 14, $noreg $sp = tADDspi $sp, 1, 14, $noreg
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Linesbody: |
; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2.bb9: ; CHECK: bb.2.bb9:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r3
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv24, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1, align 4) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1, align 4) ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.bb27: ; CHECK: bb.3.bb27:
; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.bb: bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $lr liveins: $r0, $r1, $r2, $r3, $lr
Show All 22 Lines bb.1.bb3:
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.bb9: bb.2.bb9:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0) renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0)
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv24, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1, align 4) renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1, align 4) MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r3, 14, $noreg $r0 = tMOVr $r3, 14, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.bb27: bb.3.bb27:
$sp = tADDspi $sp, 1, 14, $noreg $sp = tADDspi $sp, 1, 14, $noreg
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
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; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.bb9: ; CHECK: bb.2.bb9:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg
; CHECK: VSTR_P0_off renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) ; CHECK: VSTR_P0_off renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg
; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.bb27: ; CHECK: bb.3.bb27:
; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.bb: bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $lr liveins: $r0, $r1, $r2, $r3, $lr
Show All 22 Lines bb.1.bb3:
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.bb9: bb.2.bb9:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0) renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0)
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg
renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg
VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0) VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg :: (store (s32) into %stack.0)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r3, 14, $noreg $r0 = tMOVr $r3, 14, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.bb27: bb.3.bb27:
$sp = tADDspi $sp, 1, 14, $noreg $sp = tADDspi $sp, 1, 14, $noreg
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
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; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.bb9: ; CHECK: bb.2.bb9:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg
; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr, $noreg
; CHECK: $vpr = VMSR_P0 $r3, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg
; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.bb27: ; CHECK: bb.3.bb27:
; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.bb: bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $lr liveins: $r0, $r1, $r2, $r3, $lr
Show All 22 Lines bb.1.bb3:
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.bb9: bb.2.bb9:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0) renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0)
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg
renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg
$vpr = VMSR_P0 $r3, 14, $noreg $vpr = VMSR_P0 $r3, 14, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r3, 14, $noreg $r0 = tMOVr $r3, 14, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.bb27: bb.3.bb27:
$sp = tADDspi $sp, 1, 14, $noreg $sp = tADDspi $sp, 1, 14, $noreg
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
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; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.bb9: ; CHECK: bb.2.bb9:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg
; CHECK: dead renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr ; CHECK: dead renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg
; CHECK: $r3 = VMRS_P0 $vpr, 14 /* CC::al */, $noreg ; CHECK: $r3 = VMRS_P0 $vpr, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg
; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.bb27: ; CHECK: bb.3.bb27:
; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg ; CHECK: $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.bb: bb.0.bb:
successors: %bb.3(0x30000000), %bb.1(0x50000000) successors: %bb.3(0x30000000), %bb.1(0x50000000)
liveins: $r0, $r1, $r2, $r3, $lr liveins: $r0, $r1, $r2, $r3, $lr
Show All 22 Lines bb.1.bb3:
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.bb9: bb.2.bb9:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0) renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load (s32) from %stack.0)
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg
renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr, $noreg
$r3 = VMRS_P0 $vpr, 14, $noreg $r3 = VMRS_P0 $vpr, 14, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
$r0 = tMOVr $r3, 14, $noreg $r0 = tMOVr $r3, 14, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.bb27: bb.3.bb27:
$sp = tADDspi $sp, 1, 14, $noreg $sp = tADDspi $sp, 1, 14, $noreg
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Linesbody: |
; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
Show All 14 Lines bb.1.vector.ph:
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
renamable $r3, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14, $noreg
renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1719, align 4) renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Linesbody: |
; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
Show All 14 Lines bb.1.vector.ph:
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
renamable $r3 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg renamable $r3 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1719, align 4) renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Linesbody: |
; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv13, align 4) ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store (s128) into %ir.lsr.iv1719, align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r7, $lr
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
Show All 14 Lines bb.1.vector.ph:
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv13, align 4)
renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1416, align 4)
renamable $r3 = t2SUBri12 killed renamable $r3, 4, 14, $noreg renamable $r3 = t2SUBri12 killed renamable $r3, 4, 14, $noreg
renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1719, align 4) renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1719, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r7, def $pc tPOP_RET 14, $noreg, def $r7, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 8, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 8, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q1
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv19, align 1) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv19, align 1)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv2022, align 1) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv2022, align 1)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0, $q1, $r3 ; CHECK: liveins: $q0, $q1, $r3
; CHECK: renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: renamable $r0 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg ; CHECK: renamable $r0 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
; CHECK: bb.4 (align 16): ; CHECK: bb.4 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
Show All 16 Lines bb.1.vector.ph:
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg
renamable $r3 = t2BICri killed renamable $r3, 7, 14, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 7, 14, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 8, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 8, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14, $noreg, $noreg
renamable $r3 = tLEApcrel %const.0, 14, $noreg renamable $r3 = tLEApcrel %const.0, 14, $noreg
renamable $r12 = t2LSRri killed renamable $r12, 3, 14, $noreg, $noreg renamable $r12 = t2LSRri killed renamable $r12, 3, 14, $noreg, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14, $noreg, $noreg renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3 liveins: $lr, $q0, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
$q1 = MVE_VORR killed $q0, $q0, 0, $noreg, undef $q1 $q1 = MVE_VORR killed $q0, $q0, 0, $noreg, $noreg, undef $q1
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv19, align 1) renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv19, align 1)
renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv2022, align 1) renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv2022, align 1)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14, $noreg
renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0, $q1, $r3 liveins: $q0, $q1, $r3
renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg
$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr
renamable $r0 = tSXTH killed renamable $r0, 14, $noreg renamable $r0 = tSXTH killed renamable $r0, 14, $noreg
tBX_RET 14, $noreg, implicit killed $r0 tBX_RET 14, $noreg, implicit killed $r0
bb.4 (align 16): bb.4 (align 16):
CONSTPOOL_ENTRY 0, %const.0, 16 CONSTPOOL_ENTRY 0, %const.0, 16
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector_spill_in_loop.mir

Show All 23 Linesbody: |
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 ; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_16 renamable $r3 ; CHECK: $lr = MVE_DLSTP_16 renamable $r3
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r10, $r11, $r12 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r10, $r11, $r12
; CHECK: renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, $noreg ; CHECK: renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, $noreg, $noreg
; CHECK: renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 0, $noreg ; CHECK: renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 0, $noreg, $noreg
; CHECK: renamable $q5 = MVE_VSHR_immu16 killed renamable $q3, 11, 0, $noreg, undef renamable $q5 ; CHECK: renamable $q5 = MVE_VSHR_immu16 killed renamable $q3, 11, 0, $noreg, $noreg, undef renamable $q5
; CHECK: MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg :: (store (s128) into %stack.0, align 8) ; CHECK: MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg, $noreg :: (store (s128) into %stack.0, align 8)
; CHECK: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg :: (load (s128) from %stack.0, align 8) ; CHECK: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
; CHECK: dead renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 0, killed $noreg ; CHECK: dead renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 0, killed $noreg, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2:
; CHECK: successors: %bb.3(0x04000000), %bb.0(0x7c000000)
; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
; CHECK: renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.3:
; CHECK: $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg
; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15
; CHECK: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
bb.0: bb.0:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
$r6 = tMOVr $r2, 14 /* CC::al */, $noreg $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
$r0 = tMOVr $r12, 14 /* CC::al */, $noreg $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
$r9 = tMOVr $r3, 14 /* CC::al */, $noreg $r9 = tMOVr $r3, 14 /* CC::al */, $noreg
renamable $lr = t2DoLoopStartTP renamable $r1, renamable $r3 renamable $lr = t2DoLoopStartTP renamable $r1, renamable $r3
bb.1: bb.1:
successors: %bb.1(0x7c000000), %bb.2(0x04000000) successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $q5 = MVE_VSHR_immu16 renamable $q3, 11, 1, renamable $vpr, undef renamable $q5 renamable $q5 = MVE_VSHR_immu16 renamable $q3, 11, 1, renamable $vpr, $noreg, undef renamable $q5
renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg
MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg :: (store (s128) into %stack.0, align 8) MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg, $noreg :: (store (s128) into %stack.0, align 8)
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg :: (load (s128) from %stack.0, align 8) renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
MVE_VPST 1, implicit $vpr MVE_VPST 1, implicit $vpr
renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1, implicit-def dead $cpsr renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14 /* CC::al */, $noreg tB %bb.2, 14 /* CC::al */, $noreg
bb.2: bb.2:
successors: %bb.3(0x04000000), %bb.0(0x7c000000) successors: %bb.3(0x04000000), %bb.0(0x7c000000)
liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg
Show All 25 Linesbody: |
; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 ; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: $r9 = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $r9 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS renamable $r1 ; CHECK: $lr = t2DLS renamable $r1
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr ; CHECK: renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
; CHECK: renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr ; CHECK: renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr, $noreg
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $q5 = MVE_VSHR_immu16 killed renamable $q3, 11, 1, renamable $vpr, undef renamable $q5 ; CHECK: renamable $q5 = MVE_VSHR_immu16 killed renamable $q3, 11, 1, renamable $vpr, $noreg, undef renamable $q5
; CHECK: renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg
; CHECK: MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg :: (store (s128) into %stack.0, align 8) ; CHECK: MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg, $noreg :: (store (s128) into %stack.0, align 8)
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg :: (load (s128) from %stack.0, align 8) ; CHECK: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
; CHECK: MVE_VPST 1, implicit $vpr ; CHECK: MVE_VPST 1, implicit $vpr
; CHECK: dead renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr ; CHECK: dead renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2:
; CHECK: successors: %bb.3(0x04000000), %bb.0(0x7c000000)
; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
; CHECK: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
; CHECK: renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.3:
; CHECK: $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg
; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15
; CHECK: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
bb.0: bb.0:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
$r6 = tMOVr $r2, 14 /* CC::al */, $noreg $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
$r0 = tMOVr $r12, 14 /* CC::al */, $noreg $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
$r9 = tMOVr $r3, 14 /* CC::al */, $noreg $r9 = tMOVr $r3, 14 /* CC::al */, $noreg
renamable $lr = t2DoLoopStartTP renamable $r1, renamable $r3 renamable $lr = t2DoLoopStartTP renamable $r1, renamable $r3
bb.1: bb.1:
successors: %bb.1(0x7c000000), %bb.2(0x04000000) successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $q5 = MVE_VSHR_immu16 renamable $q3, 11, 1, renamable $vpr, undef renamable $q5 renamable $q5 = MVE_VSHR_immu16 renamable $q3, 11, 1, renamable $vpr, $noreg, undef renamable $q5
renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg
MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg :: (store (s128) into %stack.0, align 8) MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg, $noreg :: (store (s128) into %stack.0, align 8)
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg :: (load (s128) from %stack.0, align 8) renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
MVE_VPST 1, implicit $vpr MVE_VPST 1, implicit $vpr
renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1, implicit-def dead $cpsr renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14 /* CC::al */, $noreg tB %bb.2, 14 /* CC::al */, $noreg
bb.2: bb.2:
successors: %bb.3(0x04000000), %bb.0(0x7c000000) successors: %bb.3(0x04000000), %bb.0(0x7c000000)
liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg :: (load (s128) from %stack.0, align 8) renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg
renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg
renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg
tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
tBcc %bb.0, 1 /* CC::ne */, killed $cpsr tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
bb.3: bb.3:
$sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg
$sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15 $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15
$sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
$sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
; CHECK: renamable $r12 = t2LDRi12 $sp, 44, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.6, align 8) ; CHECK: renamable $r12 = t2LDRi12 $sp, 44, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.6, align 8)
; CHECK: $lr = MVE_WLSTP_32 killed renamable $r12, %bb.3 ; CHECK: $lr = MVE_WLSTP_32 killed renamable $r12, %bb.3
; CHECK: bb.1.for.body.lr.ph: ; CHECK: bb.1.for.body.lr.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: $r7, $r6 = t2LDRDi8 $sp, 36, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.4, align 8), (load (s32) from %fixed-stack.5) ; CHECK: $r7, $r6 = t2LDRDi8 $sp, 36, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.4, align 8), (load (s32) from %fixed-stack.5)
; CHECK: $r5, $r4 = t2LDRDi8 $sp, 20, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8), (load (s32) from %fixed-stack.1) ; CHECK: $r5, $r4 = t2LDRDi8 $sp, 20, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8), (load (s32) from %fixed-stack.1)
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r7, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r7, 0, $noreg, $noreg, undef renamable $q1
; CHECK: bb.2.for.body: ; CHECK: bb.2.for.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5 ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg :: (load (s128) from %ir.input_2_cast, align 4) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s128) from %ir.input_2_cast, align 4)
; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg :: (load (s128) from %ir.input_1_cast, align 4) ; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s128) from %ir.input_1_cast, align 4)
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3 ; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3
; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r4, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r4, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $r5 = MVE_VSTRWU32_post killed renamable $q2, killed renamable $r5, 4, 0, killed $noreg :: (store (s128) into %ir.output_cast, align 4) ; CHECK: renamable $r5 = MVE_VSTRWU32_post killed renamable $q2, killed renamable $r5, 4, 0, killed $noreg, $noreg :: (store (s128) into %ir.output_cast, align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x40000000), %bb.3(0x40000000) successors: %bb.1(0x40000000), %bb.3(0x40000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $lr
Show All 11 Lines bb.0.entry:
tB %bb.1, 14, $noreg tB %bb.1, 14, $noreg
bb.1.for.body.lr.ph: bb.1.for.body.lr.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r12 liveins: $lr, $r0, $r1, $r2, $r3, $r12
$r7, $r6 = t2LDRDi8 $sp, 36, 14, $noreg :: (load (s32) from %fixed-stack.2, align 8), (load (s32) from %fixed-stack.1) $r7, $r6 = t2LDRDi8 $sp, 36, 14, $noreg :: (load (s32) from %fixed-stack.2, align 8), (load (s32) from %fixed-stack.1)
$r5, $r4 = t2LDRDi8 $sp, 20, 14, $noreg :: (load (s32) from %fixed-stack.6, align 8), (load (s32) from %fixed-stack.5) $r5, $r4 = t2LDRDi8 $sp, 20, 14, $noreg :: (load (s32) from %fixed-stack.6, align 8), (load (s32) from %fixed-stack.5)
renamable $q0 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q0
renamable $q1 = MVE_VDUP32 killed renamable $r7, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VDUP32 killed renamable $r7, 0, $noreg, $noreg, undef renamable $q1
bb.2.for.body: bb.2.for.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r12 liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r12
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load (s128) from %ir.input_2_cast, align 4) renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_2_cast, align 4)
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load (s128) from %ir.input_1_cast, align 4) renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_1_cast, align 4)
renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2
renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3 renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, $noreg, undef renamable $q2
renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r4, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r4, 0, $noreg, $noreg, undef renamable $q2
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2 renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2
renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, renamable $vpr, undef renamable $q2 renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q2
renamable $r5 = MVE_VSTRWU32_post killed renamable $q2, killed renamable $r5, 4, 1, killed renamable $vpr :: (store (s128) into %ir.output_cast, align 4) renamable $r5 = MVE_VSTRWU32_post killed renamable $q2, killed renamable $r5, 4, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.output_cast, align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
$r0, dead $cpsr = tMOVi8 0, 14, $noreg $r0, dead $cpsr = tMOVi8 0, 14, $noreg
tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0 tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir

Show First 20 Lines • Show All 146 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r4 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.5) ; CHECK: renamable $r4 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.5)
; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = MVE_WLSTP_32 killed renamable $r4, %bb.3 ; CHECK: $lr = MVE_WLSTP_32 killed renamable $r4, %bb.3
; CHECK: bb.1.for.body.lr.ph: ; CHECK: bb.1.for.body.lr.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
; CHECK: $r6, $r12 = t2LDRDi8 $sp, 28, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.3), (load (s32) from %fixed-stack.4, align 8) ; CHECK: $r6, $r12 = t2LDRDi8 $sp, 28, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.3), (load (s32) from %fixed-stack.4, align 8)
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.for.body: ; CHECK: bb.2.for.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r5, $r12 ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r5, $r12
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg :: (load (s128) from %ir.input_2_cast, align 4) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg, $noreg :: (load (s128) from %ir.input_2_cast, align 4)
; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg :: (load (s128) from %ir.input_1_cast, align 4) ; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg, $noreg :: (load (s128) from %ir.input_1_cast, align 4)
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3 ; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3
; CHECK: renamable $q3 = MVE_VMLAS_qr_u32 killed renamable $q3, killed renamable $q2, renamable $r5, 0, $noreg ; CHECK: renamable $q3 = MVE_VMLAS_qr_u32 killed renamable $q3, killed renamable $q2, renamable $r5, 0, $noreg, $noreg
; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q3, renamable $q1, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q3, renamable $q1, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 0, $noreg, undef renamable $q3 ; CHECK: renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 0, $noreg, $noreg, undef renamable $q3
; CHECK: renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 0, killed $noreg ; CHECK: renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 0, killed $noreg, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: liveins: $r12 ; CHECK: liveins: $r12
; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $pc, implicit killed $r0 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x40000000), %bb.3(0x40000000) successors: %bb.1(0x40000000), %bb.3(0x40000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr
Show All 12 Lines bb.0.entry:
tB %bb.1, 14 /* CC::al */, $noreg tB %bb.1, 14 /* CC::al */, $noreg
bb.1.for.body.lr.ph: bb.1.for.body.lr.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r4 liveins: $lr, $r0, $r1, $r2, $r3, $r4
renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.5, align 8) renamable $r5 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.5, align 8)
$r6, $r12 = t2LDRDi8 $sp, 28, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.2), (load (s32) from %fixed-stack.1, align 8) $r6, $r12 = t2LDRDi8 $sp, 28, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.2), (load (s32) from %fixed-stack.1, align 8)
renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, $noreg, undef renamable $q0
renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, $noreg, undef renamable $q1
renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
bb.2.for.body: bb.2.for.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r12 liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r12
renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r4, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load (s128) from %ir.input_2_cast, align 4) renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_2_cast, align 4)
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load (s128) from %ir.input_1_cast, align 4) renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr, $noreg :: (load (s128) from %ir.input_1_cast, align 4)
renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, $noreg, undef renamable $q2
renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3 renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, $noreg, undef renamable $q3
renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14 /* CC::al */, $noreg renamable $r4, dead $cpsr = tSUBi8 killed renamable $r4, 4, 14 /* CC::al */, $noreg
renamable $q3 = MVE_VMLAS_qr_u32 killed renamable $q3, killed renamable $q2, renamable $r5, 0, $noreg renamable $q3 = MVE_VMLAS_qr_u32 killed renamable $q3, killed renamable $q2, renamable $r5, 0, $noreg, $noreg
MVE_VPST 2, implicit $vpr MVE_VPST 2, implicit $vpr
renamable $q2 = MVE_VMAXu32 killed renamable $q3, renamable $q1, 1, renamable $vpr, undef renamable $q2 renamable $q2 = MVE_VMAXu32 killed renamable $q3, renamable $q1, 1, renamable $vpr, $noreg, undef renamable $q2
renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 1, renamable $vpr, undef renamable $q3 renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q3
renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
liveins: $r12 liveins: $r12
$r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $pc, implicit killed $r0 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir

Show First 20 Lines • Show All 219 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r2, $r3
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg
; CHECK: MVE_VPTv4s32r 4, renamable $q1, renamable $r2, 11, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 4, renamable $q1, renamable $r2, 11, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3 liveins: $lr, $q0, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr
renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg
renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
... ...
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr ; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr, $noreg
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
; CHECK: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; ;
; Tests that secondary VCTPs are refused when their operand's reaching definition is not the same as the main ; Tests that secondary VCTPs are refused when their operand's reaching definition is not the same as the main
; VCTP's. ; VCTP's.
; ;
Show All 9 Lines bb.0.entry:
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3 liveins: $lr, $q0, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr, $noreg
renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr
renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg
renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
... ...
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
; CHECK: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; ;
; Tests that secondary VCTPs are refused when their operand is not the same register as the main VCTP's. ; Tests that secondary VCTPs are refused when their operand is not the same register as the main VCTP's.
; ;
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3 liveins: $lr, $q0, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr
renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
... ...
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r2, $r3
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg
; CHECK: MVE_VPTv4s32r 12, renamable $q1, renamable $r2, 10, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 12, renamable $q1, renamable $r2, 10, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; ;
; Test including a else-predicated VCTP. ; Test including a else-predicated VCTP.
; ;
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3 liveins: $lr, $q0, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
MVE_VPTv4s32r 14, renamable $q1, renamable $r2, 10, implicit-def $vpr MVE_VPTv4s32r 14, renamable $q1, renamable $r2, 10, implicit-def $vpr
renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VCTP32 renamable $r1, 2, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r1, 2, killed renamable $vpr, $noreg
renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
... ...
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r2, $r3
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg
; CHECK: MVE_VPTv4s32r 4, renamable $q0, renamable $r2, 11, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 4, renamable $q0, renamable $r2, 11, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3 liveins: $lr, $q0, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 11, implicit-def $vpr MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 11, implicit-def $vpr
renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg
renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
... ...
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r1, $r2 ; CHECK: liveins: $r1, $r2
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r2, $r3
; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr
; CHECK: dead renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r3, 12, 1, killed renamable $vpr ; CHECK: dead renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r3, 12, 1, killed renamable $vpr, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3 liveins: $lr, $q0, $r0, $r1, $r2, $r3
MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr
renamable $vpr = MVE_VCMPs32r killed renamable $q0, renamable $r3, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r killed renamable $q0, renamable $r3, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
... ...
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg ; CHECK: dead renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2
; CHECK: MVE_VPTv4s32r 2, killed renamable $q0, renamable $r2, 2, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 2, killed renamable $q0, renamable $r2, 2, implicit-def $vpr
; CHECK: renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr ; CHECK: renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr, $noreg
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed $vpr, $noreg
; CHECK: MVE_VSTRWU32 renamable $q0, renamable $r0, 0, 1, killed $vpr ; CHECK: MVE_VSTRWU32 renamable $q0, renamable $r0, 0, 1, killed $vpr, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; ;
; This shouldn't be tail-predicated because the VLDR isn't predicated on the VCTP. ; This shouldn't be tail-predicated because the VLDR isn't predicated on the VCTP.
; ;
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3 liveins: $lr, $q0, $r0, $r1, $r2, $r3
MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 2, implicit-def $vpr MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 2, implicit-def $vpr
renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr, $noreg
renamable $vpr = MVE_VCTP32 renamable $r1, 1, $vpr renamable $vpr = MVE_VCTP32 renamable $r1, 1, $vpr, $noreg
MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, $vpr MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, $vpr, $noreg
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
... ...
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 12 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 12
; CHECK: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr ; CHECK: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg
; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r0 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r0
; CHECK: bb.2 (align 4): ; CHECK: bb.2 (align 4):
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r1 ; CHECK: liveins: $lr, $q0, $r1
; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr :: (store (s128), align 4) ; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg ; CHECK: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0
bb.0: bb.0:
successors: %bb.1(0x50000000), %bb.3(0x30000000) successors: %bb.1(0x50000000), %bb.3(0x30000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
$sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
frame-setup CFI_INSTRUCTION def_cfa_offset 12 frame-setup CFI_INSTRUCTION def_cfa_offset 12
tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
tBcc %bb.3, 11 /* CC::lt */, killed $cpsr tBcc %bb.3, 11 /* CC::lt */, killed $cpsr
bb.1: bb.1:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr
renamable $r3, dead $cpsr = tADDi3 renamable $r0, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r0, 3, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg
$vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg
VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r0 renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r0
bb.2 (align 4): bb.2 (align 4):
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1 liveins: $lr, $q0, $r0, $r1
renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $vpr = MVE_VCTP32 renamable $r0, 1, killed renamable $vpr renamable $vpr = MVE_VCTP32 renamable $r0, 1, killed renamable $vpr, $noreg
renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr :: (store (s128), align 4) renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3: bb.3:
$sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0
... ...
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load (s128) from constant-pool, align 8) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)
; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
; CHECK: bb.2 (align 4): ; CHECK: bb.2 (align 4):
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1 ; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1
; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr
; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128), align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.4 (align 8): ; CHECK: bb.4 (align 8):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0: bb.0:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
bb.1: bb.1:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg
renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load (s128) from constant-pool, align 8) renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2
renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r2 renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r2
bb.2 (align 4): bb.2 (align 4):
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r1, 11, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r1, 11, 1, killed renamable $vpr, $noreg
renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128), align 4) renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3: bb.3:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.4 (align 8): bb.4 (align 8):
Show All 33 Linesbody: |
; CHECK: t2IT 11, 8, implicit-def $itstate ; CHECK: t2IT 11, 8, implicit-def $itstate
; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load (s128) from constant-pool, align 8) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2
; CHECK: bb.2 (align 4): ; CHECK: bb.2 (align 4):
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 ; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2
; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed $vpr, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128), align 4) ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
; CHECK: bb.4 (align 8): ; CHECK: bb.4 (align 8):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0: bb.0:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
t2IT 11, 8, implicit-def $itstate t2IT 11, 8, implicit-def $itstate
frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
bb.1: bb.1:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg
renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load (s128) from constant-pool, align 8) renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)
renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2
renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r2 renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r2
bb.2 (align 4): bb.2 (align 4):
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2
MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr
renamable $vpr = MVE_VCTP32 renamable $r2, 1, $vpr renamable $vpr = MVE_VCTP32 renamable $r2, 1, $vpr, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128), align 4) renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14 /* CC::al */, $noreg tB %bb.3, 14 /* CC::al */, $noreg
bb.3: bb.3:
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.4 (align 8): bb.4 (align 8):
CONSTPOOL_ENTRY 0, %const.0, 16 CONSTPOOL_ENTRY 0, %const.0, 16
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/wls-search-pred.mir

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Linesbody: |
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0
; CHECK: t2CMPri [[COPY]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: t2CMPri [[COPY]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.5, 0 /* CC::eq */, $cpsr ; CHECK: t2Bcc %bb.5, 0 /* CC::eq */, $cpsr
; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1.prehead: ; CHECK: bb.1.prehead:
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
; CHECK: [[MVE_VMOVimmi32_:%[0-9]+]]:mqpr = MVE_VMOVimmi32 0, 0, $noreg, [[DEF]] ; CHECK: [[MVE_VMOVimmi32_:%[0-9]+]]:mqpr = MVE_VMOVimmi32 0, 0, $noreg, $noreg, [[DEF]]
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2BICri:%[0-9]+]]:rgpr = t2BICri killed [[t2ADDri]], 16, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2BICri:%[0-9]+]]:rgpr = t2BICri killed [[t2ADDri]], 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2LSRri:%[0-9]+]]:gprlr = t2LSRri killed [[t2BICri]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2LSRri:%[0-9]+]]:gprlr = t2LSRri killed [[t2BICri]], 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2WhileLoopStartTP:%[0-9]+]]:gprlr = t2WhileLoopStartTP killed [[t2LSRri]], [[COPY]], %bb.3, implicit-def $cpsr ; CHECK: [[t2WhileLoopStartTP:%[0-9]+]]:gprlr = t2WhileLoopStartTP killed [[t2LSRri]], [[COPY]], %bb.3, implicit-def $cpsr
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %11, %bb.2 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %11, %bb.2
; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopStartTP]], %bb.1, %13, %bb.2 ; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopStartTP]], %bb.1, %13, %bb.2
; CHECK: [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %15, %bb.2 ; CHECK: [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %15, %bb.2
; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg, $noreg
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VMOVimmi32_]], [[PHI]], 16, 1, [[MVE_VCTP8_]] ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VMOVimmi32_]], [[PHI]], 16, 1, [[MVE_VCTP8_]], [[PHI1]]
; CHECK: [[t2LoopEndDec:%[0-9]+]]:gprlr = t2LoopEndDec [[PHI1]], %bb.2, implicit-def $cpsr ; CHECK: [[t2LoopEndDec:%[0-9]+]]:gprlr = t2LoopEndDec [[PHI1]], %bb.2, implicit-def $cpsr
; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.3.prehead: ; CHECK: bb.3.prehead:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: [[t2DoLoopStart:%[0-9]+]]:gprlr = t2DoLoopStart [[COPY]] ; CHECK: [[t2DoLoopStart:%[0-9]+]]:gprlr = t2DoLoopStart [[COPY]]
; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.4.for.body: ; CHECK: bb.4.for.body:
; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000) ; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000)
Show All 17 Lines bb.0.entry:
%10:gprlr = t2WhileLoopSetup %9 %10:gprlr = t2WhileLoopSetup %9
t2WhileLoopStart %10, %bb.3, implicit-def dead $cpsr t2WhileLoopStart %10, %bb.3, implicit-def dead $cpsr
t2B %bb.1, 14 /* CC::al */, $noreg t2B %bb.1, 14 /* CC::al */, $noreg
bb.1.prehead: bb.1.prehead:
successors: %bb.5(0x40000000), %bb.4(0x40000000) successors: %bb.5(0x40000000), %bb.4(0x40000000)
%12:mqpr = IMPLICIT_DEF %12:mqpr = IMPLICIT_DEF
%11:mqpr = MVE_VMOVimmi32 0, 0, $noreg, %12 %11:mqpr = MVE_VMOVimmi32 0, 0, $noreg, $noreg, %12
%17:rgpr = t2ADDri %9, 15, 14 /* CC::al */, $noreg, $noreg %17:rgpr = t2ADDri %9, 15, 14 /* CC::al */, $noreg, $noreg
%18:rgpr = t2BICri killed %17, 16, 14 /* CC::al */, $noreg, $noreg %18:rgpr = t2BICri killed %17, 16, 14 /* CC::al */, $noreg, $noreg
%19:gprlr = t2LSRri killed %18, 4, 14 /* CC::al */, $noreg, $noreg %19:gprlr = t2LSRri killed %18, 4, 14 /* CC::al */, $noreg, $noreg
%20:gprlr = t2WhileLoopSetup killed %19 %20:gprlr = t2WhileLoopSetup killed %19
t2WhileLoopStart %20, %bb.5, implicit-def $cpsr t2WhileLoopStart %20, %bb.5, implicit-def $cpsr
bb.4: bb.4:
successors: %bb.4(0x40000000), %bb.5(0x40000000) successors: %bb.4(0x40000000), %bb.5(0x40000000)
%21:rgpr = PHI %7, %bb.1, %22, %bb.4 %21:rgpr = PHI %7, %bb.1, %22, %bb.4
%23:gprlr = PHI %20, %bb.1, %24, %bb.4 %23:gprlr = PHI %20, %bb.1, %24, %bb.4
%25:rgpr = PHI %9, %bb.1, %26, %bb.4 %25:rgpr = PHI %9, %bb.1, %26, %bb.4
%27:vccr = MVE_VCTP8 %25, 0, $noreg %27:vccr = MVE_VCTP8 %25, 0, $noreg, $noreg
%26:rgpr = t2SUBri %25, 16, 14 /* CC::al */, $noreg, $noreg %26:rgpr = t2SUBri %25, 16, 14 /* CC::al */, $noreg, $noreg
%22:rgpr = MVE_VSTRBU8_post %11, %21, 16, 1, %27 %22:rgpr = MVE_VSTRBU8_post %11, %21, 16, 1, %27, $noreg
%24:gprlr = t2LoopDec %23, 1 %24:gprlr = t2LoopDec %23, 1
t2LoopEnd %24, %bb.4, implicit-def $cpsr t2LoopEnd %24, %bb.4, implicit-def $cpsr
t2B %bb.5, 14 /* CC::al */, $noreg t2B %bb.5, 14 /* CC::al */, $noreg
bb.5.prehead: bb.5.prehead:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
%0:gpr = COPY %10 %0:gpr = COPY %10
Show All 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir

Show First 20 Lines • Show All 199 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000) ; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r12 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r12
; CHECK: renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg :: (load (s128) from %ir.scevgep45, align 1) ; CHECK: renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep45, align 1)
; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q1 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg :: (load (s128) from %ir.scevgep23, align 1) ; CHECK: renamable $q1 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep23, align 1)
; CHECK: renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2ADDri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2ADDri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 0, killed $noreg :: (store (s128) into %ir.scevgep1, align 1) ; CHECK: MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.scevgep1, align 1)
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.3(0x40000000), %bb.1(0x40000000) successors: %bb.3(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
Show All 14 Lines bb.1.vector.ph:
renamable $r12 = t2MOVi 0, 14, $noreg, $noreg renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.3(0x04000000), %bb.2(0x7c000000) successors: %bb.3(0x04000000), %bb.2(0x7c000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r12 liveins: $lr, $r0, $r1, $r2, $r3, $r12
renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14, $noreg, $noreg renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14, $noreg, $noreg
renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 1, renamable $vpr :: (load (s128) from %ir.scevgep45, align 1) renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.scevgep45, align 1)
renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14, $noreg, $noreg renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14, $noreg, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q1 = MVE_VLDRBU8 killed renamable $r4, 0, 1, renamable $vpr :: (load (s128) from %ir.scevgep23, align 1) renamable $q1 = MVE_VLDRBU8 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.scevgep23, align 1)
renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14, $noreg, $noreg renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14, $noreg, $noreg
renamable $r12 = t2ADDri killed renamable $r12, 16, 14, $noreg, $noreg renamable $r12 = t2ADDri killed renamable $r12, 16, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg
renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 1, killed renamable $vpr :: (store (s128) into %ir.scevgep1, align 1) MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.scevgep1, align 1)
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r4, def $pc tPOP_RET 14, $noreg, def $r4, def $pc
... ...
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $lr = MVE_WLSTP_16 killed renamable $r3, %bb.1 ; CHECK: $lr = MVE_WLSTP_16 killed renamable $r3, %bb.1
; CHECK: tB %bb.2, 14 /* CC::al */, $noreg ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.1.vector.body: ; CHECK: bb.1.vector.body:
; CHECK: successors: %bb.2(0x04000000), %bb.1(0x7c000000) ; CHECK: successors: %bb.2(0x04000000), %bb.1(0x7c000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $q0 = MVE_VLDRHU16 renamable $r1, 0, 0, $noreg :: (load (s128) from %ir.lsr.iv57, align 2) ; CHECK: renamable $q0 = MVE_VLDRHU16 renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv57, align 2)
; CHECK: renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 0, $noreg :: (load (s128) from %ir.lsr.iv24, align 2) ; CHECK: renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv24, align 2)
; CHECK: renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VSTRHU16 killed renamable $q0, renamable $r0, 0, 0, killed $noreg :: (store (s128) into %ir.lsr.iv1, align 2) ; CHECK: MVE_VSTRHU16 killed renamable $q0, renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1, align 2)
; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.2(0x40000000), %bb.1(0x40000000) successors: %bb.2(0x40000000), %bb.1(0x40000000)
Show All 10 Lines bb.0.entry:
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 27, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 27, 14, $noreg, $noreg
$lr = t2WhileLoopStartLR renamable $lr, %bb.1, implicit-def dead $cpsr $lr = t2WhileLoopStartLR renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14, $noreg tB %bb.2, 14, $noreg
bb.1.vector.body: bb.1.vector.body:
successors: %bb.2(0x04000000), %bb.1(0x7c000000) successors: %bb.2(0x04000000), %bb.1(0x7c000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $q0 = MVE_VLDRHU16 renamable $r1, 0, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv57, align 2) renamable $q0 = MVE_VLDRHU16 renamable $r1, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv57, align 2)
renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv24, align 2) renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 2)
renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
MVE_VSTRHU16 killed renamable $q0, renamable $r0, 0, 1, killed renamable $vpr :: (store (s128) into %ir.lsr.iv1, align 2) MVE_VSTRHU16 killed renamable $q0, renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 2)
renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg
renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14, $noreg renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14, $noreg
renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14, $noreg tB %bb.2, 14, $noreg
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Linesbody: |
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2WLS killed renamable $lr, %bb.1 ; CHECK: $lr = t2WLS killed renamable $lr, %bb.1
; CHECK: tB %bb.4, 14 /* CC::al */, $noreg ; CHECK: tB %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000) ; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000)
; CHECK: liveins: $lr, $q1, $r0, $r1, $r2 ; CHECK: liveins: $lr, $q1, $r0, $r1, $r2
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0
; CHECK: renamable $vpr = MVE_VCTP32 $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 $r2, 0, $noreg, $noreg
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv24, align 4) ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
; CHECK: renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1, align 4) ; CHECK: renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 1, killed renamable $vpr, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 1, killed renamable $vpr, $noreg, undef renamable $q1
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: liveins: $q0, $q1, $r3 ; CHECK: liveins: $q0, $q1, $r3
; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: bb.4.for.cond.cleanup: ; CHECK: bb.4.for.cond.cleanup:
; CHECK: liveins: $r12 ; CHECK: liveins: $r12
; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.4(0x40000000), %bb.1(0x40000000) successors: %bb.4(0x40000000), %bb.1(0x40000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
Show All 9 Lines bb.0.entry:
renamable $r12 = t2MOVi 0, 14, $noreg, $noreg renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
$lr = t2WhileLoopStartLR renamable $lr, %bb.1, implicit-def dead $cpsr $lr = t2WhileLoopStartLR renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.4, 14, $noreg tB %bb.4, 14, $noreg
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $lr, $r0, $r1, $r2 liveins: $lr, $r0, $r1, $r2
renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
bb.2.vector.body: bb.2.vector.body:
successors: %bb.3(0x04000000), %bb.2(0x7c000000) successors: %bb.3(0x04000000), %bb.2(0x7c000000)
liveins: $lr, $q1, $r0, $r1, $r2 liveins: $lr, $q1, $r0, $r1, $r2
$q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q0
renamable $vpr = MVE_VCTP32 $r2, 0, $noreg renamable $vpr = MVE_VCTP32 $r2, 0, $noreg, $noreg
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv24, align 4) renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1, align 4) renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
$r3 = tMOVr $r2, 14, $noreg $r3 = tMOVr $r2, 14, $noreg
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg
renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14, $noreg
MVE_VPST 8, implicit $vpr MVE_VPST 8, implicit $vpr
renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 1, renamable $vpr, undef renamable $q1 renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q1
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.middle.block: bb.3.middle.block:
successors: %bb.4(0x80000000) successors: %bb.4(0x80000000)
liveins: $q0, $q1, $r3 liveins: $q0, $q1, $r3
renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
bb.4.for.cond.cleanup: bb.4.for.cond.cleanup:
liveins: $r12 liveins: $r12
$r0 = tMOVr killed $r12, 14, $noreg $r0 = tMOVr killed $r12, 14, $noreg
tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Linesbody: |
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 8, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 8, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q1
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv19, align 1) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv19, align 1)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv2022, align 1) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv2022, align 1)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0, $q1, $r3 ; CHECK: liveins: $q0, $q1, $r3
; CHECK: renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr ; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr
; CHECK: renamable $r0 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg ; CHECK: renamable $r0 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
; CHECK: bb.4 (align 16): ; CHECK: bb.4 (align 16):
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr liveins: $r0, $r1, $r2, $lr
Show All 16 Lines bb.1.vector.ph:
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14, $noreg
renamable $r3 = t2BICri killed renamable $r3, 7, 14, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 7, 14, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 8, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 8, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14, $noreg, $noreg renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14, $noreg, $noreg
renamable $r3 = tLEApcrel %const.0, 14, $noreg renamable $r3 = tLEApcrel %const.0, 14, $noreg
renamable $r12 = t2LSRri killed renamable $r12, 2, 14, $noreg, $noreg renamable $r12 = t2LSRri killed renamable $r12, 2, 14, $noreg, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool)
renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14, $noreg, $noreg renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $lr $lr = t2DoLoopStart renamable $lr
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3 liveins: $lr, $q0, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg, $noreg
$q1 = MVE_VORR killed $q0, $q0, 0, $noreg, undef $q1 $q1 = MVE_VORR killed $q0, $q0, 0, $noreg, $noreg, undef $q1
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv19, align 1) renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv19, align 1)
renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv2022, align 1) renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv2022, align 1)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14, $noreg
renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0, $q1, $r3 liveins: $q0, $q1, $r3
renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP16 killed renamable $r3, 0, $noreg, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg, $noreg
$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr
renamable $r0 = tSXTH killed renamable $r0, 14, $noreg renamable $r0 = tSXTH killed renamable $r0, 14, $noreg
tBX_RET 14, $noreg, implicit killed $r0 tBX_RET 14, $noreg, implicit killed $r0
bb.4 (align 16): bb.4 (align 16):
CONSTPOOL_ENTRY 0, %const.0, 16 CONSTPOOL_ENTRY 0, %const.0, 16
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r3 ; CHECK: dead $lr = t2DLS renamable $r3
; CHECK: $r12 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: $r12 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q1, $r0, $r1, $r2, $r3, $r12 ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0, $q1, $r2, $r3 ; CHECK: liveins: $q0, $q1, $r2, $r3
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = MVE_VDUP32 killed renamable $r0, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VDUP32 killed renamable $r0, 0, $noreg, $noreg, undef renamable $q2
; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $vpr = MVE_VCMPu32r killed renamable $q2, killed renamable $r0, 8, 0, $noreg ; CHECK: renamable $vpr = MVE_VCMPu32r killed renamable $q2, killed renamable $r0, 8, 0, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $r3 $lr = t2DoLoopStart renamable $r3
$r12 = tMOVr killed $r3, 14, $noreg $r12 = tMOVr killed $r3, 14, $noreg
$r3 = tMOVr $r2, 14, $noreg $r3 = tMOVr $r2, 14, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q1, $r0, $r1, $r2, $r3, $r12 liveins: $q1, $r0, $r1, $r2, $r3, $r12
renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
$q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q0
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
$lr = tMOVr $r12, 14, $noreg $lr = tMOVr $r12, 14, $noreg
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r12 = nsw t2SUBri killed $r12, 1, 14, $noreg, $noreg renamable $r12 = nsw t2SUBri killed $r12, 1, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0, $q1, $r2, $r3 liveins: $q0, $q1, $r2, $r3
renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 1, 14, $noreg renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 1, 14, $noreg
renamable $q2 = MVE_VDUP32 killed renamable $r0, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VDUP32 killed renamable $r0, 0, $noreg, $noreg, undef renamable $q2
renamable $r0, dead $cpsr = tADDi3 killed renamable $r3, 4, 14, $noreg renamable $r0, dead $cpsr = tADDi3 killed renamable $r3, 4, 14, $noreg
renamable $vpr = MVE_VCMPu32r killed renamable $q2, killed renamable $r0, 8, 0, $noreg renamable $vpr = MVE_VCMPu32r killed renamable $q2, killed renamable $r0, 8, 0, $noreg, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir

Show First 20 Lines • Show All 114 Lines • ▼ Show 20 Linesbody: |
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead $lr = t2DLS renamable $r12 ; CHECK: dead $lr = t2DLS renamable $r12
; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $q1, $r0, $r1, $r2, $r3 ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.middle.block: ; CHECK: bb.3.middle.block:
; CHECK: liveins: $q0, $q1, $r2 ; CHECK: liveins: $q0, $q1, $r2
; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r2, 0, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 4, implicit-def $itstate t2IT 0, 4, implicit-def $itstate
renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
bb.1.vector.ph: bb.1.vector.ph:
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $lr, $r7 liveins: $r0, $r1, $r2, $lr, $r7
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
$lr = t2DoLoopStart renamable $r12 $lr = t2DoLoopStart renamable $r12
$r3 = tMOVr killed $r12, 14, $noreg $r3 = tMOVr killed $r12, 14, $noreg
bb.2.vector.body: bb.2.vector.body:
successors: %bb.2(0x7c000000), %bb.3(0x04000000) successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $q1, $r0, $r1, $r2, $r3 liveins: $q1, $r0, $r1, $r2, $r3
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
$q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q0
MVE_VPST 4, implicit $vpr MVE_VPST 4, implicit $vpr
renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv17, align 2)
renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1820, align 2)
$lr = tMOVr $r3, 14, $noreg $lr = tMOVr $r3, 14, $noreg
renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, $noreg, undef renamable $q1
renamable $lr = t2LoopDec killed renamable $lr, 1 renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg tB %bb.3, 14, $noreg
bb.3.middle.block: bb.3.middle.block:
liveins: $q0, $q1, $r2 liveins: $q0, $q1, $r2
renamable $vpr = MVE_VCTP32 killed renamable $r2, 0, $noreg renamable $vpr = MVE_VCTP32 killed renamable $r2, 0, $noreg, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
... ...

llvm/test/CodeGen/Thumb2/mve-gatherscatter-mmo.ll

; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -stop-after=finalize-isel -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -stop-after=finalize-isel -o - %s | FileCheck %s
define arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_s16(i8* %base, <8 x i16> %offset) { define arm_aapcs_vfpcc <8 x i16> @test_vldrbq_gather_offset_s16(i8* %base, <8 x i16> %offset) {
; CHECK-LABEL: name: test_vldrbq_gather_offset_s16 ; CHECK-LABEL: name: test_vldrbq_gather_offset_s16
; CHECK: early-clobber %2:mqpr = MVE_VLDRBS16_rq %0, %1, 0, $noreg :: (load (s64), align 1) ; CHECK: early-clobber %2:mqpr = MVE_VLDRBS16_rq %0, %1, 0, $noreg, $noreg :: (load (s64), align 1)
entry: entry:
%0 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0i8.v8i16(i8* %base, <8 x i16> %offset, i32 8, i32 0, i32 0) %0 = call <8 x i16> @llvm.arm.mve.vldr.gather.offset.v8i16.p0i8.v8i16(i8* %base, <8 x i16> %offset, i32 8, i32 0, i32 0)
ret <8 x i16> %0 ret <8 x i16> %0
} }
define arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_s32(i8* %base, <4 x i32> %offset, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vldrbq_gather_offset_z_s32(i8* %base, <4 x i32> %offset, i16 zeroext %p) {
; CHECK-LABEL: name: test_vldrbq_gather_offset_z_s32 ; CHECK-LABEL: name: test_vldrbq_gather_offset_z_s32
; CHECK: early-clobber %4:mqpr = MVE_VLDRBS32_rq %0, %1, 1, killed %3 :: (load (s32), align 1) ; CHECK: early-clobber %4:mqpr = MVE_VLDRBS32_rq %0, %1, 1, killed %3, $noreg :: (load (s32), align 1)
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0i8.v4i32.v4i1(i8* %base, <4 x i32> %offset, i32 8, i32 0, i32 0, <4 x i1> %1) %2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0i8.v4i32.v4i1(i8* %base, <4 x i32> %offset, i32 8, i32 0, i32 0, <4 x i1> %1)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_s64(<2 x i64> %addr) { define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_s64(<2 x i64> %addr) {
; CHECK-LABEL: name: test_vldrdq_gather_base_s64 ; CHECK-LABEL: name: test_vldrdq_gather_base_s64
; CHECK: early-clobber %1:mqpr = MVE_VLDRDU64_qi %0, 616, 0, $noreg :: (load (s128), align 1) ; CHECK: early-clobber %1:mqpr = MVE_VLDRDU64_qi %0, 616, 0, $noreg, $noreg :: (load (s128), align 1)
entry: entry:
%0 = call <2 x i64> @llvm.arm.mve.vldr.gather.base.v2i64.v2i64(<2 x i64> %addr, i32 616) %0 = call <2 x i64> @llvm.arm.mve.vldr.gather.base.v2i64.v2i64(<2 x i64> %addr, i32 616)
ret <2 x i64> %0 ret <2 x i64> %0
} }
define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_z_f32(<4 x i32> %addr, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_z_f32(<4 x i32> %addr, i16 zeroext %p) {
; CHECK-LABEL: name: test_vldrwq_gather_base_z_f32 ; CHECK-LABEL: name: test_vldrwq_gather_base_z_f32
; CHECK: early-clobber %3:mqpr = MVE_VLDRWU32_qi %0, -300, 1, killed %2 :: (load (s128), align 1) ; CHECK: early-clobber %3:mqpr = MVE_VLDRWU32_qi %0, -300, 1, killed %2, $noreg :: (load (s128), align 1)
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = call <4 x float> @llvm.arm.mve.vldr.gather.base.predicated.v4f32.v4i32.v4i1(<4 x i32> %addr, i32 -300, <4 x i1> %1) %2 = call <4 x float> @llvm.arm.mve.vldr.gather.base.predicated.v4f32.v4i32.v4i1(<4 x i32> %addr, i32 -300, <4 x i1> %1)
ret <4 x float> %2 ret <4 x float> %2
} }
define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_s64(<2 x i64>* %addr) { define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_s64(<2 x i64>* %addr) {
; CHECK-LABEL: name: test_vldrdq_gather_base_wb_s64 ; CHECK-LABEL: name: test_vldrdq_gather_base_wb_s64
; CHECK: %2:mqpr, early-clobber %3:mqpr = MVE_VLDRDU64_qi_pre %1, 576, 0, $noreg :: (load (s128), align 1) ; CHECK: %2:mqpr, early-clobber %3:mqpr = MVE_VLDRDU64_qi_pre %1, 576, 0, $noreg, $noreg :: (load (s128), align 1)
entry: entry:
%0 = load <2 x i64>, <2 x i64>* %addr, align 8 %0 = load <2 x i64>, <2 x i64>* %addr, align 8
%1 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %0, i32 576) %1 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> %0, i32 576)
%2 = extractvalue { <2 x i64>, <2 x i64> } %1, 1 %2 = extractvalue { <2 x i64>, <2 x i64> } %1, 1
store <2 x i64> %2, <2 x i64>* %addr, align 8 store <2 x i64> %2, <2 x i64>* %addr, align 8
%3 = extractvalue { <2 x i64>, <2 x i64> } %1, 0 %3 = extractvalue { <2 x i64>, <2 x i64> } %1, 0
ret <2 x i64> %3 ret <2 x i64> %3
} }
define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_z_f32(<4 x i32>* %addr, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_z_f32(<4 x i32>* %addr, i16 zeroext %p) {
; CHECK-LABEL: name: test_vldrwq_gather_base_wb_z_f32 ; CHECK-LABEL: name: test_vldrwq_gather_base_wb_z_f32
; CHECK: %4:mqpr, early-clobber %5:mqpr = MVE_VLDRWU32_qi_pre %3, -352, 1, killed %2 :: (load (s128), align 1) ; CHECK: %4:mqpr, early-clobber %5:mqpr = MVE_VLDRWU32_qi_pre %3, -352, 1, killed %2, $noreg :: (load (s128), align 1)
entry: entry:
%0 = load <4 x i32>, <4 x i32>* %addr, align 8 %0 = load <4 x i32>, <4 x i32>* %addr, align 8
%1 = zext i16 %p to i32 %1 = zext i16 %p to i32
%2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
%3 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 -352, <4 x i1> %2) %3 = call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> %0, i32 -352, <4 x i1> %2)
%4 = extractvalue { <4 x float>, <4 x i32> } %3, 1 %4 = extractvalue { <4 x float>, <4 x i32> } %3, 1
store <4 x i32> %4, <4 x i32>* %addr, align 8 store <4 x i32> %4, <4 x i32>* %addr, align 8
%5 = extractvalue { <4 x float>, <4 x i32> } %3, 0 %5 = extractvalue { <4 x float>, <4 x i32> } %3, 0
ret <4 x float> %5 ret <4 x float> %5
} }
define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_s32(i8* %base, <4 x i32> %offset, <4 x i32> %value) { define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_s32(i8* %base, <4 x i32> %offset, <4 x i32> %value) {
; CHECK-LABEL: name: test_vstrbq_scatter_offset_s32 ; CHECK-LABEL: name: test_vstrbq_scatter_offset_s32
; CHECK: MVE_VSTRB32_rq %2, %0, %1, 0, $noreg :: (store (s32), align 1) ; CHECK: MVE_VSTRB32_rq %2, %0, %1, 0, $noreg, $noreg :: (store (s32), align 1)
entry: entry:
call void @llvm.arm.mve.vstr.scatter.offset.p0i8.v4i32.v4i32(i8* %base, <4 x i32> %offset, <4 x i32> %value, i32 8, i32 0) call void @llvm.arm.mve.vstr.scatter.offset.p0i8.v4i32.v4i32(i8* %base, <4 x i32> %offset, <4 x i32> %value, i32 8, i32 0)
ret void ret void
} }
define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_p_s8(i8* %base, <16 x i8> %offset, <16 x i8> %value, i16 zeroext %p) { define arm_aapcs_vfpcc void @test_vstrbq_scatter_offset_p_s8(i8* %base, <16 x i8> %offset, <16 x i8> %value, i16 zeroext %p) {
; CHECK-LABEL: name: test_vstrbq_scatter_offset_p_s8 ; CHECK-LABEL: name: test_vstrbq_scatter_offset_p_s8
; CHECK: MVE_VSTRB8_rq %2, %0, %1, 1, killed %4 :: (store (s128), align 1) ; CHECK: MVE_VSTRB8_rq %2, %0, %1, 1, killed %4, $noreg :: (store (s128), align 1)
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0i8.v16i8.v16i8.v16i1(i8* %base, <16 x i8> %offset, <16 x i8> %value, i32 8, i32 0, <16 x i1> %1) call void @llvm.arm.mve.vstr.scatter.offset.predicated.p0i8.v16i8.v16i8.v16i1(i8* %base, <16 x i8> %offset, <16 x i8> %value, i32 8, i32 0, <16 x i1> %1)
ret void ret void
} }
define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_u64(<2 x i64> %addr, <2 x i64> %value) { define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_u64(<2 x i64> %addr, <2 x i64> %value) {
; CHECK-LABEL: name: test_vstrdq_scatter_base_u64 ; CHECK-LABEL: name: test_vstrdq_scatter_base_u64
; CHECK: MVE_VSTRD64_qi %1, %0, -472, 0, $noreg :: (store (s128), align 1) ; CHECK: MVE_VSTRD64_qi %1, %0, -472, 0, $noreg, $noreg :: (store (s128), align 1)
entry: entry:
call void @llvm.arm.mve.vstr.scatter.base.v2i64.v2i64(<2 x i64> %addr, i32 -472, <2 x i64> %value) call void @llvm.arm.mve.vstr.scatter.base.v2i64.v2i64(<2 x i64> %addr, i32 -472, <2 x i64> %value)
ret void ret void
} }
define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_p_s64(<2 x i64> %addr, <2 x i64> %value, i16 zeroext %p) { define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_p_s64(<2 x i64> %addr, <2 x i64> %value, i16 zeroext %p) {
; CHECK-LABEL: name: test_vstrdq_scatter_base_p_s64 ; CHECK-LABEL: name: test_vstrdq_scatter_base_p_s64
; CHECK: MVE_VSTRD64_qi %1, %0, 888, 1, killed %3 :: (store (s128), align 1) ; CHECK: MVE_VSTRD64_qi %1, %0, 888, 1, killed %3, $noreg :: (store (s128), align 1)
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
call void @llvm.arm.mve.vstr.scatter.base.predicated.v2i64.v2i64.v4i1(<2 x i64> %addr, i32 888, <2 x i64> %value, <4 x i1> %1) call void @llvm.arm.mve.vstr.scatter.base.predicated.v2i64.v2i64.v4i1(<2 x i64> %addr, i32 888, <2 x i64> %value, <4 x i1> %1)
ret void ret void
} }
define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_wb_s64(<2 x i64>* %addr, <2 x i64> %value) { define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_wb_s64(<2 x i64>* %addr, <2 x i64> %value) {
; CHECK-LABEL: name: test_vstrdq_scatter_base_wb_s64 ; CHECK-LABEL: name: test_vstrdq_scatter_base_wb_s64
; CHECK: %3:mqpr = MVE_VSTRD64_qi_pre %1, %2, 208, 0, $noreg :: (store (s128), align 1) ; CHECK: %3:mqpr = MVE_VSTRD64_qi_pre %1, %2, 208, 0, $noreg, $noreg :: (store (s128), align 1)
entry: entry:
%0 = load <2 x i64>, <2 x i64>* %addr, align 8 %0 = load <2 x i64>, <2 x i64>* %addr, align 8
%1 = call <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.v2i64.v2i64(<2 x i64> %0, i32 208, <2 x i64> %value) %1 = call <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.v2i64.v2i64(<2 x i64> %0, i32 208, <2 x i64> %value)
store <2 x i64> %1, <2 x i64>* %addr, align 8 store <2 x i64> %1, <2 x i64>* %addr, align 8
ret void ret void
} }
define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_wb_p_s64(<2 x i64>* %addr, <2 x i64> %value, i16 zeroext %p) { define arm_aapcs_vfpcc void @test_vstrdq_scatter_base_wb_p_s64(<2 x i64>* %addr, <2 x i64> %value, i16 zeroext %p) {
; CHECK-LABEL: name: test_vstrdq_scatter_base_wb_p_s64 ; CHECK-LABEL: name: test_vstrdq_scatter_base_wb_p_s64
; CHECK: %5:mqpr = MVE_VSTRD64_qi_pre %1, %3, 248, 1, killed %4 :: (store (s128), align 1) ; CHECK: %5:mqpr = MVE_VSTRD64_qi_pre %1, %3, 248, 1, killed %4, $noreg :: (store (s128), align 1)
entry: entry:
%0 = load <2 x i64>, <2 x i64>* %addr, align 8 %0 = load <2 x i64>, <2 x i64>* %addr, align 8
%1 = zext i16 %p to i32 %1 = zext i16 %p to i32
%2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1) %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
%3 = call <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.predicated.v2i64.v2i64.v4i1(<2 x i64> %0, i32 248, <2 x i64> %value, <4 x i1> %2) %3 = call <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.predicated.v2i64.v2i64.v4i1(<2 x i64> %0, i32 248, <2 x i64> %value, <4 x i1> %2)
store <2 x i64> %3, <2 x i64>* %addr, align 8 store <2 x i64> %3, <2 x i64>* %addr, align 8
ret void ret void
} }
Show All 15 Lines

llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Linesliveins:
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRWU32 ; CHECK-LABEL: name: MVE_VLDRWU32
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRHU16 name: MVE_VLDRHU16
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRHU16 ; CHECK-LABEL: name: MVE_VLDRHU16
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]] ; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRHU16 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRHU16 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBU8 name: MVE_VLDRBU8
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBU8 ; CHECK-LABEL: name: MVE_VLDRBU8
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]] ; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRBU8 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRBU8 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBS32 name: MVE_VLDRBS32
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBS32 ; CHECK-LABEL: name: MVE_VLDRBS32
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRBS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_post1:%[0-9]+]]:mqpr = MVE_VLDRBS32_post [[COPY]], 32, 0, $noreg :: (load (s32), align 8) ; CHECK: [[MVE_VLDRBS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_post1:%[0-9]+]]:mqpr = MVE_VLDRBS32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s32), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBS32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRBS32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%1:mqpr = MVE_VLDRBS32 %0, 0, 0, $noreg :: (load (s32), align 8) %1:mqpr = MVE_VLDRBS32 %0, 0, 0, $noreg, $noreg :: (load (s32), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBU32 name: MVE_VLDRBU32
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBU32 ; CHECK-LABEL: name: MVE_VLDRBU32
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRBU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_post1:%[0-9]+]]:mqpr = MVE_VLDRBU32_post [[COPY]], 32, 0, $noreg :: (load (s32), align 8) ; CHECK: [[MVE_VLDRBU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_post1:%[0-9]+]]:mqpr = MVE_VLDRBU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s32), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRBU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%1:mqpr = MVE_VLDRBU32 %0, 0, 0, $noreg :: (load (s32), align 8) %1:mqpr = MVE_VLDRBU32 %0, 0, 0, $noreg, $noreg :: (load (s32), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRHS32 name: MVE_VLDRHS32
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRHS32 ; CHECK-LABEL: name: MVE_VLDRHS32
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRHS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_post1:%[0-9]+]]:mqpr = MVE_VLDRHS32_post [[COPY]], 32, 0, $noreg :: (load (s64)) ; CHECK: [[MVE_VLDRHS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_post1:%[0-9]+]]:mqpr = MVE_VLDRHS32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s64))
; CHECK: $r0 = COPY [[MVE_VLDRHS32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRHS32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%1:mqpr = MVE_VLDRHS32 %0, 0, 0, $noreg :: (load (s64), align 8) %1:mqpr = MVE_VLDRHS32 %0, 0, 0, $noreg, $noreg :: (load (s64), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRHU32 name: MVE_VLDRHU32
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRHU32 ; CHECK-LABEL: name: MVE_VLDRHU32
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRHU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_post1:%[0-9]+]]:mqpr = MVE_VLDRHU32_post [[COPY]], 32, 0, $noreg :: (load (s64)) ; CHECK: [[MVE_VLDRHU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_post1:%[0-9]+]]:mqpr = MVE_VLDRHU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s64))
; CHECK: $r0 = COPY [[MVE_VLDRHU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRHU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%1:mqpr = MVE_VLDRHU32 %0, 0, 0, $noreg :: (load (s64), align 8) %1:mqpr = MVE_VLDRHU32 %0, 0, 0, $noreg, $noreg :: (load (s64), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBS16 name: MVE_VLDRBS16
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBS16 ; CHECK-LABEL: name: MVE_VLDRBS16
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRBS16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_post1:%[0-9]+]]:mqpr = MVE_VLDRBS16_post [[COPY]], 32, 0, $noreg :: (load (s64)) ; CHECK: [[MVE_VLDRBS16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_post1:%[0-9]+]]:mqpr = MVE_VLDRBS16_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s64))
; CHECK: $r0 = COPY [[MVE_VLDRBS16_post]] ; CHECK: $r0 = COPY [[MVE_VLDRBS16_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%1:mqpr = MVE_VLDRBS16 %0, 0, 0, $noreg :: (load (s64), align 8) %1:mqpr = MVE_VLDRBS16 %0, 0, 0, $noreg, $noreg :: (load (s64), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBU16 name: MVE_VLDRBU16
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBU16 ; CHECK-LABEL: name: MVE_VLDRBU16
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRBU16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_post1:%[0-9]+]]:mqpr = MVE_VLDRBU16_post [[COPY]], 32, 0, $noreg :: (load (s64)) ; CHECK: [[MVE_VLDRBU16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_post1:%[0-9]+]]:mqpr = MVE_VLDRBU16_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s64))
; CHECK: $r0 = COPY [[MVE_VLDRBU16_post]] ; CHECK: $r0 = COPY [[MVE_VLDRBU16_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%1:mqpr = MVE_VLDRBU16 %0, 0, 0, $noreg :: (load (s64), align 8) %1:mqpr = MVE_VLDRBU16 %0, 0, 0, $noreg, $noreg :: (load (s64), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRWU32 name: MVE_VSTRWU32
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRWU32 ; CHECK-LABEL: name: MVE_VSTRWU32
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VSTRWU32_post:%[0-9]+]]:rgpr = MVE_VSTRWU32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRWU32_post:%[0-9]+]]:rgpr = MVE_VSTRWU32_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VSTRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
MVE_VSTRWU32 %1, %0, 0, 0, $noreg :: (store (s128), align 8) MVE_VSTRWU32 %1, %0, 0, 0, $noreg, $noreg :: (store (s128), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRHU16 name: MVE_VSTRHU16
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRHU16 ; CHECK-LABEL: name: MVE_VSTRHU16
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VSTRHU16_post:%[0-9]+]]:rgpr = MVE_VSTRHU16_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRHU16_post:%[0-9]+]]:rgpr = MVE_VSTRHU16_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRHU16_post]] ; CHECK: $r0 = COPY [[MVE_VSTRHU16_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
MVE_VSTRHU16 %1, %0, 0, 0, $noreg :: (store (s128), align 8) MVE_VSTRHU16 %1, %0, 0, 0, $noreg, $noreg :: (store (s128), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRBU8 name: MVE_VSTRBU8
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRBU8 ; CHECK-LABEL: name: MVE_VSTRBU8
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRBU8_post]] ; CHECK: $r0 = COPY [[MVE_VSTRBU8_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
MVE_VSTRBU8 %1, %0, 0, 0, $noreg :: (store (s128), align 8) MVE_VSTRBU8 %1, %0, 0, 0, $noreg, $noreg :: (store (s128), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRH32 name: MVE_VSTRH32
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRH32 ; CHECK-LABEL: name: MVE_VSTRH32
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRH32_post:%[0-9]+]]:tgpr = MVE_VSTRH32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s64)) ; CHECK: [[MVE_VSTRH32_post:%[0-9]+]]:tgpr = MVE_VSTRH32_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s64))
; CHECK: $r0 = COPY [[MVE_VSTRH32_post]] ; CHECK: $r0 = COPY [[MVE_VSTRH32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
MVE_VSTRH32 %1, %0, 0, 0, $noreg :: (store (s64), align 8) MVE_VSTRH32 %1, %0, 0, 0, $noreg, $noreg :: (store (s64), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRB32 name: MVE_VSTRB32
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRB32 ; CHECK-LABEL: name: MVE_VSTRB32
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRB32_post:%[0-9]+]]:tgpr = MVE_VSTRB32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s32), align 8) ; CHECK: [[MVE_VSTRB32_post:%[0-9]+]]:tgpr = MVE_VSTRB32_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s32), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRB32_post]] ; CHECK: $r0 = COPY [[MVE_VSTRB32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
MVE_VSTRB32 %1, %0, 0, 0, $noreg :: (store (s32), align 8) MVE_VSTRB32 %1, %0, 0, 0, $noreg, $noreg :: (store (s32), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRB16 name: MVE_VSTRB16
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRB16 ; CHECK-LABEL: name: MVE_VSTRB16
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRB16_post:%[0-9]+]]:tgpr = MVE_VSTRB16_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s64)) ; CHECK: [[MVE_VSTRB16_post:%[0-9]+]]:tgpr = MVE_VSTRB16_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s64))
; CHECK: $r0 = COPY [[MVE_VSTRB16_post]] ; CHECK: $r0 = COPY [[MVE_VSTRB16_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
MVE_VSTRB16 %1, %0, 0, 0, $noreg :: (store (s64), align 8) MVE_VSTRB16 %1, %0, 0, 0, $noreg, $noreg :: (store (s64), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: ld0ld4 name: ld0ld4
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: mqpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: ld0ld4 ; CHECK-LABEL: name: ld0ld4
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load (s128), align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: ld4ld0 name: ld4ld0
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: mqpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: ld4ld0 ; CHECK-LABEL: name: ld4ld0
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %3:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: ld0ld4ld0 name: ld0ld4ld0
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: mqpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' }
- { id: 4, class: mqpr, preferred-register: '' } - { id: 4, class: mqpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: ld0ld4ld0 ; CHECK-LABEL: name: ld0ld4ld0
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load (s128), align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
%4:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %4:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: ld4ld0ld4 name: ld4ld0ld4
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: mqpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' }
- { id: 4, class: mqpr, preferred-register: '' } - { id: 4, class: mqpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: ld4ld0ld4 ; CHECK-LABEL: name: ld4ld0ld4
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %3:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%4:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load (s128), align 8) %4:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: addload name: addload
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: mqpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: addload ; CHECK-LABEL: name: addload
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load (s128), align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: sub name: sub
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: mqpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: sub ; CHECK-LABEL: name: sub
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load (s128), align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: otherUse name: otherUse
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: mqpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: otherUse ; CHECK-LABEL: name: otherUse
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[COPY]] ; CHECK: $r0 = COPY [[COPY]]
; CHECK: $r0 = COPY [[t2ADDri]] ; CHECK: $r0 = COPY [[t2ADDri]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load (s128), align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %0 $r0 = COPY %0
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: postincUse name: postincUse
tracksRegLiveness: true tracksRegLiveness: true
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: postincUse ; CHECK-LABEL: name: postincUse
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 4, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[t2ADDri]] ; CHECK: $r0 = COPY [[t2ADDri]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%4:rgpr, %3:mqpr = MVE_VLDRWU32_post %0, 4, 0, $noreg :: (load (s128), align 8) %4:rgpr, %3:mqpr = MVE_VLDRWU32_post %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: badScale name: badScale
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: mqpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: badScale ; CHECK-LABEL: name: badScale
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[t2SUBri]] ; CHECK: $r0 = COPY [[t2SUBri]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%2:rgpr = nuw t2SUBri %0, 3, 14, $noreg, $noreg %2:rgpr = nuw t2SUBri %0, 3, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load (s128), align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: badRange name: badRange
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: mqpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: badRange ; CHECK-LABEL: name: badRange
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], -300, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], -300, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], -300, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], -300, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[t2SUBri]] ; CHECK: $r0 = COPY [[t2SUBri]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%2:rgpr = nuw t2SUBri %0, -300, 14, $noreg, $noreg %2:rgpr = nuw t2SUBri %0, -300, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, -300, 0, $noreg :: (load (s128), align 8) %3:mqpr = MVE_VLDRWU32 %0, -300, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: addUseOK name: addUseOK
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: mqpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' }
- { id: 4, class: rgpr, preferred-register: '' } - { id: 4, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: addUseOK ; CHECK-LABEL: name: addUseOK
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2LSRri]] ; CHECK: $r0 = COPY [[t2LSRri]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load (s128), align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
%4:rgpr = nuw t2LSRri %2, 2, 14, $noreg, $noreg %4:rgpr = nuw t2LSRri %2, 2, 14, $noreg, $noreg
$r0 = COPY %4 $r0 = COPY %4
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: addUseDom name: addUseDom
tracksRegLiveness: true tracksRegLiveness: true
Show All 10 Linesbody: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: addUseDom ; CHECK-LABEL: name: addUseDom
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = nuw t2SUBri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[t2SUBri]], 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[t2SUBri]], 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[t2LSRri]] ; CHECK: $r0 = COPY [[t2LSRri]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg
%4:rgpr = nuw t2LSRri %2, 2, 14, $noreg, $noreg %4:rgpr = nuw t2LSRri %2, 2, 14, $noreg, $noreg
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load (s128), align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %4 $r0 = COPY %4
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: addUseKilled name: addUseKilled
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprnopc, preferred-register: '' } - { id: 0, class: gprnopc, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: mqpr, preferred-register: '' } - { id: 3, class: mqpr, preferred-register: '' }
- { id: 4, class: rgpr, preferred-register: '' } - { id: 4, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: addUseKilled ; CHECK-LABEL: name: addUseKilled
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[t2LSRri]] ; CHECK: $r0 = COPY [[t2LSRri]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:gprnopc = COPY $r0 %0:gprnopc = COPY $r0
%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg, $noreg :: (load (s128), align 8)
%2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg %2:rgpr = nuw t2SUBri %0, 32, 14, $noreg, $noreg
%4:rgpr = nuw t2LSRri killed %2, 2, 14, $noreg, $noreg %4:rgpr = nuw t2LSRri killed %2, 2, 14, $noreg, $noreg
%3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg :: (load (s128), align 8) %3:mqpr = MVE_VLDRWU32 %0, 4, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %4 $r0 = COPY %4
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRWU32_post name: MVE_VLDRWU32_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRWU32_post ; CHECK-LABEL: name: MVE_VLDRWU32_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr, %1:mqpr = MVE_VLDRWU32_post %0, 32, 0, $noreg :: (load (s128), align 8) %2:rgpr, %1:mqpr = MVE_VLDRWU32_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRWU32 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRHU16_post name: MVE_VLDRHU16_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRHU16_post ; CHECK-LABEL: name: MVE_VLDRHU16_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[MVE_VLDRHU16_post]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[MVE_VLDRHU16_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]] ; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr, %1:mqpr = MVE_VLDRHU16_post %0, 32, 0, $noreg :: (load (s128), align 8) %2:rgpr, %1:mqpr = MVE_VLDRHU16_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRHU16 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRHU16 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBU8_post name: MVE_VLDRBU8_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBU8_post ; CHECK-LABEL: name: MVE_VLDRBU8_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[MVE_VLDRBU8_post]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[MVE_VLDRBU8_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]] ; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr, %1:mqpr = MVE_VLDRBU8_post %0, 32, 0, $noreg :: (load (s128), align 8) %2:rgpr, %1:mqpr = MVE_VLDRBU8_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRBU8 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRBU8 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBS32_post name: MVE_VLDRBS32_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBS32_post ; CHECK-LABEL: name: MVE_VLDRBS32_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRBS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_post1:%[0-9]+]]:mqpr = MVE_VLDRBS32_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_post1:%[0-9]+]]:mqpr = MVE_VLDRBS32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRBS32_:%[0-9]+]]:mqpr = MVE_VLDRBS32 [[MVE_VLDRBS32_post]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBS32_:%[0-9]+]]:mqpr = MVE_VLDRBS32 [[MVE_VLDRBS32_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBS32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRBS32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, %1:mqpr = MVE_VLDRBS32_post %0, 32, 0, $noreg :: (load (s128), align 8) %2:tgpr, %1:mqpr = MVE_VLDRBS32_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRBS32 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRBS32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBU32_post name: MVE_VLDRBU32_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBU32_post ; CHECK-LABEL: name: MVE_VLDRBU32_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRBU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_post1:%[0-9]+]]:mqpr = MVE_VLDRBU32_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_post1:%[0-9]+]]:mqpr = MVE_VLDRBU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRBU32_:%[0-9]+]]:mqpr = MVE_VLDRBU32 [[MVE_VLDRBU32_post]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU32_:%[0-9]+]]:mqpr = MVE_VLDRBU32 [[MVE_VLDRBU32_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRBU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, %1:mqpr = MVE_VLDRBU32_post %0, 32, 0, $noreg :: (load (s128), align 8) %2:tgpr, %1:mqpr = MVE_VLDRBU32_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRBU32 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRBU32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRHS32_post name: MVE_VLDRHS32_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRHS32_post ; CHECK-LABEL: name: MVE_VLDRHS32_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRHS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_post1:%[0-9]+]]:mqpr = MVE_VLDRHS32_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHS32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_post1:%[0-9]+]]:mqpr = MVE_VLDRHS32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRHS32_:%[0-9]+]]:mqpr = MVE_VLDRHS32 [[MVE_VLDRHS32_post]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHS32_:%[0-9]+]]:mqpr = MVE_VLDRHS32 [[MVE_VLDRHS32_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRHS32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRHS32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, %1:mqpr = MVE_VLDRHS32_post %0, 32, 0, $noreg :: (load (s128), align 8) %2:tgpr, %1:mqpr = MVE_VLDRHS32_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRHS32 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRHS32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRHU32_post name: MVE_VLDRHU32_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRHU32_post ; CHECK-LABEL: name: MVE_VLDRHU32_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRHU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_post1:%[0-9]+]]:mqpr = MVE_VLDRHU32_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHU32_post:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_post1:%[0-9]+]]:mqpr = MVE_VLDRHU32_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRHU32_:%[0-9]+]]:mqpr = MVE_VLDRHU32 [[MVE_VLDRHU32_post]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHU32_:%[0-9]+]]:mqpr = MVE_VLDRHU32 [[MVE_VLDRHU32_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRHU32_post]] ; CHECK: $r0 = COPY [[MVE_VLDRHU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, %1:mqpr = MVE_VLDRHU32_post %0, 32, 0, $noreg :: (load (s128), align 8) %2:tgpr, %1:mqpr = MVE_VLDRHU32_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRHU32 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRHU32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBS16_post name: MVE_VLDRBS16_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBS16_post ; CHECK-LABEL: name: MVE_VLDRBS16_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRBS16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_post1:%[0-9]+]]:mqpr = MVE_VLDRBS16_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBS16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_post1:%[0-9]+]]:mqpr = MVE_VLDRBS16_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRBS16_:%[0-9]+]]:mqpr = MVE_VLDRBS16 [[MVE_VLDRBS16_post]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBS16_:%[0-9]+]]:mqpr = MVE_VLDRBS16 [[MVE_VLDRBS16_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBS16_post]] ; CHECK: $r0 = COPY [[MVE_VLDRBS16_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, %1:mqpr = MVE_VLDRBS16_post %0, 32, 0, $noreg :: (load (s128), align 8) %2:tgpr, %1:mqpr = MVE_VLDRBS16_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRBS16 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRBS16 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBU16_post name: MVE_VLDRBU16_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBU16_post ; CHECK-LABEL: name: MVE_VLDRBU16_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRBU16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_post1:%[0-9]+]]:mqpr = MVE_VLDRBU16_post [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU16_post:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_post1:%[0-9]+]]:mqpr = MVE_VLDRBU16_post [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRBU16_:%[0-9]+]]:mqpr = MVE_VLDRBU16 [[MVE_VLDRBU16_post]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU16_:%[0-9]+]]:mqpr = MVE_VLDRBU16 [[MVE_VLDRBU16_post]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBU16_post]] ; CHECK: $r0 = COPY [[MVE_VLDRBU16_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, %1:mqpr = MVE_VLDRBU16_post %0, 32, 0, $noreg :: (load (s128), align 8) %2:tgpr, %1:mqpr = MVE_VLDRBU16_post %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRBU16 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRBU16 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRWU32_post name: MVE_VSTRWU32_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRWU32_post ; CHECK-LABEL: name: MVE_VSTRWU32_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VSTRWU32_post:%[0-9]+]]:rgpr = MVE_VSTRWU32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRWU32_post:%[0-9]+]]:rgpr = MVE_VSTRWU32_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRWU32 [[COPY]], [[MVE_VSTRWU32_post]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRWU32 [[COPY]], [[MVE_VSTRWU32_post]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRWU32_post]] ; CHECK: $r0 = COPY [[MVE_VSTRWU32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr = MVE_VSTRWU32_post %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:rgpr = MVE_VSTRWU32_post %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRWU32 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRWU32 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRHU16_post name: MVE_VSTRHU16_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRHU16_post ; CHECK-LABEL: name: MVE_VSTRHU16_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VSTRHU16_post:%[0-9]+]]:rgpr = MVE_VSTRHU16_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRHU16_post:%[0-9]+]]:rgpr = MVE_VSTRHU16_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRHU16 [[COPY]], [[MVE_VSTRHU16_post]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRHU16 [[COPY]], [[MVE_VSTRHU16_post]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRHU16_post]] ; CHECK: $r0 = COPY [[MVE_VSTRHU16_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr = MVE_VSTRHU16_post %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:rgpr = MVE_VSTRHU16_post %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRHU16 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRHU16 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRBU8_post name: MVE_VSTRBU8_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRBU8_post ; CHECK-LABEL: name: MVE_VSTRBU8_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRBU8 [[COPY]], [[MVE_VSTRBU8_post]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRBU8 [[COPY]], [[MVE_VSTRBU8_post]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRBU8_post]] ; CHECK: $r0 = COPY [[MVE_VSTRBU8_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr = MVE_VSTRBU8_post %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:rgpr = MVE_VSTRBU8_post %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRBU8 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRBU8 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRH32_post name: MVE_VSTRH32_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRH32_post ; CHECK-LABEL: name: MVE_VSTRH32_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRH32_post:%[0-9]+]]:tgpr = MVE_VSTRH32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRH32_post:%[0-9]+]]:tgpr = MVE_VSTRH32_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRH32 [[COPY]], [[MVE_VSTRH32_post]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRH32 [[COPY]], [[MVE_VSTRH32_post]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRH32_post]] ; CHECK: $r0 = COPY [[MVE_VSTRH32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr = MVE_VSTRH32_post %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:tgpr = MVE_VSTRH32_post %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRH32 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRH32 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRB32_post name: MVE_VSTRB32_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRB32_post ; CHECK-LABEL: name: MVE_VSTRB32_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRB32_post:%[0-9]+]]:tgpr = MVE_VSTRB32_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRB32_post:%[0-9]+]]:tgpr = MVE_VSTRB32_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRB32 [[COPY]], [[MVE_VSTRB32_post]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRB32 [[COPY]], [[MVE_VSTRB32_post]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRB32_post]] ; CHECK: $r0 = COPY [[MVE_VSTRB32_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr = MVE_VSTRB32_post %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:tgpr = MVE_VSTRB32_post %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRB32 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRB32 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRB16_post name: MVE_VSTRB16_post
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRB16_post ; CHECK-LABEL: name: MVE_VSTRB16_post
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRB16_post:%[0-9]+]]:tgpr = MVE_VSTRB16_post [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRB16_post:%[0-9]+]]:tgpr = MVE_VSTRB16_post [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_post]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_post]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRB16_post]] ; CHECK: $r0 = COPY [[MVE_VSTRB16_post]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr = MVE_VSTRB16_post %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:tgpr = MVE_VSTRB16_post %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRB16 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRB16 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRWU32_pre name: MVE_VLDRWU32_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRWU32_pre ; CHECK-LABEL: name: MVE_VLDRWU32_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRWU32_pre:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_pre1:%[0-9]+]]:mqpr = MVE_VLDRWU32_pre [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_pre:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_pre1:%[0-9]+]]:mqpr = MVE_VLDRWU32_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_pre]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRWU32_pre]] ; CHECK: $r0 = COPY [[MVE_VLDRWU32_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr, %1:mqpr = MVE_VLDRWU32_pre %0, 32, 0, $noreg :: (load (s128), align 8) %2:rgpr, %1:mqpr = MVE_VLDRWU32_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRWU32 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRWU32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRHU16_pre name: MVE_VLDRHU16_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRHU16_pre ; CHECK-LABEL: name: MVE_VLDRHU16_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRHU16_pre:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_pre1:%[0-9]+]]:mqpr = MVE_VLDRHU16_pre [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHU16_pre:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_pre1:%[0-9]+]]:mqpr = MVE_VLDRHU16_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[MVE_VLDRHU16_pre]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[MVE_VLDRHU16_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRHU16_pre]] ; CHECK: $r0 = COPY [[MVE_VLDRHU16_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr, %1:mqpr = MVE_VLDRHU16_pre %0, 32, 0, $noreg :: (load (s128), align 8) %2:rgpr, %1:mqpr = MVE_VLDRHU16_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRHU16 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRHU16 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBU8_pre name: MVE_VLDRBU8_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBU8_pre ; CHECK-LABEL: name: MVE_VLDRBU8_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VLDRBU8_pre:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_pre1:%[0-9]+]]:mqpr = MVE_VLDRBU8_pre [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU8_pre:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_pre1:%[0-9]+]]:mqpr = MVE_VLDRBU8_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[MVE_VLDRBU8_pre]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[MVE_VLDRBU8_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBU8_pre]] ; CHECK: $r0 = COPY [[MVE_VLDRBU8_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr, %1:mqpr = MVE_VLDRBU8_pre %0, 32, 0, $noreg :: (load (s128), align 8) %2:rgpr, %1:mqpr = MVE_VLDRBU8_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRBU8 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRBU8 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBS32_pre name: MVE_VLDRBS32_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBS32_pre ; CHECK-LABEL: name: MVE_VLDRBS32_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRBS32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_pre1:%[0-9]+]]:mqpr = MVE_VLDRBS32_pre [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBS32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBS32_pre1:%[0-9]+]]:mqpr = MVE_VLDRBS32_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRBS32_:%[0-9]+]]:mqpr = MVE_VLDRBS32 [[MVE_VLDRBS32_pre]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBS32_:%[0-9]+]]:mqpr = MVE_VLDRBS32 [[MVE_VLDRBS32_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBS32_pre]] ; CHECK: $r0 = COPY [[MVE_VLDRBS32_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, %1:mqpr = MVE_VLDRBS32_pre %0, 32, 0, $noreg :: (load (s128), align 8) %2:tgpr, %1:mqpr = MVE_VLDRBS32_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRBS32 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRBS32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBU32_pre name: MVE_VLDRBU32_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBU32_pre ; CHECK-LABEL: name: MVE_VLDRBU32_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRBU32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_pre1:%[0-9]+]]:mqpr = MVE_VLDRBU32_pre [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBU32_pre1:%[0-9]+]]:mqpr = MVE_VLDRBU32_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRBU32_:%[0-9]+]]:mqpr = MVE_VLDRBU32 [[MVE_VLDRBU32_pre]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU32_:%[0-9]+]]:mqpr = MVE_VLDRBU32 [[MVE_VLDRBU32_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBU32_pre]] ; CHECK: $r0 = COPY [[MVE_VLDRBU32_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, %1:mqpr = MVE_VLDRBU32_pre %0, 32, 0, $noreg :: (load (s128), align 8) %2:tgpr, %1:mqpr = MVE_VLDRBU32_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRBU32 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRBU32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRHS32_pre name: MVE_VLDRHS32_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRHS32_pre ; CHECK-LABEL: name: MVE_VLDRHS32_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRHS32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_pre1:%[0-9]+]]:mqpr = MVE_VLDRHS32_pre [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHS32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRHS32_pre1:%[0-9]+]]:mqpr = MVE_VLDRHS32_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRHS32_:%[0-9]+]]:mqpr = MVE_VLDRHS32 [[MVE_VLDRHS32_pre]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHS32_:%[0-9]+]]:mqpr = MVE_VLDRHS32 [[MVE_VLDRHS32_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRHS32_pre]] ; CHECK: $r0 = COPY [[MVE_VLDRHS32_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, %1:mqpr = MVE_VLDRHS32_pre %0, 32, 0, $noreg :: (load (s128), align 8) %2:tgpr, %1:mqpr = MVE_VLDRHS32_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRHS32 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRHS32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRHU32_pre name: MVE_VLDRHU32_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRHU32_pre ; CHECK-LABEL: name: MVE_VLDRHU32_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRHU32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_pre1:%[0-9]+]]:mqpr = MVE_VLDRHU32_pre [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHU32_pre:%[0-9]+]]:tgpr, [[MVE_VLDRHU32_pre1:%[0-9]+]]:mqpr = MVE_VLDRHU32_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRHU32_:%[0-9]+]]:mqpr = MVE_VLDRHU32 [[MVE_VLDRHU32_pre]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRHU32_:%[0-9]+]]:mqpr = MVE_VLDRHU32 [[MVE_VLDRHU32_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRHU32_pre]] ; CHECK: $r0 = COPY [[MVE_VLDRHU32_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, %1:mqpr = MVE_VLDRHU32_pre %0, 32, 0, $noreg :: (load (s128), align 8) %2:tgpr, %1:mqpr = MVE_VLDRHU32_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRHU32 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRHU32 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBS16_pre name: MVE_VLDRBS16_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBS16_pre ; CHECK-LABEL: name: MVE_VLDRBS16_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRBS16_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_pre1:%[0-9]+]]:mqpr = MVE_VLDRBS16_pre [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBS16_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBS16_pre1:%[0-9]+]]:mqpr = MVE_VLDRBS16_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRBS16_:%[0-9]+]]:mqpr = MVE_VLDRBS16 [[MVE_VLDRBS16_pre]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBS16_:%[0-9]+]]:mqpr = MVE_VLDRBS16 [[MVE_VLDRBS16_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBS16_pre]] ; CHECK: $r0 = COPY [[MVE_VLDRBS16_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, %1:mqpr = MVE_VLDRBS16_pre %0, 32, 0, $noreg :: (load (s128), align 8) %2:tgpr, %1:mqpr = MVE_VLDRBS16_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRBS16 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRBS16 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VLDRBU16_pre name: MVE_VLDRBU16_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VLDRBU16_pre ; CHECK-LABEL: name: MVE_VLDRBU16_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VLDRBU16_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_pre1:%[0-9]+]]:mqpr = MVE_VLDRBU16_pre [[COPY]], 32, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU16_pre:%[0-9]+]]:tgpr, [[MVE_VLDRBU16_pre1:%[0-9]+]]:mqpr = MVE_VLDRBU16_pre [[COPY]], 32, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: [[MVE_VLDRBU16_:%[0-9]+]]:mqpr = MVE_VLDRBU16 [[MVE_VLDRBU16_pre]], -16, 0, $noreg :: (load (s128), align 8) ; CHECK: [[MVE_VLDRBU16_:%[0-9]+]]:mqpr = MVE_VLDRBU16 [[MVE_VLDRBU16_pre]], -16, 0, $noreg, $noreg :: (load (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VLDRBU16_pre]] ; CHECK: $r0 = COPY [[MVE_VLDRBU16_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr, %1:mqpr = MVE_VLDRBU16_pre %0, 32, 0, $noreg :: (load (s128), align 8) %2:tgpr, %1:mqpr = MVE_VLDRBU16_pre %0, 32, 0, $noreg, $noreg :: (load (s128), align 8)
%1:mqpr = MVE_VLDRBU16 %0, 16, 0, $noreg :: (load (s128), align 8) %1:mqpr = MVE_VLDRBU16 %0, 16, 0, $noreg, $noreg :: (load (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRWU32_pre name: MVE_VSTRWU32_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRWU32_pre ; CHECK-LABEL: name: MVE_VSTRWU32_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VSTRWU32_pre:%[0-9]+]]:rgpr = MVE_VSTRWU32_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRWU32_pre:%[0-9]+]]:rgpr = MVE_VSTRWU32_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRWU32 [[COPY]], [[MVE_VSTRWU32_pre]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRWU32 [[COPY]], [[MVE_VSTRWU32_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRWU32_pre]] ; CHECK: $r0 = COPY [[MVE_VSTRWU32_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr = MVE_VSTRWU32_pre %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:rgpr = MVE_VSTRWU32_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRWU32 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRWU32 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRHU16_pre name: MVE_VSTRHU16_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRHU16_pre ; CHECK-LABEL: name: MVE_VSTRHU16_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VSTRHU16_pre:%[0-9]+]]:rgpr = MVE_VSTRHU16_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRHU16_pre:%[0-9]+]]:rgpr = MVE_VSTRHU16_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRHU16 [[COPY]], [[MVE_VSTRHU16_pre]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRHU16 [[COPY]], [[MVE_VSTRHU16_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRHU16_pre]] ; CHECK: $r0 = COPY [[MVE_VSTRHU16_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr = MVE_VSTRHU16_pre %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:rgpr = MVE_VSTRHU16_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRHU16 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRHU16 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRBU8_pre name: MVE_VSTRBU8_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: rgpr, preferred-register: '' } - { id: 0, class: rgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRBU8_pre ; CHECK-LABEL: name: MVE_VSTRBU8_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[MVE_VSTRBU8_pre:%[0-9]+]]:rgpr = MVE_VSTRBU8_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRBU8_pre:%[0-9]+]]:rgpr = MVE_VSTRBU8_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRBU8 [[COPY]], [[MVE_VSTRBU8_pre]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRBU8 [[COPY]], [[MVE_VSTRBU8_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRBU8_pre]] ; CHECK: $r0 = COPY [[MVE_VSTRBU8_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
%2:rgpr = MVE_VSTRBU8_pre %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:rgpr = MVE_VSTRBU8_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRBU8 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRBU8 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRH32_pre name: MVE_VSTRH32_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRH32_pre ; CHECK-LABEL: name: MVE_VSTRH32_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRH32_pre:%[0-9]+]]:tgpr = MVE_VSTRH32_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRH32_pre:%[0-9]+]]:tgpr = MVE_VSTRH32_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRH32 [[COPY]], [[MVE_VSTRH32_pre]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRH32 [[COPY]], [[MVE_VSTRH32_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRH32_pre]] ; CHECK: $r0 = COPY [[MVE_VSTRH32_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr = MVE_VSTRH32_pre %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:tgpr = MVE_VSTRH32_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRH32 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRH32 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRB32_pre name: MVE_VSTRB32_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRB32_pre ; CHECK-LABEL: name: MVE_VSTRB32_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRB32_pre:%[0-9]+]]:tgpr = MVE_VSTRB32_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRB32_pre:%[0-9]+]]:tgpr = MVE_VSTRB32_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRB32 [[COPY]], [[MVE_VSTRB32_pre]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRB32 [[COPY]], [[MVE_VSTRB32_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRB32_pre]] ; CHECK: $r0 = COPY [[MVE_VSTRB32_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr = MVE_VSTRB32_pre %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:tgpr = MVE_VSTRB32_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRB32 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRB32 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: MVE_VSTRB16_pre name: MVE_VSTRB16_pre
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: MVE_VSTRB16_pre ; CHECK-LABEL: name: MVE_VSTRB16_pre
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRB16_pre]] ; CHECK: $r0 = COPY [[MVE_VSTRB16_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRB16 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRB16 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: multiple2 name: multiple2
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: multiple2 ; CHECK-LABEL: name: multiple2
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], -16, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], -16, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], -48, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], -48, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], 2, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre]], 2, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRB16_pre]] ; CHECK: $r0 = COPY [[MVE_VSTRB16_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRB16 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRB16 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRB16 %1, %0, -16, 0, $noreg :: (store (s128), align 8) MVE_VSTRB16 %1, %0, -16, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRB16 %1, %0, 34, 0, $noreg :: (store (s128), align 8) MVE_VSTRB16 %1, %0, 34, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: multiple3 name: multiple3
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
- { id: 3, class: tgpr, preferred-register: '' } - { id: 3, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: multiple3 ; CHECK-LABEL: name: multiple3
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: [[MVE_VSTRB16_pre1:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 64, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRB16_pre1:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 64, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre1]], -48, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRB16 [[COPY]], [[MVE_VSTRB16_pre1]], -48, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRB16_pre1]] ; CHECK: $r0 = COPY [[MVE_VSTRB16_pre1]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
%3:tgpr = MVE_VSTRB16_pre %1, %0, 64, 0, $noreg :: (store (s128), align 8) %3:tgpr = MVE_VSTRB16_pre %1, %0, 64, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRB16 %1, %0, 16, 0, $noreg :: (store (s128), align 8) MVE_VSTRB16 %1, %0, 16, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %3 $r0 = COPY %3
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: multiple4 name: multiple4
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
- { id: 3, class: tgpr, preferred-register: '' } - { id: 3, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: multiple4 ; CHECK-LABEL: name: multiple4
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 32, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRB16 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRB16 [[COPY]], [[COPY1]], 0, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: [[t2ADDri:%[0-9]+]]:tgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2ADDri:%[0-9]+]]:tgpr = nuw t2ADDri [[COPY1]], 32, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r0 = COPY [[t2ADDri]] ; CHECK: $r0 = COPY [[t2ADDri]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg :: (store (s128), align 8) %2:tgpr = MVE_VSTRB16_pre %1, %0, 32, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRB16 %1, %0, 0, 0, $noreg :: (store (s128), align 8) MVE_VSTRB16 %1, %0, 0, 0, $noreg, $noreg :: (store (s128), align 8)
%3:tgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %3:tgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %3 $r0 = COPY %3
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: badScale2 name: badScale2
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: badScale2 ; CHECK-LABEL: name: badScale2
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRBU8_pre:%[0-9]+]]:tgpr = MVE_VSTRBU8_pre [[COPY]], [[COPY1]], 33, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRBU8_pre:%[0-9]+]]:tgpr = MVE_VSTRBU8_pre [[COPY]], [[COPY1]], 33, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRWU32 [[COPY]], [[COPY1]], 0, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRWU32 [[COPY]], [[COPY1]], 0, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRBU8_pre]] ; CHECK: $r0 = COPY [[MVE_VSTRBU8_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr = MVE_VSTRBU8_pre %1, %0, 33, 0, $noreg :: (store (s128), align 8) %2:tgpr = MVE_VSTRBU8_pre %1, %0, 33, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRWU32 %1, %0, 0, 0, $noreg :: (store (s128), align 8) MVE_VSTRWU32 %1, %0, 0, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: badRange2 name: badRange2
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: tgpr, preferred-register: '' } - { id: 2, class: tgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: badRange2 ; CHECK-LABEL: name: badRange2
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 100, 0, $noreg :: (store (s128), align 8) ; CHECK: [[MVE_VSTRB16_pre:%[0-9]+]]:tgpr = MVE_VSTRB16_pre [[COPY]], [[COPY1]], 100, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: MVE_VSTRB16 [[COPY]], [[COPY1]], -100, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRB16 [[COPY]], [[COPY1]], -100, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[MVE_VSTRB16_pre]] ; CHECK: $r0 = COPY [[MVE_VSTRB16_pre]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:tgpr = MVE_VSTRB16_pre %1, %0, 100, 0, $noreg :: (store (s128), align 8) %2:tgpr = MVE_VSTRB16_pre %1, %0, 100, 0, $noreg, $noreg :: (store (s128), align 8)
MVE_VSTRB16 %1, %0, -100, 0, $noreg :: (store (s128), align 8) MVE_VSTRB16 %1, %0, -100, 0, $noreg, $noreg :: (store (s128), align 8)
$r0 = COPY %2 $r0 = COPY %2
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...
--- ---
name: regtype name: regtype
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: tgpr, preferred-register: '' } - { id: 0, class: tgpr, preferred-register: '' }
- { id: 1, class: mqpr, preferred-register: '' } - { id: 1, class: mqpr, preferred-register: '' }
- { id: 2, class: rgpr, preferred-register: '' } - { id: 2, class: rgpr, preferred-register: '' }
- { id: 3, class: rgpr, preferred-register: '' } - { id: 3, class: rgpr, preferred-register: '' }
liveins: liveins:
- { reg: '$r0', virtual-reg: '%0' } - { reg: '$r0', virtual-reg: '%0' }
- { reg: '$q0', virtual-reg: '%1' } - { reg: '$q0', virtual-reg: '%1' }
body: | body: |
bb.0: bb.0:
liveins: $r0, $q0 liveins: $r0, $q0
; CHECK-LABEL: name: regtype ; CHECK-LABEL: name: regtype
; CHECK: liveins: $r0, $q0 ; CHECK: liveins: $r0, $q0
; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:mqpr = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0
; CHECK: [[t2LDRB_POST:%[0-9]+]]:rgpr, [[t2LDRB_POST1:%[0-9]+]]:tgpr = t2LDRB_POST [[COPY1]], 32, 14 /* CC::al */, $noreg :: (load (s8), align 2) ; CHECK: [[t2LDRB_POST:%[0-9]+]]:rgpr, [[t2LDRB_POST1:%[0-9]+]]:tgpr = t2LDRB_POST [[COPY1]], 32, 14 /* CC::al */, $noreg :: (load (s8), align 2)
; CHECK: MVE_VSTRB16 [[COPY]], [[t2LDRB_POST1]], -22, 0, $noreg :: (store (s128), align 8) ; CHECK: MVE_VSTRB16 [[COPY]], [[t2LDRB_POST1]], -22, 0, $noreg, $noreg :: (store (s128), align 8)
; CHECK: $r0 = COPY [[t2LDRB_POST1]] ; CHECK: $r0 = COPY [[t2LDRB_POST1]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
%1:mqpr = COPY $q0 %1:mqpr = COPY $q0
%0:tgpr = COPY $r0 %0:tgpr = COPY $r0
%2:rgpr = t2LDRBi12 %0:tgpr, 0, 14, $noreg :: (load (s8), align 2) %2:rgpr = t2LDRBi12 %0:tgpr, 0, 14, $noreg :: (load (s8), align 2)
MVE_VSTRB16 %1, %0, 10, 0, $noreg :: (store (s128), align 8) MVE_VSTRB16 %1, %0, 10, 0, $noreg, $noreg :: (store (s128), align 8)
%3:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg %3:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
$r0 = COPY %3 $r0 = COPY %3
tBX_RET 14, $noreg, implicit $r0 tBX_RET 14, $noreg, implicit $r0
... ...

llvm/test/CodeGen/Thumb2/mve-stacksplot.mir

Show All 35 Lines bb.0:
; CHECK: $r8 = IMPLICIT_DEF ; CHECK: $r8 = IMPLICIT_DEF
; CHECK: $r9 = IMPLICIT_DEF ; CHECK: $r9 = IMPLICIT_DEF
; CHECK: $r10 = IMPLICIT_DEF ; CHECK: $r10 = IMPLICIT_DEF
; CHECK: $r11 = IMPLICIT_DEF ; CHECK: $r11 = IMPLICIT_DEF
; CHECK: $r12 = IMPLICIT_DEF ; CHECK: $r12 = IMPLICIT_DEF
; CHECK: $lr = IMPLICIT_DEF ; CHECK: $lr = IMPLICIT_DEF
; CHECK: t2STRi12 killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1) ; CHECK: t2STRi12 killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1)
; CHECK: $r0 = tMOVr killed $sp, 14 /* CC::al */, $noreg ; CHECK: $r0 = tMOVr killed $sp, 14 /* CC::al */, $noreg
; CHECK: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg :: (load (s32) from %stack.0 + 12) ; CHECK: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg, $noreg :: (load (s32) from %stack.0 + 12)
; CHECK: $r0 = t2LDRi12 $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1) ; CHECK: $r0 = t2LDRi12 $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.1)
; CHECK: KILL $r0 ; CHECK: KILL $r0
; CHECK: KILL $r1 ; CHECK: KILL $r1
; CHECK: KILL $r2 ; CHECK: KILL $r2
; CHECK: KILL $r3 ; CHECK: KILL $r3
; CHECK: KILL $r4 ; CHECK: KILL $r4
; CHECK: KILL $r5 ; CHECK: KILL $r5
; CHECK: KILL $r6 ; CHECK: KILL $r6
Show All 14 Lines bb.0:
$r7 = IMPLICIT_DEF $r7 = IMPLICIT_DEF
$r8 = IMPLICIT_DEF $r8 = IMPLICIT_DEF
$r9 = IMPLICIT_DEF $r9 = IMPLICIT_DEF
$r10 = IMPLICIT_DEF $r10 = IMPLICIT_DEF
$r11 = IMPLICIT_DEF $r11 = IMPLICIT_DEF
$r12 = IMPLICIT_DEF $r12 = IMPLICIT_DEF
$lr = IMPLICIT_DEF $lr = IMPLICIT_DEF
renamable $q2 = MVE_VLDRBU32 %stack.0, 12, 0, $noreg :: (load (s32) from %stack.0 + 12) renamable $q2 = MVE_VLDRBU32 %stack.0, 12, 0, $noreg, $noreg :: (load (s32) from %stack.0 + 12)
KILL $r0 KILL $r0
KILL $r1 KILL $r1
KILL $r2 KILL $r2
KILL $r3 KILL $r3
KILL $r4 KILL $r4
KILL $r5 KILL $r5
KILL $r6 KILL $r6
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines bb.0:
; CHECK: $r8 = IMPLICIT_DEF ; CHECK: $r8 = IMPLICIT_DEF
; CHECK: $r9 = IMPLICIT_DEF ; CHECK: $r9 = IMPLICIT_DEF
; CHECK: $r10 = IMPLICIT_DEF ; CHECK: $r10 = IMPLICIT_DEF
; CHECK: $r11 = IMPLICIT_DEF ; CHECK: $r11 = IMPLICIT_DEF
; CHECK: $r12 = IMPLICIT_DEF ; CHECK: $r12 = IMPLICIT_DEF
; CHECK: $lr = IMPLICIT_DEF ; CHECK: $lr = IMPLICIT_DEF
; CHECK: t2STRi12 killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2) ; CHECK: t2STRi12 killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.2)
; CHECK: $r0 = t2ADDri killed $sp, 1152, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r0 = t2ADDri killed $sp, 1152, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg :: (load (s32) from %stack.0) ; CHECK: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg, $noreg :: (load (s32) from %stack.0)
; CHECK: $r0 = t2LDRi12 $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2) ; CHECK: $r0 = t2LDRi12 $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.2)
; CHECK: KILL $r0 ; CHECK: KILL $r0
; CHECK: KILL $r1 ; CHECK: KILL $r1
; CHECK: KILL $r2 ; CHECK: KILL $r2
; CHECK: KILL $r3 ; CHECK: KILL $r3
; CHECK: KILL $r4 ; CHECK: KILL $r4
; CHECK: KILL $r5 ; CHECK: KILL $r5
; CHECK: KILL $r6 ; CHECK: KILL $r6
Show All 14 Lines bb.0:
$r7 = IMPLICIT_DEF $r7 = IMPLICIT_DEF
$r8 = IMPLICIT_DEF $r8 = IMPLICIT_DEF
$r9 = IMPLICIT_DEF $r9 = IMPLICIT_DEF
$r10 = IMPLICIT_DEF $r10 = IMPLICIT_DEF
$r11 = IMPLICIT_DEF $r11 = IMPLICIT_DEF
$r12 = IMPLICIT_DEF $r12 = IMPLICIT_DEF
$lr = IMPLICIT_DEF $lr = IMPLICIT_DEF
renamable $q2 = MVE_VLDRBU8 %stack.0, 0, 0, $noreg :: (load (s32) from %stack.0) renamable $q2 = MVE_VLDRBU8 %stack.0, 0, 0, $noreg, $noreg :: (load (s32) from %stack.0)
KILL $r0 KILL $r0
KILL $r1 KILL $r1
KILL $r2 KILL $r2
KILL $r3 KILL $r3
KILL $r4 KILL $r4
KILL $r5 KILL $r5
KILL $r6 KILL $r6
KILL $r7 KILL $r7
KILL $r8 KILL $r8
KILL $r9 KILL $r9
KILL $r10 KILL $r10
KILL $r11 KILL $r11
KILL $r12 KILL $r12
KILL $lr KILL $lr
... ...

llvm/test/CodeGen/Thumb2/mve-tp-loop.mir

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2
; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]] ; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]
; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.2, implicit-def $cpsr ; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.2, implicit-def $cpsr
; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
; CHECK: .1: ; CHECK: .1:
; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.0, %7, %bb.1 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.0, %7, %bb.1
; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.0, %9, %bb.1 ; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.0, %9, %bb.1
; CHECK: [[PHI2:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.0, %11, %bb.1 ; CHECK: [[PHI2:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.0, %11, %bb.1
; CHECK: [[PHI3:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.0, %13, %bb.1 ; CHECK: [[PHI3:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.0, %13, %bb.1
; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI3]], 0, $noreg ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI3]], 0, $noreg, $noreg
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI3]], 16, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI3]], 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[PHI]], 16, 1, [[MVE_VCTP8_]] ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg
; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VLDRBU8_post1]], [[PHI1]], 16, 1, [[MVE_VCTP8_]] ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VLDRBU8_post1]], [[PHI1]], 16, 1, [[MVE_VCTP8_]], $noreg
; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI2]], 1 ; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI2]], 1
; CHECK: t2LoopEnd [[t2LoopDec]], %bb.1, implicit-def $cpsr ; CHECK: t2LoopEnd [[t2LoopDec]], %bb.1, implicit-def $cpsr
; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
; CHECK: .2.entry: ; CHECK: .2.entry:
; CHECK: tBX_RET 14 /* CC::al */, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
%2:rgpr = COPY $r2 %2:rgpr = COPY $r2
%1:rgpr = COPY $r1 %1:rgpr = COPY $r1
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
Show All 15 Linesbody: |
; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, $cpsr ; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, $cpsr
; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1.for.body.preheader: ; CHECK: bb.1.for.body.preheader:
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]] ; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]
; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.4, implicit-def $cpsr ; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.4, implicit-def $cpsr
; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.1, %7, %bb.3 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.1, %7, %bb.3
; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %9, %bb.3 ; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %9, %bb.3
; CHECK: [[PHI2:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.1, %11, %bb.3 ; CHECK: [[PHI2:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.1, %11, %bb.3
; CHECK: [[PHI3:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %13, %bb.3 ; CHECK: [[PHI3:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %13, %bb.3
; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI3]], 0, $noreg ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI3]], 0, $noreg, $noreg
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI3]], 16, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI3]], 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[PHI]], 16, 1, [[MVE_VCTP8_]] ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg
; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VLDRBU8_post1]], [[PHI1]], 16, 1, [[MVE_VCTP8_]] ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[MVE_VLDRBU8_post1]], [[PHI1]], 16, 1, [[MVE_VCTP8_]], $noreg
; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI2]], 1 ; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI2]], 1
; CHECK: t2LoopEnd [[t2LoopDec]], %bb.3, implicit-def $cpsr ; CHECK: t2LoopEnd [[t2LoopDec]], %bb.3, implicit-def $cpsr
; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.4.for.body.preheader: ; CHECK: bb.4.for.body.preheader:
; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tBX_RET 14 /* CC::al */, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
bb.0.entry: bb.0.entry:
Show All 27 Lines bb.0.entry:
; CHECK: liveins: $r0, $r1, $r2 ; CHECK: liveins: $r0, $r1, $r2
; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2 ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r2
; CHECK: [[COPY1:%[0-9]+]]:mqpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:mqpr = COPY $r1
; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r0
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]] ; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]
; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.2, implicit-def $cpsr ; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.2, implicit-def $cpsr
; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
; CHECK: .1: ; CHECK: .1:
; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.0, %7, %bb.1 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.0, %7, %bb.1
; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.0, %9, %bb.1 ; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.0, %9, %bb.1
; CHECK: [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.0, %11, %bb.1 ; CHECK: [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.0, %11, %bb.1
; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg, $noreg
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY1]], [[PHI]], 16, 1, [[MVE_VCTP8_]] ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY1]], [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg
; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI1]], 1 ; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI1]], 1
; CHECK: t2LoopEnd [[t2LoopDec]], %bb.1, implicit-def $cpsr ; CHECK: t2LoopEnd [[t2LoopDec]], %bb.1, implicit-def $cpsr
; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
; CHECK: .2.entry: ; CHECK: .2.entry:
; CHECK: tBX_RET 14 /* CC::al */, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
%2:rgpr = COPY $r2 %2:rgpr = COPY $r2
%1:mqpr = COPY $r1 %1:mqpr = COPY $r1
%0:rgpr = COPY $r0 %0:rgpr = COPY $r0
Show All 16 Linesbody: |
; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, $cpsr ; CHECK: t2Bcc %bb.2, 11 /* CC::lt */, $cpsr
; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1.for.body.preheader: ; CHECK: bb.1.for.body.preheader:
; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 15, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = t2LSRri killed [[t2ADDri]], 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]] ; CHECK: [[t2WhileLoopSetup:%[0-9]+]]:gprlr = t2WhileLoopSetup killed [[t2LSRri]]
; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.4, implicit-def $cpsr ; CHECK: t2WhileLoopStart [[t2WhileLoopSetup]], %bb.4, implicit-def $cpsr
; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %7, %bb.3 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.1, %7, %bb.3
; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.1, %9, %bb.3 ; CHECK: [[PHI1:%[0-9]+]]:gprlr = PHI [[t2WhileLoopSetup]], %bb.1, %9, %bb.3
; CHECK: [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %11, %bb.3 ; CHECK: [[PHI2:%[0-9]+]]:rgpr = PHI [[COPY]], %bb.1, %11, %bb.3
; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[PHI2]], 0, $noreg, $noreg
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY1]], [[PHI]], 16, 1, [[MVE_VCTP8_]] ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post [[COPY1]], [[PHI]], 16, 1, [[MVE_VCTP8_]], $noreg
; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI1]], 1 ; CHECK: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[PHI1]], 1
; CHECK: t2LoopEnd [[t2LoopDec]], %bb.3, implicit-def $cpsr ; CHECK: t2LoopEnd [[t2LoopDec]], %bb.3, implicit-def $cpsr
; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg
; CHECK: bb.4.for.body.preheader: ; CHECK: bb.4.for.body.preheader:
; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.2.for.cond.cleanup: ; CHECK: bb.2.for.cond.cleanup:
; CHECK: tBX_RET 14 /* CC::al */, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
bb.0.entry: bb.0.entry:
Show All 17 Lines

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12
; CHECK-LABEL: name: vpt_2_blocks_1_pred ; CHECK-LABEL: name: vpt_2_blocks_1_pred
; CHECK: successors: %bb.0(0x80000000) ; CHECK: successors: %bb.0(0x80000000)
; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12 ; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12
; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14 /* CC::al */, $noreg, $noreg
; CHECK: BUNDLE implicit-def $vpr, implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $q1, implicit $q5, implicit killed $r4 { ; CHECK: BUNDLE implicit-def $vpr, implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $q1, implicit $q5, implicit killed $r4 {
; CHECK: MVE_VPTv4u32 8, renamable $q1, renamable $q5, 2, implicit-def $vpr ; CHECK: MVE_VPTv4u32 8, renamable $q1, renamable $q5, 2, implicit-def $vpr
; CHECK: renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, internal renamable $vpr ; CHECK: renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, internal renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14 /* CC::al */, $noreg, $noreg
; CHECK: BUNDLE implicit-def $q7, implicit-def $d14, implicit-def $s28, implicit-def $s29, implicit-def $d15, implicit-def $s30, implicit-def $s31, implicit killed $vpr, implicit killed $r4 { ; CHECK: BUNDLE implicit-def $q7, implicit-def $d14, implicit-def $s28, implicit-def $s29, implicit-def $d15, implicit-def $s30, implicit-def $s31, implicit killed $vpr, implicit killed $r4 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr ; CHECK: renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr ; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr
; CHECK: t2B %bb.0, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.0, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg, $noreg
renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg
renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg
renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14, $noreg, $noreg renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14, $noreg, $noreg
renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr, $noreg
t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr
t2B %bb.0, 14, $noreg t2B %bb.0, 14, $noreg
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
constants: [] constants: []
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $r0, $r1 liveins: $q0, $q1, $q2, $r0, $r1
; CHECK-LABEL: name: vpt_2_blocks_2_preds ; CHECK-LABEL: name: vpt_2_blocks_2_preds
; CHECK: liveins: $q0, $q1, $q2, $r0, $r1 ; CHECK: liveins: $q0, $q1, $q2, $r0, $r1
; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit killed $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit killed $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q3
; CHECK: } ; CHECK: }
; CHECK: $vpr = VMSR_P0 killed $r1, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 killed $r1, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q3, implicit killed $q2, implicit killed $q0 { ; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q3, implicit killed $q2, implicit killed $q0 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q3
$vpr = VMSR_P0 killed $r1, 14, $noreg $vpr = VMSR_P0 killed $r1, 14, $noreg
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
stack: [] stack: []
constants: [] constants: []
body: | body: |
; CHECK-LABEL: name: vpt_2_blocks_ctrl_flow ; CHECK-LABEL: name: vpt_2_blocks_ctrl_flow
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q0, $q1, $q2, $r0 ; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal renamable $q3, internal renamable $q3, 1, renamable $vpr, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal renamable $q3, internal renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q1
; CHECK: } ; CHECK: }
; CHECK: bb.1.bb2: ; CHECK: bb.1.bb2:
; CHECK: liveins: $q0, $q1, $q2, $q3, $vpr ; CHECK: liveins: $q0, $q1, $q2, $q3, $vpr
; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 { ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $r0 liveins: $q0, $q1, $q2, $r0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 renamable $q3, renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q1
bb.1.bb2: bb.1.bb2:
liveins: $q0, $q1, $q2, $q3, $vpr liveins: $q0, $q1, $q2, $q3, $vpr
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $r0 liveins: $q0, $q1, $q2, $r0
; CHECK-LABEL: name: vpt_2_blocks_non_consecutive_ins ; CHECK-LABEL: name: vpt_2_blocks_non_consecutive_ins
; CHECK: liveins: $q0, $q1, $q2, $r0 ; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 1, renamable $vpr, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q1
; CHECK: } ; CHECK: }
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 { ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q1
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $q3, $r0 liveins: $q0, $q1, $q2, $q3, $r0
; CHECK-LABEL: name: vpt_2_blocks ; CHECK-LABEL: name: vpt_2_blocks
; CHECK: liveins: $q0, $q1, $q2, $q3, $r0 ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def dead $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $vpr, implicit killed $q2, implicit $q3, implicit killed $q0 { ; CHECK: BUNDLE implicit-def dead $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $vpr, implicit killed $q2, implicit $q3, implicit killed $q0 {
; CHECK: MVE_VPST 1, implicit $vpr ; CHECK: MVE_VPST 1, implicit $vpr
; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2 ; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q2
; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, internal renamable $q2, 1, renamable $vpr, internal undef renamable $q2 ; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, internal renamable $q2, 1, renamable $vpr, $noreg, internal undef renamable $q2
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, renamable $q3, 1, renamable $vpr, $noreg, killed renamable $q0
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, renamable $q3, 1, renamable $vpr, internal undef renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, renamable $q3, 1, renamable $vpr, $noreg, internal undef renamable $q0
; CHECK: } ; CHECK: }
; CHECK: BUNDLE implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q0, implicit killed $q3, implicit killed $q1 { ; CHECK: BUNDLE implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q0, implicit killed $q3, implicit killed $q1 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, $noreg, killed renamable $q1
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2 renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q2
renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, undef renamable $q2 renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, undef renamable $q2
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, $noreg, killed renamable $q0
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, renamable $q3, 1, renamable $vpr, undef renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q0
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, $noreg, killed renamable $q1
$q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
constants: [] constants: []
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $r0 liveins: $q0, $q1, $q2, $r0
; CHECK-LABEL: name: vpt_3_blocks_kill_vpr ; CHECK-LABEL: name: vpt_3_blocks_kill_vpr
; CHECK: liveins: $q0, $q1, $q2, $r0 ; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 {
; CHECK: MVE_VPST 12, implicit $vpr ; CHECK: MVE_VPST 12, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 2, renamable $vpr, undef renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, internal renamable $q3, 2, renamable $vpr, $noreg, undef renamable $q1
; CHECK: } ; CHECK: }
; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 { ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, undef renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q1
$q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $r0 liveins: $q0, $q1, $q2, $r0
; CHECK-LABEL: name: vpt_block_1_ins ; CHECK-LABEL: name: vpt_block_1_ins
; CHECK: liveins: $q0, $q1, $q2, $r0 ; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q0 { ; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q0 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $q3, $r0 liveins: $q0, $q1, $q2, $q3, $r0
; CHECK-LABEL: name: vpt_block_2_ins ; CHECK-LABEL: name: vpt_block_2_ins
; CHECK: liveins: $q0, $q1, $q2, $q3, $r0 ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q2, implicit killed $q3, implicit killed $q0, implicit killed $q1 { ; CHECK: BUNDLE implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q2, implicit killed $q3, implicit killed $q0, implicit killed $q1 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, $noreg, killed renamable $q0
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, $noreg, killed renamable $q1
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, $noreg, killed renamable $q0
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, $noreg, killed renamable $q1
$q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2, $q3, $r0 liveins: $q0, $q1, $q2, $q3, $r0
; CHECK-LABEL: name: vpt_block_4_ins ; CHECK-LABEL: name: vpt_block_4_ins
; CHECK: liveins: $q0, $q1, $q2, $q3, $r0 ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def dead $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q2, implicit killed $q3, implicit killed $q0, implicit killed $q1 { ; CHECK: BUNDLE implicit-def dead $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q2, implicit killed $q3, implicit killed $q0, implicit killed $q1 {
; CHECK: MVE_VPST 1, implicit $vpr ; CHECK: MVE_VPST 1, implicit $vpr
; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2 ; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q2
; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, internal renamable $q2, 1, renamable $vpr, internal undef renamable $q2 ; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, internal renamable $q2, 1, renamable $vpr, $noreg, internal undef renamable $q2
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q2, renamable $q3, 1, renamable $vpr, $noreg, killed renamable $q0
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, $noreg, killed renamable $q1
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2 renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q2
renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, undef renamable $q2 renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, undef renamable $q2
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, $noreg, killed renamable $q0
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, $noreg, killed renamable $q1
$q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-block-debug.mir

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK: DBG_VALUE $q0, $noreg, !17, !DIExpression(), debug-location !21 ; CHECK: DBG_VALUE $q0, $noreg, !17, !DIExpression(), debug-location !21
; CHECK: DBG_VALUE $q1, $noreg, !18, !DIExpression(), debug-location !21 ; CHECK: DBG_VALUE $q1, $noreg, !18, !DIExpression(), debug-location !21
; CHECK: DBG_VALUE $q1, $noreg, !18, !DIExpression(), debug-location !21 ; CHECK: DBG_VALUE $q1, $noreg, !18, !DIExpression(), debug-location !21
; CHECK: DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21 ; CHECK: DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
; CHECK: DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21 ; CHECK: DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
; CHECK: DBG_VALUE $noreg, $noreg, !20, !DIExpression(), debug-location !21 ; CHECK: DBG_VALUE $noreg, $noreg, !20, !DIExpression(), debug-location !21
; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit killed $q1, implicit killed $q0, implicit killed $q2, debug-location !23 { ; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit killed $q1, implicit killed $q0, implicit killed $q2, debug-location !23 {
; CHECK: MVE_VPTv4s32 12, renamable $q1, renamable $q0, 10, implicit-def $vpr, debug-location !23 ; CHECK: MVE_VPTv4s32 12, renamable $q1, renamable $q0, 10, implicit-def $vpr, debug-location !23
; CHECK: renamable $q2 = MVE_VADDi32 renamable $q0, renamable $q1, 1, internal renamable $vpr, killed renamable $q2, debug-location !23 ; CHECK: renamable $q2 = MVE_VADDi32 renamable $q0, renamable $q1, 1, internal renamable $vpr, $noreg, killed renamable $q2, debug-location !23
; CHECK: DBG_VALUE $noreg, $noreg, !20, !DIExpression(), debug-location !21 ; CHECK: DBG_VALUE $noreg, $noreg, !20, !DIExpression(), debug-location !21
; CHECK: DBG_VALUE internal $q2, $noreg, !19, !DIExpression(), debug-location !21 ; CHECK: DBG_VALUE internal $q2, $noreg, !19, !DIExpression(), debug-location !21
; CHECK: renamable $q2 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 2, internal killed renamable $vpr, internal killed renamable $q2, debug-location !25 ; CHECK: renamable $q2 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 2, internal killed renamable $vpr, $noreg, internal killed renamable $q2, debug-location !25
; CHECK: DBG_VALUE internal $q2, $noreg, !19, !DIExpression(), debug-location !21 ; CHECK: DBG_VALUE internal $q2, $noreg, !19, !DIExpression(), debug-location !21
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q2, killed $q2, 0, $noreg, undef $q0, debug-location !26 ; CHECK: $q0 = MVE_VORR killed $q2, killed $q2, 0, $noreg, $noreg, undef $q0, debug-location !26
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0, debug-location !26 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0, debug-location !26
DBG_VALUE $q0, $noreg, !17, !DIExpression(), debug-location !21 DBG_VALUE $q0, $noreg, !17, !DIExpression(), debug-location !21
DBG_VALUE $q0, $noreg, !17, !DIExpression(), debug-location !21 DBG_VALUE $q0, $noreg, !17, !DIExpression(), debug-location !21
DBG_VALUE $q1, $noreg, !18, !DIExpression(), debug-location !21 DBG_VALUE $q1, $noreg, !18, !DIExpression(), debug-location !21
DBG_VALUE $q1, $noreg, !18, !DIExpression(), debug-location !21 DBG_VALUE $q1, $noreg, !18, !DIExpression(), debug-location !21
DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21 DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21 DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 10, 0, $noreg, debug-location !22 renamable $vpr = MVE_VCMPs32 renamable $q1, renamable $q0, 10, 0, $noreg, $noreg, debug-location !22
DBG_VALUE $noreg, $noreg, !20, !DIExpression(), debug-location !21 DBG_VALUE $noreg, $noreg, !20, !DIExpression(), debug-location !21
renamable $q2 = MVE_VADDi32 renamable $q0, renamable $q1, 1, renamable $vpr, killed renamable $q2, debug-location !23 renamable $q2 = MVE_VADDi32 renamable $q0, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q2, debug-location !23
DBG_VALUE $noreg, $noreg, !20, !DIExpression(), debug-location !21 DBG_VALUE $noreg, $noreg, !20, !DIExpression(), debug-location !21
DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21 DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, debug-location !24 renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg, debug-location !24
renamable $q2 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, killed renamable $q2, debug-location !25 renamable $q2 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, $noreg, killed renamable $q2, debug-location !25
DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21 DBG_VALUE $q2, $noreg, !19, !DIExpression(), debug-location !21
$q0 = MVE_VORR killed $q2, killed $q2, 0, $noreg, undef $q0, debug-location !26 $q0 = MVE_VORR killed $q2, killed $q2, 0, $noreg, $noreg, undef $q0, debug-location !26
tBX_RET 14 /* CC::al */, $noreg, implicit $q0, debug-location !26 tBX_RET 14 /* CC::al */, $noreg, implicit $q0, debug-location !26
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-block-elses.mir

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
stack: [] stack: []
constants: [] constants: []
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2 liveins: $q0, $q1, $q2
; CHECK-LABEL: name: vpt_block_else ; CHECK-LABEL: name: vpt_block_else
; CHECK: liveins: $q0, $q1, $q2 ; CHECK: liveins: $q0, $q1, $q2
; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit killed $q0, implicit $q2, implicit $q1, implicit killed $q3, implicit $zr { ; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit killed $q0, implicit $q2, implicit $q1, implicit killed $q3, implicit $zr {
; CHECK: MVE_VPTv4s32 7, renamable $q0, renamable $q2, 10, implicit-def $vpr ; CHECK: MVE_VPTv4s32 7, renamable $q0, renamable $q2, 10, implicit-def $vpr
; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q0, $zr, 12, 1, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q0, $zr, 12, 1, internal killed renamable $vpr, $noreg
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 2, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 2, internal killed renamable $vpr, $noreg
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, internal renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, $noreg, internal renamable $q3
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR $q3, $q3, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR $q3, $q3, 0, $noreg, $noreg, undef $q0
; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit killed $q0, implicit $q2, implicit $q1, implicit killed $q3, implicit $zr { ; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit killed $q0, implicit $q2, implicit $q1, implicit killed $q3, implicit $zr {
; CHECK: MVE_VPTv4s32 7, renamable $q0, renamable $q2, 10, implicit-def $vpr ; CHECK: MVE_VPTv4s32 7, renamable $q0, renamable $q2, 10, implicit-def $vpr
; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q0, $zr, 12, 1, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q0, $zr, 12, 1, internal killed renamable $vpr, $noreg
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, internal renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, $noreg, internal renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, internal renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, $noreg, internal renamable $q3
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR $q3, $q3, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR $q3, $q3, 0, $noreg, $noreg, undef $q0
; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit $q1, implicit killed $q3, implicit $zr { ; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit $q1, implicit killed $q3, implicit $zr {
; CHECK: MVE_VPTv4s32 15, renamable $q0, renamable $q2, 10, implicit-def $vpr ; CHECK: MVE_VPTv4s32 15, renamable $q0, renamable $q2, 10, implicit-def $vpr
; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, internal renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, $noreg, internal renamable $q3
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 2, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 2, internal killed renamable $vpr, $noreg
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, internal killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, $noreg, internal killed renamable $q3
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit $q1, implicit killed $q3, implicit $zr { ; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit $q1, implicit killed $q3, implicit $zr {
; CHECK: MVE_VPTv4s32 15, renamable $q0, renamable $q2, 10, implicit-def $vpr ; CHECK: MVE_VPTv4s32 15, renamable $q0, renamable $q2, 10, implicit-def $vpr
; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 2, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 2, internal killed renamable $vpr, $noreg
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, internal renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, $noreg, internal renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, internal killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, $noreg, internal killed renamable $q3
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit $q1, implicit killed $q3 { ; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit $q1, implicit killed $q3 {
; CHECK: MVE_VPTv4s32 15, renamable $q0, renamable $q2, 10, implicit-def $vpr ; CHECK: MVE_VPTv4s32 15, renamable $q0, renamable $q2, 10, implicit-def $vpr
; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, internal renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, $noreg, internal renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, internal renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, $noreg, internal renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, internal killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, $noreg, internal killed renamable $q3
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit $q1, implicit killed $q3 { ; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit $q1, implicit killed $q3 {
; CHECK: MVE_VPTv4s32 14, renamable $q0, renamable $q2, 10, implicit-def $vpr ; CHECK: MVE_VPTv4s32 14, renamable $q0, renamable $q2, 10, implicit-def $vpr
; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, internal renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, $noreg, internal renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, internal killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, $noreg, internal killed renamable $q3
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit $q1, implicit killed $q3, implicit $zr { ; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit $q1, implicit killed $q3, implicit $zr {
; CHECK: MVE_VPTv4s32 14, renamable $q0, renamable $q2, 10, implicit-def $vpr ; CHECK: MVE_VPTv4s32 14, renamable $q0, renamable $q2, 10, implicit-def $vpr
; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 2, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 2, internal killed renamable $vpr, $noreg
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, internal killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, $noreg, internal killed renamable $q3
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit $q1, implicit killed $q3 { ; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit $q1, implicit killed $q3 {
; CHECK: MVE_VPTv4s32 6, renamable $q0, renamable $q2, 10, implicit-def $vpr ; CHECK: MVE_VPTv4s32 6, renamable $q0, renamable $q2, 10, implicit-def $vpr
; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, internal renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, internal renamable $vpr, internal killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, internal renamable $vpr, $noreg, internal killed renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, internal killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal killed renamable $vpr, $noreg, internal killed renamable $q3
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit killed $q3 { ; CHECK: BUNDLE implicit-def $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit killed $q3 {
; CHECK: MVE_VPTv4s32 11, renamable $q0, renamable $q2, 10, implicit-def $vpr ; CHECK: MVE_VPTv4s32 11, renamable $q0, renamable $q2, 10, implicit-def $vpr
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, internal renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, internal renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, internal killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, $noreg, internal killed renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, internal renamable $vpr, internal killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, internal renamable $vpr, $noreg, internal killed renamable $q3
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, internal killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, $noreg, internal killed renamable $q3
; CHECK: } ; CHECK: }
; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 ; CHECK: $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 ; CHECK: $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
; CHECK: BUNDLE implicit-def $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit killed $q3 { ; CHECK: BUNDLE implicit-def $vpr, implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $q0, implicit $q2, implicit killed $q3 {
; CHECK: MVE_VPTv4s32 13, renamable $q0, renamable $q2, 10, implicit-def $vpr ; CHECK: MVE_VPTv4s32 13, renamable $q0, renamable $q2, 10, implicit-def $vpr
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, internal renamable $vpr, killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, internal renamable $vpr, $noreg, killed renamable $q3
; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 11, 2, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 11, 2, internal killed renamable $vpr, $noreg
; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, internal killed renamable $q3 ; CHECK: renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 2, internal renamable $vpr, $noreg, internal killed renamable $q3
; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 11, 1, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 11, 1, internal killed renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg, $noreg
$q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VCMPs32r killed renamable $q0, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r killed renamable $q0, $zr, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, $noreg, renamable $q3
$q0 = MVE_VORR $q3, $q3, 0, $noreg, undef $q0 $q0 = MVE_VORR $q3, $q3, 0, $noreg, $noreg, undef $q0
renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg, $noreg
$q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VCMPs32r killed renamable $q0, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r killed renamable $q0, $zr, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, renamable $q3
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, $noreg, renamable $q3
$q0 = MVE_VORR $q3, $q3, 0, $noreg, undef $q0 $q0 = MVE_VORR $q3, $q3, 0, $noreg, $noreg, undef $q0
renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg, $noreg
$q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, renamable $q3
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q3
$q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg, $noreg
$q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, renamable $q3
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q3
$q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg, $noreg
$q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, renamable $q3
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, renamable $q3
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q3
$q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg, $noreg
$q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, renamable $q3
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q3
$q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg, $noreg
$q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q3
$q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg, $noreg
$q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VMAXs32 renamable $q0, renamable $q1, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q3
$q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
$q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
$q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, undef $q0 $q0 = MVE_VORR killed $q3, killed $q3, 0, $noreg, $noreg, undef $q0
$q3 = MVE_VORR $q2, $q2, 0, $noreg, undef $q3 $q3 = MVE_VORR $q2, $q2, 0, $noreg, $noreg, undef $q3
renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 10, 0, $noreg, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 11, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 11, 1, killed renamable $vpr, $noreg
renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, killed renamable $q3 renamable $q3 = MVE_VORR renamable $q2, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 11, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32 renamable $q0, renamable $q2, 11, 1, killed renamable $vpr, $noreg
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
; CHECK: $r7 = frame-setup tMOVr killed $sp, 14 /* CC::al */, $noreg ; CHECK: $r7 = frame-setup tMOVr killed $sp, 14 /* CC::al */, $noreg
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $r12 = t2LDRi12 $r7, 16, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.2) ; CHECK: renamable $r12 = t2LDRi12 $r7, 16, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.2)
; CHECK: renamable $lr = t2LDRi12 $r7, 12, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1) ; CHECK: renamable $lr = t2LDRi12 $r7, 12, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1)
; CHECK: renamable $r3 = t2LDRi12 $r7, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0) ; CHECK: renamable $r3 = t2LDRi12 $r7, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0)
; CHECK: BUNDLE implicit-def $vpr, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $q0, implicit $zr, implicit killed $r0, implicit killed $r3, implicit killed $r1, implicit killed $lr { ; CHECK: BUNDLE implicit-def $vpr, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $q0, implicit $zr, implicit killed $r0, implicit killed $r3, implicit killed $r1, implicit killed $lr {
; CHECK: MVE_VPTv4f32r 1, renamable $q0, $zr, 10, implicit-def $vpr ; CHECK: MVE_VPTv4f32r 1, renamable $q0, $zr, 10, implicit-def $vpr
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r0, 0, 1, internal renamable $vpr :: (load (s128) from %ir.src, align 4) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r0, 0, 1, internal renamable $vpr, $noreg :: (load (s128) from %ir.src, align 4)
; CHECK: MVE_VSTRWU32 internal killed renamable $q0, killed renamable $r3, 0, 1, internal renamable $vpr :: (store (s128) into %ir.dest, align 4) ; CHECK: MVE_VSTRWU32 internal killed renamable $q0, killed renamable $r3, 0, 1, internal renamable $vpr, $noreg :: (store (s128) into %ir.dest, align 4)
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 1, internal renamable $vpr :: (load (s128) from %ir.src2, align 4) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 1, internal renamable $vpr, $noreg :: (load (s128) from %ir.src2, align 4)
; CHECK: MVE_VSTRWU32 internal killed renamable $q0, killed renamable $lr, 0, 1, internal renamable $vpr :: (store (s128) into %ir.dest2, align 4) ; CHECK: MVE_VSTRWU32 internal killed renamable $q0, killed renamable $lr, 0, 1, internal renamable $vpr, $noreg :: (store (s128) into %ir.dest2, align 4)
; CHECK: } ; CHECK: }
; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $r2, implicit killed $r12 { ; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $r2, implicit killed $r12 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 1, renamable $vpr :: (load (s128) from %ir.src3, align 4) ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.src3, align 4)
; CHECK: MVE_VSTRWU32 internal renamable $q0, killed renamable $r12, 0, 1, killed renamable $vpr :: (store (s128) into %ir.dest3, align 4) ; CHECK: MVE_VSTRWU32 internal renamable $q0, killed renamable $r12, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.dest3, align 4)
; CHECK: } ; CHECK: }
; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc, implicit $q0 ; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc, implicit $q0
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8 frame-setup CFI_INSTRUCTION offset $r7, -8
$r7 = frame-setup tMOVr killed $sp, 14, $noreg $r7 = frame-setup tMOVr killed $sp, 14, $noreg
frame-setup CFI_INSTRUCTION def_cfa_register $r7 frame-setup CFI_INSTRUCTION def_cfa_register $r7
renamable $r12 = t2LDRi12 $r7, 16, 14, $noreg :: (load (s32) from %fixed-stack.1) renamable $r12 = t2LDRi12 $r7, 16, 14, $noreg :: (load (s32) from %fixed-stack.1)
renamable $lr = t2LDRi12 $r7, 12, 14, $noreg :: (load (s32) from %fixed-stack.2) renamable $lr = t2LDRi12 $r7, 12, 14, $noreg :: (load (s32) from %fixed-stack.2)
renamable $r3 = t2LDRi12 $r7, 8, 14, $noreg :: (load (s32) from %fixed-stack.3) renamable $r3 = t2LDRi12 $r7, 8, 14, $noreg :: (load (s32) from %fixed-stack.3)
renamable $vpr = MVE_VCMPf32r renamable $q0, $zr, 10, 0, $noreg renamable $vpr = MVE_VCMPf32r renamable $q0, $zr, 10, 0, $noreg, $noreg
renamable $q0 = MVE_VLDRWU32 killed renamable $r0, 0, 1, renamable $vpr :: (load (s128) from %ir.src, align 4) renamable $q0 = MVE_VLDRWU32 killed renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.src, align 4)
MVE_VSTRWU32 killed renamable $q0, killed renamable $r3, 0, 1, renamable $vpr :: (store (s128) into %ir.dest, align 4) MVE_VSTRWU32 killed renamable $q0, killed renamable $r3, 0, 1, renamable $vpr, $noreg :: (store (s128) into %ir.dest, align 4)
renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 1, renamable $vpr :: (load (s128) from %ir.src2, align 4) renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.src2, align 4)
MVE_VSTRWU32 killed renamable $q0, killed renamable $lr, 0, 1, renamable $vpr :: (store (s128) into %ir.dest2, align 4) MVE_VSTRWU32 killed renamable $q0, killed renamable $lr, 0, 1, renamable $vpr, $noreg :: (store (s128) into %ir.dest2, align 4)
renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 1, renamable $vpr :: (load (s128) from %ir.src3, align 4) renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.src3, align 4)
MVE_VSTRWU32 renamable $q0, killed renamable $r12, 0, 1, killed renamable $vpr :: (store (s128) into %ir.dest3, align 4) MVE_VSTRWU32 renamable $q0, killed renamable $r12, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.dest3, align 4)
$sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit $q0 $sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-block-kill.mir

Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $r0, $r1, $r4, $r6, $r7, $lr liveins: $r0, $r1, $r4, $r6, $r7, $lr
; CHECK-LABEL: name: b ; CHECK-LABEL: name: b
; CHECK: liveins: $r0, $r1, $r4, $r6, $r7, $lr ; CHECK: liveins: $r0, $r1, $r4, $r6, $r7, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r6, killed $r7, killed $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r6, killed $r7, killed $lr
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $q1 = MVE_VMOVimmi32 1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q2 = MVE_VADD_qr_i32 renamable $q1, renamable $r1, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VADD_qr_i32 renamable $q1, renamable $r1, 0, $noreg, $noreg, undef renamable $q2
; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $q0, implicit $q1, implicit killed $q2 { ; CHECK: BUNDLE implicit-def dead $vpr, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $q0, implicit $q1, implicit killed $q2 {
; CHECK: MVE_VPTv4u32 8, renamable $q0, renamable $q1, 8, implicit-def $vpr ; CHECK: MVE_VPTv4u32 8, renamable $q0, renamable $q1, 8, implicit-def $vpr
; CHECK: renamable $q0 = MVE_VORR killed renamable $q0, killed renamable $q2, 1, internal killed renamable $vpr, renamable $q0 ; CHECK: renamable $q0 = MVE_VORR killed renamable $q0, killed renamable $q2, 1, internal killed renamable $vpr, $noreg, renamable $q0
; CHECK: } ; CHECK: }
; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, implicit undef $r0 ; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, implicit undef $r0
$sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r6, killed $r7, killed $lr $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r6, killed $r7, killed $lr
renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
renamable $q1 = MVE_VMOVimmi32 1, 0, $noreg, undef renamable $q1 renamable $q1 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q1
renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q1, 8, 0, $noreg renamable $vpr = MVE_VCMPu32 renamable $q0, renamable $q1, 8, 0, $noreg, $noreg
renamable $q2 = MVE_VADD_qr_i32 killed renamable $q1, renamable $r1, 0, $noreg, undef renamable $q2 renamable $q2 = MVE_VADD_qr_i32 killed renamable $q1, renamable $r1, 0, $noreg, $noreg, undef renamable $q2
renamable $q0 = MVE_VORR killed renamable $q0, killed renamable $q2, 1, killed renamable $vpr, renamable $q0 renamable $q0 = MVE_VORR killed renamable $q0, killed renamable $q2, 1, killed renamable $vpr, $noreg, renamable $q0
$sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, implicit undef $r0 $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r6, def $r7, def $pc, implicit undef $r0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines bb.0.entry:
liveins: $q0, $q1, $q2, $r0 liveins: $q0, $q1, $q2, $r0
; CHECK-LABEL: name: test_vminnmq_m_f32_v2 ; CHECK-LABEL: name: test_vminnmq_m_f32_v2
; CHECK: liveins: $q0, $q1, $q2, $r0 ; CHECK: liveins: $q0, $q1, $q2, $r0
; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg ; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q0 { ; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q0 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
; CHECK: } ; CHECK: }
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
$vpr = VMSR_P0 killed $r0, 14, $noreg $vpr = VMSR_P0 killed $r0, 14, $noreg
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2 liveins: $q0, $q1, $q2
; CHECK-LABEL: name: vpnot ; CHECK-LABEL: name: vpnot
; CHECK: liveins: $q0, $q1, $q2 ; CHECK: liveins: $q0, $q1, $q2
; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1, implicit killed $q2 { ; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1, implicit killed $q2 {
; CHECK: MVE_VPTv4s32r 12, renamable $q0, $zr, 11, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 12, renamable $q0, $zr, 11, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr, $noreg
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 2, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 2, internal killed renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...
--- ---
name: vpnot_end name: vpnot_end
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$q0', virtual-reg: '' } - { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' } - { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' } - { reg: '$q2', virtual-reg: '' }
body: | body: |
; CHECK-LABEL: name: vpnot_end ; CHECK-LABEL: name: vpnot_end
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q0, $q1, $q2 ; CHECK: liveins: $q0, $q1, $q2
; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1 { ; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1 {
; CHECK: MVE_VPTv4s32r 8, renamable $q0, $zr, 11, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 8, renamable $q0, $zr, 11, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: bb.1.bb2: ; CHECK: bb.1.bb2:
; CHECK: liveins: $q0, $q1, $q2, $vpr ; CHECK: liveins: $q0, $q1, $q2, $vpr
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr { ; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2 liveins: $q0, $q1, $q2
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
bb.1.bb2: bb.1.bb2:
liveins: $q0, $q1, $q2, $vpr liveins: $q0, $q1, $q2, $vpr
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...
--- ---
name: vpnot_two name: vpnot_two
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$q0', virtual-reg: '' } - { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' } - { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' } - { reg: '$q2', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2 liveins: $q0, $q1, $q2
; CHECK-LABEL: name: vpnot_two ; CHECK-LABEL: name: vpnot_two
; CHECK: liveins: $q0, $q1, $q2 ; CHECK: liveins: $q0, $q1, $q2
; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1 { ; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1 {
; CHECK: MVE_VPTv4s32r 8, renamable $q0, $zr, 11, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 8, renamable $q0, $zr, 11, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr { ; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...
--- ---
name: vpnot_lots name: vpnot_lots
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$q0', virtual-reg: '' } - { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' } - { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' } - { reg: '$q2', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2 liveins: $q0, $q1, $q2
; CHECK-LABEL: name: vpnot_lots ; CHECK-LABEL: name: vpnot_lots
; CHECK: liveins: $q0, $q1, $q2 ; CHECK: liveins: $q0, $q1, $q2
; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1 { ; CHECK: BUNDLE implicit-def $vpr, implicit $q0, implicit $zr, implicit $q1 {
; CHECK: MVE_VPTv4s32r 8, renamable $q0, $zr, 11, implicit-def $vpr ; CHECK: MVE_VPTv4s32r 8, renamable $q0, $zr, 11, implicit-def $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, internal killed renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr { ; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit killed $q2, implicit $zr {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...
--- ---
name: vpnot_first name: vpnot_first
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$q0', virtual-reg: '' } - { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' } - { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' } - { reg: '$q2', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2 liveins: $q0, $q1, $q2
; CHECK-LABEL: name: vpnot_first ; CHECK-LABEL: name: vpnot_first
; CHECK: liveins: $q0, $q1, $q2 ; CHECK: liveins: $q0, $q1, $q2
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit $q1, implicit $zr, implicit killed $q2 { ; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit $q1, implicit $zr, implicit killed $q2 {
; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, internal killed renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...
--- ---
name: vpnot_many name: vpnot_many
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '$q0', virtual-reg: '' } - { reg: '$q0', virtual-reg: '' }
- { reg: '$q1', virtual-reg: '' } - { reg: '$q1', virtual-reg: '' }
- { reg: '$q2', virtual-reg: '' } - { reg: '$q2', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $q0, $q1, $q2 liveins: $q0, $q1, $q2
; CHECK-LABEL: name: vpnot_many ; CHECK-LABEL: name: vpnot_many
; CHECK: liveins: $q0, $q1, $q2 ; CHECK: liveins: $q0, $q1, $q2
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit $q1, implicit $zr, implicit killed $q2 { ; CHECK: BUNDLE implicit-def $vpr, implicit killed $vpr, implicit $q1, implicit $zr, implicit killed $q2 {
; CHECK: MVE_VPST 12, implicit $vpr ; CHECK: MVE_VPST 12, implicit $vpr
; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 2, internal killed renamable $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 2, internal killed renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr, $noreg
renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg, $noreg
renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr, $noreg
tBX_RET 14, $noreg, implicit $q0 tBX_RET 14, $noreg, implicit $q0
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-optimisations.mir

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
... ...
--- ---
name: vcmp_with_opposite_cond name: vcmp_with_opposite_cond
alignment: 4 alignment: 4
body: | body: |
; CHECK-LABEL: name: vcmp_with_opposite_cond ; CHECK-LABEL: name: vcmp_with_opposite_cond
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16_]], 0, $noreg ; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16_]], 0, $noreg, $noreg
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf32_]], 0, $noreg ; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf32_]], 0, $noreg, $noreg
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16_]], 0, $noreg ; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16_]], 0, $noreg, $noreg
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32_]], 0, $noreg ; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32_]], 0, $noreg, $noreg
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: [[MVE_VCMPi8_:%[0-9]+]]:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi8_:%[0-9]+]]:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8_]], 0, $noreg ; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8_]], 0, $noreg, $noreg
; CHECK: bb.5: ; CHECK: bb.5:
; CHECK: successors: %bb.6(0x80000000) ; CHECK: successors: %bb.6(0x80000000)
; CHECK: [[MVE_VCMPs16_:%[0-9]+]]:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs16_:%[0-9]+]]:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16_]], 0, $noreg ; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16_]], 0, $noreg, $noreg
; CHECK: bb.6: ; CHECK: bb.6:
; CHECK: successors: %bb.7(0x80000000) ; CHECK: successors: %bb.7(0x80000000)
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg ; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
; CHECK: bb.7: ; CHECK: bb.7:
; CHECK: successors: %bb.8(0x80000000) ; CHECK: successors: %bb.8(0x80000000)
; CHECK: [[MVE_VCMPs8_:%[0-9]+]]:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs8_:%[0-9]+]]:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8_]], 0, $noreg ; CHECK: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8_]], 0, $noreg, $noreg
; CHECK: bb.8: ; CHECK: bb.8:
; CHECK: successors: %bb.9(0x80000000) ; CHECK: successors: %bb.9(0x80000000)
; CHECK: [[MVE_VCMPu16_:%[0-9]+]]:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPu16_:%[0-9]+]]:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16_]], 0, $noreg ; CHECK: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16_]], 0, $noreg, $noreg
; CHECK: bb.9: ; CHECK: bb.9:
; CHECK: successors: %bb.10(0x80000000) ; CHECK: successors: %bb.10(0x80000000)
; CHECK: [[MVE_VCMPu32_:%[0-9]+]]:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPu32_:%[0-9]+]]:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32_]], 0, $noreg ; CHECK: [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32_]], 0, $noreg, $noreg
; CHECK: bb.10: ; CHECK: bb.10:
; CHECK: successors: %bb.11(0x80000000) ; CHECK: successors: %bb.11(0x80000000)
; CHECK: [[MVE_VCMPu8_:%[0-9]+]]:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPu8_:%[0-9]+]]:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8_]], 0, $noreg ; CHECK: [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8_]], 0, $noreg, $noreg
; CHECK: bb.11: ; CHECK: bb.11:
; CHECK: successors: %bb.12(0x80000000) ; CHECK: successors: %bb.12(0x80000000)
; CHECK: [[MVE_VCMPf16r:%[0-9]+]]:vccr = MVE_VCMPf16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg ; CHECK: [[MVE_VCMPf16r:%[0-9]+]]:vccr = MVE_VCMPf16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT11:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16r]], 0, $noreg ; CHECK: [[MVE_VPNOT11:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16r]], 0, $noreg, $noreg
; CHECK: bb.12: ; CHECK: bb.12:
; CHECK: successors: %bb.13(0x80000000) ; CHECK: successors: %bb.13(0x80000000)
; CHECK: [[MVE_VCMPf32r:%[0-9]+]]:vccr = MVE_VCMPf32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg ; CHECK: [[MVE_VCMPf32r:%[0-9]+]]:vccr = MVE_VCMPf32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT12:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf32r]], 0, $noreg ; CHECK: [[MVE_VPNOT12:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf32r]], 0, $noreg, $noreg
; CHECK: bb.13: ; CHECK: bb.13:
; CHECK: successors: %bb.14(0x80000000) ; CHECK: successors: %bb.14(0x80000000)
; CHECK: [[MVE_VCMPi16r:%[0-9]+]]:vccr = MVE_VCMPi16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi16r:%[0-9]+]]:vccr = MVE_VCMPi16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT13:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16r]], 0, $noreg ; CHECK: [[MVE_VPNOT13:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16r]], 0, $noreg, $noreg
; CHECK: bb.14: ; CHECK: bb.14:
; CHECK: successors: %bb.15(0x80000000) ; CHECK: successors: %bb.15(0x80000000)
; CHECK: [[MVE_VCMPi32r:%[0-9]+]]:vccr = MVE_VCMPi32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi32r:%[0-9]+]]:vccr = MVE_VCMPi32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT14:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32r]], 0, $noreg ; CHECK: [[MVE_VPNOT14:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32r]], 0, $noreg, $noreg
; CHECK: bb.15: ; CHECK: bb.15:
; CHECK: successors: %bb.16(0x80000000) ; CHECK: successors: %bb.16(0x80000000)
; CHECK: [[MVE_VCMPi8r:%[0-9]+]]:vccr = MVE_VCMPi8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi8r:%[0-9]+]]:vccr = MVE_VCMPi8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT15:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8r]], 0, $noreg ; CHECK: [[MVE_VPNOT15:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8r]], 0, $noreg, $noreg
; CHECK: bb.16: ; CHECK: bb.16:
; CHECK: successors: %bb.17(0x80000000) ; CHECK: successors: %bb.17(0x80000000)
; CHECK: [[MVE_VCMPs16r:%[0-9]+]]:vccr = MVE_VCMPs16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs16r:%[0-9]+]]:vccr = MVE_VCMPs16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT16:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16r]], 0, $noreg ; CHECK: [[MVE_VPNOT16:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16r]], 0, $noreg, $noreg
; CHECK: bb.17: ; CHECK: bb.17:
; CHECK: successors: %bb.18(0x80000000) ; CHECK: successors: %bb.18(0x80000000)
; CHECK: [[MVE_VCMPs32r:%[0-9]+]]:vccr = MVE_VCMPs32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32r:%[0-9]+]]:vccr = MVE_VCMPs32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT17:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32r]], 0, $noreg ; CHECK: [[MVE_VPNOT17:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32r]], 0, $noreg, $noreg
; CHECK: bb.18: ; CHECK: bb.18:
; CHECK: successors: %bb.19(0x80000000) ; CHECK: successors: %bb.19(0x80000000)
; CHECK: [[MVE_VCMPs8r:%[0-9]+]]:vccr = MVE_VCMPs8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs8r:%[0-9]+]]:vccr = MVE_VCMPs8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT18:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8r]], 0, $noreg ; CHECK: [[MVE_VPNOT18:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8r]], 0, $noreg, $noreg
; CHECK: bb.19: ; CHECK: bb.19:
; CHECK: successors: %bb.20(0x80000000) ; CHECK: successors: %bb.20(0x80000000)
; CHECK: [[MVE_VCMPu16r:%[0-9]+]]:vccr = MVE_VCMPu16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg ; CHECK: [[MVE_VCMPu16r:%[0-9]+]]:vccr = MVE_VCMPu16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT19:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16r]], 0, $noreg ; CHECK: [[MVE_VPNOT19:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16r]], 0, $noreg, $noreg
; CHECK: bb.20: ; CHECK: bb.20:
; CHECK: successors: %bb.21(0x80000000) ; CHECK: successors: %bb.21(0x80000000)
; CHECK: [[MVE_VCMPu32r:%[0-9]+]]:vccr = MVE_VCMPu32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg ; CHECK: [[MVE_VCMPu32r:%[0-9]+]]:vccr = MVE_VCMPu32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT20:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32r]], 0, $noreg ; CHECK: [[MVE_VPNOT20:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32r]], 0, $noreg, $noreg
; CHECK: bb.21: ; CHECK: bb.21:
; CHECK: successors: %bb.22(0x80000000) ; CHECK: successors: %bb.22(0x80000000)
; CHECK: [[MVE_VCMPu8r:%[0-9]+]]:vccr = MVE_VCMPu8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg ; CHECK: [[MVE_VCMPu8r:%[0-9]+]]:vccr = MVE_VCMPu8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT21:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8r]], 0, $noreg ; CHECK: [[MVE_VPNOT21:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8r]], 0, $noreg, $noreg
; CHECK: bb.22: ; CHECK: bb.22:
; CHECK: [[MVE_VCMPu8r1:%[0-9]+]]:vccr = MVE_VCMPu8r %1:mqpr, $zr, 10, 0, $noreg ; CHECK: [[MVE_VCMPu8r1:%[0-9]+]]:vccr = MVE_VCMPu8r %1:mqpr, $zr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT22:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8r1]], 0, $noreg ; CHECK: [[MVE_VPNOT22:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8r1]], 0, $noreg, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
; ;
; Tests that VCMPs with an opposite condition are correctly converted into VPNOTs. ; Tests that VCMPs with an opposite condition are correctly converted into VPNOTs.
; ;
bb.0: bb.0:
%3:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg %3:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%4:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 11, 0, $noreg %4:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
bb.1: bb.1:
%5:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg %5:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%6:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 11, 0, $noreg %6:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
bb.2: bb.2:
%7:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg %7:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%8:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 11, 0, $noreg %8:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
bb.3: bb.3:
%9:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg %9:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%10:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 11, 0, $noreg %10:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
bb.4: bb.4:
%11:vccr = MVE_VCMPi8 %0:mqpr, %1:mqpr, 10, 0, $noreg %11:vccr = MVE_VCMPi8 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%12:vccr = MVE_VCMPi8 %0:mqpr, %1:mqpr, 11, 0, $noreg %12:vccr = MVE_VCMPi8 %0:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
bb.5: bb.5:
%13:vccr = MVE_VCMPs16 %0:mqpr, %1:mqpr, 10, 0, $noreg %13:vccr = MVE_VCMPs16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%14:vccr = MVE_VCMPs16 %0:mqpr, %1:mqpr, 11, 0, $noreg %14:vccr = MVE_VCMPs16 %0:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
bb.6: bb.6:
%15:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %15:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%16:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 11, 0, $noreg %16:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
bb.7: bb.7:
%17:vccr = MVE_VCMPs8 %0:mqpr, %1:mqpr, 10, 0, $noreg %17:vccr = MVE_VCMPs8 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%18:vccr = MVE_VCMPs8 %0:mqpr, %1:mqpr, 11, 0, $noreg %18:vccr = MVE_VCMPs8 %0:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
bb.8: bb.8:
%19:vccr = MVE_VCMPu16 %0:mqpr, %1:mqpr, 10, 0, $noreg %19:vccr = MVE_VCMPu16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%20:vccr = MVE_VCMPu16 %0:mqpr, %1:mqpr, 11, 0, $noreg %20:vccr = MVE_VCMPu16 %0:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
bb.9: bb.9:
%21:vccr = MVE_VCMPu32 %0:mqpr, %1:mqpr, 10, 0, $noreg %21:vccr = MVE_VCMPu32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%22:vccr = MVE_VCMPu32 %0:mqpr, %1:mqpr, 11, 0, $noreg %22:vccr = MVE_VCMPu32 %0:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
bb.10: bb.10:
%23:vccr = MVE_VCMPu8 %0:mqpr, %1:mqpr, 10, 0, $noreg %23:vccr = MVE_VCMPu8 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%24:vccr = MVE_VCMPu8 %0:mqpr, %1:mqpr, 11, 0, $noreg %24:vccr = MVE_VCMPu8 %0:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
bb.11: bb.11:
%25:vccr = MVE_VCMPf16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg %25:vccr = MVE_VCMPf16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg, $noreg
%26:vccr = MVE_VCMPf16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg %26:vccr = MVE_VCMPf16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg, $noreg
bb.12: bb.12:
%27:vccr = MVE_VCMPf32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg %27:vccr = MVE_VCMPf32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg, $noreg
%28:vccr = MVE_VCMPf32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg %28:vccr = MVE_VCMPf32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg, $noreg
bb.13: bb.13:
%29:vccr = MVE_VCMPi16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg %29:vccr = MVE_VCMPi16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg, $noreg
%30:vccr = MVE_VCMPi16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg %30:vccr = MVE_VCMPi16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg, $noreg
bb.14: bb.14:
%31:vccr = MVE_VCMPi32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg %31:vccr = MVE_VCMPi32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg, $noreg
%32:vccr = MVE_VCMPi32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg %32:vccr = MVE_VCMPi32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg, $noreg
bb.15: bb.15:
%33:vccr = MVE_VCMPi8r %0:mqpr, %2:gprwithzr, 10, 0, $noreg %33:vccr = MVE_VCMPi8r %0:mqpr, %2:gprwithzr, 10, 0, $noreg, $noreg
%34:vccr = MVE_VCMPi8r %0:mqpr, %2:gprwithzr, 11, 0, $noreg %34:vccr = MVE_VCMPi8r %0:mqpr, %2:gprwithzr, 11, 0, $noreg, $noreg
bb.16: bb.16:
%35:vccr = MVE_VCMPs16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg %35:vccr = MVE_VCMPs16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg, $noreg
%36:vccr = MVE_VCMPs16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg %36:vccr = MVE_VCMPs16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg, $noreg
bb.17: bb.17:
%37:vccr = MVE_VCMPs32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg %37:vccr = MVE_VCMPs32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg, $noreg
%38:vccr = MVE_VCMPs32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg %38:vccr = MVE_VCMPs32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg, $noreg
bb.18: bb.18:
%39:vccr = MVE_VCMPs8r %0:mqpr, %2:gprwithzr, 10, 0, $noreg %39:vccr = MVE_VCMPs8r %0:mqpr, %2:gprwithzr, 10, 0, $noreg, $noreg
%40:vccr = MVE_VCMPs8r %0:mqpr, %2:gprwithzr, 11, 0, $noreg %40:vccr = MVE_VCMPs8r %0:mqpr, %2:gprwithzr, 11, 0, $noreg, $noreg
bb.19: bb.19:
%41:vccr = MVE_VCMPu16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg %41:vccr = MVE_VCMPu16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg, $noreg
%42:vccr = MVE_VCMPu16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg %42:vccr = MVE_VCMPu16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg, $noreg
bb.20: bb.20:
%43:vccr = MVE_VCMPu32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg %43:vccr = MVE_VCMPu32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg, $noreg
%44:vccr = MVE_VCMPu32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg %44:vccr = MVE_VCMPu32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg, $noreg
bb.21: bb.21:
%45:vccr = MVE_VCMPu8r %0:mqpr, %2:gprwithzr, 10, 0, $noreg %45:vccr = MVE_VCMPu8r %0:mqpr, %2:gprwithzr, 10, 0, $noreg, $noreg
%46:vccr = MVE_VCMPu8r %0:mqpr, %2:gprwithzr, 11, 0, $noreg %46:vccr = MVE_VCMPu8r %0:mqpr, %2:gprwithzr, 11, 0, $noreg, $noreg
bb.22: bb.22:
; There shouldn't be any exception for $zr, so the second VCMP should ; There shouldn't be any exception for $zr, so the second VCMP should
; be transformed into a VPNOT. ; be transformed into a VPNOT.
%47:vccr = MVE_VCMPu8r %0:mqpr, $zr, 10, 0, $noreg %47:vccr = MVE_VCMPu8r %0:mqpr, $zr, 10, 0, $noreg, $noreg
%48:vccr = MVE_VCMPu8r %0:mqpr, $zr, 11, 0, $noreg %48:vccr = MVE_VCMPu8r %0:mqpr, $zr, 11, 0, $noreg, $noreg
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: vcmp_with_opposite_cond_and_swapped_operands name: vcmp_with_opposite_cond_and_swapped_operands
alignment: 4 alignment: 4
body: | body: |
; CHECK-LABEL: name: vcmp_with_opposite_cond_and_swapped_operands ; CHECK-LABEL: name: vcmp_with_opposite_cond_and_swapped_operands
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16_]], 0, $noreg ; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16_]], 0, $noreg, $noreg
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32_]], 0, $noreg ; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32_]], 0, $noreg, $noreg
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[MVE_VCMPi8_:%[0-9]+]]:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi8_:%[0-9]+]]:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8_]], 0, $noreg ; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8_]], 0, $noreg, $noreg
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: [[MVE_VCMPs16_:%[0-9]+]]:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs16_:%[0-9]+]]:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16_]], 0, $noreg ; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16_]], 0, $noreg, $noreg
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg ; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
; CHECK: bb.5: ; CHECK: bb.5:
; CHECK: successors: %bb.6(0x80000000) ; CHECK: successors: %bb.6(0x80000000)
; CHECK: [[MVE_VCMPs8_:%[0-9]+]]:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs8_:%[0-9]+]]:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8_]], 0, $noreg ; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8_]], 0, $noreg, $noreg
; CHECK: bb.6: ; CHECK: bb.6:
; CHECK: successors: %bb.7(0x80000000) ; CHECK: successors: %bb.7(0x80000000)
; CHECK: [[MVE_VCMPu16_:%[0-9]+]]:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPu16_:%[0-9]+]]:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16_]], 0, $noreg ; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16_]], 0, $noreg, $noreg
; CHECK: bb.7: ; CHECK: bb.7:
; CHECK: successors: %bb.8(0x80000000) ; CHECK: successors: %bb.8(0x80000000)
; CHECK: [[MVE_VCMPu32_:%[0-9]+]]:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPu32_:%[0-9]+]]:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32_]], 0, $noreg ; CHECK: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32_]], 0, $noreg, $noreg
; CHECK: bb.8: ; CHECK: bb.8:
; CHECK: [[MVE_VCMPu8_:%[0-9]+]]:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPu8_:%[0-9]+]]:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8_]], 0, $noreg ; CHECK: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8_]], 0, $noreg, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
; ;
; Tests that VCMPs with an opposite condition and swapped operands are ; Tests that VCMPs with an opposite condition and swapped operands are
; correctly converted into VPNOTs. ; correctly converted into VPNOTs.
; ;
bb.0: bb.0:
%2:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg %2:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%3:vccr = MVE_VCMPi16 %1:mqpr, %0:mqpr, 12, 0, $noreg %3:vccr = MVE_VCMPi16 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
bb.1: bb.1:
%4:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg %4:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%5:vccr = MVE_VCMPi32 %1:mqpr, %0:mqpr, 12, 0, $noreg %5:vccr = MVE_VCMPi32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
bb.2: bb.2:
%6:vccr = MVE_VCMPi8 %0:mqpr, %1:mqpr, 10, 0, $noreg %6:vccr = MVE_VCMPi8 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%7:vccr = MVE_VCMPi8 %1:mqpr, %0:mqpr, 12, 0, $noreg %7:vccr = MVE_VCMPi8 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
bb.3: bb.3:
%8:vccr = MVE_VCMPs16 %0:mqpr, %1:mqpr, 10, 0, $noreg %8:vccr = MVE_VCMPs16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%9:vccr = MVE_VCMPs16 %1:mqpr, %0:mqpr, 12, 0, $noreg %9:vccr = MVE_VCMPs16 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
bb.4: bb.4:
%10:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %10:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%11:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg %11:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
bb.5: bb.5:
%12:vccr = MVE_VCMPs8 %0:mqpr, %1:mqpr, 10, 0, $noreg %12:vccr = MVE_VCMPs8 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%13:vccr = MVE_VCMPs8 %1:mqpr, %0:mqpr, 12, 0, $noreg %13:vccr = MVE_VCMPs8 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
bb.6: bb.6:
%14:vccr = MVE_VCMPu16 %0:mqpr, %1:mqpr, 10, 0, $noreg %14:vccr = MVE_VCMPu16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%15:vccr = MVE_VCMPu16 %1:mqpr, %0:mqpr, 12, 0, $noreg %15:vccr = MVE_VCMPu16 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
bb.7: bb.7:
%16:vccr = MVE_VCMPu32 %0:mqpr, %1:mqpr, 10, 0, $noreg %16:vccr = MVE_VCMPu32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%17:vccr = MVE_VCMPu32 %1:mqpr, %0:mqpr, 12, 0, $noreg %17:vccr = MVE_VCMPu32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
bb.8: bb.8:
%18:vccr = MVE_VCMPu8 %0:mqpr, %1:mqpr, 10, 0, $noreg %18:vccr = MVE_VCMPu8 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%19:vccr = MVE_VCMPu8 %1:mqpr, %0:mqpr, 12, 0, $noreg %19:vccr = MVE_VCMPu8 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: triple_vcmp name: triple_vcmp
alignment: 4 alignment: 4
body: | body: |
; ;
; Tests that, when there are 2 "VPNOT-like VCMPs" in a row, only the first ; Tests that, when there are 2 "VPNOT-like VCMPs" in a row, only the first
; becomes a VPNOT. ; becomes a VPNOT.
; ;
bb.0: bb.0:
; CHECK-LABEL: name: triple_vcmp ; CHECK-LABEL: name: triple_vcmp
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg ; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg ; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%3:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg %3:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
%4:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg %4:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: killed_vccr_values name: killed_vccr_values
alignment: 4 alignment: 4
body: | body: |
; CHECK-LABEL: name: killed_vccr_values ; CHECK-LABEL: name: killed_vccr_values
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, [[MVE_VCMPf16_]], undef [[MVE_VORR]] ; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, [[MVE_VCMPf16_]], $noreg, undef [[MVE_VORR]]
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16_]], 0, $noreg ; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16_]], 0, $noreg, $noreg
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg ; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT1]], undef [[MVE_VORR1]] ; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR1]]
; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT1]], 0, $noreg ; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT1]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VPNOT2]], undef [[MVE_VORR2]] ; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR2]]
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg ; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT3]], undef [[MVE_VORR3]] ; CHECK: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT3]], $noreg, undef [[MVE_VORR3]]
; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT3]], 0, $noreg ; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT3]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR3]], [[MVE_VORR3]], 1, [[MVE_VPNOT4]], undef [[MVE_VORR4]] ; CHECK: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR3]], [[MVE_VORR3]], 1, [[MVE_VPNOT4]], $noreg, undef [[MVE_VORR4]]
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_2]], 0, $noreg ; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_2]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT5]], undef [[MVE_VORR5]] ; CHECK: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT5]], $noreg, undef [[MVE_VORR5]]
; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT5]], 0, $noreg ; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT5]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 1, [[MVE_VPNOT6]], undef [[MVE_VORR6]] ; CHECK: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 1, [[MVE_VPNOT6]], $noreg, undef [[MVE_VORR6]]
; CHECK: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VPNOT6]], undef [[MVE_VORR7]] ; CHECK: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VPNOT6]], $noreg, undef [[MVE_VORR7]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
bb.0: bb.0:
; ;
; Tests that, if the result of the VCMP is killed before the ; Tests that, if the result of the VCMP is killed before the
; second VCMP (that will be converted into a VPNOT) is found, ; second VCMP (that will be converted into a VPNOT) is found,
; the kill flag is removed. ; the kill flag is removed.
; ;
%2:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg %2:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%3:mqpr = MVE_VORR %0:mqpr, %1:mqpr, 1, killed %2:vccr, undef %3:mqpr %3:mqpr = MVE_VORR %0:mqpr, %1:mqpr, 1, killed %2:vccr, $noreg, undef %3:mqpr
%4:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 11, 0, $noreg %4:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
bb.1: bb.1:
; ;
; Tests that, if the result of the VCMP that has been replaced with a ; Tests that, if the result of the VCMP that has been replaced with a
; VPNOT is killed (before the insertion of the second VPNOT), ; VPNOT is killed (before the insertion of the second VPNOT),
; the kill flag is removed. ; the kill flag is removed.
; ;
%5:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %5:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%6:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg %6:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
%7:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, killed %6:vccr, undef %7:mqpr %7:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, killed %6:vccr, $noreg, undef %7:mqpr
%8:mqpr = MVE_VORR %7:mqpr, %7:mqpr, 1, %5:vccr, undef %8:mqpr %8:mqpr = MVE_VORR %7:mqpr, %7:mqpr, 1, %5:vccr, $noreg, undef %8:mqpr
bb.2: bb.2:
; ;
; Tests that the kill flag is removed when inserting a VPNOT for ; Tests that the kill flag is removed when inserting a VPNOT for
; an instruction. ; an instruction.
; ;
%9:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %9:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%10:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg %10:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
%11:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %10:vccr, undef %11:mqpr %11:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %10:vccr, $noreg, undef %11:mqpr
%12:mqpr = MVE_VORR %11:mqpr, %11:mqpr, 1, killed %9:vccr, undef %12:mqpr %12:mqpr = MVE_VORR %11:mqpr, %11:mqpr, 1, killed %9:vccr, $noreg, undef %12:mqpr
bb.3: bb.3:
; ;
; Tests that the kill flag is correctly removed when replacing a use ; Tests that the kill flag is correctly removed when replacing a use
; of the opposite VCCR value with the last VPNOT's result ; of the opposite vccr, $noreg value with the last VPNOT's result
; ;
%13:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %13:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%14:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg %14:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
%15:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %14:vccr, undef %15:mqpr %15:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %14:vccr, $noreg, undef %15:mqpr
%16:mqpr = MVE_VORR %15:mqpr, %15:mqpr, 1, %13:vccr, undef %16:mqpr %16:mqpr = MVE_VORR %15:mqpr, %15:mqpr, 1, %13:vccr, $noreg, undef %16:mqpr
%17:mqpr = MVE_VORR %16:mqpr, %16:mqpr, 1, killed %13:vccr, undef %17:mqpr %17:mqpr = MVE_VORR %16:mqpr, %16:mqpr, 1, killed %13:vccr, $noreg, undef %17:mqpr
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: predicated_vcmps name: predicated_vcmps
alignment: 4 alignment: 4
body: | body: |
; CHECK-LABEL: name: predicated_vcmps ; CHECK-LABEL: name: predicated_vcmps
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPi16_1:%[0-9]+]]:vccr = MVE_VCMPi16 %2:mqpr, %1:mqpr, 12, 1, [[MVE_VCMPi16_]] ; CHECK: [[MVE_VCMPi16_1:%[0-9]+]]:vccr = MVE_VCMPi16 %2:mqpr, %1:mqpr, 12, 1, [[MVE_VCMPi16_]], $noreg
; CHECK: [[MVE_VCMPi16_2:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi16_]] ; CHECK: [[MVE_VCMPi16_2:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi16_]], $noreg
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPi32_1:%[0-9]+]]:vccr = MVE_VCMPi32 %2:mqpr, %1:mqpr, 12, 1, [[MVE_VCMPi32_]] ; CHECK: [[MVE_VCMPi32_1:%[0-9]+]]:vccr = MVE_VCMPi32 %2:mqpr, %1:mqpr, 12, 1, [[MVE_VCMPi32_]], $noreg
; CHECK: [[MVE_VCMPi32_2:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi32_]] ; CHECK: [[MVE_VCMPi32_2:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi32_]], $noreg
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPf16_1:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPf16_]] ; CHECK: [[MVE_VCMPf16_1:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPf16_]], $noreg
; CHECK: [[MVE_VCMPf16_2:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPf16_]] ; CHECK: [[MVE_VCMPf16_2:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPf16_]], $noreg
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPf32_1:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPf32_]] ; CHECK: [[MVE_VCMPf32_1:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPf32_]], $noreg
; CHECK: [[MVE_VCMPf32_2:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPf32_]] ; CHECK: [[MVE_VCMPf32_2:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPf32_]], $noreg
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: [[MVE_VCMPi16_3:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi16_3:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPi16_4:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPi16_3]] ; CHECK: [[MVE_VCMPi16_4:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPi16_3]], $noreg
; CHECK: [[MVE_VCMPi16_5:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi16_3]] ; CHECK: [[MVE_VCMPi16_5:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi16_3]], $noreg
; CHECK: bb.5: ; CHECK: bb.5:
; CHECK: [[MVE_VCMPi32_3:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPi32_3:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPi32_4:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPi32_3]] ; CHECK: [[MVE_VCMPi32_4:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPi32_3]], $noreg
; CHECK: [[MVE_VCMPi32_5:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi32_3]] ; CHECK: [[MVE_VCMPi32_5:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi32_3]], $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
; ;
; Tests that predicated VCMPs are not replaced. ; Tests that predicated VCMPs are not replaced.
; ;
bb.0: bb.0:
%2:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg %2:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%3:vccr = MVE_VCMPi16 %1:mqpr, %0:mqpr, 12, 1, %2:vccr %3:vccr = MVE_VCMPi16 %1:mqpr, %0:mqpr, 12, 1, %2:vccr, $noreg
%4:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 1, %2:vccr %4:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 1, %2:vccr, $noreg
bb.1: bb.1:
%5:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg %5:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%6:vccr = MVE_VCMPi32 %1:mqpr, %0:mqpr, 12, 1, %5:vccr %6:vccr = MVE_VCMPi32 %1:mqpr, %0:mqpr, 12, 1, %5:vccr, $noreg
%7:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 1, %5:vccr %7:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 1, %5:vccr, $noreg
bb.2: bb.2:
%8:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg %8:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%9:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 11, 1, %8:vccr %9:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 11, 1, %8:vccr, $noreg
%10:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 1, %8:vccr %10:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 1, %8:vccr, $noreg
bb.3: bb.3:
%11:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg %11:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%12:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 11, 1, %11:vccr %12:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 11, 1, %11:vccr, $noreg
%13:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 1, %11:vccr %13:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 1, %11:vccr, $noreg
bb.4: bb.4:
%14:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg %14:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%15:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 11, 1, %14:vccr %15:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 11, 1, %14:vccr, $noreg
%16:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 1, %14:vccr %16:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 1, %14:vccr, $noreg
bb.5: bb.5:
%17:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg %17:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%18:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 11, 1, %17:vccr %18:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 11, 1, %17:vccr, $noreg
%19:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 1, %17:vccr %19:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 1, %17:vccr, $noreg
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: flt_with_swapped_operands name: flt_with_swapped_operands
alignment: 4 alignment: 4
body: | body: |
; CHECK-LABEL: name: flt_with_swapped_operands ; CHECK-LABEL: name: flt_with_swapped_operands
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPf16_1:%[0-9]+]]:vccr = MVE_VCMPf16 %2:mqpr, %1:mqpr, 12, 0, $noreg ; CHECK: [[MVE_VCMPf16_1:%[0-9]+]]:vccr = MVE_VCMPf16 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPf32_1:%[0-9]+]]:vccr = MVE_VCMPf32 %2:mqpr, %1:mqpr, 12, 0, $noreg ; CHECK: [[MVE_VCMPf32_1:%[0-9]+]]:vccr = MVE_VCMPf32 %2:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[MVE_VCMPf16_2:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPf16_2:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPf16_3:%[0-9]+]]:vccr = MVE_VCMPf16 %2:mqpr, %1:mqpr, 11, 0, $noreg ; CHECK: [[MVE_VCMPf16_3:%[0-9]+]]:vccr = MVE_VCMPf16 %2:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: [[MVE_VCMPf32_2:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPf32_2:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPf32_3:%[0-9]+]]:vccr = MVE_VCMPf32 %2:mqpr, %1:mqpr, 11, 0, $noreg ; CHECK: [[MVE_VCMPf32_3:%[0-9]+]]:vccr = MVE_VCMPf32 %2:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
; ;
; Tests that float VCMPs with an opposite condition and swapped operands ; Tests that float VCMPs with an opposite condition and swapped operands
; are not transformed into VPNOTs. ; are not transformed into VPNOTs.
; ;
bb.0: bb.0:
%2:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg %2:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%3:vccr = MVE_VCMPf16 %1:mqpr, %0:mqpr, 12, 0, $noreg %3:vccr = MVE_VCMPf16 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
bb.1: bb.1:
%4:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg %4:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%5:vccr = MVE_VCMPf32 %1:mqpr, %0:mqpr, 12, 0, $noreg %5:vccr = MVE_VCMPf32 %1:mqpr, %0:mqpr, 12, 0, $noreg, $noreg
bb.2: bb.2:
%6:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg %6:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%7:vccr = MVE_VCMPf16 %1:mqpr, %0:mqpr, 11, 0, $noreg %7:vccr = MVE_VCMPf16 %1:mqpr, %0:mqpr, 11, 0, $noreg, $noreg
bb.3: bb.3:
%8:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg %8:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%9:vccr = MVE_VCMPf32 %1:mqpr, %0:mqpr, 11, 0, $noreg %9:vccr = MVE_VCMPf32 %1:mqpr, %0:mqpr, 11, 0, $noreg, $noreg
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: different_opcodes name: different_opcodes
alignment: 4 alignment: 4
body: | body: |
; ;
; Tests that a "VPNOT-like VCMP" with an opcode different from the previous VCMP ; Tests that a "VPNOT-like VCMP" with an opcode different from the previous VCMP
; is not transformed into a VPNOT. ; is not transformed into a VPNOT.
; ;
bb.0: bb.0:
; CHECK-LABEL: name: different_opcodes ; CHECK-LABEL: name: different_opcodes
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 0, 0, $noreg ; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 0, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 1, 1, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 1, 1, $noreg, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
%2:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 0, 0, $noreg %2:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 0, 0, $noreg, $noreg
%3:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 1, 1, $noreg %3:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 1, 1, $noreg, $noreg
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: incorrect_condcode name: incorrect_condcode
alignment: 4 alignment: 4
body: | body: |
; CHECK-LABEL: name: incorrect_condcode ; CHECK-LABEL: name: incorrect_condcode
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 11, 0, $noreg ; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 11, 0, $noreg, $noreg
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VCMPs32_3:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg ; CHECK: [[MVE_VCMPs32_3:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
; ;
; Tests that a VCMP is not transformed into a VPNOT if its CondCode is not ; Tests that a VCMP is not transformed into a VPNOT if its CondCode is not
; the opposite CondCode. ; the opposite CondCode.
; ;
bb.0: bb.0:
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%3:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 11, 0, $noreg %3:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 11, 0, $noreg, $noreg
bb.1: bb.1:
%4:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %4:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%5:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 12, 0, $noreg %5:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: vpr_or_vccr_write_between_vcmps name: vpr_or_vccr_write_between_vcmps
alignment: 4 alignment: 4
body: | body: |
; ;
; Tests that a "VPNOT-like VCMP" will not be transformed into a VPNOT if ; Tests that a "VPNOT-like VCMP" will not be transformed into a VPNOT if
; VCCR/VPR is written to in-between. ; VCCR/VPR is written to in-between.
; ;
bb.0: bb.0:
; CHECK-LABEL: name: vpr_or_vccr_write_between_vcmps ; CHECK-LABEL: name: vpr_or_vccr_write_between_vcmps
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT killed [[MVE_VCMPs32_]], 0, $noreg ; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT killed [[MVE_VCMPs32_]], 0, $noreg, $noreg
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 12, 0, $noreg %2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 12, 0, $noreg, $noreg
%3:vccr = MVE_VPNOT killed %2:vccr, 0, $noreg %3:vccr = MVE_VPNOT killed %2:vccr, 0, $noreg, $noreg
%4:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 10, 0, $noreg %4:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 10, 0, $noreg, $noreg
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: spill_prevention name: spill_prevention
alignment: 4 alignment: 4
body: | body: |
; CHECK-LABEL: name: spill_prevention ; CHECK-LABEL: name: spill_prevention
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg ; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], undef [[MVE_VORR]] ; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR]]
; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT]], 0, $noreg ; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT1]], undef [[MVE_VORR1]] ; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR1]]
; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT1]], 0, $noreg ; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT1]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VPNOT2]], undef [[MVE_VORR2]] ; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR2]]
; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT2]], 0, $noreg ; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT2]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR2]], [[MVE_VORR2]], 1, [[MVE_VPNOT3]], undef [[MVE_VORR3]] ; CHECK: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR2]], [[MVE_VORR2]], 1, [[MVE_VPNOT3]], $noreg, undef [[MVE_VORR3]]
; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT3]], 0, $noreg ; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT3]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR3]], [[MVE_VORR3]], 1, [[MVE_VPNOT4]], undef [[MVE_VORR4]] ; CHECK: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR3]], [[MVE_VORR3]], 1, [[MVE_VPNOT4]], $noreg, undef [[MVE_VORR4]]
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg ; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT5]], undef [[MVE_VORR5]] ; CHECK: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT5]], $noreg, undef [[MVE_VORR5]]
; CHECK: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 0, $noreg, undef [[MVE_VORR6]] ; CHECK: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 0, $noreg, $noreg, undef [[MVE_VORR6]]
; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT5]], 0, $noreg ; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT5]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VPNOT6]], undef [[MVE_VORR7]] ; CHECK: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VPNOT6]], $noreg, undef [[MVE_VORR7]]
; CHECK: [[MVE_VORR8:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR7]], [[MVE_VORR7]], 0, $noreg, undef [[MVE_VORR8]] ; CHECK: [[MVE_VORR8:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR7]], [[MVE_VORR7]], 0, $noreg, $noreg, undef [[MVE_VORR8]]
; CHECK: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT6]], 0, $noreg ; CHECK: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT6]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR9:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR8]], [[MVE_VORR8]], 1, [[MVE_VPNOT7]], undef [[MVE_VORR9]] ; CHECK: [[MVE_VORR9:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR8]], [[MVE_VORR8]], 1, [[MVE_VPNOT7]], $noreg, undef [[MVE_VORR9]]
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_2]], 0, $noreg ; CHECK: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_2]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR10:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT8]], undef [[MVE_VORR10]] ; CHECK: [[MVE_VORR10:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT8]], $noreg, undef [[MVE_VORR10]]
; CHECK: [[MVE_VORR11:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR10]], [[MVE_VORR10]], 1, [[MVE_VPNOT8]], undef [[MVE_VORR11]] ; CHECK: [[MVE_VORR11:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR10]], [[MVE_VORR10]], 1, [[MVE_VPNOT8]], $noreg, undef [[MVE_VORR11]]
; CHECK: [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT8]], 0, $noreg ; CHECK: [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT8]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR12:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR11]], [[MVE_VORR11]], 1, [[MVE_VPNOT9]], undef [[MVE_VORR12]] ; CHECK: [[MVE_VORR12:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR11]], [[MVE_VORR11]], 1, [[MVE_VPNOT9]], $noreg, undef [[MVE_VORR12]]
; CHECK: [[MVE_VORR13:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR12]], [[MVE_VORR12]], 1, [[MVE_VPNOT9]], undef [[MVE_VORR13]] ; CHECK: [[MVE_VORR13:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR12]], [[MVE_VORR12]], 1, [[MVE_VPNOT9]], $noreg, undef [[MVE_VORR13]]
; CHECK: [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT9]], 0, $noreg ; CHECK: [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT9]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR14:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR13]], [[MVE_VORR13]], 1, [[MVE_VPNOT10]], undef [[MVE_VORR14]] ; CHECK: [[MVE_VORR14:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR13]], [[MVE_VORR13]], 1, [[MVE_VPNOT10]], $noreg, undef [[MVE_VORR14]]
; CHECK: [[MVE_VORR15:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR14]], [[MVE_VORR14]], 1, [[MVE_VPNOT10]], undef [[MVE_VORR15]] ; CHECK: [[MVE_VORR15:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR14]], [[MVE_VORR14]], 1, [[MVE_VPNOT10]], $noreg, undef [[MVE_VORR15]]
; CHECK: [[MVE_VPNOT11:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT10]], 0, $noreg ; CHECK: [[MVE_VPNOT11:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT10]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR16:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR15]], [[MVE_VORR15]], 1, [[MVE_VPNOT11]], undef [[MVE_VORR16]] ; CHECK: [[MVE_VORR16:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR15]], [[MVE_VORR15]], 1, [[MVE_VPNOT11]], $noreg, undef [[MVE_VORR16]]
; CHECK: [[MVE_VORR17:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR16]], [[MVE_VORR16]], 1, [[MVE_VPNOT11]], undef [[MVE_VORR17]] ; CHECK: [[MVE_VORR17:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR16]], [[MVE_VORR16]], 1, [[MVE_VPNOT11]], $noreg, undef [[MVE_VORR17]]
; CHECK: bb.3: ; CHECK: bb.3:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: [[MVE_VCMPs32_3:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_3:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT12:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_3]], 0, $noreg ; CHECK: [[MVE_VPNOT12:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_3]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR18:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT12]], undef [[MVE_VORR11]] ; CHECK: [[MVE_VORR18:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT12]], $noreg, undef [[MVE_VORR11]]
; CHECK: [[MVE_VPNOT13:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT12]], 0, $noreg ; CHECK: [[MVE_VPNOT13:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT12]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR19:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT13]], undef [[MVE_VORR19]] ; CHECK: [[MVE_VORR19:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT13]], $noreg, undef [[MVE_VORR19]]
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: [[VMSR_P0_:%[0-9]+]]:vccr = VMSR_P0 killed %32:gpr, 14 /* CC::al */, $noreg ; CHECK: [[VMSR_P0_:%[0-9]+]]:vccr = VMSR_P0 killed %32:gpr, 14 /* CC::al */, $noreg
; CHECK: [[MVE_VPNOT14:%[0-9]+]]:vccr = MVE_VPNOT [[VMSR_P0_]], 0, $noreg ; CHECK: [[MVE_VPNOT14:%[0-9]+]]:vccr = MVE_VPNOT [[VMSR_P0_]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR20:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR19]], [[MVE_VORR19]], 1, [[MVE_VPNOT14]], undef [[MVE_VORR20]] ; CHECK: [[MVE_VORR20:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR19]], [[MVE_VORR19]], 1, [[MVE_VPNOT14]], $noreg, undef [[MVE_VORR20]]
; CHECK: [[MVE_VPNOT15:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT14]], 0, $noreg ; CHECK: [[MVE_VPNOT15:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT14]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR21:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR20]], [[MVE_VORR20]], 1, [[MVE_VPNOT15]], undef [[MVE_VORR21]] ; CHECK: [[MVE_VORR21:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR20]], [[MVE_VORR20]], 1, [[MVE_VPNOT15]], $noreg, undef [[MVE_VORR21]]
; CHECK: [[MVE_VPNOT16:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT15]], 0, $noreg ; CHECK: [[MVE_VPNOT16:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT15]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR22:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR21]], [[MVE_VORR21]], 1, [[MVE_VPNOT16]], undef [[MVE_VORR22]] ; CHECK: [[MVE_VORR22:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR21]], [[MVE_VORR21]], 1, [[MVE_VPNOT16]], $noreg, undef [[MVE_VORR22]]
; CHECK: [[MVE_VPNOT17:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT16]], 0, $noreg ; CHECK: [[MVE_VPNOT17:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT16]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR23:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR22]], [[MVE_VORR22]], 1, [[MVE_VPNOT17]], undef [[MVE_VORR23]] ; CHECK: [[MVE_VORR23:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR22]], [[MVE_VORR22]], 1, [[MVE_VPNOT17]], $noreg, undef [[MVE_VORR23]]
; CHECK: [[MVE_VPNOT18:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT17]], 0, $noreg ; CHECK: [[MVE_VPNOT18:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT17]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR24:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR23]], [[MVE_VORR23]], 1, [[MVE_VPNOT18]], undef [[MVE_VORR24]] ; CHECK: [[MVE_VORR24:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR23]], [[MVE_VORR23]], 1, [[MVE_VPNOT18]], $noreg, undef [[MVE_VORR24]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
bb.0: bb.0:
; ;
; Basic test case ; Basic test case
; ;
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%3:vccr = MVE_VPNOT %2:vccr, 0, $noreg %3:vccr = MVE_VPNOT %2:vccr, 0, $noreg, $noreg
%4:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %3:vccr, undef %4:mqpr %4:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %3:vccr, $noreg, undef %4:mqpr
%5:mqpr = MVE_VORR %4:mqpr, %4:mqpr, 1, %2:vccr, undef %5:mqpr %5:mqpr = MVE_VORR %4:mqpr, %4:mqpr, 1, %2:vccr, $noreg, undef %5:mqpr
%6:mqpr = MVE_VORR %5:mqpr, %5:mqpr, 1, %3:vccr, undef %6:mqpr %6:mqpr = MVE_VORR %5:mqpr, %5:mqpr, 1, %3:vccr, $noreg, undef %6:mqpr
%7:mqpr = MVE_VORR %6:mqpr, %6:mqpr, 1, %2:vccr, undef %7:mqpr %7:mqpr = MVE_VORR %6:mqpr, %6:mqpr, 1, %2:vccr, $noreg, undef %7:mqpr
%8:mqpr = MVE_VORR %7:mqpr, %7:mqpr, 1, %3:vccr, undef %8:mqpr %8:mqpr = MVE_VORR %7:mqpr, %7:mqpr, 1, %3:vccr, $noreg, undef %8:mqpr
bb.1: bb.1:
; ;
; Tests that unpredicated instructions in the middle of the block ; Tests that unpredicated instructions in the middle of the block
; don't interfere with the replacement. ; don't interfere with the replacement.
; ;
%9:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %9:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%10:vccr = MVE_VPNOT %9:vccr, 0, $noreg %10:vccr = MVE_VPNOT %9:vccr, 0, $noreg, $noreg
%11:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %10:vccr, undef %11:mqpr %11:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %10:vccr, $noreg, undef %11:mqpr
%12:mqpr = MVE_VORR %11:mqpr, %11:mqpr, 0, $noreg, undef %12:mqpr %12:mqpr = MVE_VORR %11:mqpr, %11:mqpr, 0, $noreg, $noreg, undef %12:mqpr
%13:mqpr = MVE_VORR %12:mqpr, %12:mqpr, 1, %9:vccr, undef %13:mqpr %13:mqpr = MVE_VORR %12:mqpr, %12:mqpr, 1, %9:vccr, $noreg, undef %13:mqpr
%14:mqpr = MVE_VORR %13:mqpr, %13:mqpr, 0, $noreg, undef %14:mqpr %14:mqpr = MVE_VORR %13:mqpr, %13:mqpr, 0, $noreg, $noreg, undef %14:mqpr
%15:mqpr = MVE_VORR %14:mqpr, %14:mqpr, 1, %10:vccr, undef %15:mqpr %15:mqpr = MVE_VORR %14:mqpr, %14:mqpr, 1, %10:vccr, $noreg, undef %15:mqpr
bb.2: bb.2:
; ;
; Tests that all uses of the register are replaced, even when it's used ; Tests that all uses of the register are replaced, even when it's used
; multiple times in a row. ; multiple times in a row.
; ;
%16:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %16:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%17:vccr = MVE_VPNOT %16:vccr, 0, $noreg %17:vccr = MVE_VPNOT %16:vccr, 0, $noreg, $noreg
%18:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %17:vccr, undef %18:mqpr %18:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %17:vccr, $noreg, undef %18:mqpr
%19:mqpr = MVE_VORR %18:mqpr, %18:mqpr, 1, %17:vccr, undef %19:mqpr %19:mqpr = MVE_VORR %18:mqpr, %18:mqpr, 1, %17:vccr, $noreg, undef %19:mqpr
%20:mqpr = MVE_VORR %19:mqpr, %19:mqpr, 1, %16:vccr, undef %20:mqpr %20:mqpr = MVE_VORR %19:mqpr, %19:mqpr, 1, %16:vccr, $noreg, undef %20:mqpr
%21:mqpr = MVE_VORR %20:mqpr, %20:mqpr, 1, %16:vccr, undef %21:mqpr %21:mqpr = MVE_VORR %20:mqpr, %20:mqpr, 1, %16:vccr, $noreg, undef %21:mqpr
%22:mqpr = MVE_VORR %21:mqpr, %21:mqpr, 1, %17:vccr, undef %22:mqpr %22:mqpr = MVE_VORR %21:mqpr, %21:mqpr, 1, %17:vccr, $noreg, undef %22:mqpr
%23:mqpr = MVE_VORR %22:mqpr, %22:mqpr, 1, %17:vccr, undef %23:mqpr %23:mqpr = MVE_VORR %22:mqpr, %22:mqpr, 1, %17:vccr, $noreg, undef %23:mqpr
%24:mqpr = MVE_VORR %23:mqpr, %23:mqpr, 1, %16:vccr, undef %24:mqpr %24:mqpr = MVE_VORR %23:mqpr, %23:mqpr, 1, %16:vccr, $noreg, undef %24:mqpr
%25:mqpr = MVE_VORR %24:mqpr, %24:mqpr, 1, %16:vccr, undef %25:mqpr %25:mqpr = MVE_VORR %24:mqpr, %24:mqpr, 1, %16:vccr, $noreg, undef %25:mqpr
bb.3: bb.3:
; ;
; Tests that already present VPNOTs are "registered" by the pass so ; Tests that already present VPNOTs are "registered" by the pass so
; it does not insert a useless VPNOT. ; it does not insert a useless VPNOT.
; ;
%26:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %26:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%27:vccr = MVE_VPNOT %26:vccr, 0, $noreg %27:vccr = MVE_VPNOT %26:vccr, 0, $noreg, $noreg
%28:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %27:vccr, undef %19:mqpr %28:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %27:vccr, $noreg, undef %19:mqpr
%29:vccr = MVE_VPNOT %27:vccr, 0, $noreg %29:vccr = MVE_VPNOT %27:vccr, 0, $noreg, $noreg
%30:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %26:vccr, undef %30:mqpr %30:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %26:vccr, $noreg, undef %30:mqpr
bb.4: bb.4:
; ;
; Tests that the pass works with instructions other than vcmp. ; Tests that the pass works with instructions other than vcmp.
; ;
%32:vccr = VMSR_P0 killed %31:gpr, 14, $noreg %32:vccr = VMSR_P0 killed %31:gpr, 14, $noreg
%33:vccr = MVE_VPNOT %32:vccr, 0, $noreg %33:vccr = MVE_VPNOT %32:vccr, 0, $noreg, $noreg
%34:mqpr = MVE_VORR %30:mqpr, %30:mqpr, 1, %33:vccr, undef %34:mqpr %34:mqpr = MVE_VORR %30:mqpr, %30:mqpr, 1, %33:vccr, $noreg, undef %34:mqpr
%35:mqpr = MVE_VORR %34:mqpr, %34:mqpr, 1, %32:vccr, undef %35:mqpr %35:mqpr = MVE_VORR %34:mqpr, %34:mqpr, 1, %32:vccr, $noreg, undef %35:mqpr
%36:mqpr = MVE_VORR %35:mqpr, %35:mqpr, 1, %33:vccr, undef %36:mqpr %36:mqpr = MVE_VORR %35:mqpr, %35:mqpr, 1, %33:vccr, $noreg, undef %36:mqpr
%37:mqpr = MVE_VORR %36:mqpr, %36:mqpr, 1, %32:vccr, undef %37:mqpr %37:mqpr = MVE_VORR %36:mqpr, %36:mqpr, 1, %32:vccr, $noreg, undef %37:mqpr
%38:mqpr = MVE_VORR %37:mqpr, %37:mqpr, 1, %33:vccr, undef %38:mqpr %38:mqpr = MVE_VORR %37:mqpr, %37:mqpr, 1, %33:vccr, $noreg, undef %38:mqpr
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: spill_prevention_multi name: spill_prevention_multi
alignment: 4 alignment: 4
body: | body: |
bb.0: bb.0:
; ;
; Tests that multiple groups of predicated instructions in the same basic block are optimized. ; Tests that multiple groups of predicated instructions in the same basic block are optimized.
; ;
; CHECK-LABEL: name: spill_prevention_multi ; CHECK-LABEL: name: spill_prevention_multi
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg ; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], undef [[MVE_VORR]] ; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR]]
; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT]], 0, $noreg ; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT1]], undef [[MVE_VORR1]] ; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR1]]
; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT1]], 0, $noreg ; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT1]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VPNOT2]], undef [[MVE_VORR2]] ; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR2]]
; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT2]], 0, $noreg ; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT2]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR2]], [[MVE_VORR2]], 1, [[MVE_VPNOT3]], undef [[MVE_VORR3]] ; CHECK: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR2]], [[MVE_VORR2]], 1, [[MVE_VPNOT3]], $noreg, undef [[MVE_VORR3]]
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VCMPs32_1]], undef [[MVE_VORR4]] ; CHECK: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR4]]
; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg ; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR4]], [[MVE_VORR4]], 1, [[MVE_VPNOT4]], undef [[MVE_VORR5]] ; CHECK: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR4]], [[MVE_VORR4]], 1, [[MVE_VPNOT4]], $noreg, undef [[MVE_VORR5]]
; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT4]], 0, $noreg ; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT4]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 1, [[MVE_VPNOT5]], undef [[MVE_VORR6]] ; CHECK: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 1, [[MVE_VPNOT5]], $noreg, undef [[MVE_VORR6]]
; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT5]], 0, $noreg ; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT5]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VPNOT6]], undef [[MVE_VORR7]] ; CHECK: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VPNOT6]], $noreg, undef [[MVE_VORR7]]
; CHECK: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_2]], 0, $noreg ; CHECK: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_2]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR8:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT7]], undef [[MVE_VORR8]] ; CHECK: [[MVE_VORR8:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT7]], $noreg, undef [[MVE_VORR8]]
; CHECK: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT7]], 0, $noreg ; CHECK: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT7]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR9:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR8]], [[MVE_VORR8]], 1, [[MVE_VPNOT8]], undef [[MVE_VORR9]] ; CHECK: [[MVE_VORR9:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR8]], [[MVE_VORR8]], 1, [[MVE_VPNOT8]], $noreg, undef [[MVE_VORR9]]
; CHECK: [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT8]], 0, $noreg ; CHECK: [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT8]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR10:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR9]], [[MVE_VORR9]], 1, [[MVE_VPNOT9]], undef [[MVE_VORR10]] ; CHECK: [[MVE_VORR10:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR9]], [[MVE_VORR9]], 1, [[MVE_VPNOT9]], $noreg, undef [[MVE_VORR10]]
; CHECK: [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT9]], 0, $noreg ; CHECK: [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT9]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR11:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR10]], [[MVE_VORR10]], 1, [[MVE_VPNOT10]], undef [[MVE_VORR11]] ; CHECK: [[MVE_VORR11:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR10]], [[MVE_VORR10]], 1, [[MVE_VPNOT10]], $noreg, undef [[MVE_VORR11]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%3:vccr = MVE_VPNOT %2:vccr, 0, $noreg %3:vccr = MVE_VPNOT %2:vccr, 0, $noreg, $noreg
%4:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %3:vccr, undef %4:mqpr %4:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %3:vccr, $noreg, undef %4:mqpr
%5:mqpr = MVE_VORR %4:mqpr, %4:mqpr, 1, %2:vccr, undef %5:mqpr %5:mqpr = MVE_VORR %4:mqpr, %4:mqpr, 1, %2:vccr, $noreg, undef %5:mqpr
%6:mqpr = MVE_VORR %5:mqpr, %5:mqpr, 1, %3:vccr, undef %6:mqpr %6:mqpr = MVE_VORR %5:mqpr, %5:mqpr, 1, %3:vccr, $noreg, undef %6:mqpr
%7:mqpr = MVE_VORR %6:mqpr, %6:mqpr, 1, %2:vccr, undef %7:mqpr %7:mqpr = MVE_VORR %6:mqpr, %6:mqpr, 1, %2:vccr, $noreg, undef %7:mqpr
%8:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %8:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%9:vccr = MVE_VPNOT %8:vccr, 0, $noreg %9:vccr = MVE_VPNOT %8:vccr, 0, $noreg, $noreg
%10:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %8:vccr, undef %10:mqpr %10:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %8:vccr, $noreg, undef %10:mqpr
%11:mqpr = MVE_VORR %10:mqpr, %10:mqpr, 1, %9:vccr, undef %11:mqpr %11:mqpr = MVE_VORR %10:mqpr, %10:mqpr, 1, %9:vccr, $noreg, undef %11:mqpr
%12:mqpr = MVE_VORR %11:mqpr, %11:mqpr, 1, %8:vccr, undef %12:mqpr %12:mqpr = MVE_VORR %11:mqpr, %11:mqpr, 1, %8:vccr, $noreg, undef %12:mqpr
%13:mqpr = MVE_VORR %12:mqpr, %12:mqpr, 1, %9:vccr, undef %13:mqpr %13:mqpr = MVE_VORR %12:mqpr, %12:mqpr, 1, %9:vccr, $noreg, undef %13:mqpr
%14:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %14:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%15:vccr = MVE_VPNOT %14:vccr, 0, $noreg %15:vccr = MVE_VPNOT %14:vccr, 0, $noreg, $noreg
%16:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %15:vccr, undef %16:mqpr %16:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %15:vccr, $noreg, undef %16:mqpr
%17:mqpr = MVE_VORR %16:mqpr, %16:mqpr, 1, %14:vccr, undef %17:mqpr %17:mqpr = MVE_VORR %16:mqpr, %16:mqpr, 1, %14:vccr, $noreg, undef %17:mqpr
%18:mqpr = MVE_VORR %17:mqpr, %17:mqpr, 1, %15:vccr, undef %18:mqpr %18:mqpr = MVE_VORR %17:mqpr, %17:mqpr, 1, %15:vccr, $noreg, undef %18:mqpr
%19:mqpr = MVE_VORR %18:mqpr, %18:mqpr, 1, %14:vccr, undef %19:mqpr %19:mqpr = MVE_VORR %18:mqpr, %18:mqpr, 1, %14:vccr, $noreg, undef %19:mqpr
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: spill_prevention_predicated_vpnots name: spill_prevention_predicated_vpnots
alignment: 4 alignment: 4
body: | body: |
; CHECK-LABEL: name: spill_prevention_predicated_vpnots ; CHECK-LABEL: name: spill_prevention_predicated_vpnots
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 1, [[MVE_VCMPs32_]] ; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 1, [[MVE_VCMPs32_]], $noreg
; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VCMPs32_]], undef [[MVE_VORR]] ; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VCMPs32_]], $noreg, undef [[MVE_VORR]]
; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT]], undef [[MVE_VORR1]] ; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR1]]
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 1, [[MVE_VCMPs32_1]] ; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 1, [[MVE_VCMPs32_1]], $noreg
; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, [[MVE_VPNOT1]], undef [[MVE_VORR2]] ; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR]]
; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VCMPs32_1]], undef [[MVE_VORR2]] ; CHECK: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR1]]
; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR %2:mqpr, %1:mqpr, 1, [[MVE_VPNOT1]], undef [[MVE_VORR2]] ; CHECK: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR %2:mqpr, %1:mqpr, 1, [[MVE_VPNOT1]], $noreg, undef %11:mqpr
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
; ;
; Tests that predicated VPNOTs are not considered by this pass ; Tests that predicated VPNOTs are not considered by this pass
; (This means that these examples should not be optimized.) ; (This means that these examples should not be optimized.)
; ;
bb.0: bb.0:
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%3:vccr = MVE_VPNOT %2:vccr, 1, %2:vccr %3:vccr = MVE_VPNOT %2:vccr, 1, %2:vccr, $noreg
%4:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %2:vccr, undef %4:mqpr %4:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %2:vccr, $noreg, undef %4:mqpr
%5:mqpr = MVE_VORR %4:mqpr, %4:mqpr, 1, %3:vccr, undef %5:mqpr %5:mqpr = MVE_VORR %4:mqpr, %4:mqpr, 1, %3:vccr, $noreg, undef %5:mqpr
bb.1: bb.1:
%12:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %12:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%13:vccr = MVE_VPNOT %12:vccr, 1, %12:vccr %13:vccr = MVE_VPNOT %2:vccr, 1, %12:vccr, $noreg
%14:mqpr = MVE_VORR %0:mqpr, %1:mqpr, 1, %13:vccr, undef %14:mqpr %14:mqpr = MVE_VORR %0:mqpr, %1:mqpr, 1, %13:vccr, $noreg, undef %4:mqpr
%15:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %12:vccr, undef %15:mqpr %15:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %12:vccr, $noreg, undef %5:mqpr
%16:mqpr = MVE_VORR %1:mqpr, %0:mqpr, 1, %13:vccr, undef %16:mqpr %16:mqpr = MVE_VORR %1:mqpr, %0:mqpr, 1, %13:vccr, $noreg, undef %6:mqpr
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: spill_prevention_copies name: spill_prevention_copies
alignment: 4 alignment: 4
body: | body: |
; ;
; Tests that VPNOTs are replaced by a COPY instead of inserting a VPNOT ; Tests that VPNOTs are replaced by a COPY instead of inserting a VPNOT
; (which would result in a double VPNOT). ; (which would result in a double VPNOT).
; ;
bb.0: bb.0:
; CHECK-LABEL: name: spill_prevention_copies ; CHECK-LABEL: name: spill_prevention_copies
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg ; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], undef [[MVE_VORR]] ; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR]]
; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], undef [[MVE_VORR1]] ; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR1]]
; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], undef [[MVE_VORR2]] ; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR2]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%3:vccr = MVE_VPNOT %2:vccr, 0, $noreg %3:vccr = MVE_VPNOT %2:vccr, 0, $noreg, $noreg
%4:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %3:vccr, undef %4:mqpr %4:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %3:vccr, $noreg, undef %4:mqpr
%5:vccr = MVE_VPNOT %2:vccr, 0, $noreg %5:vccr = MVE_VPNOT %2:vccr, 0, $noreg, $noreg
%6:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %5:vccr, undef %6:mqpr %6:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %5:vccr, $noreg, undef %6:mqpr
%7:vccr = MVE_VPNOT %2:vccr, 0, $noreg %7:vccr = MVE_VPNOT %2:vccr, 0, $noreg, $noreg
%8:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %7:vccr, undef %8:mqpr %8:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %7:vccr, $noreg, undef %8:mqpr
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: spill_prevention_vpnot_reordering name: spill_prevention_vpnot_reordering
alignment: 4 alignment: 4
body: | body: |
; CHECK-LABEL: name: spill_prevention_vpnot_reordering ; CHECK-LABEL: name: spill_prevention_vpnot_reordering
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, [[MVE_VCMPs32_]], undef [[MVE_VORR]] ; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, [[MVE_VCMPs32_]], $noreg, undef [[MVE_VORR]]
; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR %2:mqpr, %1:mqpr, 1, [[MVE_VCMPs32_]], undef [[MVE_VORR1]] ; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR %2:mqpr, %1:mqpr, 1, [[MVE_VCMPs32_]], $noreg, undef [[MVE_VORR1]]
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg ; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR1]], 1, [[MVE_VPNOT]], undef [[MVE_VORR2]] ; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR1]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR2]]
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, [[MVE_VCMPs32_1]], undef [[MVE_VORR3]] ; CHECK: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR3]]
; CHECK: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR %2:mqpr, %1:mqpr, 1, [[MVE_VCMPs32_1]], undef [[MVE_VORR4]] ; CHECK: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR %2:mqpr, %1:mqpr, 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR4]]
; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg ; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR3]], [[MVE_VORR4]], 1, [[MVE_VPNOT1]], undef [[MVE_VORR5]] ; CHECK: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR3]], [[MVE_VORR4]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR5]]
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
; ;
; Tests that the first VPNOT is moved down when the result of the VCMP is used ; Tests that the first VPNOT is moved down when the result of the VCMP is used
; before the first usage of the VPNOT's result. ; before the first usage of the VPNOT's result.
; ;
bb.0: bb.0:
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%3:vccr = MVE_VPNOT %2:vccr, 0, $noreg %3:vccr = MVE_VPNOT %2:vccr, 0, $noreg, $noreg
%4:mqpr = MVE_VORR %0:mqpr, %1:mqpr, 1, %2:vccr, undef %4:mqpr %4:mqpr = MVE_VORR %0:mqpr, %1:mqpr, 1, %2:vccr, $noreg, undef %4:mqpr
%5:mqpr = MVE_VORR %1:mqpr, %0:mqpr, 1, %2:vccr, undef %5:mqpr %5:mqpr = MVE_VORR %1:mqpr, %0:mqpr, 1, %2:vccr, $noreg, undef %5:mqpr
%6:mqpr = MVE_VORR %4:mqpr, %5:mqpr, 1, %3:vccr, undef %6:mqpr %6:mqpr = MVE_VORR %4:mqpr, %5:mqpr, 1, %3:vccr, $noreg, undef %6:mqpr
bb.1: bb.1:
; Test again with a "killed" flag to check if it's properly removed. ; Test again with a "killed" flag to check if it's properly removed.
%7:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %7:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%8:vccr = MVE_VPNOT %7:vccr, 0, $noreg %8:vccr = MVE_VPNOT %7:vccr, 0, $noreg, $noreg
%9:mqpr = MVE_VORR %0:mqpr, %1:mqpr, 1, %7:vccr, undef %9:mqpr %9:mqpr = MVE_VORR %0:mqpr, %1:mqpr, 1, %7:vccr, $noreg, undef %9:mqpr
%10:mqpr = MVE_VORR %1:mqpr, %0:mqpr, 1, killed %7:vccr, undef %10:mqpr %10:mqpr = MVE_VORR %1:mqpr, %0:mqpr, 1, killed %7:vccr, $noreg, undef %10:mqpr
%11:mqpr = MVE_VORR %9:mqpr, %10:mqpr, 1, %8:vccr, undef %11:mqpr %11:mqpr = MVE_VORR %9:mqpr, %10:mqpr, 1, %8:vccr, $noreg, undef %11:mqpr
tBX_RET 14, $noreg, implicit %0:mqpr tBX_RET 14, $noreg, implicit %0:mqpr
... ...
--- ---
name: spill_prevention_stop_after_write name: spill_prevention_stop_after_write
alignment: 4 alignment: 4
body: | body: |
; CHECK-LABEL: name: spill_prevention_stop_after_write ; CHECK-LABEL: name: spill_prevention_stop_after_write
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000) ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg ; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], undef [[MVE_VORR]] ; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR]]
; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT]], 0, $noreg ; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT1]], undef [[MVE_VORR1]] ; CHECK: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR]], [[MVE_VORR]], 1, [[MVE_VPNOT1]], $noreg, undef [[MVE_VORR1]]
; CHECK: [[VMSR_P0_:%[0-9]+]]:vccr = VMSR_P0 killed %7:gpr, 14 /* CC::al */, $noreg ; CHECK: [[VMSR_P0_:%[0-9]+]]:vccr = VMSR_P0 killed %7:gpr, 14 /* CC::al */, $noreg
; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VCMPs32_]], undef [[MVE_VORR2]] ; CHECK: [[MVE_VORR2:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR1]], [[MVE_VORR1]], 1, [[MVE_VCMPs32_]], $noreg, undef [[MVE_VORR2]]
; CHECK: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR2]], [[MVE_VORR2]], 1, [[MVE_VPNOT]], undef [[MVE_VORR3]] ; CHECK: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR2]], [[MVE_VORR2]], 1, [[MVE_VPNOT]], $noreg, undef [[MVE_VORR3]]
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg ; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_1]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT2]], undef [[MVE_VORR]] ; CHECK: [[MVE_VORR4:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %1:mqpr, 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR]]
; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT2]], 0, $noreg ; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VPNOT2]], 0, $noreg, $noreg
; CHECK: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR4]], [[MVE_VORR4]], 1, [[MVE_VPNOT3]], undef [[MVE_VORR5]] ; CHECK: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR4]], [[MVE_VORR4]], 1, [[MVE_VPNOT3]], $noreg, undef [[MVE_VORR5]]
; CHECK: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 10, 0, $noreg ; CHECK: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
; CHECK: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 1, [[MVE_VPNOT2]], undef [[MVE_VORR6]] ; CHECK: [[MVE_VORR6:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR5]], [[MVE_VORR5]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR6]]
; CHECK: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VCMPs32_1]], undef [[MVE_VORR7]] ; CHECK: [[MVE_VORR7:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR6]], [[MVE_VORR6]], 1, [[MVE_VCMPs32_1]], $noreg, undef [[MVE_VORR7]]
; CHECK: [[MVE_VORR8:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR7]], [[MVE_VORR7]], 1, [[MVE_VPNOT2]], undef [[MVE_VORR8]] ; CHECK: [[MVE_VORR8:%[0-9]+]]:mqpr = MVE_VORR [[MVE_VORR7]], [[MVE_VORR7]], 1, [[MVE_VPNOT2]], $noreg, undef [[MVE_VORR8]]
; ;
; Tests that the optimisation stops when it sees an instruction ; Tests that the optimisation stops when it sees an instruction
; that writes to VPR, and that doesn't use any of the registers we care about. ; that writes to VPR, and that doesn't use any of the registers we care about.
; ;
bb.0: bb.0:
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%3:vccr = MVE_VPNOT %2:vccr, 0, $noreg %3:vccr = MVE_VPNOT %2:vccr, 0, $noreg, $noreg
%4:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %3:vccr, undef %4:mqpr %4:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %3:vccr, $noreg, undef %4:mqpr
%5:mqpr = MVE_VORR %4:mqpr, %4:mqpr, 1, %2:vccr, undef %5:mqpr %5:mqpr = MVE_VORR %4:mqpr, %4:mqpr, 1, %2:vccr, $noreg, undef %5:mqpr
%6:vccr = VMSR_P0 killed %20:gpr, 14, $noreg %6:vccr = VMSR_P0 killed %20:gpr, 14, $noreg
%7:mqpr = MVE_VORR %5:mqpr, %5:mqpr, 1, %2:vccr, undef %7:mqpr %7:mqpr = MVE_VORR %5:mqpr, %5:mqpr, 1, %2:vccr, $noreg, undef %7:mqpr
%8:mqpr = MVE_VORR %7:mqpr, %7:mqpr, 1, %3:vccr, undef %8:mqpr %8:mqpr = MVE_VORR %7:mqpr, %7:mqpr, 1, %3:vccr, $noreg, undef %8:mqpr
bb.1: bb.1:
%9:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg %9:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg, $noreg
%10:vccr = MVE_VPNOT %9:vccr, 0, $noreg %10:vccr = MVE_VPNOT %9:vccr, 0, $noreg, $noreg
%11:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %10:vccr, undef %4:mqpr %11:mqpr = MVE_VORR %0:mqpr, %0:mqpr, 1, %10:vccr, $noreg, undef %4:mqpr
%12:mqpr = MVE_VORR %11:mqpr, %11:mqpr, 1, %9:vccr, undef %12:mqpr %12:mqpr = MVE_VORR %11:mqpr, %11:mqpr, 1, %9:vccr, $noreg, undef %12:mqpr
%13:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 10, 0, $noreg %13:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 10, 0, $noreg, $noreg
%14:mqpr = MVE_VORR %12:mqpr, %12:mqpr, 1, %10:vccr, undef %14:mqpr %14:mqpr = MVE_VORR %12:mqpr, %12:mqpr, 1, %10:vccr, $noreg, undef %14:mqpr
%15:mqpr = MVE_VORR %14:mqpr, %14:mqpr, 1, %9:vccr, undef %15:mqpr %15:mqpr = MVE_VORR %14:mqpr, %14:mqpr, 1, %9:vccr, $noreg, undef %15:mqpr
%16:mqpr = MVE_VORR %15:mqpr, %15:mqpr, 1, %10:vccr, undef %16:mqpr %16:mqpr = MVE_VORR %15:mqpr, %15:mqpr, 1, %10:vccr, $noreg, undef %16:mqpr
... ...

llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12 liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12
; CHECK-LABEL: name: vpt_preuse ; CHECK-LABEL: name: vpt_preuse
; CHECK: successors: %bb.0(0x80000000) ; CHECK: successors: %bb.0(0x80000000)
; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12 ; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12
; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg, $noreg
; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14 /* CC::al */, $noreg, $noreg
; CHECK: VSTR_P0_off renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg ; CHECK: VSTR_P0_off renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg
; CHECK: BUNDLE implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $vpr, implicit killed $r4 { ; CHECK: BUNDLE implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $vpr, implicit killed $r4 {
; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr ; CHECK: renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg
; CHECK: } ; CHECK: }
; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr ; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr
; CHECK: t2B %bb.0, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.0, 14 /* CC::al */, $noreg
renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg, $noreg
renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg
VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg
renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr, $noreg
t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr
t2B %bb.0, 14, $noreg t2B %bb.0, 14, $noreg
... ...

llvm/test/CodeGen/Thumb2/mve-wls-block-placement.mir

Show First 20 Lines • Show All 617 Lines • ▼ Show 20 Linesbody: |
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $lr, $r2 ; CHECK: liveins: $lr, $r2
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r1 = t2ADDri $sp, 2, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r1 = t2ADDri $sp, 2, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r0 = IMPLICIT_DEF ; CHECK: renamable $r0 = IMPLICIT_DEF
; CHECK: bb.5: ; CHECK: bb.5:
; CHECK: successors: %bb.5(0x7c000000), %bb.1(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.1(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
; CHECK: renamable $q0, renamable $r0 = MVE_VIWDUPu16 killed renamable $r0, renamable $r3, 1, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0, renamable $r0 = MVE_VIWDUPu16 killed renamable $r0, renamable $r3, 1, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VSTRH16_rq undef renamable $q0, renamable $r1, killed renamable $q0, 0, $noreg ; CHECK: MVE_VSTRH16_rq undef renamable $q0, renamable $r1, killed renamable $q0, 0, $noreg, $noreg
; CHECK: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.5, implicit-def dead $cpsr ; CHECK: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.5, implicit-def dead $cpsr
; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.6: ; CHECK: bb.6:
; CHECK: successors: %bb.7(0x80000000) ; CHECK: successors: %bb.7(0x80000000)
; CHECK: liveins: $lr, $r0, $r1 ; CHECK: liveins: $lr, $r0, $r1
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.7: ; CHECK: bb.7:
; CHECK: successors: %bb.7(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.7(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r3
; CHECK: renamable $q0, renamable $r0 = MVE_VIWDUPu16 killed renamable $r0, renamable $r3, 2, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0, renamable $r0 = MVE_VIWDUPu16 killed renamable $r0, renamable $r3, 2, 0, $noreg, $noreg, undef renamable $q0
; CHECK: MVE_VSTRH16_rq undef renamable $q0, renamable $r1, killed renamable $q0, 0, $noreg ; CHECK: MVE_VSTRH16_rq undef renamable $q0, renamable $r1, killed renamable $q0, 0, $noreg, $noreg
; CHECK: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.7, implicit-def dead $cpsr ; CHECK: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.7, implicit-def dead $cpsr
; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg
bb.0: bb.0:
successors: %bb.7(0x80000000), %bb.1(0x40000000) successors: %bb.7(0x80000000), %bb.1(0x40000000)
liveins: $r0, $r1, $r2, $r7, $lr liveins: $r0, $r1, $r2, $r7, $lr
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
Show All 24 Lines bb.3:
renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
renamable $r1 = t2ADDri $sp, 2, 14 /* CC::al */, $noreg, $noreg renamable $r1 = t2ADDri $sp, 2, 14 /* CC::al */, $noreg, $noreg
renamable $r0 = IMPLICIT_DEF renamable $r0 = IMPLICIT_DEF
bb.4: bb.4:
successors: %bb.4(0x7c000000), %bb.2(0x04000000) successors: %bb.4(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $r0, $r1, $r2, $r3 liveins: $lr, $r0, $r1, $r2, $r3
renamable $q0, renamable $r0 = MVE_VIWDUPu16 killed renamable $r0, renamable $r3, 1, 0, $noreg, undef renamable $q0 renamable $q0, renamable $r0 = MVE_VIWDUPu16 killed renamable $r0, renamable $r3, 1, 0, $noreg, $noreg, undef renamable $q0
MVE_VSTRH16_rq undef renamable $q0, renamable $r1, killed renamable $q0, 0, $noreg MVE_VSTRH16_rq undef renamable $q0, renamable $r1, killed renamable $q0, 0, $noreg, $noreg
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.4, implicit-def dead $cpsr renamable $lr = t2LoopEndDec killed renamable $lr, %bb.4, implicit-def dead $cpsr
t2B %bb.2, 14 /* CC::al */, $noreg t2B %bb.2, 14 /* CC::al */, $noreg
bb.2: bb.2:
successors: %bb.5(0x40000000), %bb.7(0x40000000) successors: %bb.5(0x40000000), %bb.7(0x40000000)
liveins: $r0, $r1, $r2 liveins: $r0, $r1, $r2
renamable $lr = t2WhileLoopStartLR killed renamable $r2, %bb.7, implicit-def dead $cpsr renamable $lr = t2WhileLoopStartLR killed renamable $r2, %bb.7, implicit-def dead $cpsr
t2B %bb.5, 14 /* CC::al */, $noreg t2B %bb.5, 14 /* CC::al */, $noreg
bb.5: bb.5:
successors: %bb.6(0x80000000) successors: %bb.6(0x80000000)
liveins: $lr, $r0, $r1 liveins: $lr, $r0, $r1
renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
bb.6: bb.6:
successors: %bb.6(0x7c000000), %bb.7(0x04000000) successors: %bb.6(0x7c000000), %bb.7(0x04000000)
liveins: $lr, $r0, $r1, $r3 liveins: $lr, $r0, $r1, $r3
renamable $q0, renamable $r0 = MVE_VIWDUPu16 killed renamable $r0, renamable $r3, 2, 0, $noreg, undef renamable $q0 renamable $q0, renamable $r0 = MVE_VIWDUPu16 killed renamable $r0, renamable $r3, 2, 0, $noreg, $noreg, undef renamable $q0
MVE_VSTRH16_rq undef renamable $q0, renamable $r1, killed renamable $q0, 0, $noreg MVE_VSTRH16_rq undef renamable $q0, renamable $r1, killed renamable $q0, 0, $noreg, $noreg
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.6, implicit-def dead $cpsr renamable $lr = t2LoopEndDec killed renamable $lr, %bb.6, implicit-def dead $cpsr
t2B %bb.7, 14 /* CC::al */, $noreg t2B %bb.7, 14 /* CC::al */, $noreg
... ...

llvm/test/CodeGen/Thumb2/phi_prevent_copy.mir

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Linesbody: |
; CHECK: [[COPY4:%[0-9]+]]:rgpr = COPY [[COPY2]] ; CHECK: [[COPY4:%[0-9]+]]:rgpr = COPY [[COPY2]]
; CHECK: [[COPY5:%[0-9]+]]:rgpr = COPY [[COPY]] ; CHECK: [[COPY5:%[0-9]+]]:rgpr = COPY [[COPY]]
; CHECK: [[t2WhileLoopStartLR:%[0-9]+]]:gprlr = t2WhileLoopStartLR killed [[t2LSRri]], %bb.3, implicit-def dead $cpsr ; CHECK: [[t2WhileLoopStartLR:%[0-9]+]]:gprlr = t2WhileLoopStartLR killed [[t2LSRri]], %bb.3, implicit-def dead $cpsr
; CHECK: bb.2: ; CHECK: bb.2:
; CHECK: [[COPY6:%[0-9]+]]:rgpr = COPY [[COPY5]] ; CHECK: [[COPY6:%[0-9]+]]:rgpr = COPY [[COPY5]]
; CHECK: [[COPY7:%[0-9]+]]:gprlr = COPY [[t2WhileLoopStartLR]] ; CHECK: [[COPY7:%[0-9]+]]:gprlr = COPY [[t2WhileLoopStartLR]]
; CHECK: [[COPY8:%[0-9]+]]:rgpr = COPY [[COPY4]] ; CHECK: [[COPY8:%[0-9]+]]:rgpr = COPY [[COPY4]]
; CHECK: [[COPY9:%[0-9]+]]:rgpr = COPY [[COPY3]] ; CHECK: [[COPY9:%[0-9]+]]:rgpr = COPY [[COPY3]]
; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[COPY6]], 0, $noreg ; CHECK: [[MVE_VCTP8_:%[0-9]+]]:vccr = MVE_VCTP8 [[COPY6]], 0, $noreg, $noreg
; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri killed [[COPY6]], 16, 14 /* CC::al */, $noreg, $noreg ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri killed [[COPY6]], 16, 14 /* CC::al */, $noreg, $noreg
; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post killed [[COPY9]], 16, 1, [[MVE_VCTP8_]] ; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post killed [[COPY9]], 16, 1, [[MVE_VCTP8_]], $noreg
; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post killed [[MVE_VLDRBU8_post1]], killed [[COPY8]], 16, 1, killed [[MVE_VCTP8_]] ; CHECK: [[MVE_VSTRBU8_post:%[0-9]+]]:rgpr = MVE_VSTRBU8_post killed [[MVE_VLDRBU8_post1]], killed [[COPY8]], 16, 1, killed [[MVE_VCTP8_]], $noreg
; CHECK: [[COPY10:%[0-9]+]]:rgpr = COPY [[MVE_VLDRBU8_post]] ; CHECK: [[COPY10:%[0-9]+]]:rgpr = COPY [[MVE_VLDRBU8_post]]
; CHECK: [[COPY10:%[0-9]+]]:rgpr = COPY [[MVE_VSTRBU8_post]] ; CHECK: [[COPY10:%[0-9]+]]:rgpr = COPY [[MVE_VSTRBU8_post]]
; CHECK: [[COPY10:%[0-9]+]]:rgpr = COPY [[t2SUBri]] ; CHECK: [[COPY10:%[0-9]+]]:rgpr = COPY [[t2SUBri]]
; CHECK: [[t2LoopEndDec:%[0-9]+]]:gprlr = t2LoopEndDec killed [[COPY7]], %bb.2, implicit-def dead $cpsr ; CHECK: [[t2LoopEndDec:%[0-9]+]]:gprlr = t2LoopEndDec killed [[COPY7]], %bb.2, implicit-def dead $cpsr
; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg ; CHECK: t2B %bb.3, 14 /* CC::al */, $noreg
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tBX_RET 14 /* CC::al */, $noreg ; CHECK: tBX_RET 14 /* CC::al */, $noreg
bb.0.entry: bb.0.entry:
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bb.2: bb.2:
successors: %bb.2(0x40000000), %bb.3(0x40000000) successors: %bb.2(0x40000000), %bb.3(0x40000000)
%7:rgpr = PHI %1, %bb.1, %8, %bb.2 %7:rgpr = PHI %1, %bb.1, %8, %bb.2
%9:rgpr = PHI %0, %bb.1, %10, %bb.2 %9:rgpr = PHI %0, %bb.1, %10, %bb.2
%11:gprlr = PHI %6, %bb.1, %12, %bb.2 %11:gprlr = PHI %6, %bb.1, %12, %bb.2
%13:rgpr = PHI %2, %bb.1, %14, %bb.2 %13:rgpr = PHI %2, %bb.1, %14, %bb.2
%15:vccr = MVE_VCTP8 %13, 0, $noreg %15:vccr = MVE_VCTP8 %13, 0, $noreg, $noreg
%14:rgpr = t2SUBri killed %13, 16, 14 /* CC::al */, $noreg, $noreg %14:rgpr = t2SUBri killed %13, 16, 14 /* CC::al */, $noreg, $noreg
%8:rgpr, %16:mqpr = MVE_VLDRBU8_post killed %7, 16, 1, %15 %8:rgpr, %16:mqpr = MVE_VLDRBU8_post killed %7, 16, 1, %15, $noreg
%10:rgpr = MVE_VSTRBU8_post killed %16, killed %9, 16, 1, killed %15 %10:rgpr = MVE_VSTRBU8_post killed %16, killed %9, 16, 1, killed %15, $noreg
%12:gprlr = t2LoopEndDec killed %11, %bb.2, implicit-def dead $cpsr %12:gprlr = t2LoopEndDec killed %11, %bb.2, implicit-def dead $cpsr
t2B %bb.3, 14 /* CC::al */, $noreg t2B %bb.3, 14 /* CC::al */, $noreg
bb.3.for.cond.cleanup: bb.3.for.cond.cleanup:
tBX_RET 14 /* CC::al */, $noreg tBX_RET 14 /* CC::al */, $noreg
... ...