[PowerPC] Fix shift amount of xxsldwi when performing vector int_to_double

[lkail]

Summary

POC

// main.c
#include <stdio.h>
#include <altivec.h>
extern vector double foo(vector int s);
int main() {
  vector int s = {0, 1, 0, 4};
  vector double vd;
  vd = foo(s);
  printf("%lf %lf\n", vd[0], vd[1]);
  return 0;
}
// poc.c
vector double foo(vector int s) {
  int x1 = s[1];
  int x3 = s[3];
  double d1 = x1;
  double d3 = x3;
  vector double x = { d1, d3 };
  return x;
}

Compiled with poc.c main.c -mcpu=pwr8 -O3 on BE machine.
Current clang gives

4.000000 1.000000

while xlc gives

1.000000 4.000000

Xlc's output should be correct.

[lkail]

Add poc's codegen.

[shchenz]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

2969

I assume for unsigned, it has the same issue?

[lkail]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

2969

Yes, I'll update it.

[qiucf]

llvm/test/CodeGen/PowerPC/vec_int_to_double_shuffle.ll

1 ↗

(On Diff #364673)

Pre-commit it or generate git-diff after git-add.

[lkail]

Rebased.

[shchenz]

LGTM. Thanks for fixing this.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def : Pat<(v2i64 (fp_to_sint
           (v2i64 (XVCVSPSXDS (XXSLDWI $A, $A, 1)))>;
 def : Pat<(v2i64 (fp_to_uint
                    (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))),
                                  (f64 (fpextend (extractelt v4f32:$A, 3)))))),
           (v2i64 (XVCVSPUXDS (XXSLDWI $A, $A, 1)))>;
 def : Pat<WToDPExtractConv.BV02S,
           (v2f64 (XVCVSXWDP $A))>;
 def : Pat<WToDPExtractConv.BV13S,
-          (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 3)))>;
+          (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>;
 def : Pat<WToDPExtractConv.BV02U,
           (v2f64 (XVCVUXWDP $A))>;
 def : Pat<WToDPExtractConv.BV13U,
           (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 3)))>;
 def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)),
           (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>;
 def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)),
           (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>;
 } // HasVSX, IsBigEndian
 
 // Any little endian VSX subtarget.
 let Predicates = [HasVSX, IsLittleEndian] in {

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

entry:
   %conv2 = sitofp i32 %vecext1 to double
   %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
   ret <2 x double> %vecinit3
 }
 
 define dso_local <2 x double> @sint_to_fp_widen13(<4 x i32> %a) {
 ; P9BE-LABEL: sint_to_fp_widen13:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; P9BE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; P9BE-NEXT:    xvcvsxwdp v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: sint_to_fp_widen13:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    xvcvsxwdp v2, v2
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: sint_to_fp_widen13:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; P8BE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; P8BE-NEXT:    xvcvsxwdp v2, vs0
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: sint_to_fp_widen13:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    xvcvsxwdp v2, v2
 ; P8LE-NEXT:    blr
 entry:

llvm/test/CodeGen/PowerPC/vec_sitofp_shuffle.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-LE
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown \
+; RUN:   -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-BE
+
+define <2 x double> @foo(<4 x i32> %s) {
+; CHECK-LE-LABEL: foo:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xvcvsxwdp 34, 34
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: foo:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xxsldwi 0, 34, 34, 1
+; CHECK-BE-NEXT:    xvcvsxwdp 34, 0
+; CHECK-BE-NEXT:    blr
+entry:
+  %0 = shufflevector <4 x i32> %s, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
+  %1 = sitofp <2 x i32> %0 to <2 x double>
+  ret <2 x double> %1
+}