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Differential D107245

[X86] Support auto-detect for tigerlake and alderlake
ClosedPublic

Authored by FreddyYe on Aug 1 2021, 5:57 PM.

Details

Reviewers
pengfei
LuoYuanke
craig.topper
skan
Commits
rGd268c2007017: [X86] Support auto-detect for tigerlake and alderlake

Diff Detail

Event Timeline

FreddyYe created this revision.Aug 1 2021, 5:57 PM
Herald added subscribers: dexonsmith, hiraditya. · View Herald TranscriptAug 1 2021, 5:57 PM
FreddyYe requested review of this revision.Aug 1 2021, 5:57 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptAug 1 2021, 5:58 PM
Herald added subscribers: llvm-commits, Restricted Project. · View Herald Transcript
FreddyYe added reviewers: pengfei, LuoYuanke, craig.topper, skan.Aug 1 2021, 5:59 PM
Harbormaster completed remote builds in B117369: Diff 363361.Aug 1 2021, 6:37 PM
FreddyYe added a comment.Aug 1 2021, 6:57 PM

model value copied from https://github.com/torvalds/linux/blob/master/arch/x86/include/asm/intel-family.h

skan accepted this revision.Aug 1 2021, 7:47 PM

LGTM

This revision is now accepted and ready to land.Aug 1 2021, 7:47 PM
craig.topper accepted this revision.Aug 1 2021, 7:57 PM

LGTM

Closed by commit rGd268c2007017: [X86] Support auto-detect for tigerlake and alderlake (authored by FreddyYe). · Explain WhyAug 1 2021, 8:01 PM
This revision was automatically updated to reflect the committed changes.
FreddyYe added a commit: rGd268c2007017: [X86] Support auto-detect for tigerlake and alderlake.

Revision Contents

PathSize
compiler-rt/
lib/
builtins/
16 lines
llvm/
lib/
Support/
16 lines

Diff 363364

compiler-rt/lib/builtins/cpu_model.c

Show First 20 Lines • Show All 416 Lines • ▼ Show 20 Lines case 6:
// Icelake: // Icelake:
case 0x7d: case 0x7d:
case 0x7e: case 0x7e:
CPU = "icelake-client"; CPU = "icelake-client";
*Type = INTEL_COREI7; *Type = INTEL_COREI7;
*Subtype = INTEL_COREI7_ICELAKE_CLIENT; *Subtype = INTEL_COREI7_ICELAKE_CLIENT;
break; break;
// Tigerlake:
case 0x8c:
case 0x8d:
CPU = "tigerlake";
*Type = INTEL_COREI7;
*Subtype = INTEL_COREI7_TIGERLAKE;
break;
// Alderlake:
case 0x97:
case 0x9a:
CPU = "alderlake";
*Type = INTEL_COREI7;
*Subtype = INTEL_COREI7_ALDERLAKE;
break;
// Icelake Xeon: // Icelake Xeon:
case 0x6a: case 0x6a:
case 0x6c: case 0x6c:
CPU = "icelake-server"; CPU = "icelake-server";
*Type = INTEL_COREI7; *Type = INTEL_COREI7;
*Subtype = INTEL_COREI7_ICELAKE_SERVER; *Subtype = INTEL_COREI7_ICELAKE_SERVER;
break; break;
▲ Show 20 Lines • Show All 359 Lines • Show Last 20 Lines

llvm/lib/Support/Host.cpp

Show First 20 Lines • Show All 766 Lines • ▼ Show 20 Lines case 6:
// Icelake: // Icelake:
case 0x7d: case 0x7d:
case 0x7e: case 0x7e:
CPU = "icelake-client"; CPU = "icelake-client";
*Type = X86::INTEL_COREI7; *Type = X86::INTEL_COREI7;
*Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
break; break;
// Tigerlake:
case 0x8c:
case 0x8d:
CPU = "tigerlake";
*Type = X86::INTEL_COREI7;
*Subtype = X86::INTEL_COREI7_TIGERLAKE;
break;
// Alderlake:
case 0x97:
case 0x9a:
CPU = "alderlake";
*Type = X86::INTEL_COREI7;
*Subtype = X86::INTEL_COREI7_ALDERLAKE;
break;
// Icelake Xeon: // Icelake Xeon:
case 0x6a: case 0x6a:
case 0x6c: case 0x6c:
CPU = "icelake-server"; CPU = "icelake-server";
*Type = X86::INTEL_COREI7; *Type = X86::INTEL_COREI7;
*Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
break; break;
▲ Show 20 Lines • Show All 956 Lines • Show Last 20 Lines