[PowerPC] custom v2i64 for scalar_to_vector

[shchenz]

Summary

this is a follow-up for D106353.

customize v2i64 for scalar_to_vector so that we can benefit from the change in D106353.

[shchenz]

https://reviews.llvm.org/D106555 is a preferable way to handle these cases.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.hasAltivec()) {
     // Altivec does not contain unordered floating-point compare instructions
     setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
     setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
     setCondCodeAction(ISD::SETO,   MVT::v4f32, Expand);
     setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
 
     if (Subtarget.hasVSX()) {
       setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
+      setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Custom);
       setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
       if (Subtarget.hasP8Vector()) {
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
       }
       if (Subtarget.hasDirectMove() && isPPC64) {
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
Register PPCTargetLowering::getExceptionPointerRegister(
   return Subtarget.isPPC64() ? PPC::X3 : PPC::R3;
 }
 
 Register PPCTargetLowering::getExceptionSelectorRegister(
     const Constant *PersonalityFn) const {
   return Subtarget.isPPC64() ? PPC::X4 : PPC::R4;
 }
 
-bool
-PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
-                     EVT VT , unsigned DefinedValues) const {
-  if (VT == MVT::v2i64)
-    return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves
+bool PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
+    EVT VT, unsigned DefinedValues) const {
+  if (VT == MVT::v2i64) {
+    // Don't need stack ops with direct moves.
+    if (Subtarget.hasDirectMove())
+      return true;
+
+    // Only one scalar_to_vector is needed for splat build_vector.
+    assert(DefinedValues && "no defined values!\n");
+    if (DefinedValues == 1)
+      return true;
+
+    // After expanding to shuffles, we need one scalar_to_vector for one defined
+    // values, and one scalar_to_vector may need one stack ops, so don't expand
+    // for more than one defined values.
+    return false;
+  }
 
   if (Subtarget.hasVSX())
     return true;
 
   return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
 }
 
 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

 ; CHECK-NOVSX-NEXT:    addi r3, r1, -16
 ; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
 ; CHECK-NOVSX-NEXT:    vmrglb v2, v2, v3
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: no_RAUW_in_combine_during_legalize:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    sldi r4, r4, 2
-; CHECK-P7-NEXT:    addi r5, r1, -16
-; CHECK-P7-NEXT:    xxlxor v3, v3, v3
-; CHECK-P7-NEXT:    lwzx r3, r3, r4
-; CHECK-P7-NEXT:    std r3, -16(r1)
-; CHECK-P7-NEXT:    lxvd2x vs0, 0, r5
-; CHECK-P7-NEXT:    xxswapd v2, vs0
-; CHECK-P7-NEXT:    vmrglb v2, v3, v2
+; CHECK-P7-NEXT:    xxlxor v2, v2, v2
+; CHECK-P7-NEXT:    lfiwzx f0, r3, r4
+; CHECK-P7-NEXT:    xxlor v3, vs0, vs0
+; CHECK-P7-NEXT:    vmrglb v2, v2, v3
 ; CHECK-P7-NEXT:    blr
 entry:
   %idx.ext = sext i32 %offset to i64
   %add.ptr = getelementptr inbounds i32, i32* %ptr, i64 %idx.ext
   %0 = load i32, i32* %add.ptr, align 4
   %conv = zext i32 %0 to i64
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
   %1 = bitcast <2 x i64> %splat.splatinsert to <16 x i8>

llvm/test/CodeGen/PowerPC/load-and-splat.ll

entry:
   %arrayidx = getelementptr inbounds i64, i64* %a, i64 3
   %0 = load i64, i64* %arrayidx, align 8
   %splat.splatinsert.i = insertelement <2 x i64> undef, i64 %0, i32 0
   %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> undef, <2 x i32> zeroinitializer
   store <2 x i64> %splat.splat.i, <2 x i64>* %c, align 16
   ret void
 }
 
-; FIXME: use lfiwax for this case at PWR7.
 define void @test5(<2 x i64>* %a, i32* %in) {
 ; P9-LABEL: test5:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lfiwax f0, 0, r4
 ; P9-NEXT:    xxspltd vs0, vs0, 0
 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test5:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lfiwax f0, 0, r4
 ; P8-NEXT:    xxspltd vs0, vs0, 0
 ; P8-NEXT:    stxvd2x vs0, 0, r3
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test5:
 ; P7:       # %bb.0: # %entry
-; P7-NEXT:    lwa r4, 0(r4)
-; P7-NEXT:    addi r5, r1, -16
-; P7-NEXT:    std r4, -8(r1)
-; P7-NEXT:    std r4, -16(r1)
-; P7-NEXT:    lxvd2x vs0, 0, r5
+; P7-NEXT:    lfiwax f0, 0, r4
+; P7-NEXT:    xxspltd vs0, vs0, 0
 ; P7-NEXT:    stxvd2x vs0, 0, r3
 ; P7-NEXT:    blr
 entry:
   %0 = load i32, i32* %in, align 4
   %conv = sext i32 %0 to i64
   %splat.splatinsert.i = insertelement <2 x i64> poison, i64 %conv, i32 0
   %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> poison, <2 x i32> zeroinitializer
   store <2 x i64> %splat.splat.i, <2 x i64>* %a, align 16
   ret void
 }
 
-; FIXME: use lfiwzx for this case at PWR7.
 define void @test6(<2 x i64>* %a, i32* %in) {
 ; P9-LABEL: test6:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lfiwzx f0, 0, r4
 ; P9-NEXT:    xxspltd vs0, vs0, 0
 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
 ; P8-LABEL: test6:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lfiwzx f0, 0, r4
 ; P8-NEXT:    xxspltd vs0, vs0, 0
 ; P8-NEXT:    stxvd2x vs0, 0, r3
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test6:
 ; P7:       # %bb.0: # %entry
-; P7-NEXT:    lwz r4, 0(r4)
-; P7-NEXT:    addi r5, r1, -16
-; P7-NEXT:    std r4, -8(r1)
-; P7-NEXT:    std r4, -16(r1)
-; P7-NEXT:    lxvd2x vs0, 0, r5
+; P7-NEXT:    lfiwzx f0, 0, r4
+; P7-NEXT:    xxspltd vs0, vs0, 0
 ; P7-NEXT:    stxvd2x vs0, 0, r3
 ; P7-NEXT:    blr
 entry:
   %0 = load i32, i32* %in, align 4
   %conv = zext i32 %0 to i64
   %splat.splatinsert.i = insertelement <2 x i64> poison, i64 %conv, i32 0
   %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> poison, <2 x i32> zeroinitializer
   store <2 x i64> %splat.splat.i, <2 x i64>* %a, align 16

llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll

 ; VSX-NEXT:    mtfprd 0, 5
 ; VSX-NEXT:    xxspltd 35, 0, 0
 ; VSX-NEXT:    vaddudm 2, 2, 3
 ; VSX-NEXT:    blr
 ;
 ; NOVSX-LABEL: increment_by_val:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    addi 3, 1, -16
-; NOVSX-NEXT:    std 5, -8(1)
 ; NOVSX-NEXT:    std 5, -16(1)
 ; NOVSX-NEXT:    lvx 3, 0, 3
+; NOVSX-NEXT:    vsldoi 4, 3, 3, 8
+; NOVSX-NEXT:    vsldoi 3, 4, 3, 8
 ; NOVSX-NEXT:    vaddudm 2, 2, 3
 ; NOVSX-NEXT:    blr
   %tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 0
   %tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 1
   %result = add <2 x i64> %x, %tmpvec2
   ret <2 x i64> %result
 ; FIXME: This is currently generating the following instruction sequence
 ;   std 5, -8(1)

 ; VSX-NEXT:    mtfprd 0, 5
 ; VSX-NEXT:    xxspltd 35, 0, 0
 ; VSX-NEXT:    vsubudm 2, 2, 3
 ; VSX-NEXT:    blr
 ;
 ; NOVSX-LABEL: decrement_by_val:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    addi 3, 1, -16
-; NOVSX-NEXT:    std 5, -8(1)
 ; NOVSX-NEXT:    std 5, -16(1)
 ; NOVSX-NEXT:    lvx 3, 0, 3
+; NOVSX-NEXT:    vsldoi 4, 3, 3, 8
+; NOVSX-NEXT:    vsldoi 3, 4, 3, 8
 ; NOVSX-NEXT:    vsubudm 2, 2, 3
 ; NOVSX-NEXT:    blr
   %tmpvec = insertelement <2 x i64> <i64 0, i64 0>, i64 %val, i32 0
   %tmpvec2 = insertelement <2 x i64> %tmpvec, i64 %val, i32 1
   %result = sub <2 x i64> %x, %tmpvec2
   ret <2 x i64> %result
 }