[SLP]Fix possible crash on unreachable incoming values sorting.

[ABataev]

Summary

The incoming values for PHI nodes may come from unreachable BasicBlocks,
need to handle this case.

llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

stable_sort(Incoming, [this, &PHIToOpcodes](Value *V1, Value *V2) {
       for (int I = 0, E = Opcodes1.size(); I < E; ++I) {
         // Undefs are compatible with any other value.
         if (isa<UndefValue>(Opcodes1[I]) || isa<UndefValue>(Opcodes2[I]))
           continue;
         if (auto *I1 = dyn_cast<Instruction>(Opcodes1[I]))
           if (auto *I2 = dyn_cast<Instruction>(Opcodes2[I])) {
             DomTreeNodeBase<BasicBlock> *NodeI1 = DT->getNode(I1->getParent());
             DomTreeNodeBase<BasicBlock> *NodeI2 = DT->getNode(I2->getParent());
-            assert(NodeI1 && "Should only process reachable instructions");
-            assert(NodeI2 && "Should only process reachable instructions");
+            if (!NodeI1)
+              return NodeI2 != nullptr;
+            if (!NodeI2)
+              return false;
             assert((NodeI1 == NodeI2) ==
                        (NodeI1->getDFSNumIn() == NodeI2->getDFSNumIn()) &&
                    "Different nodes should have different DFS numbers");
             if (NodeI1 != NodeI2)
               return NodeI1->getDFSNumIn() < NodeI2->getDFSNumIn();
             InstructionsState S = getSameOpcode({I1, I2});
             if (S.getOpcode())
               continue;

llvm/test/Transforms/SLPVectorizer/X86/unreachable.ll

bb2:
   store i32 %t2.0, i32* %t12, align 4
   %t13 = getelementptr inbounds i32, i32* %x, i64 2
   store i32 %t3.0, i32* %t13, align 4
   %t14 = getelementptr inbounds i32, i32* %x, i64 3
   store i32 %t4.0, i32* %t14, align 4
   ret void
 }
 
+define void @bar() {
+; CHECK-LABEL: @bar(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[TMP:%.*]] = load atomic i8*, i8** undef unordered, align 8
+; CHECK-NEXT:    br label [[BB6:%.*]]
+; CHECK:       bb5:
+; CHECK-NEXT:    [[TMP4:%.*]] = load atomic i8*, i8** undef unordered, align 8
+; CHECK-NEXT:    br label [[BB6]]
+; CHECK:       bb6:
+; CHECK-NEXT:    [[TMP7:%.*]] = phi i8* [ [[TMP]], [[BB5:%.*]] ], [ undef, [[BB:%.*]] ]
+; CHECK-NEXT:    [[TMP8:%.*]] = phi i8* [ [[TMP4]], [[BB5]] ], [ undef, [[BB]] ]
+; CHECK-NEXT:    ret void
+;
+bb:
+  %tmp = load atomic i8*, i8** undef unordered, align 8
+  br label %bb6
+
+bb5:                                              ; No predecessors!
+  %tmp4 = load atomic i8*, i8** undef unordered, align 8
+  br label %bb6
+
+bb6:                                              ; preds = %bb5, %bb
+  %tmp7 = phi i8* [ %tmp, %bb5 ], [ undef, %bb ]
+  %tmp8 = phi i8* [ %tmp4, %bb5 ], [ undef, %bb ]
+  ret void
+}