[PowerPC] prepare update form with non-const increment

[shchenz]

Summary

This is a follow-up of https://reviews.llvm.org/D105872
In this patch, we handle update-form with non-const increment.

[shchenz]

rebase due to patent change

[shchenz]

gentle ping

[shchenz]

ping

[shchenz]

rebase

[shchenz]

rebase

[shchenz]

gentle ping

[jsji]

LGTM. Thanks.

llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp

if (BasePtrIncConstantSCEV)
     IsConstantInc = true;
 
   // No valid representation for the increment.
   if (!IncNode) {
     LLVM_DEBUG(dbgs() << "Loop Increasement can not be represented!\n");
     return MadeChange;
   }
 
-  // Now we only handle update form for constant increment.
-  // FIXME: add support for non-constant increment UpdateForm.
-  if (!IsConstantInc && Form == UpdateForm) {
-    LLVM_DEBUG(dbgs() << "not a constant increment for update form!\n");
-    return MadeChange;
-  }
-
   // For some DS form load/store instructions, it can also be an update form,
   // if the stride is constant and is a multipler of 4. Use update form if
   // prefer it.
   bool CanPreInc =
       (Form == UpdateForm ||
        ((Form == DSForm) && IsConstantInc &&
         !BasePtrIncConstantSCEV->getAPInt().urem(4) && PreferUpdateForm));
   const SCEV *BasePtrStartSCEV = nullptr;
-  if (CanPreInc)
-    BasePtrStartSCEV =
-        SE->getMinusSCEV(BasePtrSCEV->getStart(), BasePtrIncConstantSCEV);
-  else
+  if (CanPreInc) {
+    assert(SE->isLoopInvariant(BasePtrIncSCEV, L) &&
+           "Increment is not loop invariant!\n");
+    BasePtrStartSCEV = SE->getMinusSCEV(BasePtrSCEV->getStart(),
+                                        IsConstantInc ? BasePtrIncConstantSCEV
+                                                      : BasePtrIncSCEV);
+  } else
     BasePtrStartSCEV = BasePtrSCEV->getStart();
 
   if (!isSafeToExpand(BasePtrStartSCEV, *SE))
     return MadeChange;
 
   if (alreadyPrepared(L, MemI, BasePtrStartSCEV, BasePtrIncSCEV, Form)) {
     LLVM_DEBUG(dbgs() << "Instruction form is already prepared!\n");
     return MadeChange;
if (PI != LoopPredecessor)
       continue;
 
     NewPHI->addIncoming(BasePtrStart, LoopPredecessor);
   }
 
   Instruction *PtrInc = nullptr;
   Instruction *NewBasePtr = nullptr;
   if (CanPreInc) {
-    assert(BasePtrIncConstantSCEV &&
-           "update form now only supports constant increment.");
     Instruction *InsPoint = &*Header->getFirstInsertionPt();
-    PtrInc = GetElementPtrInst::Create(
-        I8Ty, NewPHI, BasePtrIncConstantSCEV->getValue(),
-        getInstrName(MemI, GEPNodeIncNameSuffix), InsPoint);
+    PtrInc = GetElementPtrInst::Create(I8Ty, NewPHI, IncNode,
+                                       getInstrName(MemI, GEPNodeIncNameSuffix),
+                                       InsPoint);
     cast<GetElementPtrInst>(PtrInc)->setIsInBounds(IsPtrInBounds(BasePtr));
     for (auto PI : predecessors(Header)) {
       if (PI == LoopPredecessor)
         continue;
 
       NewPHI->addIncoming(PtrInc, PI);
     }
     if (PtrInc->getType() != BasePtr->getType())

llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll

 ; }
 
 define zeroext i8 @foo1(i8* %p, i32 signext %n, i32 signext %count) {
 ; CHECK-LABEL: foo1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r4, 1
 ; CHECK-NEXT:    blt cr0, .LBB1_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
-; CHECK-NEXT:    addi r4, r4, -1
-; CHECK-NEXT:    addi r3, r3, 1000
 ; CHECK-NEXT:    extsw r5, r5
-; CHECK-NEXT:    li r6, 0
-; CHECK-NEXT:    clrldi r4, r4, 32
-; CHECK-NEXT:    addi r4, r4, 1
-; CHECK-NEXT:    mtctr r4
-; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    sub r3, r3, r5
+; CHECK-NEXT:    addi r6, r3, 1000
+; CHECK-NEXT:    addi r3, r4, -1
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    mtctr r3
+; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB1_2: # %for.body
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lbzx r7, r3, r6
-; CHECK-NEXT:    add r6, r6, r5
-; CHECK-NEXT:    add r4, r7, r4
+; CHECK-NEXT:    lbzux r4, r6, r5
+; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    bdnz .LBB1_2
 ; CHECK-NEXT:  # %bb.3: # %for.cond.cleanup
-; CHECK-NEXT:    clrldi r3, r4, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB1_4:
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    blr
 entry:
   %cmp10 = icmp sgt i32 %n, 0
   br i1 %cmp10, label %for.body.preheader, label %for.cond.cleanup
 

llvm/test/CodeGen/PowerPC/lsr-profitable-chain.ll

 ; CHECK-NEXT:    cmpd 5, 7
 ; CHECK-NEXT:    bge 0, .LBB0_6
 ; CHECK-NEXT:  .LBB0_3: # =>This Loop Header: Depth=1
 ; CHECK-NEXT:    # Child Loop BB0_5 Depth 2
 ; CHECK-NEXT:    sub 24, 5, 10
 ; CHECK-NEXT:    cmpd 6, 24
 ; CHECK-NEXT:    bge 0, .LBB0_2
 ; CHECK-NEXT:  # %bb.4:
-; CHECK-NEXT:    maddld 19, 0, 27, 30
+; CHECK-NEXT:    maddld 21, 0, 27, 30
 ; CHECK-NEXT:    maddld 20, 0, 27, 12
-; CHECK-NEXT:    add 22, 6, 28
-; CHECK-NEXT:    add 21, 6, 8
+; CHECK-NEXT:    add 23, 6, 28
+; CHECK-NEXT:    add 22, 6, 8
 ; CHECK-NEXT:    add 20, 6, 20
-; CHECK-NEXT:    add 19, 6, 19
-; CHECK-NEXT:    sldi 23, 6, 3
+; CHECK-NEXT:    add 19, 6, 21
+; CHECK-NEXT:    sldi 23, 23, 3
 ; CHECK-NEXT:    sldi 22, 22, 3
-; CHECK-NEXT:    sldi 21, 21, 3
-; CHECK-NEXT:    add 23, 4, 23
+; CHECK-NEXT:    sldi 21, 6, 3
+; CHECK-NEXT:    add 23, 29, 23
 ; CHECK-NEXT:    add 22, 29, 22
-; CHECK-NEXT:    add 21, 29, 21
 ; CHECK-NEXT:    sldi 20, 20, 3
 ; CHECK-NEXT:    sldi 19, 19, 3
+; CHECK-NEXT:    add 21, 4, 21
 ; CHECK-NEXT:    add 20, 3, 20
 ; CHECK-NEXT:    add 19, 3, 19
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_5: # Parent Loop BB0_3 Depth=1
 ; CHECK-NEXT:    # => This Inner Loop Header: Depth=2
-; CHECK-NEXT:    lfd 0, 0(23)
+; CHECK-NEXT:    lfd 0, 0(21)
 ; CHECK-NEXT:    lfd 1, 0(20)
 ; CHECK-NEXT:    add 6, 6, 10
 ; CHECK-NEXT:    cmpd 6, 24
 ; CHECK-NEXT:    xsadddp 0, 0, 1
 ; CHECK-NEXT:    lfd 1, 8(20)
 ; CHECK-NEXT:    xsadddp 0, 0, 1
 ; CHECK-NEXT:    lfd 1, 16(20)
 ; CHECK-NEXT:    xsadddp 0, 0, 1
 ; CHECK-NEXT:    lfd 1, 24(20)
 ; CHECK-NEXT:    add 20, 20, 11
 ; CHECK-NEXT:    xsadddp 0, 0, 1
 ; CHECK-NEXT:    lfd 1, 0(19)
 ; CHECK-NEXT:    xsadddp 0, 0, 1
 ; CHECK-NEXT:    lfd 1, 8(19)
 ; CHECK-NEXT:    xsadddp 0, 0, 1
 ; CHECK-NEXT:    lfd 1, 16(19)
 ; CHECK-NEXT:    xsadddp 0, 0, 1
 ; CHECK-NEXT:    lfd 1, 24(19)
 ; CHECK-NEXT:    add 19, 19, 11
 ; CHECK-NEXT:    xsadddp 0, 0, 1
-; CHECK-NEXT:    lfd 1, -16(21)
-; CHECK-NEXT:    xsadddp 0, 0, 1
-; CHECK-NEXT:    lfd 1, -8(21)
-; CHECK-NEXT:    xsadddp 0, 0, 1
-; CHECK-NEXT:    lfd 1, 0(21)
-; CHECK-NEXT:    xsadddp 0, 0, 1
-; CHECK-NEXT:    lfd 1, 8(21)
-; CHECK-NEXT:    add 21, 21, 11
-; CHECK-NEXT:    xsadddp 0, 0, 1
 ; CHECK-NEXT:    lfd 1, -16(22)
 ; CHECK-NEXT:    xsadddp 0, 0, 1
 ; CHECK-NEXT:    lfd 1, -8(22)
 ; CHECK-NEXT:    xsadddp 0, 0, 1
 ; CHECK-NEXT:    lfd 1, 0(22)
 ; CHECK-NEXT:    xsadddp 0, 0, 1
 ; CHECK-NEXT:    lfd 1, 8(22)
 ; CHECK-NEXT:    add 22, 22, 11
 ; CHECK-NEXT:    xsadddp 0, 0, 1
-; CHECK-NEXT:    stfd 0, 0(23)
+; CHECK-NEXT:    lfd 1, -16(23)
+; CHECK-NEXT:    xsadddp 0, 0, 1
+; CHECK-NEXT:    lfd 1, -8(23)
+; CHECK-NEXT:    xsadddp 0, 0, 1
+; CHECK-NEXT:    lfd 1, 0(23)
+; CHECK-NEXT:    xsadddp 0, 0, 1
+; CHECK-NEXT:    lfd 1, 8(23)
 ; CHECK-NEXT:    add 23, 23, 11
+; CHECK-NEXT:    xsadddp 0, 0, 1
+; CHECK-NEXT:    stfd 0, 0(21)
+; CHECK-NEXT:    add 21, 21, 11
 ; CHECK-NEXT:    blt 0, .LBB0_5
 ; CHECK-NEXT:    b .LBB0_2
 ; CHECK-NEXT:  .LBB0_6:
 ; CHECK-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 29, -24(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 28, -32(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 27, -40(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 26, -48(1) # 8-byte Folded Reload