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Differential D105952

[AArch64][GlobalISel] Clamp <n x p0> vecs when legalizing G_EXTRACT_VECTOR_ELT
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Authored by paquette on Jul 13 2021, 5:47 PM.

Details

Reviewers
aemerson
jroelofs
Commits
rG46c8e7122b51: [AArch64][GlobalISel] Clamp <n x p0> vecs when legalizing G_EXTRACT_VECTOR_ELT
Summary

This case was missing from G_EXTRACT_VECTOR_ELT. It's the same as for s64.

https://godbolt.org/z/Tnq4acY8z

Diff Detail

Event Timeline

paquette created this revision.Jul 13 2021, 5:47 PM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka. · View Herald TranscriptJul 13 2021, 5:47 PM
paquette requested review of this revision.Jul 13 2021, 5:47 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 13 2021, 5:47 PM
arsenm added a subscriber: arsenm.Jul 13 2021, 5:49 PM
arsenm added inline comments.
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
264

Also need to be careful of other address space pointer vectors

Harbormaster completed remote builds in B113881: Diff 358467.Jul 13 2021, 6:21 PM
aemerson accepted this revision.Jul 14 2021, 1:12 PM
This revision is now accepted and ready to land.Jul 14 2021, 1:12 PM
paquette added inline comments.Jul 15 2021, 2:03 PM
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
264

Yeah, I'll add a testcase.

This revision was landed with ongoing or failed builds.Jul 15 2021, 2:06 PM
Closed by commit rG46c8e7122b51: [AArch64][GlobalISel] Clamp <n x p0> vecs when legalizing G_EXTRACT_VECTOR_ELT (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rG46c8e7122b51: [AArch64][GlobalISel] Clamp <n x p0> vecs when legalizing G_EXTRACT_VECTOR_ELT.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
3 lines
test/
CodeGen/
AArch64/
GlobalISel/
39 lines

Diff 359131

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Show First 20 Lines • Show All 644 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder(G_EXTRACT_VECTOR_ELT)
.minScalarOrEltIf( .minScalarOrEltIf(
[=](const LegalityQuery &Query) { [=](const LegalityQuery &Query) {
return Query.Types[1].getNumElements() <= 16; return Query.Types[1].getNumElements() <= 16;
}, },
0, s8) 0, s8)
.minScalarOrElt(0, s8) // Worst case, we need at least s8. .minScalarOrElt(0, s8) // Worst case, we need at least s8.
.clampMaxNumElements(1, s64, 2) .clampMaxNumElements(1, s64, 2)
.clampMaxNumElements(1, s32, 4) .clampMaxNumElements(1, s32, 4)
.clampMaxNumElements(1, s16, 8); .clampMaxNumElements(1, s16, 8)
.clampMaxNumElements(1, p0, 2);
getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT) getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
.legalIf(typeInSet(0, {v8s16, v2s32, v4s32, v2s64})); .legalIf(typeInSet(0, {v8s16, v2s32, v4s32, v2s64}));
getActionDefinitionsBuilder(G_BUILD_VECTOR) getActionDefinitionsBuilder(G_BUILD_VECTOR)
.legalFor({{v8s8, s8}, .legalFor({{v8s8, s8},
{v16s8, s8}, {v16s8, s8},
{v2s16, s16}, {v2s16, s16},
▲ Show 20 Lines • Show All 530 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o - -global-isel-abort=1 | FileCheck %s # RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer -global-isel-abort=0 -verify-machineinstrs %s -o - | FileCheck %s
--- ---
name: test_eve_1 name: test_eve_1
body: | body: |
bb.0: bb.0:
liveins: $q0 liveins: $q0
; CHECK-LABEL: name: test_eve_1 ; CHECK-LABEL: name: test_eve_1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
▲ Show 20 Lines • Show All 229 Lines • ▼ Show 20 Lines bb.0:
%concat:_(<16 x s16>) = G_CONCAT_VECTORS %0(<8 x s16>), %1(<8 x s16>) %concat:_(<16 x s16>) = G_CONCAT_VECTORS %0(<8 x s16>), %1(<8 x s16>)
%idx:_(s32) = G_CONSTANT i32 9 %idx:_(s32) = G_CONSTANT i32 9
%idxprom:_(s64) = G_SEXT %idx(s32) %idxprom:_(s64) = G_SEXT %idx(s32)
%3:_(s16) = G_EXTRACT_VECTOR_ELT %concat:_(<16 x s16>), %idxprom:_(s64) %3:_(s16) = G_EXTRACT_VECTOR_ELT %concat:_(<16 x s16>), %idxprom:_(s64)
%ext:_(s32) = G_ANYEXT %3 %ext:_(s32) = G_ANYEXT %3
$w0 = COPY %ext(s32) $w0 = COPY %ext(s32)
RET_ReallyLR RET_ReallyLR
... ...
---
name: test_eve_v4p0
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: test_eve_v4p0
; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; CHECK: %idx:_(s64) = G_CONSTANT i64 1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[DEF]](p0), [[DEF]](p0)
; CHECK: %eve:_(p0) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x p0>), %idx(s64)
; CHECK: $x0 = COPY %eve(p0)
; CHECK: RET_ReallyLR
%vec:_(<4 x p0>) = G_IMPLICIT_DEF
%idx:_(s64) = G_CONSTANT i64 1
%eve:_(p0) = G_EXTRACT_VECTOR_ELT %vec:_(<4 x p0>), %idx:_(s64)
$x0 = COPY %eve(p0)
RET_ReallyLR
arsenmUnsubmitted
Not Done
ReplyInline Actions

Also need to be careful of other address space pointer vectors

arsenm: Also need to be careful of other address space pointer vectors
paquetteAuthorUnsubmitted
Done
ReplyInline Actions

Yeah, I'll add a testcase.

paquette: Yeah, I'll add a testcase.
...
---
name: cant_legalize_different_address_spaces
body: |
bb.0:
liveins: $x0
; Make sure that the pointer legalization rules don't apply when we have
; different address spaces.
; CHECK-LABEL: name: cant_legalize_different_address_spaces
; CHECK: %vec:_(<4 x p1>) = G_IMPLICIT_DEF
; CHECK: %idx:_(s64) = G_CONSTANT i64 1
; CHECK: %eve:_(p0) = G_EXTRACT_VECTOR_ELT %vec(<4 x p1>), %idx(s64)
; CHECK: $x0 = COPY %eve(p0)
; CHECK: RET_ReallyLR
%vec:_(<4 x p1>) = G_IMPLICIT_DEF
%idx:_(s64) = G_CONSTANT i64 1
%eve:_(p0) = G_EXTRACT_VECTOR_ELT %vec:_(<4 x p1>), %idx:_(s64)
$x0 = COPY %eve(p0)
RET_ReallyLR