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Differential D105855

[mlir][memref] adjust integration tests to new lowering passes
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Authored by aartbik on Jul 12 2021, 4:05 PM.

Details

Reviewers
nicolasvasilache
mehdi_amini
ftynse
Commits
rG7039dfc6dd15: [mlir][memref] adjust integration tests to new lowering passes
Summary

these tests run under the emulator and thus were overlooked

Diff Detail

Event Timeline

aartbik created this revision.Jul 12 2021, 4:05 PM
Herald added subscribers: dcaballe, cota, teijeong and 15 others. · View Herald TranscriptJul 12 2021, 4:05 PM
aartbik requested review of this revision.Jul 12 2021, 4:05 PM
Herald added a reviewer: nicolasvasilache. · View Herald TranscriptJul 12 2021, 4:05 PM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: stephenneuendorffer, nicolasvasilache. · View Herald Transcript
aartbik added reviewers: mehdi_amini, ftynse.Jul 12 2021, 4:06 PM
Harbormaster completed remote builds in B113609: Diff 358094.Jul 12 2021, 4:41 PM
ftynse accepted this revision.Jul 13 2021, 12:25 AM
This revision is now accepted and ready to land.Jul 13 2021, 12:25 AM
Closed by commit rG7039dfc6dd15: [mlir][memref] adjust integration tests to new lowering passes (authored by aartbik). · Explain WhyJul 13 2021, 9:14 AM
This revision was automatically updated to reflect the committed changes.
aartbik added a commit: rG7039dfc6dd15: [mlir][memref] adjust integration tests to new lowering passes.

Revision Contents

PathSize
mlir/
test/
Integration/
Dialect/
Vector/
CPU/
AMX/
2 lines
2 lines
2 lines
2 lines
2 lines
X86Vector/
2 lines

Diff 358094

mlir/test/Integration/Dialect/Vector/CPU/AMX/test-mulf.mlir

// RUN: mlir-opt %s -convert-vector-to-scf -lower-affine -convert-scf-to-std -convert-vector-to-llvm="enable-amx" -convert-std-to-llvm | \ // RUN: mlir-opt %s -convert-vector-to-scf -lower-affine -convert-scf-to-std -convert-vector-to-llvm="enable-amx" -convert-memref-to-llvm -convert-std-to-llvm | \
// RUN: mlir-translate -mlir-to-llvmir | \ // RUN: mlir-translate -mlir-to-llvmir | \
// RUN: %lli --entry-function=entry --mattr="+amx-tile,+amx-int8,+amx-bf16" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \ // RUN: %lli --entry-function=entry --mattr="+amx-tile,+amx-int8,+amx-bf16" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
// RUN: FileCheck %s // RUN: FileCheck %s
// Note: To run this test, your CPU must support AMX. // Note: To run this test, your CPU must support AMX.
// Multiply into zeroed destination. // Multiply into zeroed destination.
func @kernel1(%arg0: memref<2x4xbf16>, func @kernel1(%arg0: memref<2x4xbf16>,
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mlir/test/Integration/Dialect/Vector/CPU/AMX/test-muli-ext.mlir

// RUN: mlir-opt %s -convert-vector-to-scf -lower-affine -convert-scf-to-std -convert-vector-to-llvm="enable-amx" -convert-std-to-llvm | \ // RUN: mlir-opt %s -convert-vector-to-scf -lower-affine -convert-scf-to-std -convert-vector-to-llvm="enable-amx" -convert-memref-to-llvm -convert-std-to-llvm | \
// RUN: mlir-translate -mlir-to-llvmir | \ // RUN: mlir-translate -mlir-to-llvmir | \
// RUN: %lli --entry-function=entry --mattr="+amx-tile,+amx-int8,+amx-bf16" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \ // RUN: %lli --entry-function=entry --mattr="+amx-tile,+amx-int8,+amx-bf16" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
// RUN: FileCheck %s // RUN: FileCheck %s
// Note: To run this test, your CPU must support AMX. // Note: To run this test, your CPU must support AMX.
func @print(%arg0: memref<16x4xi32>) { func @print(%arg0: memref<16x4xi32>) {
%iu = constant -1: i32 %iu = constant -1: i32
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mlir/test/Integration/Dialect/Vector/CPU/AMX/test-muli.mlir

// RUN: mlir-opt %s -convert-vector-to-scf -lower-affine -convert-scf-to-std -convert-vector-to-llvm="enable-amx" -convert-std-to-llvm | \ // RUN: mlir-opt %s -convert-vector-to-scf -lower-affine -convert-scf-to-std -convert-vector-to-llvm="enable-amx" -convert-memref-to-llvm -convert-std-to-llvm | \
// RUN: mlir-translate -mlir-to-llvmir | \ // RUN: mlir-translate -mlir-to-llvmir | \
// RUN: %lli --entry-function=entry --mattr="+amx-tile,+amx-int8,+amx-bf16" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \ // RUN: %lli --entry-function=entry --mattr="+amx-tile,+amx-int8,+amx-bf16" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
// RUN: FileCheck %s // RUN: FileCheck %s
// Note: To run this test, your CPU must support AMX. // Note: To run this test, your CPU must support AMX.
// Multiply into zeroed destination. // Multiply into zeroed destination.
func @kernel1(%arg0: memref<2x8xi8>, func @kernel1(%arg0: memref<2x8xi8>,
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mlir/test/Integration/Dialect/Vector/CPU/AMX/test-tilezero-block.mlir

// RUN: mlir-opt %s -convert-vector-to-scf -lower-affine -convert-scf-to-std -convert-vector-to-llvm="enable-amx" -convert-std-to-llvm | \ // RUN: mlir-opt %s -convert-vector-to-scf -lower-affine -convert-scf-to-std -convert-vector-to-llvm="enable-amx" -convert-memref-to-llvm -convert-std-to-llvm | \
// RUN: mlir-translate -mlir-to-llvmir | \ // RUN: mlir-translate -mlir-to-llvmir | \
// RUN: %lli --entry-function=entry --mattr="+amx-tile,+amx-int8,+amx-bf16" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \ // RUN: %lli --entry-function=entry --mattr="+amx-tile,+amx-int8,+amx-bf16" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
// RUN: FileCheck %s // RUN: FileCheck %s
// Note: To run this test, your CPU must support AMX. // Note: To run this test, your CPU must support AMX.
func @print(%arg0: memref<4x32xf32>) { func @print(%arg0: memref<4x32xf32>) {
%fu = constant -1.0: f32 %fu = constant -1.0: f32
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mlir/test/Integration/Dialect/Vector/CPU/AMX/test-tilezero.mlir

// RUN: mlir-opt %s -convert-vector-to-scf -lower-affine -convert-scf-to-std -convert-vector-to-llvm="enable-amx" -convert-std-to-llvm | \ // RUN: mlir-opt %s -convert-vector-to-scf -lower-affine -convert-scf-to-std -convert-vector-to-llvm="enable-amx" -convert-memref-to-llvm -convert-std-to-llvm | \
// RUN: mlir-translate -mlir-to-llvmir | \ // RUN: mlir-translate -mlir-to-llvmir | \
// RUN: %lli --entry-function=entry --mattr="+amx-tile,+amx-int8,+amx-bf16" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \ // RUN: %lli --entry-function=entry --mattr="+amx-tile,+amx-int8,+amx-bf16" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
// RUN: FileCheck %s // RUN: FileCheck %s
// Note: To run this test, your CPU must support AMX. // Note: To run this test, your CPU must support AMX.
func @tilezero(%arg0: memref<?x?xi32>, %i: index, %j: index) { func @tilezero(%arg0: memref<?x?xi32>, %i: index, %j: index) {
%1 = amx.tile_zero : vector<16x16xi32> %1 = amx.tile_zero : vector<16x16xi32>
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mlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-sparse-dot-product.mlir

// RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm="enable-x86vector" -convert-std-to-llvm | \ // RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm="enable-x86vector" -convert-memref-to-llvm -convert-std-to-llvm | \
// RUN: mlir-translate --mlir-to-llvmir | \ // RUN: mlir-translate --mlir-to-llvmir | \
// RUN: %lli --entry-function=entry --mattr="avx512bw,avx512vp2intersect" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \ // RUN: %lli --entry-function=entry --mattr="avx512bw,avx512vp2intersect" --dlopen=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
// RUN: FileCheck %s // RUN: FileCheck %s
// This test shows how to implement a sparse vector-vector dot product with // This test shows how to implement a sparse vector-vector dot product with
// AVX512. It uses vp2intersect, mask.compress and vector.contract to compute // AVX512. It uses vp2intersect, mask.compress and vector.contract to compute
// the dot product of two sparse HW vectors of 8 float64 elements ("segment"). // the dot product of two sparse HW vectors of 8 float64 elements ("segment").
// Each sparse vector is represented by an index memref (A or C) and by a data // Each sparse vector is represented by an index memref (A or C) and by a data
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